Three-dimensional silicon-based adapter structure processing method and device based on silicon-based-air back cavity structure

Abstract

The invention discloses a three-dimensional silicon-based switching structure processing method and device based on a silicon-based-air back cavity structure, and the method comprises the steps: firstly, etching a TSV blind groove in the front surface of a silicon-based substrate, sputtering a seed layer on the surface of the silicon-based substrate to carry out blind groove electroplating, and carrying out the mechanical grinding after the interior of the groove is completely plated with metal; and then top layer and bottom metal patterning and silicon substrate-air back cavity structure etching are completed. Through the determination and implementation of the scheme, the difficulty of integrating the metal side wall of the cavity in the silicon-based wafer is overcome, the conversion from the grounded coplanar waveguide wire to the metal waveguide is realized, and an efficient and reliable switching scheme is provided for three-dimensional heterogeneous integration. In the process flow, the stability of the process effect is ensured by improving the photoresist spin-coating process parameters and the mask scheme.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a method for fabricating a three-dimensional silicon-based transition structure based on a silicon-based air cavity structure. Background Technology

[0002] Wafer-level 3D heterogeneous integration packaging technology directly integrates chips and various passive devices into a system on a silicon-based wafer, and performs rewiring on the chip surface to achieve a fan-out effect. Utilizing micro- and nano-scale equipment during the process, hundreds or even more chips can be integrated into a large-scale system at once, and interconnected with passive devices such as filters, antennas, and baluns. This significantly improves packaging efficiency, reduces costs, and enhances overall system performance, making it a crucial method for achieving system-level packaging.

[0003] TSV blind trench plating is a core process in the three-dimensional heterogeneous integration process. It involves electroplating and growing metal on the blind trench portion of a silicon-based surface. This vertical interconnection scheme can reduce the interconnect length of the system, reduce transmission delay, and improve capacitance and inductance effects, thereby achieving device miniaturization and high-density integration.

[0004] With the rapid development of the information age, radar communication systems are constantly iterating and updating towards miniaturization, high performance, and high integration. The traditional Moore's Law is no longer applicable to the current high-density iterative processes within a two-dimensional plane, thus leading to the widespread development of three-dimensional heterogeneous integration technology. Currently, the primary challenge facing radar communication systems in the millimeter-wave band, moving towards miniaturization and high performance, is solving the interconnection problem. Traditional interconnection schemes primarily rely on planar transitions, fanning out from the chip via microstrip lines. This results in large system sizes on substrates of equal thickness, and the fan-out interface is difficult to integrate with waveguides and other interfaces. Reducing the overall system size and transforming the planar transition structure into a three-dimensional structure to achieve three-dimensional integration has become a major research hotspot. Simultaneously, when integrating metal waveguides into silicon substrates for interconnection with chips, the fabrication of the transition structure from the chip's fan-out microstrip line to the rectangular waveguide is a highly challenging aspect. Chip flip-chip technology or embedded wafer-level ball grid arrays in three-dimensional integration methods have been extensively studied; however, the bonding array size is large, transmission performance is heavily influenced by the ball grid size, and high consistency in packaging processes is required. Furthermore, chip-to-waveguide interconnection solutions need to fully consider the integration level and the complexity of the fabrication process, and the fabrication of high-performance interconnect structures for millimeter waves still faces challenges. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a method and apparatus for fabricating a three-dimensional silicon-based transition structure based on a silicon-based air cavity structure.

[0006] According to the present invention, a method and apparatus for fabricating a three-dimensional silicon-based transition structure based on a silicon-based air cavity structure are provided, the scheme of which is as follows:

[0007] In a first aspect, a method for fabricating a three-dimensional silicon-based transition structure based on a silicon-based air cavity structure is provided, the method comprising:

[0008] Step S1: Form and metallize a TSV blind trench on the front side of the silicon substrate;

[0009] Step S2: Prepare metal layers on both sides of a silicon substrate;

[0010] Step S3: After dicing the sample on the back side of the silicon substrate using a photolithography mask and dry etching, the sample is mounted on the waveguide stage.

[0011] Preferably, step S1 includes:

[0012] Step S1.1: Spin-coat positive photoresist onto the front wafer and develop to prepare a mask;

[0013] Step S1.2: Complete bulk silicon etching using dry etching;

[0014] Step S1.3: Wash away the positive photoresist using acetone solution;

[0015] Step S1.4: Sputter a metal seed layer on the front side of the silicon substrate;

[0016] Step S1.5: Cover the front side of the silicon substrate with a layer of dry film photoresist to protect the area outside the etched structure from the effects of electroplating;

[0017] Step S1.6: Perform blind trench electroplating, that is, electroplating and solidifying the deep trenches formed after bulk silicon etching;

[0018] Step S1.7: Mechanically grind down the protruding copper metal after electroplating.

[0019] Preferably, in step S1.2, the blind trench silicon etching is performed at a depth of 250 micrometers;

[0020] In the sputtering process of step S1.4, a layer of metallic chromium is sputtered first;

[0021] In step S1.6, an inhibitor for the activity of surface metal atoms is added to the electroplating solution;

[0022] In step S1.7, a 600-BLD04 grinding wheel is used to mechanically grind the metal.

[0023] Preferably, step S2 includes:

[0024] Step S2.1: Sputter a metal seed layer on the front side of the silicon substrate;

[0025] Step S2.2: Spin-coat positive photoresist onto the formation seed layer and then photolithographically form a mask layer;

[0026] Step S2.3: Electroplating the top metal layer and removing the adhesive, then etching away the metal seed layer using an ion beam to form a complete top metal layer structure;

[0027] Step S2.4: Sputter a metal seed layer on the bottom of the silicon substrate and spin-coat a positive photoresist;

[0028] Step S2.5: Electroplating the bottom metal layer and removing the adhesive is performed. The metal seed layer is etched away using an ion beam to form a complete bottom metal layer structure.

[0029] Preferably, in step S2.1, the copper layer thickness in the sputtered metal seed layer is 300 nm;

[0030] In step S2.3, the electroplating thickness of the top metal layer is 10 μm;

[0031] In step S2.5, the thickness of the bottom metal layer electroplating is 10 μm;

[0032] Preferably, step S3 includes:

[0033] Step S3.1: Spin-coat positive photoresist on the back side of a silicon substrate and develop to prepare a mask;

[0034] Step S3.2: Complete bulk silicon etching using dry etching to form a silicon-based air cavity structure;

[0035] Step S3.3: Remove residual adhesive using acetone solution;

[0036] Step S3.4: Dice the silicon substrate to complete the fabrication of the transition structure.

[0037] All dry etching methods are inductively coupled plasma dry etching.

[0038] Secondly, an apparatus is provided, which is fabricated by the three-dimensional silicon-based transition structure fabrication method based on the silicon-based air cavity structure.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] 1. This invention solves the thickness limitation of the interconnect dielectric layer by directly using high-resistivity silicon, a system-in-package substrate, as the dielectric material for the transition structure, thereby increasing the dielectric thickness;

[0041] 2. This invention simultaneously solves the edge cracking phenomenon caused by the difference in thermal expansion coefficients between different materials, thereby preventing the risk of breakage of the top layer metal traces; and proposes a scheme for preparing metallized through-slots on silicon substrates, which reduces interconnection losses by combining the fabrication of TSV blind slots with dry etching, and improves the diversity and reliability of wafer-level heterogeneous integration packaging processes.

[0042] 3. This invention addresses the problem of chip RF fan-out interconnection in silicon-based system-level integration. By introducing a silicon-air back cavity on a silicon substrate to form a three-dimensional interconnection structure, it replaces the traditional planar fan-out interconnection scheme and greatly reduces the overall size of the RF system. Attached Figure Description

[0043] Figure 1 It is a cross-sectional view of the three-dimensional transition structure;

[0044] Figure 2 This is a basic flowchart of the method of the present invention.

[0045] Figure label:

[0046] 101 Four-inch high-resistivity circular silicon wafer; 102 Metallized through-slot structure; 103 Silicon-based air-back cavity structure; 104 Top metal layer; 105 Bottom metal layer; 106 Metal waveguide stage Detailed Implementation

[0047] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0048] This invention addresses the problem of insufficient thickness in interconnect dielectric layers; the issue of edge cracking during fabrication due to differences in thermal expansion coefficients between different materials, leading to breakage of the top-layer metal traces; and the problems encountered when improving traditional planar interconnect structures by integrating metal rectangular waveguides into silicon substrates to achieve three-dimensional integrated architectures. It provides a method for fabricating a three-dimensional silicon-based interconnect structure based on a silicon-air cavity structure, referring to... Figure 1 As shown, the method specifically includes:

[0049] Step S1: Form and metallize a TSV blind trench on the front side of the silicon substrate.

[0050] Specifically, step S1 includes the following steps:

[0051] Step S1.1: Spin-coat positive photoresist onto the front wafer and develop to prepare a mask;

[0052] Step S1.2: Complete bulk silicon etching using dry etching, and perform blind trench bulk silicon etching to 250 micrometers;

[0053] Step S1.3: Wash away the positive photoresist using acetone solution;

[0054] Step S1.4: Sputter a metal seed layer on the front side of the silicon substrate. During the sputtering process in this step, a layer of metallic chromium is sputtered first, which helps to increase the adhesion of metallic copper.

[0055] Step S1.5: Cover the front side of the silicon substrate with a layer of dry film photoresist to protect the area outside the etched structure from the effects of electroplating;

[0056] Step S1.6: Perform blind tank electroplating, that is, electroplating and plating the deep tank formed after bulk silicon etching; surface metal atom activity inhibitors are added to the electroplating solution in this step to ensure anisotropy of electroplating inside and outside the tank.

[0057] Step S1.7: Mechanically grind the protruding copper metal after electroplating; this step uses a 600-BLD04 grinding wheel to mechanically grind the metal.

[0058] Step S2: Prepare metal layers on both sides of a silicon substrate.

[0059] In step S2, this step specifically includes:

[0060] Step S2.1: Sputter a metal seed layer on the front side of the silicon substrate, wherein the copper layer in the sputtered metal seed layer is 300 nm thick;

[0061] Step S2.2: Spin-coat positive photoresist onto the formation seed layer and then photolithographically form a mask layer;

[0062] Step S2.3: Electroplating the top metal layer 104 and removing the resist and cleaning, using an ion beam to etch away the metal seed layer to form a complete top metal layer 104 structure. The electroplating thickness of the top metal layer 104 is 10 μm.

[0063] Step S2.4: Sputter a metal seed layer on the bottom of the silicon substrate and spin-coat a positive photoresist;

[0064] Step S2.5: Electroplating the bottom metal layer 105 and removing the adhesive is performed. The metal seed layer is etched away using an ion beam to form a complete bottom metal layer 105 structure. The electroplating thickness of the bottom metal layer 105 is 10 μm.

[0065] Step S3: After dicing the sample on the back side of the silicon substrate using a photolithography mask and dry etching, the sample is mounted on the waveguide stage.

[0066] Step S3.1: Spin-coat positive photoresist on the back side of a silicon substrate and develop to prepare a mask;

[0067] Step S3.2: Complete bulk silicon etching using dry etching to form silicon-based air cavity structure 103. The dry etching adopts Bosch deep silicon etching process.

[0068] Step S3.3: Remove residual adhesive using acetone solution;

[0069] Step S3.4: Dice the silicon substrate to complete the fabrication of the transition structure.

[0070] All dry etching processes involved in this invention are inductively coupled plasma (ICP) dry etching. Specifically, all dry etching methods used are reactive plasma etching, which utilizes plasma generated after gas glow discharge to perform anisotropic etching on the silicon substrate. The etching process employs alternating etching and protection steps. Fluorine-based reactive radicals are used to etch the silicon substrate, followed by fluorine-based gas passivation of the sidewalls. After isotropic etching, the passivation film on the longitudinal sidewalls, formed by gas bombardment, is not etched away in the next etching cycle. The fluorine-based reactive radical gas only etches the bottom of the etching trench. This repeated etching and passivation enhances the anisotropy of the dry etching process, resulting in a final structure with a tilt angle close to 90° and enabling the fabrication of high aspect ratio structures, ensuring the successful dry etching fabrication of subsequent structures such as TSV blind trenches.

[0071] The present invention also provides an apparatus, which is fabricated by the above-described three-dimensional silicon-based transition structure fabrication method based on a silicon-based air cavity structure.

[0072] The present invention will now be described in more detail.

[0073] This invention provides a method for fabricating a three-dimensional silicon-based transition structure based on a silicon-based air cavity structure. First, a TSV blind trench is etched on the front side of a silicon substrate, and a seed layer is sputtered onto the surface for blind trench electroplating. After the metal inside the trench is plated, it is mechanically ground smooth. Subsequently, the top and bottom metal patterns are completed, and the silicon-based air cavity structure is etched. By determining and implementing this scheme, the difficulty of integrating the cavity metal sidewalls into a silicon wafer is overcome, and the conversion from a grounded coplanar waveguide to a metal waveguide is achieved, providing an efficient and reliable transition solution for three-dimensional heterogeneous integration. In the process flow, the stability of the process effect is ensured by improving the photoresist spin coating process parameters and mask scheme.

[0074] The specific process steps are as follows:

[0075] (1) Spin-coating photoresist on the front side of the silicon wafer, baking, photolithography and development, and then etching the silicon substrate;

[0076] (2) Remove the photoresist, sputter the metal seed layer, and then cover the area with dry film photoresist to protect the structure outside the electroplating area;

[0077] (3) Perform blind trench electroplating on the silicon wafer, and then mechanically grind the front and back sides of the wafer.

[0078] (4) Sputter a metal seed layer on the top of the silicon wafer to complete the patterning of the top metal layer 104;

[0079] (5) Sputter a metal seed layer on the bottom of the silicon wafer to complete the patterning of the bottom metal layer 105;

[0080] (6) Photoresist is spin-coated on the back of the silicon substrate to complete the back silicon substrate etching and form a silicon-air cavity structure 103;

[0081] (7) The silicon-based wafer is diced to obtain a complete transition structure unit.

[0082] Reference Figure 1 and Figure 2 As shown, the method in this invention operates as follows:

[0083] (a) A 4-inch high-resistivity circular silicon wafer 101 with a thickness of 500µm and double-sided polished surface is used as the silicon substrate after cleaning, such as... Figure 2 As shown in (a).

[0084] (b) Spin-coating positive photoresist onto the front side of the silicon wafer and developing a blind trench pattern, such as... Figure 2 As shown in (b).

[0085] (c) Using photoresist as a mask, dry etching is used to perform deep silicon etching on the exposed silicon substrate to etch blind trenches, such as... Figure 2 As shown in (c).

[0086] (d) Use acetone solution to wash away the positive photoresist used as a mask, such as... Figure 2 As shown in (d).

[0087] (e) Sputter a Cr / Cu seed layer onto the etched tank, such as Figure 2 As shown in (e).

[0088] (f) Cover the surface of the structure with dry film photoresist, expose and develop to reveal the area to be electroplated, such as... Figure 2 As shown in (f).

[0089] (g) Perform TSV blind cell plating to form a metallized blind cell structure, such as Figure 2 As shown in (g).

[0090] (h) Using a DISCO-BG810 thinning machine and a 600-BLD04 grinding wheel, both sides of the silicon wafer are mechanically ground flat to prepare a metallized through-groove structure 102, such as... Figure 2 As shown in (h).

[0091] (i) A Cr / Cu seed layer with a thickness of 30 / 300 nm is sputtered onto the front side of a silicon wafer, such as... Figure 2 As shown in (i).

[0092] (j) A positive photoresist is spin-coated over the seed layer, and after photolithography and development, the top metal layer 104 pattern to be electroplated is obtained, as shown below. Figure 2 As shown in (j).

[0093] (k) Using the photoresist above the seed layer as a mask, electroplate the top metal layer 104, wash away the photoresist with acetone, and then use ion beam etching to cleanly etch the metal seed layer that was covered by the photoresist. Figure 2 As shown in (k).

[0094] (l) A Cr / Cu metal seed layer is sputtered on the back side of the silicon wafer, and a positive photoresist is spin-coated. After photolithography and development, the underlying metal layer pattern to be electroplated is obtained, such as... Figure 2 As shown in (l).

[0095] (m) Using the photoresist above the seed layer as a mask, electroplate the bottom metal layer 105. Remove the photoresist with acetone, and then use ion beam etching to cleanly etch the metal seed layer that was covered by the photoresist. Figure 2 As shown in (m).

[0096] (n) A positive photoresist is spin-coated over the bottom metal layer 105, and the rectangular area of ​​the back cavity structure is exposed and developed, as shown. Figure 2 As shown in (n).

[0097] (o) Using photoresist as a mask, dry etching is performed on the exposed silicon substrate. Once the target depth is reached, a silicon-air cavity structure, i.e., silicon-air back cavity 103, is formed on the back of the silicon wafer. Figure 2 As shown in (o).

[0098] (p) Clean the residual adhesive with acetone to form a complete three-dimensional silicon-based transition structure based on the silicon-based air cavity structure 103, such as Figure 2 As shown in (p).

[0099] (q) The silicon wafer is diced using a DISCO-DAD3650 dicing machine to obtain each transition structure unit, and then mounted on the metal waveguide stage 106 using laser drilling. Figure 2 As shown in (q).

[0100] This invention employs a mixed liquid containing an activity inhibitor, an accelerator, and a leveling agent in the electroplating solution, achieving a bottom-up electroplating effect during the electroplating process. This results in a structure where the plating within the tank is essentially solidified, while the surface plating is suppressed. The inhibitor, with its strong adsorption capacity, inhibits metal growth on the substrate surface at the copper atom surface; the accelerator accumulates at the bottom of the tank, increasing the metal plating speed in blind tanks with different aspect ratios; and the leveling agent suppresses metal bumps on the substrate surface caused by uneven current.

[0101] This invention provides a method and apparatus for fabricating a three-dimensional silicon-based interconnect structure based on a silicon-air cavity structure, solving the thickness limitation of the interconnect dielectric layer; it also addresses the edge cracking phenomenon caused by differences in the thermal expansion coefficients between different materials during processing, thus preventing the risk of breakage of the top-layer metal traces; and proposes a scheme for fabricating metallized through-slots on a silicon substrate, reducing interconnect losses and improving the diversity and reliability of wafer-level heterogeneous integration packaging processes by combining TSV blind trench fabrication with dry etching. This invention addresses the chip RF fan-out interconnect problem in silicon-based system-on-a-chip integration, introducing a silicon-air cavity on a silicon substrate to form a three-dimensional interconnect structure, replacing the traditional planar fan-out interconnect scheme, greatly reducing the overall size of the RF system and improving the degree of freedom and flexibility of interconnection.

[0102] Those skilled in the art will understand that, besides implementing the system and its various devices, modules, and units provided by this invention in the form of purely computer-readable program code, the same functions can be achieved entirely through logical programming of the method steps, making the system and its various devices, modules, and units of this invention function in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, the system and its various devices, modules, and units provided by this invention can be considered as a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; alternatively, the devices, modules, and units for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0103] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A method for processing a three-dimensional silicon-based transfer structure based on a silicon-air back cavity structure, comprising: Step S1: forming a TSV blind groove on the front side of a silicon-based substrate and metallizing; Step S2: preparing a metal layer on both sides of the silicon-based substrate; Step S3: using a photoetching mask and dry etching on the back side of the silicon-based substrate, completing sample dicing and mounting on a waveguide carrier; characterized in that the step S1 comprises: Step S1.1: spin-coating a positive photoresist on the front side of the wafer and developing to prepare a mask; Step S1.2: completing blind groove bulk silicon etching using dry etching, with an etching depth of 250 μm; Step S1.3: washing off the positive photoresist using an acetone solution; Step S1.4: sputtering a metal seed layer on the front side of the silicon-based substrate; Step S1.5: covering a dry film photoresist on the front side of the silicon-based substrate to protect the area outside the etching structure from being affected by electroplating; Step S1.6: blind groove electroplating, i.e. electroplating and plating the deep groove formed after bulk silicon etching; Step S1.7: mechanically grinding the protruding metal copper after electroplating.

2. The method of claim 1, wherein: In the sputtering process of step S1.4, a layer of metal chromium is first sputtered.

3. The method of claim 1 wherein: In step S1.6, a surface metal atom activity inhibitor is added to the electroplating solution.

4. The method of claim 1 wherein: In step S1.7, a 600-BLD04 type grinding wheel is used for metal mechanical grinding.

5. The method of processing according to any one of claims 1-4, wherein: The step S2 comprises: Step S2.1: sputtering a metal seed layer on the front side of the silicon-based substrate; Step S2.2: spin-coating a positive photoresist on the top seed layer and photoetching to form a mask layer; Step S2.3: electroplating and removing the photoresist for cleaning of the top metal layer, using ion beam etching to remove the metal seed layer to form a complete top metal layer structure; Step S2.4: sputtering a metal seed layer on the bottom of the silicon-based substrate and spin-coating a positive photoresist; Step S2.5: electroplating and removing the photoresist for cleaning of the bottom metal layer, using ion beam etching to remove the metal seed layer to form a complete bottom metal layer structure.

6. The method of claim 5, wherein: In step S2.1, the copper layer in the sputtered metal seed layer has a thickness of 300 nm; In step S2.3, the top metal layer has an electroplating thickness of 10 um; In step S2.5, the bottom metal layer has an electroplating thickness of 10 um.

7. The method of claim 5, wherein: The step S3 comprises: Step S3.1: spin-coating a positive photoresist on the back side of the silicon-based substrate and developing to prepare a mask; Step S3.2: completing bulk silicon etching using dry etching to form a silicon-air back cavity structure; Step S3.3: removing the residual photoresist using an acetone solution; Step S3.4: dicing the silicon-based substrate to complete the transfer structure fabrication.

8. The method of claim 7, wherein: The dry etching is all inductive coupling plasma dry etching. 9.An apparatus prepared by the method for processing a three-dimensional silicon-based transfer structure based on a silicon-air back cavity structure according to any one of claims 1-8.

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