Multi-step formation of resistive random access memory (RERAM)

Abstract

A formation process needs to be performed prior to the first use of a resistive random access memory (ReRAM). During this process, the filament of each ReRAM cell is set from an unknown state or a high resistance state (HRS) to a low resistance state (LRS). In order to prevent adjacent selector devices of already formed LRSs from being stressed, a multi-step formation process is provided. The process first applies a high voltage at a low current, then reduces the high voltage to a lower voltage, and increases the current to a higher current. In the last step of forming, a low voltage and a high current are applied. Any selector device is not subjected to stress at any time due to the application of a drain-to-source voltage drop that exceeds the selector device limitation. The drain-to-source voltage drop may be determined by the current flowing through the selector device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to resistive random-access memory (ReRAM) cells, and more particularly to improving the formation of ReRAM arrays. BACKGROUND

[0002] In the case of a resistive random-access memory (ReRAM) device, the term "formation" can be used in two unrelated ways. The first is the formation of the actual ReRAM using, for example, semiconductor process steps. The second use of the term "formation", the one discussed herein, refers to the process of applying a voltage to the ReRAM cells of a ReRAM device to initialize, and generate a conductive filament responsible for the resistance switching behavior.

[0003] In normal operation, a ReRAM cell can be switched between a low resistance state (LRS) and a high resistance state (HRS). The formation process brings the ReRAM cell from an uninitialized or HRS to a conductive state, often referred to as a "formed" state or a "set" state. Once the formation process is complete, the ReRAM cell can be programmed and read by applying appropriate voltage levels to switch the ReRAM cell between the LRS and HRS states. The formation process is a one-time initialization step performed during production or device initialization, and is not required for normal operation during the lifetime of the ReRAM cell.

[0004] The voltage formation process is typically performed by applying a voltage pulse of a specific amplitude and duration to the ReRAM device. The voltage pulse is applied across the electrode-insulator-electrode stack, which results in the formation of a conductive filament within the insulator material. In this regard, consider Figure 1 FIG. 1, which shows a portion of a ReRAM array 100 having columns and rows of ReRAM cells. For example, a first ReRAM cell includes a selector gate 101, the gate of which is connected to a word line W m-1 161, where "m" is an integer equal to or greater than "2", the source of which is connected to a source line SL n-1 181, where "n" is an integer equal to or greater than "2", the drain of which is connected to a first terminal of a filament of a resistive element 111. A second terminal of the resistive element 111 is connected to a bit line BL n-1 171. Similarly, Figure 1 Other ReRAM cells shown in FIG. 1 are also connected to form the ReRAM array 100. It should be noted that the smallest size of the array is a 2x2 array when m≥2 and n≥2.

[0005] To form the filament 132, it is necessary to have a high voltage (e.g., in the range of 2.5-2.8V) on the BL n 172, a low voltage (e.g., 0V) on the SL n 182, and a high voltage (e.g., in the range of 1.2-1.4V) on the WL m 162. The selection of the particular BL voltage and the particular WL voltage depends on process characteristics and transistor characteristics. Thus, assuming that the appropriate formation steps occur, the filament 132 will be formed, as explained further below. It will be appreciated that under such conditions, the selector gate 122 is turned on, and thus presents a low resistance, whereas as noted above, in the initial state of the filament 132, it is in a high resistance state. For this reason, the majority of the voltage will be applied across the filament 132, while the source-to-drain voltage applied across the selector gate 122 is low.

[0006] The voltage formation process can be performed using various techniques, such as a constant voltage stress (CVS) or current compliance (CC) method, among others. In the CVS method, a constant voltage is applied to the device until a conductive filament is formed, while in the CC method, a current limit is set, and the voltage is allowed to vary until a conductive filament is formed. In typical applications, a current limiter is provided on the source line (SL) for limiting the amount of current that can flow through the selector transistor.

[0007] The voltage formation process is a critical step in the manufacturing of ReRAM devices, which defines the initial resistance state of the device and affects the overall performance of the device. By adjusting the parameters of the voltage pulse, such as amplitude, duration, and polarity, as well as temperature and humidity conditions during the process, among others, the voltage formation process can be optimized. Thus, the voltage formation process is a critical step in the manufacturing of ReRAM devices, and its optimization has a significant impact on the performance and reliability of the device.

[0008] However, the existing solutions also have drawbacks that need to be overcome. In particular, as a result of the formation of the ReRAM cell described above, the impact on other devices needs to be considered. For this problem, it will be assumed that the filament 132 is being initialized. Thus, the voltage applied on the WL m 162 is in the range of 1.2-1.4V, the voltage applied on the BL n 172 is 2.65V, and the voltage applied on the SL n 182 is 0V. Furthermore, in order not to affect any other filament, the W m-1 161 voltage is 0V, the W m+1 voltage is 0V, and the BL n-1171 Voltage is 0V, SL n-1 Voltage is 0V, BL n+1 173 Voltage is 0V, SL n+1 Voltage is 0V. For this example, assume that the adjacent filament 131 is in HRS and the other adjacent filament 133 is in LRS. It should also be noted that each selector device has a maximum drain to source limit V f (for example, in the range of 1.5V - 1.8V). The particular maximum drain to source voltage (V f ) depends on process characteristics and transistor characteristics, and can be controlled by temperature or by adjusting doping levels. Regardless, this V ds voltage drop can cause stress to the selector device and adversely affect the overall performance of the device.

[0009] One of ordinary skill in the art will readily understand that the voltage ranges discussed herein are for illustrative purposes only and do not limit the scope of the disclosed embodiments. The voltage ranges can depend on the production process, on the selector transistor characteristics, on the filament resistance, and other parameters that need to be considered when applying a particular voltage. Regardless, the principles described herein for forming ReRAM filaments are key to the present disclosure described herein.

[0010] For example, in the case of filament 131, when the selection device 121 is not selected, filament 131 is in HRS, then the resistance of the selection device 121 is high. Since the resistance of filament 131 is also high, the voltage drop between BL n 172 and the drain of the selection device 121 is divided between the filament 131 and the selection device, so the selection device is not stressed. However, the case of selection device 123 is different, since filament 133 is in LRS. Now, the resistance of filament 133 is significantly lower than the drain to source resistance of selector device 122. Therefore, most of the voltage applied to BL n 172 falls between the drain and source of selector device 122, stressing the device and potentially degrading the overall performance of the ReRAM array. It should be understood that this stress to the device can occur multiple times as other adjacent filaments are formed, and further degrade the performance of the ReRAM device.

[0011] Therefore, it would be advantageous to provide a solution that overcomes the above-mentioned drawbacks. SUMMARY

[0012] The following is a summary of certain example embodiments of the present disclosure. This summary is provided to give the reader a brief overview of the embodiments and does not completely summarize the scope of the disclosure. This summary is not an extensive overview of all contemplated embodiments, and is not intended to identify key or critical elements of all embodiments or to delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later. For convenience, the term "some embodiments" or "certain embodiments" can be used herein to refer to a single embodiment or multiple embodiments of the present disclosure.

[0013] Certain embodiments disclosed herein include a method for forming a resistive random access memory (ReRAM) device. The method includes: at a first step, forming at least one ReRAM cell of the ReRAM device by applying a first forming voltage to a bit line of each of the at least one ReRAM cell and passing a first forming current through a selector device of each of the at least one ReRAM cell; repeating the forming of the at least one ReRAM cell until all of the at least one ReRAM cell of the ReRAM device have been formed at the first step; at a second step, forming at least one ReRAM cell of the ReRAM device by applying a second forming voltage to a bit line of each of the at least one ReRAM cell and passing a second forming current through a selector device of each of the at least one ReRAM cell; repeating the forming of the at least one ReRAM cell until all of the at least one ReRAM cell of the ReRAM device have been formed at the second step; wherein the ReRAM device includes a ReRAM cell array including the at least one ReRAM cell, wherein the ReRAM cell array is arranged as rows and columns of ReRAM cells; wherein each ReRAM cell of the ReRAM device includes a resistive filament having a terminal connected to a bit line and a selector device having a drain connected to a second terminal of the resistive filament, the selector device having a source connected to a source line and a gate connected to a word line; wherein, in forming the ReRAM device, the resistive filament is initialized from an un-initialized state to a low resistance state (LRS); wherein the first forming voltage is higher than the second forming voltage; and wherein the first forming current is lower than the second forming current.

[0014] Certain embodiments disclosed herein also include a resistive random access memory (ReRAM) device configured for stress-free initialization. The ReRAM device includes: a ReRAM array including a plurality of ReRAM cells arranged in rows and columns, each ReRAM cell of the plurality of ReRAM cells including a resistive filament having a terminal connected to a bit line, and a selector device having a drain connected to a second terminal of the resistive filament, the selector device having a source connected to a source line and a gate connected to a word line; a bit line / source line decoder communicatively connected to a plurality of rows of the ReRAM array; a word line decoder communicatively connected to a plurality of columns of the ReRAM array; and, control logic communicatively connected to the bit line / source line decoder and the word line decoder, wherein the control logic is configured to at least: in a first step, form at least one ReRAM cell of the ReRAM device by applying a first forming voltage to the bit line of each of the at least one ReRAM cell and causing a first forming current to pass through the selector device of each of the at least one ReRAM cell; repeat forming the at least one ReRAM cell until all of the at least one ReRAM cell of the ReRAM device have been formed in the first step; in a second step, form at least one ReRAM cell of the ReRAM device by applying a second forming voltage to the bit line of each of the at least one ReRAM cell and causing a second forming current to pass through the selector device of each of the at least one ReRAM cell; and repeat forming the at least one ReRAM cell until all of the at least one ReRAM cell of the ReRAM device have been formed in the second step; wherein, in performing the method for forming the ReRAM device, the resistive filament is initialized from an un-initialized state to a low resistance state (LRS); wherein the first forming voltage is higher than the second forming voltage; and wherein the first forming current is lower than the second forming current. BRIEF DESCRIPTION OF DRAWINGS

[0015] The subject matter disclosed herein is particularly pointed out and distinctly claimed in the claims of the specification. The foregoing and other purposes, features, and advantages of the disclosed embodiments will be apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0016] Figure 1 Part of a resistive random access memory (ReRAM) initialized using a conventional forming process.

[0017] Figure 2 Flowchart of two-step initialization of a cell of a ReRAM according to the first embodiment.

[0018] Figure 3ASchematic diagram of a portion of a ReRAM array in a first step of initialization for a two-step formation embodiment of a ReRAM device.

[0019] Figure 3B Schematic diagram of a portion of a ReRAM array in a second step of initialization for a two-step formation embodiment of a ReRAM device.

[0020] Figure 4A Schematic diagram of a ReRAM device according to an embodiment.

[0021] Figure 4B Schematic diagram of control logic for a ReRAM device according to an embodiment.

[0022] Figure 5 Method for multi-step initialization of a ReRAM cell according to a second embodiment.

[0023] Figure 6A Graph of formation voltage versus formation current for a ReRAM array according to an embodiment.

[0024] Figure 6B Formation voltage ramp graph for a ReRAM array according to an embodiment. DETAILED DESCRIPTION

[0025] It is important to note that the embodiments disclosed herein are merely examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the application do not necessarily limit any of the various claims. Additionally, some statements can apply to some inventive features but not to others. In general, unless otherwise indicated herein, aspects of a claim can be combined with aspects of another claim. In the drawings, like reference numerals refer to like parts through several views.

[0026] Various disclosed embodiments provide methods and systems for initializing resistive random access memory (ReRAM) through multi-step formation. A formation process is required before the ReRAM is used for the first time. During this process, the filament of each ReRAM cell is set from an unknown or high resistance state (HRS) to a low resistance state (LRS). Typically, the resistance is higher than the HRS before formation. To prevent adjacent selector devices with already formed LRS from being stressed, a multi-step formation process is provided. This process first applies a high voltage at a low current, then reduces the high voltage to a lower voltage and increases the current to a higher current. In the final step of formation, a low voltage and a high current are applied. According to the disclosed embodiments, at any time, no selector device will be stressed due to the application of a drain-to-source voltage drop exceeding the selector device's limits. The drain-to-source voltage drop can be determined by the current flowing through the selector device.

[0027] Figure 2 An example flowchart 200 depicts a two-step initialization of a ReRAM cell according to a first embodiment. Initialization is also referred to herein as formation; that is, the process brings the ReRAM cell from an uninitialized state or HRS to a conducting state, commonly referred to as a "formed" state or a "set" state, i.e., a low resistance state (LRS). This method is designed to perform the formation of the ReRAM device cell in the initial stage before using the ReRAM device and to ensure that the selection device of the ReRAM cell is not subjected to a voltage V exceeding its maximum permissible voltage drop between the drain and source of the selector device due to the selector device being at a voltage V. ds And it is subjected to stress.

[0028] In S210, the next ReRAM cell to be formed in the first step is identified. ReRAM arrays typically have hundreds, thousands, tens of thousands, or more such cells, a portion of which are... Figure 1 As shown in, and further in Figure 3A and Figure 3B As shown in the figure. It should be noted that formation is performed on each ReRAM cell. In the embodiments, multiple cells formed in parallel can be identified without departing from the scope of the disclosed embodiments.

[0029] In S220, multiple voltage transitions (hereinafter) are implemented. Figure 6B (More details provided) An applied voltage is applied to the bit line of the identified ReRAM cell until a predetermined first voltage value is reached. This first voltage value is lower than the maximum V0 of any selector device of the ReRAM. ds See also Figure 3A An example implementation. The maximum current is controlled by providing a voltage value at the word line of the selected ReRAM cell corresponding to the first current that can flow through the selector device.

[0030] At S230, it is checked whether all cells of the ReRAM identified in the first step have been subjected to the first voltage and the first current of the first step of formation, and if so, execution continues to S240; otherwise, execution continues to S210.

[0031] At S240, the next ReRAM cell to be formed in the second step is identified. In embodiments, multiple cells can be identified and formed in parallel without departing from the scope of the disclosed embodiments.

[0032] At S250, a plurality of voltage ramps are applied to the bit line of the identified ReRAM cell until a predetermined second voltage value is reached. The second voltage value is lower than the first voltage of any selector device of the ReRAM. See Figure 3B for an example implementation. The maximum current is controlled by providing a voltage value at the word line of the selected ReRAM cell corresponding to the second current that can flow through the selector. In embodiments, the second current is higher than the first current. The plurality of voltage ramps will be discussed in further detail in Figure 6B .

[0033] At S260, it is checked whether all cells of the ReRAM identified in the second step have been subjected to the second voltage and the second current of the second step of formation, and if so, execution terminates; otherwise, execution continues to S240.

[0034] Figure 3A An example schematic of a portion of the ReRAM array 300A for the first step of initialization according to embodiments of two-step formation of ReRAM devices. For example, it has been shown in Figure 2 that the first step comprises the steps of S210 (identify) and S220 (form). The ReRAM array 300A shown is the same array arrangement as shown in Figure 1 , but formed using the method described in Figure 2 . The ReRAM device formed in the example embodiment is a device comprising a filament 132 and a selector device 122. The ReRAM cell is connected to a WL m 162 (WL - word line), a BL n 172 (BL - bit line), and a SL n 182 (SL - source line).

[0035] In step 1 of the method 200, appropriate voltages are applied, for example according to Figure 3A implementation: a voltage of 2 V is applied on the BL n 172; a voltage of 0 V is applied on the SL n 182; and a voltage of 0 V is applied on the WL mA voltage of 0.9V is applied to 162. It should be noted that these voltages can vary depending on the design details of the ReRAM array and the manufacturing process used. Therefore, the voltage on unselected selectors (e.g., selector device 123, assuming it is an already formed filament 133 (because it has previously undergone the same process)) is reduced compared to the voltage applied according to conventional methods, such as... Figure 1 As shown.

[0036] Figure 3B This is an example schematic diagram of a portion of the ReRAM array 300B in the second step of initialization according to an embodiment of two-step formation of a ReRAM device. In step 2 of method 200, for example according to... Figure 3B Implement, apply appropriate voltage: in BL n Apply a voltage in the range of 1.5V-1.8V to 172; in SL n A voltage of 0V is applied to 182; and in WL m A voltage in the range of 1.2V-1.4V is applied to 162. It should be noted that these voltages can vary depending on the design details of the ReRAM array and the manufacturing process used. According to the disclosed embodiments, higher WL... m The voltage of 162 causes selector device 122 to have a lower resistance, thus enabling a higher current. Therefore, the voltage on an unselected selector (e.g., selector device 123, assuming it is the already formed filament 133 (because it has previously undergone the same process)) is reduced compared to the voltage applied according to conventional methods, such as... Figure 1 As shown. Therefore, the two-step approach overcomes the shortcomings of existing solutions, which generate stress on adjacent unselected selector devices by applying a high voltage. It should be noted that while this paper shows a specific example of current limiting, other current limiting methods can be implemented both inside and outside the ReRAM array (i.e., as part of the ReRAM device) using, for example, current limiters.

[0037] Figure 4A This is an example ReRAM 400 with control logic (CNTLlogic) 440 having a control initialization process according to an embodiment. ReRAM 400 includes a ReRAM array 410 having, for example, as shown... Figure 3A and Figure 3BThe illustrated ReRAM cells are connected in rows and columns in one or more ways known in the art. To set, reset, program, clear, or read any ReRAM cell, a word-line (WL) decoder 420 and a bit-line (BL) / source-line (SL) decoder 430 are used under the control of control logic 440. Control logic 440 is communicatively connected to WL decoder 420 through interface 441. WL decoder 420 is communicatively connected to ReRAM array 410 through a plurality of WLs 422-WL-m, where "m" is an integer equal to or greater than "2". Control logic 440 is further communicatively connected to BL / SL decoder 430 through interface 442. BL / SL decoder 430 is communicatively connected to ReRAM array 410 through BLs 432-BL-n and SLs 432-SL-n, where "n" is an integer equal to or greater than "2".

[0038] Read and write operations of ReRAM 400 are performed using data interface 433 provided by BL / SL decoder 430. Control logic 440 is configured to provide the necessary control signals, and in some embodiments, the necessary voltages, to perform the operations described herein. In an embodiment, BL / SL decoder 430 can further include one or more current limiters (not shown) to limit the maximum current through any selected device of the ReRAM cells. In an embodiment, a single current limiter is used and switched between SLs as needed. In another embodiment, a group of SLs share a single current limiter that is switched to provide the particular SL that is limited. In yet another embodiment, a current limiter is provided for each SL.

[0039] Figure 4B is Figure 4AAn example control logic 440 of the ReRAM 400 is configured to perform an initialization process according to embodiments. The processing circuit 443 is communicatively connected to a memory 444 by, for example but not limited to, a bus 447. The memory 444 can contain portions dedicated to code 445 stored in the memory 444. When the code contained in the code memory 445 is executed by the processing circuit 443, the ReRAM 400 is configured to perform as described herein. The memory 444 can include volatile memory, such as but not limited to random access memory (RAM) and the like. The memory 444 can include non-volatile memory (NVM), such as but not limited to flash memory, read only memory (ROM), and other types of NVM. The memory can include any combination of volatile and non-volatile memories. An input / output (IO) interface 446 is communicatively connected to the bus 447. The IO interface 446 provides control to the WL decoder 420 using an interface 441 and to the BL / SL decoder 430 using an interface 442. Additional interfaces 448 can provide, for example but not limited to, external communications to receive various command signals for the ReRAM 400 to control its operation, as well as to provide output signals that can be needed.

[0040] The processing circuit 443 can be implemented as one or more hardware logic components and circuits. Illustrative types of hardware logic components that can be used include, but are not limited to, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip systems (SOCs), general-purpose microprocessors, microcontrollers, and digital signal processors (DSPs), whether programmable or not, or any other hardware logic components that can perform calculations or other manipulations of information. It should further be understood that while the control circuit 440 is shown as operating using the processing circuit 443 with instructions stored in the memory 444, other embodiments of the control circuit 440 are possible and specifically include as embodiments of the present invention. For example, and without limitation, the control circuit 440 can include a combination of digital and analog circuitry (not shown) that provides control signals at the interface 441 and the interface 442 that configure the initialization process of the ReRAM 400 to achieve the same overall results. The control circuit 440 is configured to perform the ReRAM initialization operations described in greater detail herein.

[0041] In embodiments, Figure 2 and Figure 5 The methods described in Figure 2 and Figure 5 can be stored as a plurality of instructions in the code memory 445. For example, the method 200 or the method 500 can be executed by the processing circuit 443 when such instructions are executed, resulting in the two-step formation or the multi-step formation as described herein. In another embodiment, the control logic 440 is implemented entirely in hardware or a combination of hardware and software that, when operated, performs the acts described in the method 200 and the method 500.

[0042] Figure 5An example flowchart 500 depicting a multi-step initialization of a cell of a ReRAM according to a second embodiment is depicted. Initialization is also referred to herein as formation, i.e. the process brings a ReRAM cell from an un-initialized state or HRS to a conductive state, i.e. a "formed" or "set" state, i.e. a low resistance state (LRS). The method is designed to perform formation of cells of a ReRAM device at an initial stage before use of the ReRAM device, and to ensure that a selected device of ReRAM cells does not suffer from stress due to the selector device being at a voltage exceeding the maximum allowed voltage drop across the drain and source of the selector device ds Depending on the case, the method can perform multiple steps, e.g. three, four or more steps.

[0043] At S510, a next ReRAM cell to be formed in the first step is identified. A ReRAM array typically has hundreds, thousands, tens of thousands or more such cells, where a portion of the cells are to be formed in the first step. Figure 1 is shown in Figure 3A and further shown in Figure 3B It should be noted that formation is performed on each ReRAM cell. In an embodiment, multiple cells can be identified for parallel formation without departing from the scope of the disclosed embodiments.

[0044] At S520, a plurality of voltage ramps are applied to the bit line of the identified ReRAM cell until a predetermined first voltage value is reached. The first voltage value is lower than the maximum V ds The maximum current is controlled by providing a voltage value at the word line of the selected ReRAM cell corresponding to the first current that can flow through the selector. The plurality of voltage ramps are discussed in further detail in Figure 6B .

[0045] At S530, it is checked whether all cells of the ReRAM have been subjected to the first voltage and the first current of the i-th step of formation, and if so, execution continues into S540; otherwise, execution continues into S510. It should be noted that the maximum value of "i" is the maximum number of steps of the multi-step method. As an example, Figure 6A four steps are shown and discussed separately herein.

[0046] At S540, the first voltage is decreased by a first voltage increment and the first current is increased by a first current increment value. It should be understood that while these values are shown herein as currents, control can be performed by applying voltages, e.g. as described with respect to Figure 3A and Figure 3B After S540, according to the principles of the embodiments described herein, when the current is increased, the subsequently applied first voltage will be lower than the previous cycle.

[0047] At S550, it is checked whether the first voltage or the first current exceeds their respective limits. That is, the check determines whether the first voltage is reduced below the minimum voltage to be applied, and whether the current is increased above the maximum current allowed. If neither of these exceedances occurs, execution continues into S510; otherwise, execution terminates. After the operation of S510 is continued, the next step (or loop) of execution is formed. For example, once all ReRAM cells of the first step are formed, S510 to S550 of the second step is performed on the same ReRAM cells. In an embodiment, the method from S510 to S550 is repeated i times for the i-th step formation. Figure 5

[0048] Figure 6A is an example plot 600A of the formation voltage and the formation current of a ReRAM array according to an example embodiment. The vertical axis 610 represents the applied formation voltage. The horizontal axis represents the formation current. The formation voltage values and the formation current values shown can change depending on the technology node used (i.e., the kind of semiconductor process used to produce the ReRAM device). In an embodiment, the multi-step formation has four steps labeled 630-1, 630-2, 630-3, and 630-4. Thus, in step 630-1, a high maximum voltage (e.g., 2.0 V) is used, and a low formation current (e.g., 20 µA) is used. In the subsequent step 630-2, a lower formation voltage (e.g., 1.9 V) is used, with a higher formation current (e.g., 50 µA). This process of reducing the formation voltage and increasing the formation current is done step by step (e.g., 630-1 to 630-4) until the last step 630-4, where the lowest formation voltage (e.g., in the range of 1.5 V - 1.8 V) is used, with the highest formation current (e.g., 200 µA). It should be understood that the curve of the formation voltage and the formation current represented by the points 620-i, where “i” is an integer equal to or greater than “2”, can be linear, piecewise linear, and non-linear, etc., as long as the points monotonically decrease on the vertical axis as they increase along the horizontal axis.

[0049] It should be noted that in the case of a two-step formation, there are only 630-1 and 630-4, as they represent the first step and the second step (the last step, see Figure 2 ), respectively. That is, in the first step, the value of the formation voltage will be initially set to 2.0 V at a current of 20 µA, and in the second step (the last step), the formation voltage will be dropped to a voltage in the range of 1.5 V - 1.8 V, and the formation current is increased to 200 µA. In an embodiment, it can involve the adjustment of the programming current at the i-th step i to control the formation voltage of the BL of the i+1-th step, such that the formation voltage is below the voltage limit of the selector device. In other words, the bit line voltage V bl is equal to V 1T ​+V drop-reram where V 1T < V limit and V reram is a function of R reram , and thus a function of the programming current of the previous step.

[0050] Figure 6B is an example plot 600B of the formation voltage ramp 650 for a ReRAM array according to an embodiment. This is due to the fact that the maximum formation voltage at each step is not applied immediately, but rather the formation voltage is increased in steps until the maximum desired voltage for a particular step is reached. Plot 600B has a vertical axis 610 representing the formation voltage, while the horizontal axis 640 represents time. V pmax is the maximum voltage applied at each step. For example, at step 630-1, V pmax = 2.0 V, while at step 630-4, V pmax = 1.5 V. Each voltage increase is held for a period of time before the next voltage increase is made. While the value of each voltage increase can be the same, this depiction is for illustrative purposes and is not limiting of the scope of the disclosed embodiments, and the value of each voltage increase can be different. It should also be noted that the number of formation voltage increases shown for ramp 650 (3 in this example) is merely an example and should not be considered limiting of the disclosed embodiments.

[0051] All examples and conditional language recited herein are intended to be construed to cover all equivalents falling within the spirit and scope of the disclosed embodiments, actual filed scope being indicated by the appended claims. Furthermore, the foregoing description of the disclosed embodiments is by way of example only, and other embodiments, and modifications thereto, will be apparent to those skilled in the art without departing from the spirit of the disclosed embodiments, the scope of which is limited by the appended claims.

[0052] It should be understood that any reference to an element herein using a designation such as "first," "second," and so forth does not generally limit the quantity or order of those elements. Rather, these designations are used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must precede the second element. Also, unless otherwise specified, a set of elements comprises one or more elements.

[0053] As used herein, the phrase "at least one," followed by a listing of items, means that any of the listed items can be used individually, or any combination of two or more of the listed items can be used. For example, if a system is described as including "at least one of A, B, and C," the system can include A alone; B alone; C alone; 2A; 2B; 2C; 3A; an A and a B; an A and a C; a B and a C; A, B, and C; 2A and C; A, 3B, and 2C; and the like.

Claims

1. A method of forming a resistive random access memory (ReRAM) device, the method comprising: forming, in a first step, at least one ReRAM cell of the ReRAM device by applying a first forming voltage to a bit line of each of the at least one ReRAM cell and passing a first forming current through a selector device of each of the at least one ReRAM cell; repeating the forming of the at least one ReRAM cell until all of the at least one ReRAM cell of the ReRAM device have been formed in the first step; forming, in a second step, at least one ReRAM cell of the ReRAM device by applying a second forming voltage to a bit line of each of the at least one ReRAM cell and passing a second forming current through a selector device of each of the at least one ReRAM cell; repeating the forming of the at least one ReRAM cell until all of the at least one ReRAM cell of the ReRAM device have been formed in the second step; wherein the ReRAM device comprises an array of ReRAM cells including the at least one ReRAM cell, wherein the array of ReRAM cells is arranged in rows and columns of the ReRAM cells; wherein each ReRAM cell of the ReRAM device comprises a resistive filament having a terminal connected to a bit line and the selector device having a drain connected to a second terminal of the resistive filament, the selector device having a source connected to a source line and a gate connected to a word line; wherein, in forming the ReRAM device, the resistive filament is initialized from an un-initialized state to a low resistance state (LRS); wherein the first forming voltage is higher than the second forming voltage; and wherein the first forming current is lower than the second forming current.

2. The method of claim 1, wherein, determining a first current by applying a third voltage on a word line of each of the at least one ReRAM cell.

3. The method of claim 1, wherein, the first current is limited by a current limiter connected to the source line.

4. The method of claim 1, wherein, determining a second current by applying a third voltage on a word line of each of the at least one ReRAM cell.

5. The method of claim 1, wherein, the first current is limited by a current limiter connected to the source line.

6. The method of claim 1, further comprising: ramping the first forming voltage from a first initial voltage to a first target voltage; and, ramping the second forming voltage from a second initial voltage to a second target voltage.

7. The method of claim 6, further comprising: determining the first target voltage to be a voltage value: which is a voltage between the drain and the source of the selector device of each of the ReRAM cells of the ReRAM array, and is equal to or lower than a predetermined maximum stress voltage of the selector device.

8. The method of claim 1, further comprising: ​ a third step performed after the repeating of the first step, forming at least one ReRAM cell of the ReRAM device by applying a third forming voltage to a bit line of each of the at least one ReRAM cell and passing a third forming current through a selector device of each of the at least one ReRAM cell; repeating the forming of the at least one ReRAM cell until all of the at least one ReRAM cell of the ReRAM device have been formed at the third step; wherein the third forming voltage is higher than the second forming voltage and lower than the first forming voltage; and wherein the third forming current is lower than the second forming current and higher than the first forming current.

9. A resistive random access memory (ReRAM) device configured for stress-free initialization, the ReRAM device comprising: a ReRAM array comprising a plurality of ReRAM cells arranged in rows and columns, each of the plurality of ReRAM cells comprising a resistive filament having a terminal connected to a bit line and a selector device having a drain connected to a second terminal of the resistive filament, the selector device having a source connected to a source line and a gate connected to a word line; a bit line / source line decoder communicatively connected to a plurality of rows of the ReRAM array; a word line decoder communicatively connected to a plurality of columns of the ReRAM array; and control logic communicatively connected to the bit line / source line decoder and the word line decoder, wherein the control logic is configured to at least: at a first step, form at least one ReRAM cell of the ReRAM device by applying a first forming voltage to a bit line of each of the at least one ReRAM cell and passing a first forming current through a selector device of each of the at least one ReRAM cell; repeat the forming of the at least one ReRAM cell until all of the at least one ReRAM cell of the ReRAM device have been formed at the first step; at a second step, form at least one ReRAM cell of the ReRAM device by applying a second forming voltage to a bit line of each of the at least one ReRAM cell and passing a second forming current through a selector device of each of the at least one ReRAM cell; and repeat the forming of the at least one ReRAM cell until all of the at least one ReRAM cell of the ReRAM device have been formed at the second step; wherein, in performing the method for forming a ReRAM device, the resistive filament is initialized from an un-initialized state to a low resistance state (LRS); wherein the first forming voltage is higher than the second forming voltage; and wherein the first forming current is lower than the second forming current.

9. A resistive random access memory (ReRAM) device configured for stress-free initialization, the ReRAM device comprising: a ReRAM array comprising a plurality of ReRAM cells arranged in rows and columns, each of the plurality of ReRAM cells comprising a resistive filament having a terminal connected to a bit line and a selector device having a drain connected to a second terminal of the resistive filament, the selector device having a source connected to a source line and a gate connected to a word line; a bit line / source line decoder communicatively connected to a plurality of rows of the ReRAM array; a word line decoder communicatively connected to a plurality of columns of the ReRAM array; and control logic communicatively connected to the bit line / source line decoder and the word line decoder, wherein the control logic is configured to at least: at a first step, form at least one ReRAM cell of the ReRAM device by applying a first forming voltage to a bit line of each of the at least one ReRAM cell and passing a first forming current through a selector device of each of the at least one ReRAM cell; repeat the forming of the at least one ReRAM cell until all of the at least one ReRAM cell of the ReRAM device have been formed at the first step; at a second step, form at least one ReRAM cell of the ReRAM device by applying a second forming voltage to a bit line of each of the at least one ReRAM cell and passing a second forming current through a selector device of each of the at least one ReRAM cell; and repeat the forming of the at least one ReRAM cell until all of the at least one ReRAM cell of the ReRAM device have been formed at the second step; wherein, in performing the method for forming a ReRAM device, the resistive filament is initialized from an un-initialized state to a low resistance state (LRS); wherein the first forming voltage is higher than the second forming voltage; and wherein the first forming current is lower than the second forming current.

10. The ReRAM device of claim 9, wherein, determining a first current by applying a third voltage on a word line of each ReRAM cell of the at least one ReRAM cell.

11. The ReRAM device of claim 9, wherein, The first current is limited by a current limiter connected to the source line.

12. The ReRAM device of claim 9, wherein, determining a second current by applying a third voltage on a word line of each ReRAM cell of the one or more ReRAM cells.

13. The ReRAM device of claim 9, wherein, The second current is limited by a current limiter connected to the source line.

14. The ReRAM device of claim 9, wherein, The control logic is further configured to: ramp the first forming voltage from a first initial voltage to a first target voltage; and ramp the second forming voltage from a second initial voltage to a second target voltage.

15. The ReRAM device of claim 14, wherein, The control logic is further configured to determine the first target voltage as a voltage value that is between a drain and a source of the selector device of each ReRAM cell of the at least one ReRAM cell of the ReRAM array and is equal to or lower than a predetermined maximum stress voltage of the selector device.

16. The ReRAM device of claim 9, wherein, The control logic is further configured to perform, after the repeating of the first step is completed, a third step of forming at least one ReRAM cell of the ReRAM device by applying a third forming voltage to a bit line of each ReRAM cell of the at least one ReRAM cell and causing a third forming current to pass through a selector device of each ReRAM cell of the at least one ReRAM cell; repeating the forming of the at least one ReRAM cell until all ReRAM cells of the ReRAM device have been formed in the third step; wherein the third forming voltage is higher than the second forming voltage and lower than the first forming voltage; and wherein the third forming current is lower than the second forming current and higher than the first forming current.

17. The ReRAM device of claim 9, wherein, The control logic comprises at least one of: a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system on a chip (SOC), a general-purpose microprocessor, a microcontroller, and a digital signal processor (DSP).

18. The ReRAM device of claim 9, further comprising: a memory communicatively connected to the control logic for storing instructions executed by the control logic.

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