A signal processing device, deserializer, chip and electronic device

Abstract

The application discloses a signal processing device, a deserializer, a chip and electronic equipment, wherein the device comprises a first inverter, which is used for outputting an inverted signal of a clock signal; a first shift register circuit, which is used for obtaining even bit signals of a serial signal based on the clock signal and performing shift processing to output N first serial signals; a second shift register circuit, which is used for obtaining odd bit signals of the serial signal based on the inverted signal of the clock signal and performing shift processing to output N second serial signals; and an output circuit, which is used for sampling the first serial signals and the second serial signals based on a delay enable signal output by a third shift register circuit to obtain a parallel signal; and the application is characterized in that the first shift register circuit and the second shift register circuit are used for sampling even bits and odd bits of the serial signal respectively, and then the parallel signal is obtained based on the delay enable signal, so that the circuit design is simple, the power consumption area is small, and the design of Timing lib is simplified.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a signal processing device, a deserializer, a chip, and an electronic device. Background Technology

[0002] In high-speed data transmission, in order to reduce the number of transmission channels and improve signal integrity, data is usually converted into a serial signal by a serializer at the transmitting end for transmission, and then converted into a parallel signal by a deserializer at the receiving end.

[0003] Deserializers in related technologies primarily use clock division, where different clock frequencies correspond to different frequency data samples, and each data bit has a corresponding sampling clock for sampling. This means the number of sampling clock pulses matches the number of data bits, preventing data loss or duplication. However, this method requires multiple registers, clock dividers, and other control logic to implement data stream conversion. The circuit design not only requires numerous logic units but also fine timing control, increasing power consumption and area. Furthermore, high-speed data clock division necessitates signal transmission across multiple clock domains, potentially leading to timing inconsistencies. This, in turn, results in timing convergence difficulties and inaccurate timing data generation by timing libraries, further increasing design complexity. Summary of the Invention

[0004] This invention provides a signal processing device, deserializer, chip, and electronic device to solve the problems of complex circuit design, large power consumption and area, and difficulty in accurately generating timing lib in the prior art.

[0005] In a first aspect, this application provides a signal processing apparatus, the apparatus comprising: a first shift register circuit, a second shift register circuit, a third shift register circuit, a first inverter, and an output circuit;

[0006] The first inverter is used to input a clock signal and output an inverted signal of the clock signal;

[0007] The first shift register circuit is used to sample the input serial signal based on the clock signal to obtain an even number of bits of the serial signal; and to shift the even number of bits based on the inverted signal of the clock signal to output N first serial signals to the output circuit.

[0008] The second shift register circuit is used to sample the serial signal based on the inverted signal of the clock signal to obtain the odd-numbered bits of the serial signal; and to shift the odd-numbered bits based on the inverted signal of the clock signal to output N second serial signals to the output circuit.

[0009] the third shift register circuit is configured to perform shift processing on the enable signal based on the clock signal and an inverted signal of the clock signal, delay the enable signal to obtain a delayed enable signal, and output the delayed enable signal to the output circuit;

[0010] the output circuit is configured to sample the N first serial signals and the N second serial signals based on the delayed enable signal, and output a parallel signal; N is a positive integer.

[0011] In a possible implementation, the first shift register circuit includes a first D flip-flop and N second D flip-flops.

[0012] An input end of the first D flip-flop is configured to input the serial signal, a clock end of the first D flip-flop is configured to input the clock signal, and an output end of the first D flip-flop is electrically connected to an input end of a first second D flip-flop in the N second D flip-flops.

[0013] In the N second D flip-flops, an output end of a previous second D flip-flop is electrically connected to an input end of a subsequent second D flip-flop, and an output end of each second D flip-flop is configured to output a first serial signal, and a clock end of each second D flip-flop is electrically connected to the output end of the first inverter.

[0014] In a possible implementation, the second shift register circuit includes N third D flip-flops.

[0015] An input end of a first third D flip-flop in the N third D flip-flops is configured to input the serial signal, an output end of a previous third D flip-flop is electrically connected to an input end of a subsequent third D flip-flop, an output end of each third D flip-flop is configured to output a second serial signal, and a clock end of each third D flip-flop is electrically connected to the output end of the first inverter.

[0016] In a possible implementation, the third shift register circuit includes a fifth D flip-flop, a second inverter, a third inverter, and N fourth D flip-flops.

[0017] An input end of a first fourth D flip-flop in the N fourth D flip-flops is configured to input the enable signal, an output end of a previous fourth D flip-flop is electrically connected to an input end of a subsequent fourth D flip-flop, an output end of a last fourth D flip-flop is electrically connected to an input end of the fifth D flip-flop, and a clock end of each fourth D flip-flop is configured to input the clock signal.

[0018] An output end of the fifth D flip-flop is electrically connected to an input end of the second inverter, and a clock end of the fifth D flip-flop is electrically connected to the output end of the first inverter.

[0019] An output terminal of the second inverter is electrically connected with an input terminal of the third inverter.

[0020] An output terminal of the third inverter is used for outputting the delay enable signal.

[0021] In a possible implementation, the output circuit comprises N sixth D flip-flops and N seventh D flip-flops.

[0022] An input terminal of each sixth D flip-flop is used for inputting a first serial signal, and an output terminal of each sixth D flip-flop is used for outputting a first parallel signal.

[0023] An input terminal of each seventh D flip-flop is used for inputting a second serial signal, and an output terminal of each seventh D flip-flop is used for outputting a second parallel signal.

[0024] A clock terminal of each sixth D flip-flop and a clock terminal of each seventh D flip-flop are used for inputting the delay enable signal.

[0025] In a possible implementation, the output circuit further comprises a fourth inverter, a first selector corresponding to each sixth D flip-flop, and a second selector corresponding to each seventh D flip-flop.

[0026] An input terminal of the fourth inverter is used for inputting a mode selection signal, and an output terminal of the fourth inverter is electrically connected with a second input terminal of at least one target selector in N first selectors and N second selectors.

[0027] In a case where the N first selectors comprise a target selector, a first input terminal of the target selector is electrically connected with an output terminal of a sixth D flip-flop corresponding to the target selector; and in the N first selectors, except for the target selector, a first input terminal and a second input terminal of each of the other first selectors are electrically connected with an output terminal of a sixth D flip-flop corresponding to the other first selector.

[0028] In a case where the N second selectors comprise a target selector, a first input terminal of the target selector is electrically connected with an output terminal of a seventh D flip-flop corresponding to the target selector; and in the N second selectors, except for the target selector, a first input terminal and a second input terminal of each of the other second selectors are electrically connected with an output terminal of a seventh D flip-flop corresponding to the other second selector.

[0029] A control terminal of each first selector and a control terminal of each second selector are used for inputting the mode selection signal.

[0030] In a possible implementation, the circuit further comprises an OR gate;

[0031] The first input end of the OR gate is configured to input a reset signal, the second input end of the OR gate is configured to input the mode selection signal, and an output end of the OR gate is electrically connected to a reset end of at least one target D flip-flop in the N sixth D flip-flops and the N seventh D flip-flops.

[0032] The reset ends of the D flip-flops other than the target D flip-flops in the N sixth D flip-flops and the N seventh D flip-flops are configured to input the reset signal.

[0033] In a possible implementation, the reset end of each D flip-flop in the first shift register circuit, the second shift register circuit, and the third shift register circuit is configured to input the reset signal.

[0034] In a second aspect, the present application provides a deserializer, comprising a control module and the signal processing apparatus according to any one of the first aspect; wherein the control module is configured to output a clock signal, an enable signal, a reset signal, and a mode selection signal to the signal processing apparatus.

[0035] In a third aspect, the present application provides a chip, comprising the deserializer according to the second aspect.

[0036] In a fourth aspect, the present application provides an electronic device, comprising the chip according to the third aspect.

[0037] The present application has the following advantages:

[0038] The application provides a signal processing device, a deserializer, a chip and an electronic device. The device comprises a first inverter configured to input a clock signal and output an inverted signal of the clock signal; a first shift register circuit configured to sample an input serial signal based on the clock signal to obtain an even bit signal of the serial signal; perform shift processing on the even bit signal based on the inverted signal of the clock signal, and output N first serial signals to an output circuit; a second shift register circuit configured to sample the serial signal based on the inverted signal of the clock signal to obtain an odd bit signal of the serial signal; perform shift processing on the odd bit signal based on the inverted signal of the clock signal, and output N second serial signals to the output circuit; a third shift register circuit configured to perform shift processing on an enable signal based on the clock signal and the inverted signal of the clock signal, perform delay, obtain a delayed enable signal, and output the delayed enable signal to the output circuit; and the output circuit configured to sample the N first serial signals and the N second serial signals based on the delayed enable signal, and output a parallel signal. In other words, the first shift register circuit and the second shift register circuit are used to sample the serial signal to obtain the even bit signal and the odd bit signal, respectively, and then the parallel signal is obtained based on the delayed enable signal, so that the circuit design is simple, the power consumption area is reduced, and the design of Timing lib is simplified. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0040] Figure 1 A structural schematic diagram of a signal processing device provided by the embodiment of the present application is provided.

[0041] Figure 2 A timing diagram provided by the embodiment of the present application is provided.

[0042] Figure 3 A structural schematic diagram of another signal processing device provided by the embodiment of the present application is provided.

[0043] Figure 4 A structural schematic diagram of another signal processing device provided by the embodiment of the present application is provided.

[0044] Figure 5 A structural schematic diagram of another signal processing device provided by the embodiment of the present application is provided.

[0045] Figure 6 A structural schematic diagram of another signal processing device provided by the embodiment of the present application is provided.

[0046] Figure 7 Another structural schematic diagram of a signal processing device provided by an embodiment of the present application is shown in FIG. 3.

[0047] Figure 8 Another structural schematic diagram of a signal processing device provided by an embodiment of the present application is shown in FIG. 3.

[0048] Figure 9 Another timing diagram provided by an embodiment of the present application is shown in FIG. 4. DETAILED DESCRIPTION

[0049] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0050] Some technical terms related to the present application will be explained first.

[0051] 1) Timing lib (timing library): a library describing the timing characteristics of circuit elements (such as gate circuits, registers, etc.).

[0052] It should be noted that the terms "first", "second", etc. involved in the embodiments of the present application are only used for the purpose of distinguishing description, and cannot be understood as indicating or implying relative importance, nor can it be understood as indicating or implying sequence.

[0053] In high-speed data transmission, in order to reduce the number of transmission channels and improve signal integrity, data is usually converted into serial signals by a serializer at the sending end for transmission, and the serial signals are converted into parallel signals by a deserializer at the receiving end.

[0054] The deserializer in the related art mainly uses the method of clock division, and different frequency clocks correspond to different frequency data one-to-one sampling, and each data bit has a one-to-one sampling clock for sampling, that is, the number of sampling clock pulses is consistent with the number of data bits, avoiding missing or repeating data. However, this method needs multiple registers, clock dividers and other control logic to realize the conversion of data stream, and the circuit design not only needs more logic units, but also needs fine timing control, thereby increasing power consumption area, and high-speed data needs to pass signals between multiple clock domains after clock division, which may cause timing inconsistency problem, thereby causing the problem of difficult timing convergence and Timing lib timing library precision generation, increasing design difficulty.

[0055] In related technologies, deserializers can also use the FIFO (First In, First Out) method. During the data writing process, the received serial data is first stored in the FIFO buffer. The writing of data is controlled by a synchronous clock signal, which generates a write pointer; the reading of data is controlled by another asynchronous clock signal, which generates a read pointer. Thus, the writing and reading of data can be performed independently, reducing clock synchronization problems. However, if the serial data arrives too quickly, the FIFO buffer may become full, leading to data loss or frame dropping. Therefore, as the amount of data increases, a larger buffer may be needed to ensure data integrity, which in turn leads to problems such as complex circuit design and increased power consumption and area.

[0056] To address the aforementioned problems, embodiments of this application provide a signal processing device, a deserializer, a chip, and an electronic device. The signal processing device includes a first shift register circuit, a second shift register circuit, a third shift register circuit, a first inverter, and an output circuit. The first inverter outputs an inverted clock signal. The first shift register circuit obtains an even-numbered bit signal of a serial signal based on the clock signal, and shifts the even-numbered bit signal based on the inverted clock signal to output N first serial signals. The second shift register circuit obtains an odd-numbered bit signal of the serial signal based on the inverted clock signal, and shifts the odd-numbered bit signal to output N second serial signals. The output circuit samples the first and second serial signals to obtain parallel signals based on a delay enable signal output by the third shift register circuit. This simplifies the circuit design, reduces power consumption and area, and simplifies the design of timing lib.

[0057] like Figure 1 The diagram shown is a schematic diagram of a signal processing device provided in an embodiment of this application. The device includes: a first shift register circuit 101, a second shift register circuit 102, a third shift register circuit 103, a first inverter N1, and an output circuit 104.

[0058] like Figure 2 The diagram shown is a timing diagram provided in an embodiment of this application. The input clock signal is DQS1. In this application, the serial signal DATA_IN is D0, D1, D2, D3, D4, D5, D6, and D7 as an example for illustration. It should be understood that the illustration is based on this serial signal only for the purpose of understanding the structure and principle of this application. It should not be construed as implying or suggesting relative importance or implicitly indicating the number of bits of the input serial data, nor should it be construed as implying or suggesting relative importance or implicitly indicating the number of N first serial signals, N second serial signals, and parallel signals output.

[0059] The first inverter N1 is used for inputting a clock signal DQS1 and outputting an inverted signal DQS2 of the clock signal; the first shift register circuit 101 is used for sampling the input serial signal DATA_IN based on the clock signal to obtain even bit signals of the serial signal, i.e., D0, D2, D4 and D6; and the even bit signals are subjected to shift processing based on the inverted signal DQS2 of the clock signal to output N first serial signals to the output circuit 104;

[0060] In specific embodiments, for example, the inverted signal DQS2 of the clock signal is used to subject the even bit signals to shift processing to output four first serial signals to the output circuit, which are respectively a first serial signal 1: D0, D2, D4 and D6; a first serial signal 2: D0, D2 and D4; a first serial signal 3: D0 and D2; and a first serial signal 4: D0. Figure 2

[0061] The second shift register circuit 102 is used for sampling the serial signal DATA_IN based on the inverted signal DQS2 of the clock signal to obtain odd bit signals of the serial signal DATA_IN, i.e., D1, D3, D5 and D7; and the odd bit signals are subjected to shift processing based on the inverted signal DQS2 of the clock signal to output N second serial signals to the output circuit 104;

[0062] In specific embodiments, for example, the inverted signal DQS2 of the clock signal is used to subject the odd bit signals to shift processing to output four second serial signals to the output circuit, which are respectively a second serial signal 1: D1, D3, D5 and D7; a second serial signal 2: D1, D3 and D5; a second serial signal 3: D1 and D3; and a second serial signal 4: D1. Figure 2 The third shift register circuit 103 is used for subjecting the enable signal READ_EN to shift processing based on the clock signal DQS1 and the inverted signal DQS2 of the clock signal to obtain sync_en, delaying the sync_en to obtain a delay enable signal Caputer_out and outputting the delay enable signal Caputer_out to the output circuit 104;

[0063] The output circuit 104 is used for sampling the N first serial signals and the N second serial signals based on the delay enable signal Caputer_out and outputting a parallel signal DOUT; wherein N is a positive integer.

[0064]

[0065] ​​In specific embodiments, the delay enable signal Caputer_out is used to sample the 4 first serial signals and the 4 second serial signals, and the output parallel signals DOUT are D0, D1, D2, D3, D4, D5, D6, D7 respectively. Specifically, the output parallel signal DOUT0 is D0, the output parallel signal DOUT1 is D1, the output parallel signal DOUT2 is D2, the output parallel signal DOUT3 is D3, the output parallel signal DOUT4 is D4, the output parallel signal DOUT5 is D5, the output parallel signal DOUT6 is D6, and the output parallel signal DOUT7 is D7.

[0066] Thus, the application samples the serial signal DATA_IN with input D0, D1, D2, D3, D4, D5, D6, D7 by the first shift register circuit 101 to obtain even bit signals D0, D2, D4, D6, and further performs shift processing on the even bit signals to output 4 first serial signals to the output circuit. The application samples the serial signal DATA_IN with input D0, D1, D2, D3, D4, D5, D6, D7 by the second shift register circuit 102 to obtain odd bit signals D1, D3, D5, D7, and further performs shift processing on the odd bit signals to output 4 second serial signals to the output circuit. The application performs shift and delay processing on the enable signal READ_EN by the third shift register circuit 103 to obtain the delay enable signal Caputer_out. The application samples the 4 first serial signals and the 4 second serial signals based on the delay enable signal Caputer_out by the output circuit 104 to output parallel signals, so that the circuit design is simple, the power consumption area is reduced, and the design of Timing lib is simplified.

[0067] In a possible implementation, the first shift register circuit 101 includes a first D flip-flop DFF1 and N second D flip-flops DFF2. The input end of the first D flip-flop DFF1 is used to input the serial signal DATA_IN, the clock end of the first D flip-flop DFF1 is used to input the clock signal DQS1, and the output end of the first D flip-flop DFF1 is electrically connected to the input end of the first second D flip-flop among the N second D flip-flops DFF2.

[0068] In specific embodiments, the input end of the first D flip-flop DFF1 is used to input the serial signal DATA_IN, and the first D flip-flop DFF1 is used to sample the input serial signal DATA_IN under the action of the clock signal DQS1 to obtain the even bit signal of the serial signal.

[0069] The output terminal of a previous second D flip-flop is electrically connected with the input terminal of a subsequent second D flip-flop, the output terminal of each second D flip-flop DFF2 is used for outputting a first serial signal, and the clock terminal of each second D flip-flop DFF2 is electrically connected with the output terminal of the first inverter, respectively.

[0070] In a specific embodiment, the N second D flip-flops DFF2 are connected in sequence, used for performing shift processing on the even number signals under the action of the inverse signal DQS2 of the clock signal, so that the output terminal of each second D flip-flop DFF2 outputs a first serial signal, that is, the N second D flip-flops DFF2 output N first serial signals to the output circuit 104.

[0071] Figure 3 Another signal processing device provided by the embodiment of the present application is shown in a structural schematic diagram. Figure 2 and Figure 3 For example, the first shift register circuit includes a first D flip-flop DFF1 and four second D flip-flops DFF2, wherein the four second D flip-flops DFF2 are DFF21, DFF22, DFF23 and DFF24, respectively.

[0072] The input terminal of the first D flip-flop DFF1 is used for inputting serial signals DATA_IN with D0, D1, D2, D3, D4, D5, D6 and D7, and the first D flip-flop DFF1 is used for sampling the input serial signals DATA_IN to obtain even number signals D0, D2, D4 and D6 of the serial signals under the action of the clock signal DQS1. The first D flip-flop DFF1 outputs the even number signals D0, D2, D4 and D6 to the first second D flip-flop DFF21 in the second D flip-flops DFF2.

[0073] The four second D flip-flops DFF2 are connected in sequence, used for performing shift processing on the even number signals under the action of the inverse signal DQS2 of the clock signal, so that the output terminal of each second D flip-flop DFF2 outputs a first serial signal, that is, the four second D flip-flops DFF2 output four first serial signals to the output circuit 104.

[0074] Specifically, the first serial signal 1: D0, D2, D4, D6 output by the second D flip-flop DFF21 under the action of the inverse signal DQS2 of the clock signal realizes synchronization of the first serial signal and the second serial signal; the first serial signal 2: D0, D2, D4 output by the second D flip-flop DFF22 under the action of the inverse signal DQS2 of the clock signal; the first serial signal 3: D0, D2 output by the second D flip-flop DFF23 under the action of the inverse signal DQS2 of the clock signal; and the first serial signal 4: D0 output by the second D flip-flop DFF24 under the action of the inverse signal DQS2 of the clock signal.

[0075] In a possible implementation, the second shift register circuit 102 includes N third D flip-flops DFF3; an input end of a first third D flip-flop in the N third D flip-flops is configured to input the serial signal DATA_IN, an output end of a previous third D flip-flop is electrically connected to an input end of a next third D flip-flop, and an output end of each third D flip-flop is configured to output a second serial signal, and a clock end of each third D flip-flop is electrically connected to the output end of the first inverter.

[0076] In a specific embodiment, an input end of a first third D flip-flop in the N third D flip-flops is configured to input the serial signal DATA_IN, and the input serial signal DATA_IN is sampled under the action of the inverse signal DQS2 of the clock signal to obtain an odd bit signal of the serial signal. The N third D flip-flops DFF3 are connected in sequence to perform shift processing on the odd signal under the action of the inverse signal DQS2 of the clock signal, so that an output end of each third D flip-flop DFF3 outputs a second serial signal, that is, the N third D flip-flops DFF3 output N second serial signals to the output circuit 104.

[0077] Figure 4 Another signal processing device provided by the embodiment of the application is shown in a structural schematic diagram. Figure 2 and Figure 4 For example, the second shift register circuit 102 includes four third D flip-flops DFF3, which are DFF31, DFF32, DFF33, and DFF34.

[0078] The input end of the third D flip-flop DFF31 is used for inputting the serial signal DATA_IN which is D0, D1, D2, D3, D4, D5, D6, D7, and the third D flip-flop DFF31 samples the input serial signal DATA_IN under the action of the inverted signal DQS2 of the clock signal to obtain the odd bit signals D1, D3, D5, D7 of the serial signal. The third D flip-flop DFF3 is sequentially connected, and the third D flip-flop DFF32, DFF33 and DFF34 are all used for shifting processing the odd bit signals under the action of the inverted signal DQS2 of the clock signal, so that the third D flip-flop DFF3 outputs a second serial signal, that is, the fourth D flip-flop DFF3 outputs four second serial signals to the output circuit 104.

[0079] Specifically, the second serial signal 1 output by the third D flip-flop DFF31 under the action of the inverted signal DQS2 of the clock signal is D1, D3, D5, D7; the second serial signal 2 output by the third D flip-flop DFF31 under the action of the inverted signal DQS2 of the clock signal is D1, D3, D5; the second serial signal 3 output by the third D flip-flop DFF31 under the action of the inverted signal DQS2 of the clock signal is D1, D3; and the second serial signal 4 output by the third D flip-flop DFF31 under the action of the inverted signal DQS2 of the clock signal is D1.

[0080] It can be understood that the application aligns the time sequences of the plurality of first serial signals and the plurality of second serial signals by setting the plurality of second flip-flops and the plurality of third D flip-flops, so as to facilitate sampling the plurality of first serial signals and the plurality of second serial signals based on the delay enable signal to obtain the parallel signal.

[0081] In a possible implementation, the third shift register circuit includes a fifth D flip-flop DFF5, a second inverter N2, a third inverter N3 and N fourth D flip-flops DFF4; the input end of the first fourth D flip-flop in the N fourth D flip-flops DFF4 is used for inputting the enable signal READ_EN, the output end of the previous fourth D flip-flop is electrically connected with the input end of the subsequent fourth D flip-flop, the output end of the last fourth D flip-flop is electrically connected with the input end of the fifth D flip-flop DFF5, and the clock end of each fourth D flip-flop is used for inputting the clock signal DQS1 respectively.

[0082] In a specific embodiment, the N fourth D flip-flops DFF4 are sequentially connected and used for shifting processing the enable signal READ_EN under the action of the clock signal DQS1 to output the signal sync_en which is processed for N times by the N fourth D flip-flops DFF4.

[0083] The output end of the fifth D flip-flop DFF5 is electrically connected with the input end of the second inverter N2, and the clock end of the fifth D flip-flop DFF5 is electrically connected with the output end of the first inverter N1; the output end of the second inverter N2 is electrically connected with the input end of the third inverter N3; and the output end of the third inverter N3 is used for outputting a delay enable signal.

[0084] The signal sync_en is input to the fifth D flip-flop DFF5 through the last fourth D flip-flop, and the clock end of the fifth D flip-flop DFF5 is electrically connected with the output end of the first inverter N1, so as to perform shift processing on the signal sync_en under the action of the inverse signal DQS2 of the clock signal, and obtain the shift-processed sync_en.

[0085] The second inverter N2 and the third inverter N3 are connected in sequence, for performing delay processing, i.e. twice inversion processing, on the shift-processed sync_en, so as to obtain the delay enable signal Caputer_out, thereby making the delay enable signal Caputer_out trigger the output circuit 104 at a preset clock phase, and enabling the data to be stably and accurately output.

[0086] Figure 5 Another signal processing device provided by the embodiment of the present application is shown in a structural schematic diagram. Figure 2 and Figure 5 For example, the third shift register circuit includes the fifth D flip-flop DFF5, the second inverter N2, the third inverter N3 and four fourth D flip-flops DFF4, wherein the four fourth D flip-flops DFF4 are DFF41, DFF42, DFF43 and DFF44.

[0087] The input end of the first fourth D flip-flop DFF41 in the fourth D flip-flop DFF4 is used for inputting an enable signal READ_EN, and the four fourth D flip-flops DFF41, DFF42, DFF43 and DFF44 are connected in sequence, for performing shift processing on the enable signal READ_EN under the action of the clock signal DQS1, and obtaining the signal sync_en which is processed four times by the four fourth D flip-flops DFF4.

[0088] The signal sync_en is input to the fifth D flip-flop DFF5, and the clock end of the fifth D flip-flop DFF5 is electrically connected with the output end of the first inverter N1, so as to perform shift processing on the signal sync_en under the action of the inverse signal DQS2 of the clock signal, and obtain the shift-processed sync_en. Then, the second inverter N2 and the third inverter N3 perform twice inversion processing on the shift-processed sync_en, and obtain the delay enable signal Caputer_out.

[0089] In a possible implementation, the output circuit includes N sixth D flip-flops DFF6 and N seventh D flip-flops DFF7; an input terminal of each sixth D flip-flop DFF6 is configured to input a first serial signal, and an output terminal of each sixth D flip-flop DFF6 is configured to output a first parallel signal; an input terminal of each seventh D flip-flop DFF7 is configured to input a second serial signal, and an output terminal of each seventh D flip-flop DFF7 is configured to output a second parallel signal; and a clock terminal of each sixth D flip-flop DFF6 and a clock terminal of each seventh D flip-flop DFF7 are configured to input the delay enable signal.

[0090] In specific embodiments, each sixth D flip-flop DFF6 is configured to sample the input first serial signal under the action of the delay enable signal Caputer_out and output the first parallel signal, and each seventh D flip-flop DFF7 is configured to sample the input second serial signal under the action of the delay enable signal Caputer_out and output the second parallel signal.

[0091] Figure 6 Another structure diagram of a signal processing apparatus provided in the embodiments of the present application is shown in FIG. 4. Figure 2 and Figure 6 For example, the output circuit includes four sixth D flip-flops DFF6 and four seventh D flip-flops DFF7, where the four sixth D flip-flops are DFF61, DFF62, DFF63, and DFF64, and the four seventh D flip-flops are DFF71, DFF72, DFF73, and DFF74.

[0092] The sixth D flip-flop DFF61 inputs the first serial signal 1: D0, D2, D4, and D6, and outputs D6 under the action of the delay enable signal Caputer_out; the sixth D flip-flop DFF62 inputs the first serial signal 2: D0, D2, D4, and outputs D4 under the action of the delay enable signal Caputer_out; the sixth D flip-flop DFF63 inputs the first serial signal 3: D0, D2, and outputs D2 under the action of the delay enable signal Caputer_out; and the sixth D flip-flop DFF64 inputs the first serial signal 4: D0, and outputs D0 under the action of the delay enable signal Caputer_out.

[0093] The input of the seventh D flip-flop DFF71 is the second serial signal 1: D1, D3, D5, D7, and the output of the seventh D flip-flop DFF71 is D7 under the action of the delay enable signal Caputer_out. The input of the seventh D flip-flop DFF72 is the second serial signal 2: D1, D3, D5, and the output of the seventh D flip-flop DFF72 is D5 under the action of the delay enable signal Caputer_out. The input of the seventh D flip-flop DFF73 is the second serial signal 3: D1, D3, and the output of the seventh D flip-flop DFF73 is D3 under the action of the delay enable signal Caputer_out. The input of the seventh D flip-flop DFF74 is the second serial signal 4: D1, and the output of the seventh D flip-flop DFF74 is D1 under the action of the delay enable signal Caputer_out.

[0094] In a possible implementation, the fourth inverter N4, the first selector A1 corresponding to each sixth D flip-flop DFF6, and the second selector A2 corresponding to each seventh D flip-flop DFF7 are included.

[0095] The input end of the fourth inverter is used for inputting a mode selection signal 4BIT_MODE-SEL, and the output end of the fourth inverter is electrically connected to the second input end of at least one target selector in the N first selectors A1 and the N second selectors A2.

[0096] The control end of each first selector and the control end of each second selector are used for inputting the mode selection signal 4BIT_MODE-SEL.

[0097] In the case where the N first selectors A1 include the target selector, the first input end of the target selector is electrically connected to the output end of the sixth D flip-flop corresponding to the target selector. In the first selectors A1 except the target selector, the first input end and the second input end of each of the other first selectors are electrically connected to the output end of the sixth D flip-flop corresponding to the other first selector.

[0098] In specific embodiments, the mode selection signal 4BIT_MODE-SEL is input to the control end of the first selector A1, and under the control of the mode selection signal 4BIT_MODE-SEL, the target selector outputs the electrical signal of the second input end when the mode selection signal 4BIT_MODE-SEL is at a high level, and the target selector outputs the electrical signal of the first input end when the mode selection signal 4BIT_MODE-SEL is at a low level. It should be noted that the electrical signal of the second input end is the mode selection signal 4BIT_MODE-SEL after being processed in reverse.

[0099] That is, in the case that the mode selection signal 4BIT_MODE-SEL is high, the signal output by the target selector is 0; in the case that the target selector is in the case that the mode selection signal 4BIT_MODE-SEL is low, the signal output by the target selector is the output signal of the corresponding sixth D flip-flop.

[0100] The signal output by the other first selectors is the output signal of the corresponding sixth D flip-flop.

[0101] In the case that the N second selectors A2 include a target selector, the first input end of the target selector is electrically connected with the output end of the seventh D flip-flop corresponding to the target selector; the first input end and the second input end of the other second selectors in the second selectors A2, except the target selector, are electrically connected with the output end of the seventh D flip-flop corresponding to the other second selectors.

[0102] In a specific embodiment, the second selector A2 controls the input of the mode selection signal 4BIT_MODE-SEL signal, and for the same reason, in the case that the mode selection signal 4BIT_MODE-SEL is high, the signal output by the target selector is 0; in the case that the target selector is in the case that the mode selection signal 4BIT_MODE-SEL is low, the signal output by the target selector is the output signal of the corresponding seventh D flip-flop.

[0103] The signal output by the other first selectors is the output signal of the corresponding seventh D flip-flop.

[0104] Figure 7 Another signal processing device provided by the embodiment of the present application is shown in the structural schematic diagram. Figure 2 And Figure 7 For example, four first selectors A1 and four second selectors A2 are included, wherein the four first selectors A1 are A11, A12, A13 and A14 respectively, and the four second selectors A2 are A21, A22, A23 and A24 respectively.

[0105] A13 and A14 in the first selectors A1 and A23 and A24 in the second selectors A2 are taken as target selectors, so that in the case that the mode selection signal 4BIT_MODE-SEL is high, the output parallel signal is D0, D1, D2 and D3, and in the case that the mode selection signal 4BIT_MODE-SEL is low, the output parallel signal is D0, D1, D2, D3, D4, D5, D6 and D7. Thus, according to a preset rule, a parallel signal of a target bit number can be output.

[0106] In a possible implementation, an OR gate H1 is further included.

[0107] The first input of the OR gate is used to input the reset signal RESET, the second input of the OR gate is used to input the mode selection signal 4BIT_MODE-SEL, and the output of the OR gate is electrically connected to the reset terminal of at least one of the N sixth D flip-flops DFF6 and N seventh D flip-flops DFF7.

[0108] The reset terminals of all D flip-flops except the target D flip-flop among the N sixth D flip-flops (DFF6) and N seventh D flip-flops (DFF7) are used to input the reset signal.

[0109] In a specific embodiment, the target D flip-flops in the N sixth D flip-flops (DFF6) are configured to correspond with the target selectors in the N first selectors (A1), and the target D flip-flops in the N seventh D flip-flops (DFF7) are configured to correspond with the target selectors in the N second selectors (A2). Therefore, when the mode selection signal 4BIT_MODE-SEL is high, the level signal output by the OR gate is high, resetting the target D flip-flops in the N sixth D flip-flops (DFF6) and the target D flip-flops in the N seventh D flip-flops (DFF7).

[0110] Figure 8 This is a schematic diagram of another signal processing device provided in an embodiment of this application. Taking A13 and A14 in the first selector A1 and A23 and A24 in the second selector A2 as target selectors, and the output of the OR gate electrically connected to the reset terminals of DFF63 and DFF64 in the sixth D flip-flop and DFF73 and DFF74 in the seventh flip-flop, as an example, this will be explained. When the mode selection signal 4BIT_MODE-SEL is high, DFF63 and DFF64 in the sixth D flip-flop and DFF73 and DFF74 in the seventh flip-flop are reset, and the output signal is 0. The final parallel signals output by the sixth and seventh D flip-flops are D0, D1, D2, and D3. When the mode selection signal 4BIT_MODE-SEL is low, the parallel signals output by the sixth and seventh D flip-flops are D0, D1, D2, D3, D4, D5, D6, and D7.

[0111] Furthermore, such as Figure 8 As shown, the reset terminal of each D flip-flop in the first shift register circuit, the second shift register circuit, and the third shift register circuit is used to input the reset signal RESET, thereby resetting the flip-flop according to the reset signal.

[0112] like Figure 9 As shown, this is another timing diagram of an embodiment of this application, which is as follows: Figure 9As shown, before receiving data, the reset signal RESET is pulled high for reset processing, and after the reset processing, the enable signal READ_EN is pulled high, so that the delay enable signal Caputer_out is obtained based on the enable signal READ_EN, and then the N first serial signals and the N second serial signals are sampled based on the delay enable signal Caputer_out, and the parallel signal DOUT is output.

[0113] The application provides a signal processing device, which comprises a first inverter for inputting a clock signal and outputting an inverted signal of the clock signal; a first shift register circuit for sampling an input serial signal based on the clock signal to obtain an even bit signal of the serial signal, and performing shift processing on the even bit signal based on the inverted signal of the clock signal to output N first serial signals to an output circuit; a second shift register circuit for sampling the serial signal based on the inverted signal of the clock signal to obtain an odd bit signal of the serial signal, and performing shift processing on the odd bit signal based on the inverted signal of the clock signal to output N second serial signals to the output circuit; a third shift register circuit for performing shift processing on an enable signal based on the clock signal and the inverted signal of the clock signal, delaying the enable signal to obtain a delay enable signal, and outputting the delay enable signal to the output circuit; and an output circuit for sampling the N first serial signals and the N second serial signals based on the delay enable signal and outputting a parallel signal. In other words, the application samples the serial signal based on the first shift register circuit and the second shift register circuit to obtain the even bit signal and the odd bit signal, respectively, and then samples the parallel signal based on the delay enable signal, so that the circuit design is simple, the power consumption area is reduced, and the design of a Timing lib is simplified.

[0114] Based on the same inventive concept, the application further provides a deserializer comprising a control module and the above signal processing device, wherein the control module is configured to output a clock signal, an enable signal, a reset signal and a mode selection signal to the signal processing device. The principle for solving the technical problem of the deserializer is the same as that of the signal processing device, and the implementation of the deserializer can refer to that of the signal processing device, and the repeated parts will not be described herein.

[0115] Based on the same inventive concept, the application further provides a chip comprising the above deserializer, and the principle for solving the technical problem of the chip is the same as that of the signal processing device, and the implementation of the chip can refer to that of the signal processing device, and the repeated parts will not be described herein.

[0116] In specific embodiments, the chip can be any one of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), a NPU (Neural network Processing Unit), a DPU (Deep learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose Graphics Processing Unit).

[0117] Based on the same inventive concept, the embodiments of the present application also provide an electronic device comprising the chip described above. The principle of solving the technical problem of the electronic device is the same as that of the signal processing device, and the implementation of the electronic device can refer to that of the signal processing device. Details are not repeated here.

[0118] The present application provides a signal processing device, a deserializer, a chip and an electronic device. In the device, a first inverter is configured to input a clock signal and output an inverted signal of the clock signal; a first shift register circuit is configured to sample an input serial signal based on the clock signal to obtain an even bit signal of the serial signal; and the even bit signal is shifted based on the inverted signal of the clock signal and output to an output circuit as N first serial signals. A second shift register circuit is configured to sample the serial signal based on the inverted signal of the clock signal to obtain an odd bit signal of the serial signal; and the odd bit signal is shifted based on the inverted signal of the clock signal and output to the output circuit as N second serial signals. A third shift register circuit is configured to delay an enable signal after shifting the enable signal based on the clock signal and the inverted signal of the clock signal to obtain a delayed enable signal, and output the delayed enable signal to the output circuit. The output circuit is configured to sample the N first serial signals and the N second serial signals based on the delayed enable signal, and output a parallel signal. In other words, the present application samples the serial signal by the first shift register circuit and the second shift register circuit to obtain the even bit signal and the odd bit signal, respectively, and then samples the parallel signal based on the delayed enable signal, so that the circuit design is simple, the power consumption area is reduced, and the Timing lib design is simplified.

[0119] The computer program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other processing device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other processing device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0120] Accordingly, the present application can be embodied in hardware and / or in software (including firmware, resident software, micro-code, etc.). Furthermore, the present application can take the form of a computer program product on a computer-usable or computer-readable storage medium having computer-usable or computer-readable program code embodied in the medium for use by or in connection with an instruction execution system. In the context of the present application, a computer-usable or computer-readable medium can be any medium that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.

[0121] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A signal processing apparatus, characterized in that, The device includes: a first shift register circuit, a second shift register circuit, a third shift register circuit, a first inverter, and an output circuit; The first inverter is used to input a clock signal and output an inverted signal of the clock signal; The first shift register circuit is used to sample the input serial signal based on the clock signal to obtain an even number of bits of the serial signal; and to shift the even number of bits based on the inverted signal of the clock signal to output N first serial signals to the output circuit. The second shift register circuit is used to sample the serial signal based on the inverted signal of the clock signal to obtain the odd-numbered bits of the serial signal; and to shift the odd-numbered bits based on the inverted signal of the clock signal to output N second serial signals to the output circuit. The third shift register circuit is used to shift the enable signal based on the clock signal and the inverse signal of the clock signal, delay it to obtain a delayed enable signal, and output the delayed enable signal to the output circuit. The output circuit is used to sample the N first serial signals and the N second serial signals based on the delay enable signal, and output a parallel signal; where N is a positive integer.

2. The apparatus as claimed in claim 1, characterized in that, The first shift register circuit includes a first D flip-flop and N second D flip-flops; The input terminal of the first D flip-flop is used to input the serial signal, the clock terminal of the first D flip-flop is used to input the clock signal, and the output terminal of the first D flip-flop is electrically connected to the input terminal of the first of the N second D flip-flops. In the N second D flip-flops, the output of the previous second D flip-flop is electrically connected to the input of the next second D flip-flop, the output of each second D flip-flop is used to output a first serial signal, and the clock terminal of each second D flip-flop is electrically connected to the output of the first inverter.

3. The apparatus as described in claim 1, characterized in that, The second shift register circuit includes N third D flip-flops; The input terminal of the first third D flip-flop among the N third D flip-flops is used to input the serial signal. The output terminal of the preceding third D flip-flop is electrically connected to the input terminal of the following third D flip-flop. The output terminal of each third D flip-flop is used to output a second serial signal. The clock terminal of each third D flip-flop is electrically connected to the output terminal of the first inverter.

4. The apparatus as claimed in claim 1, characterized in that, The third shift register circuit includes a fifth D flip-flop, a second inverter, a third inverter, and N fourth D flip-flops; The input terminal of the first fourth D flip-flop among the N fourth D flip-flops is used to input the enable signal, the output terminal of the previous fourth D flip-flop is electrically connected to the input terminal of the next fourth D flip-flop, the output terminal of the last fourth D flip-flop is electrically connected to the input terminal of the fifth D flip-flop, and the clock terminal of each fourth D flip-flop is used to input the clock signal. The output terminal of the fifth D flip-flop is electrically connected to the input terminal of the second inverter, and the clock terminal of the fifth D flip-flop is electrically connected to the output terminal of the first inverter. The output terminal of the second inverter is electrically connected to the input terminal of the third inverter; The output of the third inverter is used to output the delay enable signal.

5. The apparatus according to any one of claims 1 to 4, characterized in that, The output circuit includes N sixth D flip-flops and N seventh D flip-flops; The input of each sixth D flip-flop is used to input a first serial signal, and the output of each sixth D flip-flop is used to output a first parallel signal. The input of each seventh D flip-flop is used to input a second serial signal, and the output of each seventh D flip-flop is used to output a second parallel signal. The clock input of each sixth D flip-flop and the clock input of each seventh D flip-flop are both used to input the delay enable signal.

6. The apparatus as claimed in claim 5, characterized in that, It also includes a fourth inverter, a first selector corresponding to each sixth D flip-flop, and a second selector corresponding to each seventh D flip-flop; The input terminal of the fourth inverter is used to input a mode selection signal, and the output terminal of the fourth inverter is electrically connected to the second input terminal of at least one of the N first selectors and N second selectors. When the N first selectors include a target selector, the first input terminal of the target selector is electrically connected to the output terminal of the sixth D flip-flop corresponding to the target selector; for the other first selectors besides the target selector, the first input terminal and the second input terminal of the other first selectors are both electrically connected to the output terminal of the sixth D flip-flop corresponding to the other first selector. When the N second selectors include a target selector, the first input terminal of the target selector is electrically connected to the output terminal of the seventh D flip-flop corresponding to the target selector; for the other second selectors besides the target selector, the first and second input terminals of the other second selectors are both electrically connected to the output terminal of the seventh D flip-flop corresponding to the other second selector. The control terminal of each first selector and the control terminal of each second selector are used to input the mode selection signal.

7. The apparatus as claimed in claim 6, characterized in that, It also includes OR gates; The first input terminal of the OR gate is used to input a reset signal, the second input terminal of the OR gate is used to input the mode selection signal, and the output terminal of the OR gate is electrically connected to the reset terminal of at least one of the N sixth D flip-flops and the N seventh D flip-flops. The reset terminals of the N sixth D flip-flops and the N seventh D flip-flops, excluding the target D flip-flop, are used to input the reset signal.

8. The apparatus as claimed in claim 7, characterized in that, The reset terminal of each D flip-flop in the first shift register circuit, the second shift register circuit, and the third shift register circuit is used to input the reset signal.

9. A deserializer, characterized in that, It includes a control module and a signal processing device as described in any one of claims 1 to 8; wherein the control module is used to output a clock signal, an enable signal, a reset signal and a mode selection signal to the signal processing device.

10. A chip, characterized in that, Includes the deserializer as described in claim 9.

11. An electronic device, characterized in that, Includes the chip as described in claim 10.

Images