Graphics processor, instruction scheduling method, terminal device and medium

Abstract

A graphics processor, an instruction scheduling method, a terminal device and a medium, the graphics processor comprising: a scheduling module, an instruction cache module, a memory access dynamic scheduling module, a unified description cache module, a read-write module and a texture module, wherein: the memory access dynamic scheduling module is adapted to receive a first instruction transmitted by the scheduling module, obtain corresponding first description register information based on the first instruction; after determining that the first instruction supports dynamic scheduling based on the first description register information, determine whether to schedule the first instruction to the read-write module or the texture module based on the load state of the read-write module and the load state of the texture module; and the unified description cache module is adapted to feed back the first description register information to the memory access dynamic scheduling module based on the type of the first instruction. The above scheme can balance the load of the texture module and the read-write module, and improve the execution efficiency of the memory access instruction.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of graphic processors, and particularly relates to a graphic processor, an instruction scheduling method, a terminal device and a medium. BACKGROUND

[0002] In a graphic processor (GPU), a texture module and a read-write module are usually independent and separated from each other.

[0003] When a graphic processor is used to perform tasks such as three-dimensional rendering and general computing, different task types have different usage proportions of the texture module and the read-write module. The graphic processor sends corresponding instructions into corresponding processing modules according to the different instructions. For example, instructions for processing texture data are sent into the texture module, and instructions for processing read-write data are sent into the read-write module.

[0004] However, when the tasks of the texture module and the read-write module are unbalanced, the execution efficiency of memory access instructions of the graphic processor is affected. SUMMARY

[0005] The present application aims at least to provide a graphic processor and an instruction scheduling method, which can balance the loads of a texture module and a read-write module and improve the execution efficiency of memory access instructions.

[0006] In a first aspect, the present application provides a graphic processor, comprising a scheduling module, an instruction cache module, a memory access dynamic scheduling module, a unified description cache module, a read-write module and a texture module, wherein the memory access dynamic scheduling module is adapted to receive a first instruction transmitted by the scheduling module, acquire corresponding first description register information based on the first instruction, and determine to schedule the first instruction to the read-write module or the texture module based on the load state of the read-write module and the load state of the texture module after determining that the first instruction supports dynamic scheduling based on the first description register information; and the unified description cache module is adapted to feed back the first description register information to the memory access dynamic scheduling module based on the type of the first instruction.

[0007] The graphic processor comprises a memory access dynamic scheduling module and a uniform description cache module. The first instruction transmitted by the scheduling module is received by the memory access dynamic scheduling module. After it is determined that the first instruction indicates dynamic scheduling, the first instruction is scheduled to the read-write module or the texture module based on the load state of the read-write module and the load state of the texture module, and the first description register information corresponding to the first instruction is obtained from the uniform description cache module. Thus, the first instruction can be dynamically scheduled according to the load state of the read-write module and the load state of the texture module, the load balancing of the read-write module and the texture module is realized, and the execution efficiency of the memory access instruction is improved.

[0008] Optionally, the memory access dynamic scheduling module is adapted to obtain description resources corresponding to the first description register information; if the description resources belong to read-only resources and the first instruction is not a dedicated instruction of the texture module, it is determined that the first instruction supports dynamic scheduling.

[0009] Optionally, the memory access dynamic scheduling module is further adapted to determine that the first instruction does not support dynamic scheduling if it is determined that the description resources corresponding to the first description register are read-write resources or the first instruction is a dedicated instruction of the texture module.

[0010] Optionally, the memory access dynamic scheduling module is adapted to: if it is detected that the first first-in-first-out unit of the texture module is full and the second first-in-first-out unit of the read-write module is not full, the first instruction is scheduled to the read-write module; and / or, if it is detected that the first first-in-first-out unit of the texture module is not full and the second first-in-first-out unit of the read-write module is full, the first instruction is scheduled to the texture module.

[0011] Optionally, the memory access dynamic scheduling module is adapted to: if it is detected that the first first-in-first-out unit of the texture module and the second first-in-first-out unit of the read-write module are both not full, the average load of the first first-in-first-out unit of the texture module and the average load of the second first-in-first-out unit of the read-write module are calculated; if the average load of the first first-in-first-out unit of the texture module is less than the average load of the second first-in-first-out unit of the read-write module, the first instruction is scheduled to the texture module; if the average load of the second first-in-first-out unit of the read-write module is less than the average load of the first first-in-first-out unit of the texture module, the first instruction is scheduled to the texture module.

[0012] Optionally, the average load of the first first-in-first-out unit of the texture module is associated with the current number of unprocessed instructions of the first first-in-first-out unit of the texture module and the number of effective instruction processing in a historical period; and / or the average load of the second first-in-first-out unit of the read-write module is associated with the current number of unprocessed instructions of the second first-in-first-out unit of the read-write module and the number of effective instruction processing in a historical period.

[0013] The average load of the first first-in-first-out unit of the texture module and the average load of the second first-in-first-out unit of the read-write module are obtained, the minimum of the average loads of the two first-in-first-out units is compared, and then it is determined whether the first instruction is executed by the texture module or the read-write module. Since the current number of unprocessed instructions and the number of effective instruction processing in a historical period are comprehensively considered, the finally determined average load can better reflect the load state of the texture module and the load state of the read-write module, and thus dynamic load balancing can be more optimally achieved.

[0014] In a second aspect, the present application provides an instruction scheduling method applied to the above-mentioned graphics processor, the method comprising: receiving a first instruction transmitted by a scheduling module of the graphics processor; obtaining corresponding first description register information based on the first instruction; determining that the first instruction supports dynamic scheduling based on the first description register information; and determining to schedule the first instruction to the read-write module or the texture module based on the load state of the read-write module and the load state of the texture module.

[0015] Optionally, the step of determining to schedule the first instruction to the read-write module or the texture module based on the load state of the read-write module and the load state of the texture module comprises: if it is detected that the first first-in-first-out unit of the texture module is full and the second first-in-first-out unit of the read-write module is not full, then the first instruction is scheduled to the read-write module; and / or if it is detected that the first first-in-first-out unit of the texture module is not full and the second first-in-first-out unit of the read-write module is full, then the first instruction is scheduled to the texture module; and / or if it is detected that the first first-in-first-out unit of the texture module and the second first-in-first-out unit of the read-write module are both not full, then the average load of the first first-in-first-out unit of the texture module and the average load of the second first-in-first-out unit of the read-write module are calculated; if the average load of the first first-in-first-out unit of the texture module is less than the average load of the second first-in-first-out unit of the read-write module, then the first instruction is scheduled to the texture module; and if the average load of the second first-in-first-out unit of the read-write module is less than the average load of the first first-in-first-out unit of the texture module, then the first instruction is scheduled to the read-write module.

[0016] In a third aspect, the present application further provides a terminal device comprising any of the above-mentioned graphic processors.

[0017] In a fourth aspect, the present application further provides a computer readable storage medium, which is a non-volatile storage medium or a non-transitory storage medium, and has stored thereon a computer program, which, when executed by a processor, performs the steps of the above-mentioned instruction scheduling method. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a structural schematic diagram of an existing graphic processor;

[0019] Figure 2 is a structural schematic diagram of a graphic processor in an embodiment of the present application;

[0020] Figure 3 is a flowchart of an instruction scheduling method in an embodiment of the present application. DETAILED DESCRIPTION

[0021] As shown in Figure 1 , a structural schematic diagram of an existing graphic processor is given. Figure 1 In the existing graphic processor, the graphic processor comprises a scheduling module (SCH) 11, an instruction cache module (IC) 12, a read-write module 13, a texture module 14 and a storage module 15, and the storage module 15 can be an L2 cache or a memory (Memory).

[0022] The scheduling module 11 sends an instruction reading request (Ins Fetch) to the instruction cache module 12, and obtains corresponding instructions from the instruction cache module 12. The scheduling module 11 performs instruction emission (Instruction Issue) on the obtained instructions according to a scheduling rule. If the instructions are for processing texture data, the instructions are sent to the texture module 14; if the instructions are for processing read-write data, the instructions are sent to the read-write module 13. The texture module 14 or the read-write module 13 reads corresponding data from the storage module 15 based on the received instructions.

[0023] However, there are scenes where the tasks of the texture module 14 and the read-write module 13 are not balanced, and the load states of the texture module 14 and the read-write module 13 are different. For example, the load of the texture module 14 is large, while the load of the read-write module 13 is small, and when a certain instruction is for processing texture data, the instruction will still be allocated to the texture module 14. The texture module 14 needs to execute all the instructions before the instruction, which results in low execution efficiency of the memory access instruction.

[0024] In the embodiment of the present application, the memory access dynamic scheduling module receives the first instruction transmitted by the scheduling module, and determines to schedule the first instruction to the read-write module or the texture module based on the load state of the read-write module and the load state of the texture module after determining that the first instruction indicates dynamic scheduling, and obtains the first description register information corresponding to the first instruction from the unified description cache module. Thus, the first instruction can be dynamically scheduled according to the load state of the read-write module and the load state of the texture module, load balancing of the read-write module and the texture module is achieved, and the execution efficiency of the memory access instruction is improved.

[0025] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0026] The embodiment of the present application provides a graphics processor, which refers to Figure 2 In the embodiment of the present application, the graphics processor can include a scheduling module 11, an instruction cache module 12, a memory access dynamic scheduling module 23, a unified description cache module 24, a read-write module 13 and a texture module 14.

[0027] In a specific implementation, the scheduling module 11 can send an instruction reading request to the instruction cache module 12. The corresponding first instruction is obtained from the instruction cache module 12. The scheduling module 11 performs instruction transmission (Instruction Issue) on the obtained first instruction according to the scheduling rule. If the first instruction is a memory access type instruction, the scheduling module 11 transmits the first instruction to the memory access dynamic scheduling module 23.

[0028] Specifically, the specific process of the scheduling module 11 obtaining the first instruction from the instruction cache module 12 and the specific process of the scheduling module 11 sending the first instruction can correspond to the related description in the prior art. Different from the prior art, in the embodiment of the present application, the first instruction is sent to the memory access dynamic scheduling module 23.

[0029] In a specific implementation, the memory access dynamic scheduling module 23 can receive the first instruction transmitted by the scheduling module 11, and obtain the corresponding first description register information based on the first instruction. The first description register information can be stored in the unified description cache module 24.

[0030] Specifically, the memory access dynamic scheduling module 23 can send a description register information request (Descriptor Fetch) to the unified description cache module 24 based on the first instruction. The unified description cache module 24 receives the register information request, and feeds back the first description register information corresponding to the first instruction to the memory access dynamic scheduling module 23 according to the type of the first instruction.

[0031] If the first instruction is related to texture data, the first description register information is used to describe the format, size, mipmap level, sampler parameter and other information of the texture data. If the first instruction is related to read-write data, the first description register information is used to describe the data format, access permission and other information of the read-write data.

[0032] It should be noted that the contents included in the description register information corresponding to the texture data and the description register information corresponding to the read-write data can refer to the existing related description.

[0033] In a specific implementation, the unified description cache module 24 can pre-store a plurality of description register information. By setting the unified description cache module 24, the description register information corresponding to the texture module 14 and the description register information corresponding to the read-write module 13 can be obtained at a high speed.

[0034] In a specific implementation, after receiving the first instruction, the memory access dynamic scheduling module 23 can further determine whether the first instruction supports dynamic scheduling. If it is determined that the first instruction supports dynamic scheduling, the first instruction is determined to be scheduled to the read-write module 13 or the texture module 14 based on the load state of the read-write module 13 and the load state of the texture module 14.

[0035] In a specific implementation, the memory access dynamic scheduling module 23 can first send a description register information request, and then determine whether the first instruction supports dynamic scheduling.

[0036] Specifically, the memory access dynamic scheduling module 23 can first send a description register information request, and after obtaining the first description register information, obtain a description resource corresponding to the first description register information (hereinafter referred to as a first description resource). If the memory access dynamic scheduling module 23 determines that the first description resource is a readable and writable resource, it is determined that the first instruction does not support dynamic scheduling, and the first instruction is sent to the read-write module 13. If the first description resource is a read-only resource, and the first description resource indicates that the first instruction is an exclusive instruction of the texture module 14, it is determined that the first instruction does not support dynamic scheduling, and the first instruction is sent to the texture module 14. If the first description resource belongs to a read-only resource, and the first instruction is not an exclusive instruction of the texture module 14, it can be determined that the first instruction supports dynamic scheduling.

[0037] In a specific implementation, after determining that the first instruction supports dynamic scheduling, the memory access dynamic scheduling module 23 can determine whether to schedule the first instruction to the read-write module 13 or the texture module 14 based on the load state of the read-write module 13 and the load state of the texture module 14.

[0038] In some embodiments, the texture module 14 can send its corresponding load status to the memory access dynamic scheduling module 23 in real time or periodically. The read-write module 13 can also send its corresponding load status to the memory access dynamic scheduling module 23 in real time or periodically. Thus, the memory access dynamic scheduling module 23 can obtain the load status of the texture module 14 and the load status of the read-write module 13.

[0039] In other embodiments, the memory access dynamic scheduling module 23 can send a load query request to the texture module 14 and the read-write module 13 respectively after receiving the first instruction. The texture module 14 receives the load query request and sends its load status to the memory access dynamic scheduling module 23. The read-write module 13 receives the load query request and sends its load status to the memory access dynamic scheduling module 23.

[0040] In a specific implementation, after obtaining the load status of the read-write module 13 and the load status of the texture module 14, the memory access dynamic scheduling module 23 can compare the load status of the read-write module 13 and the load status of the texture module 14, and determine whether to schedule the first instruction to the read-write module 13 or the texture module 14 according to the comparison result.

[0041] In a specific application, a first-in-first-out (FIFO) unit is arranged in the texture module 14 and the read-write module 13. For the sake of distinction, the FIFO unit arranged in the texture module 14 is referred to as a first FIFO unit, and the FIFO unit arranged in the read-write module 13 is referred to as a second FIFO unit.

[0042] In a specific implementation, the load status of the texture module 14 can be represented by the total number of instructions stored in the first FIFO unit. When the first FIFO unit is full, it means that the load of the first FIFO unit reaches the maximum. When there is no instruction in the first FIFO unit, it means that the load of the first FIFO unit reaches the minimum. That is, the load size of the texture module 14 is inversely related to the total number of instructions stored in the first FIFO unit.

[0043] Correspondingly, the load status of the read-write module 13 can be represented by the total number of instructions stored in the second FIFO unit. When the second FIFO unit is full, it means that the load of the second FIFO unit reaches the maximum. When there is no instruction in the second FIFO unit, it means that the load of the second FIFO unit reaches the minimum. That is, the load size of the read-write module 13 is inversely related to the total number of instructions stored in the second FIFO unit.

[0044] In a specific implementation, the memory access dynamic scheduling module 23 can obtain the total number of instructions stored in the first FIFO unit and the total number of instructions stored in the second FIFO unit respectively.

[0045] If the memory access dynamic scheduling module 23 detects that the first FIFO unit of the texture module 14 is full and the second FIFO unit of the read-write module 13 is not full, the first instruction can be dispatched to the read-write module 13. That is, when the load state of the texture module 14 reaches the maximum, the first instruction can be dispatched to the read-write module 13, and the read-write module 13 processes the first instruction, thereby speeding up the processing speed of the first instruction.

[0046] If the memory access dynamic scheduling module 23 detects that the second FIFO unit of the read-write module 13 is full and the first FIFO unit of the texture module 14 is not full, the first instruction can be dispatched to the texture module 14. That is, when the load of the read-write module 13 reaches the maximum, the first instruction can be dispatched to the texture module 14, and the texture module 14 processes the first instruction, thereby speeding up the processing speed of the first instruction.

[0047] If the memory access dynamic scheduling module 23 detects that neither the first FIFO unit nor the second FIFO unit is full, the average load corresponding to the first FIFO unit and the average load corresponding to the second FIFO unit can be calculated. If the average load of the first FIFO unit is less than the average load of the second FIFO unit, the first instruction is dispatched to the texture module 14. If the average load of the first FIFO unit is greater than the average load of the second FIFO unit, the first instruction is dispatched to the read-write module 13.

[0048] In a specific implementation, the average load of the first FIFO unit can be associated with the number of current pending instructions of the first FIFO unit and the number of effective instruction processing in a historical period. Correspondingly, the average load of the second FIFO unit can be associated with the number of current pending instructions of the second FIFO unit and the number of effective instruction processing in a historical period.

[0049] In some embodiments, the average load of the first / second FIFO unit can be calculated by using the following formula:

[0050] Average_Workload = Workload_counter_last * alpha + Pending_request_num * (1 - alpha);

[0051] Wherein, the Average_Workload is the average load of the first FIFO unit / second FIFO unit, the Workload_counter_last is the effective instruction processing quantity of the first FIFO unit / second FIFO unit in the historical period, the Pending_request_num is the current unprocessed instruction quantity of the first FIFO unit / second FIFO unit, the alpha is a weighting coefficient, and 0 < alpha < 1.

[0052] In the embodiment, the value of the alpha can be set in advance. The historical period can be the latest several periods, such as the latest 5 periods, the latest 10 periods, etc.

[0053] Therefore, by calculating the average load of the first FIFO unit and the average load of the second FIFO unit, the module (texture module 14 or read-write module 13) with smaller average load is selected to receive the first instruction, so as to realize the load balancing of the texture module 14 and the read-write module 13.

[0054] In the embodiment, there is also a scenario that the first FIFO unit and the second FIFO unit are both full, that is, the load state of the first FIFO unit and the load state of the second FIFO unit both reach the maximum. In this scenario, the pipeline operation can be paused.

[0055] In the embodiment, when the texture unit receives the first instruction, the first instruction can be stored in the first FIFO unit. In the process of executing the instruction, the texture unit can send the total number of instructions in the first FIFO unit, the load counter, the request quantity of the waiting queue, etc. to the memory access dynamic scheduling module 23.

[0056] Correspondingly, when the read-write unit receives the first instruction, the first instruction can be stored in the second FIFO unit. In the process of executing the instruction, the read-write unit can send the total number of instructions in the second FIFO unit, the load counter, the request quantity of the waiting queue, etc. to the memory access dynamic scheduling module 23.

[0057] In the embodiment of the application, the graphic processor can further include a storage module 15, which can be a second-level cache (L2) or a memory (Memory). The texture module 14 or the read-write module 13 can read corresponding data from the storage module 15 or write corresponding data to the storage module 15.

[0058] In summary, in the embodiment of the present application, the memory access dynamic scheduling module receives the first instruction transmitted by the scheduling module, and determines to schedule the first instruction to the read-write module or the texture module based on the load state of the read-write module and the load state of the texture module after determining that the first instruction indicates dynamic scheduling, and obtains the first description register information corresponding to the first instruction from the unified description cache module. Thus, the first instruction can be dynamically scheduled according to the load state of the read-write module and the load state of the texture module, the load balancing of the read-write module and the texture module is realized, and the execution efficiency of the memory access instruction is improved.

[0059] With reference to Figure 3 An instruction scheduling method is provided in the embodiment of the present application, which can be applied to the graphic processor provided in any of the above embodiments. That is, the instruction scheduling method can be executed by the graphic processor provided in any of the above embodiments.

[0060] The instruction scheduling method provided in the embodiment of the present application is described in detail below.

[0061] Step 301, receiving the first instruction transmitted by the scheduling module of the graphic processor.

[0062] In a specific implementation, the scheduling module can send an instruction reading request to the instruction cache module. The corresponding first instruction is obtained from the instruction cache module. The scheduling module performs instruction transmission (Instruction Issue) on the obtained first instruction according to the scheduling rule. If the first instruction is a memory access type instruction, the scheduling module transmits the first instruction to the memory access dynamic scheduling module.

[0063] Step 302, obtaining the corresponding first description register information based on the first instruction.

[0064] In a specific implementation, the memory access dynamic scheduling module can receive the first instruction transmitted by the scheduling module and obtain the corresponding first description register information based on the first instruction.

[0065] Specifically, the memory access dynamic scheduling module can send a description register information request (Descriptor Fetch) to the unified description cache module based on the first instruction. The unified description cache module receives the register information request and feeds back the first description register information corresponding to the first instruction to the memory access dynamic scheduling module according to the type of the first instruction.

[0066] Step 303, determining that the first instruction supports dynamic scheduling based on the first description register information.

[0067] In a specific implementation, if the memory access dynamic scheduling module determines that the first description resource is a readable and writable resource, it is determined that the first instruction does not support dynamic scheduling, and the first instruction is sent to the read-write module; if the first description resource is a read-only resource, and the first description resource indicates that the first instruction is a special instruction of the texture module, it is determined that the first instruction does not support dynamic scheduling, and the first instruction is sent to the texture module. If the first description resource belongs to a read-only resource, and the first instruction is not a special instruction of the texture module, it can be determined that the first instruction supports dynamic scheduling.

[0068] In step 304, based on the load state of the read-write module and the load state of the texture module, it is determined whether to schedule the first instruction to the read-write module or the texture module.

[0069] In a specific implementation, after the memory access dynamic scheduling module determines that the first instruction supports dynamic scheduling, it can determine whether to schedule the first instruction to the read-write module or the texture module based on the load state of the read-write module and the load state of the texture module.

[0070] In a specific implementation, if the memory access dynamic scheduling module detects that the first first-in-first-out unit of the texture module is full, and the second first-in-first-out unit of the read-write module is not full, the first instruction can be scheduled to the read-write module.

[0071] If the memory access dynamic scheduling module detects that the second first-in-first-out unit of the read-write module is full, and the first first-in-first-out unit of the texture module is not full, the first instruction can be scheduled to the texture module.

[0072] If the memory access dynamic scheduling module detects that neither the first first-in-first-out unit nor the second first-in-first-out unit is full, it can calculate the average load corresponding to the first first-in-first-out unit and the average load corresponding to the second first-in-first-out unit; if the average load of the first first-in-first-out unit is less than the average load of the second first-in-first-out unit, the first instruction is scheduled to the texture module; if the average load of the first first-in-first-out unit is greater than the average load of the second first-in-first-out unit, the first instruction is scheduled to the read-write module.

[0073] In a specific implementation, the specific execution process of the above steps 301-304 can correspond to the graphics processor provided in the above embodiments, and will not be described here.

[0074] The embodiment of the application also provides a computer readable storage medium, which is a non-volatile storage medium or a non-transient storage medium, and has stored thereon a computer program, which, when executed by a processor, performs the steps of the instruction scheduling method provided in any of the above embodiments.

[0075] The embodiment of the present application further provides a terminal device comprising the graphic processor provided by any of the above embodiments.

[0076] Those skilled in the art can understand that all or part of the steps in the above-mentioned various methods of the embodiments can be completed by a program instructing relevant hardware, and the program can be stored in a computer-readable storage medium, such as ROM, RAM, magnetic disk or optical disk, etc.

[0077] Although the present application is disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A graphics processor, characterized in that, include: The module comprises a scheduling module, an instruction cache module, a memory access dynamic scheduling module, a unified description cache module, a read / write module, and a texture module, among which: The memory access dynamic scheduling module is adapted to receive a first instruction issued by the scheduling module, and obtain corresponding first description register information based on the first instruction; after determining that the first instruction supports dynamic scheduling based on the first description register information, it determines to schedule the first instruction to the read-write module or the texture module based on the load status of the read-write module and the load status of the texture module; the memory access dynamic scheduling module is adapted to obtain the description resource corresponding to the first description register information; if the description resource is a read-only resource and the first instruction is not a dedicated instruction of the texture module, then it is determined that the first instruction supports dynamic scheduling; the first instruction is an instruction for processing texture data, or the first instruction is an instruction for processing read-write data; The unified description cache module is adapted to feed back the first description register information to the memory access dynamic scheduling module based on the type of the first instruction.

2. The graphics processor as described in claim 1, characterized in that, The memory access dynamic scheduling module is further adapted to determine that the first instruction does not support dynamic scheduling when it is determined that the description resource corresponding to the first description register is a readable and writable resource, or the first instruction is a dedicated instruction of the texture module.

3. The graphics processor as described in claim 1, characterized in that, The memory access dynamic scheduling module is adapted to: If the first FIFO unit of the texture module is found to be full, and the second FIFO unit of the read / write module is not full, then the first instruction is scheduled to the read / write module; and / or, If it is detected that the first FIFO unit of the texture module is not full, and the second FIFO unit of the read / write module is full, then the first instruction is scheduled to the texture module.

4. The graphics processor as described in claim 1, characterized in that, The memory access dynamic scheduling module is adapted to: If it is detected that neither the first FIFO unit of the texture module nor the second FIFO unit of the read / write module is full, calculate the average load corresponding to the first FIFO unit of the texture module and the second FIFO unit of the read / write module respectively. If the average load of the first FIFO unit of the texture module is less than the average load of the second FIFO unit of the read / write module, the first instruction is scheduled to the texture module; if the average load of the second FIFO unit of the read / write module is less than the average load of the first FIFO unit of the texture module, the first instruction is scheduled to the texture module.

5. The graphics processor as described in claim 4, characterized in that, The average load of the first FIFO unit of the texture module is related to the number of currently unprocessed instructions in the first FIFO unit of the texture module and the number of valid instructions processed in the historical period; and / or, The average load of the second FIFO unit of the read / write module is related to the number of currently unprocessed instructions in the second FIFO unit of the read / write module and the number of valid instructions processed in the historical period.

6. An instruction scheduling method, characterized in that, Applied to the graphics processor as described in any one of claims 1 to 5, the method comprises: Receive the first instruction issued by the scheduling module of the graphics processor; Obtain the corresponding first description register information based on the first instruction; Based on the first description register information, determining that the first instruction supports dynamic scheduling includes: obtaining the description resource corresponding to the first description register information; if the description resource is a read-only resource and the first instruction is not a dedicated instruction of the texture module, then determining that the first instruction supports dynamic scheduling; the first instruction is an instruction for processing texture data, or the first instruction is an instruction for processing read / write data. Based on the load status of the read / write module and the load status of the texture module, it is determined that the first instruction will be scheduled to the read / write module or the texture module.

7. The instruction scheduling method as described in claim 6, characterized in that, The step of determining whether to schedule the first instruction to the read / write module or the texture module based on the load status of the read / write module and the load status of the texture module includes: If the first FIFO unit of the texture module is found to be full, and the second FIFO unit of the read / write module is not full, then the first instruction is scheduled to the read / write module; and / or, If it is detected that the first FIFO unit of the texture module is not full, and the second FIFO unit of the read / write module is full, then the first instruction is scheduled to the texture module; and / or, If it is detected that neither the first FIFO unit of the texture module nor the second FIFO unit of the read / write module is full, calculate the average load corresponding to the first FIFO unit of the texture module and the second FIFO unit of the read / write module respectively; if the average load of the first FIFO unit of the texture module is less than the average load of the second FIFO unit of the read / write module, schedule the first instruction to the texture module; if the average load of the second FIFO unit of the read / write module is less than the average load of the first FIFO unit of the texture module, schedule the first instruction to the texture module.

8. A terminal device, characterized in that, include: The graphics processor as described in any one of claims 1 to 5.

9. A computer-readable storage medium, wherein the computer-readable storage medium is a non-volatile storage medium or a non-transient storage medium, and a computer program is stored thereon, characterized in that, The computer program is executed by the processor to perform the steps of the instruction scheduling method of claim 6 or 7.

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