Driving module and display device

Abstract

The application belongs to the field of display, and particularly relates to a driving module and a display device. The driving module comprises a plurality of source driving chips, a time sequence controller and at least one driving module. The driving module comprises a polarity partition control unit, a picture detection unit, a pixel detection unit, a column direction inversion control unit and a row direction inversion control unit. The picture detection unit controls the working of the polarity partition control unit according to the crosstalk severity of the display partition of the display panel, to form a conventional polarity mode and a polarity symmetry mode. In the polarity symmetry mode, if the display picture is a non-full-pixel picture, the pixel detection unit controls the column direction inversion control unit, so that the polarity of every 2 rows of the display partition is inverted, to weaken or eliminate bright and dark lines. If the display picture is a full-pixel picture, the pixel detection unit controls the row direction inversion control unit, so that the polarity of every 2 columns of the data line of the display partition is inverted, to weaken or eliminate horizontal lines, and improve the display effect of the display panel and the display device.

Description

Technical Field

[0001] This application belongs to the field of display, specifically relating to a driving module and a display device. Background Technology

[0002] When an LCD displays an image, the data lines provide data voltage to the pixel electrodes. Reversing the polarity causes the data voltage to alternate, meaning the data voltage can be greater or less than the voltage of the common electrode. The coupling capacitance (Cdc) formed between the data lines and the pixel electrodes causes a shift in the data voltage, resulting in crosstalk and affecting the display quality of the LCD.

[0003] Pulling up the source driver chips in even-numbered columns makes the display areas controlled by these chips polarity symmetrical with those controlled by the odd-numbered columns, forming a polarity-symmetrical mode. This ensures that the data voltage and common voltage coupling directions of adjacent display areas are opposite, thus canceling coupling and improving or eliminating crosstalk. However, in this polarity-symmetrical mode, at the boundary of adjacent display areas, entire columns of pixels may be either entirely positive or negative, while the polarity of sub-pixels in other areas alternates between positive and negative in the row and column directions. This causes the pixel columns at the boundary to be brighter or darker than other areas, forming bright or dark lines, which affects the display panel's display effect.

[0004] In existing technology, liquid crystal displays (LCDs) perform polarity reversal once per frame. Shortening the polarity reversal interval, for example, performing polarity reversal once every two lines, can improve or eliminate bright and dark lines. However, while shortening the polarity reversal interval is effective in compensating for non-full-pixel images, it can easily produce horizontal lines in full-pixel displays, affecting the display quality of the LCD. Summary of the Invention

[0005] The purpose of this application is to provide a driving module and display device to reduce or eliminate horizontal lines and improve the display effect of a liquid crystal display.

[0006] To achieve the above objectives, this application provides a driving module including multiple source driver chips. Each source driver chip is connected to multiple rows of data lines on a display panel. Odd-numbered rows of source driver chips are connected to a pull-down power supply. The driving module further includes a timing controller and at least one driving module. Each driving module controls a display zone of the display panel. The driving module includes:

[0007] The polarity partition control unit controls the even-numbered source driver chips to connect with the pull-down power supply to form a normal polarity mode, or controls the even-numbered source driver chips to connect with the pull-up power supply to form a polarity symmetry mode.

[0008] A screen detection unit is connected to the display partition and the polarity partition control unit. When the crosstalk level of the detected display screen exceeds a set value, the screen detection unit controls the polarity partition control unit to switch to the polarity symmetry mode.

[0009] A pixel detection unit is connected to the display partition. The pixel detection unit outputs a high-level control signal when it detects that the display screen is not a full-pixel screen, and outputs a low-level control signal when it detects that the display screen is a full-pixel screen.

[0010] The column orientation reversal control unit is connected to all the source driver chips of the timing controller, the screen detection unit, the pixel detection unit and the display partition. When the display screen is not a full pixel screen, the pixel detection unit controls the column orientation reversal control unit to make the polarity of the display partition reverse every 2 rows.

[0011] The horizontal direction reversal control unit is connected to the timing controller, the screen detection unit, the pixel detection unit, and all the source driver chips of the display partition. When the display screen is a full-pixel screen, the pixel detection unit controls the horizontal direction reversal control unit to make the polarity of the data lines of the display partition reverse every two columns.

[0012] Optionally, in the normal polarity mode, the pixel detection unit controls the column direction inversion control unit to operate, so that the polarity of the display partition is inverted every frame, and controls the row direction inversion control unit to operate, so that the polarity of the data lines of the display partition is inverted every column.

[0013] Optionally, the polarity partition control unit includes a first transistor and a resistor. The first transistor includes an N-type field-effect transistor. The first terminal of the first transistor is connected to the pull-up power supply, and the second terminal of the first transistor is connected to the pull-down power supply through the resistor. The control terminal of the first transistor is connected to the screen detection unit.

[0014] The image detection unit includes a waveform recognition unit, which is connected to the common electrode of the display partition and the polarity partition control unit. The waveform recognition unit is used to output a high-level control signal when the voltage of the common electrode exceeds a preset range, thereby controlling the polarity partition control unit to switch to the polarity symmetry mode.

[0015] Optionally, the column direction inversion control unit includes a second transistor, a third transistor, and a frequency converter. The second transistor includes an N-type field-effect transistor, and the third transistor includes a P-type field-effect transistor. The control terminals of the second transistor and the third transistor are both connected to the pixel detection unit. The first terminals of the second transistor and the third transistor are both connected to the timing controller. The second terminal of the second transistor is connected to all the source driver chips of the display partition through the frequency converter. The second terminal of the third transistor is connected to all the source driver chips of the display partition.

[0016] The horizontal direction inversion control unit includes a fourth transistor, a fifth transistor, and an inverter. The fourth transistor includes an N-type field-effect transistor, and the fifth transistor includes a P-type field-effect transistor. The control terminals of the fourth and fifth transistors are both connected to the pixel detection unit. The first terminals of the fourth and fifth transistors are both connected to the timing controller. The second terminal of the fourth transistor is connected to all the source driver chips of the display partition. The second terminal of the fifth transistor is connected to all the source driver chips of the display partition through the inverter.

[0017] Optionally, the horizontal direction inversion control unit includes a sixth transistor, a seventh transistor, and an eighth transistor. The sixth and eighth transistors both include N-type field-effect transistors, and the seventh transistor includes a P-type field-effect transistor. The control terminal of the sixth transistor is connected to the pixel detection unit. The first terminal of the sixth transistor is connected to the second terminal of the fourth transistor. The second terminal of the sixth transistor is connected to all the source driver chips of the display partition. The control terminal of the seventh transistor is connected to the screen detection unit. The first terminal of the seventh transistor is connected to the timing controller. The second terminal of the seventh transistor is connected to all the source driver chips of the display partition. The control terminal of the eighth transistor is connected to the screen detection unit. The first terminal of the eighth transistor is connected to the second terminal of the fifth transistor. The second terminal of the eighth transistor is connected to the inverter.

[0018] Optionally, the pixel detection unit includes a first detection converter and a ninth transistor, the ninth transistor including an N-type field-effect transistor. The first detection converter outputs a high-level control signal when it detects that the displayed image is not a full-pixel image, and outputs a low-level control signal when it detects that the displayed image is a full-pixel image. The control terminal of the ninth transistor is connected to the first detection converter, the first terminal of the ninth transistor is connected to the image detection unit, and the second terminal of the ninth transistor is connected to the column direction inversion control unit and the row direction inversion control unit; or

[0019] The control terminal of the ninth transistor is connected to the screen detection unit, the first terminal of the ninth transistor is connected to the display partition, and the second terminal of the ninth transistor is connected to the column direction inversion control unit and the row direction inversion control unit through the first detection converter.

[0020] Optionally, the driving module includes an anomaly detection unit, which includes a second detection converter and a tenth transistor. The tenth transistor includes an N-type field-effect transistor. The second detection converter is connected to the display partition. The second detection converter can determine the degree of brightness and / or darkness of the display partition based on the brightness and / or refresh rate of the display partition. When the degree of brightness and darkness of the display partition exceeds a preset value, the second detection converter outputs a high-level control signal. The control terminal of the tenth transistor is connected to the second detection converter. The first terminal of the tenth transistor is connected to the display partition, and the second terminal of the tenth transistor is connected to the pixel detection unit.

[0021] Optionally, the drive module includes multiple drive modules, each drive module's column direction inversion control unit is connected to all the source drive chips it controls via a first signal line, the timing controller is connected to the column direction inversion control unit via a second signal line, each drive module's row direction inversion control unit is connected to all the source drive chips it controls via a third signal line, and the timing controller is connected to the row direction inversion control unit via a fourth signal line;

[0022] The driving module includes multiple selectors and a selection controller. Each selector includes an eleventh transistor and a twelfth transistor. The eleventh transistor is a P-type field-effect transistor, and the twelfth transistor is an N-type field-effect transistor. The first and second terminals of the eleventh transistor in some selectors are respectively connected to the first signal line of an adjacent display partition. The first and second terminals of the eleventh transistor in some selectors are respectively connected to the third signal line of an adjacent display partition. The first and second terminals of the twelfth transistor in some selectors are respectively connected to the second signal line of an adjacent display partition. The first and second terminals of the twelfth transistor in some selectors are respectively connected to the fourth signal line of an adjacent display partition. One of the second signal lines is connected to the timing controller, and one of the fourth signal lines is connected to the timing controller. The control terminals of the eleventh and twelfth transistors are both connected to the selection controller. The selection controller can output a high-level control signal or a low-level control signal to control each display partition individually or all display partitions uniformly controlled by one driving module.

[0023] Optionally, the driving module includes at least three driving modules, and the selection controller is connected to the pixel detection unit of each driving module. When the number of received high-level control signals or low-level control signals is greater than a preset value, the selection controller outputs a high-level control signal to control all display zones to be uniformly controlled by one driving module.

[0024] This application also provides a display device, including:

[0025] Display panel;

[0026] The drive module is connected to the display panel.

[0027] The driving module and display device disclosed in this application have the following beneficial effects:

[0028] In this application, the driving module includes multiple source driver chips, a timing controller, and at least one driving module. Each source driver chip is connected to multiple columns of data lines on the display panel. The driving module includes a polarity partition control unit, a screen detection unit, a pixel detection unit, a column direction inversion control unit, and a row direction inversion control unit. The screen detection unit controls the operation of the polarity partition control unit according to the severity of crosstalk in the display partitions of the display panel, forming a normal polarity mode and a polarity symmetry mode. In the polarity symmetry mode, if the displayed screen is not a full-pixel screen, the pixel detection unit controls the column direction inversion control unit to invert the polarity of every two rows of the display partition to reduce or eliminate bright and dark lines. If the displayed screen is a full-pixel screen, the pixel detection unit controls the row direction inversion control unit to invert the polarity of every two columns of data lines in the display partition to reduce or eliminate horizontal lines and improve the display effect of the display panel and display device.

[0029] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0030] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0031] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0032] Figure 1 This is a schematic diagram of the drive module in an embodiment of this application.

[0033] Figure 2 This is a schematic diagram of the partition in the normal polarity mode in Embodiment 1 of this application.

[0034] Figure 3 This is a schematic diagram showing the polarity symmetry of the display panel in Embodiment 1 of this application.

[0035] Figure 4 This is a schematic diagram of the display panel in the conventional polarity mode in Embodiment 1 of this application.

[0036] Figure 5 This is a schematic diagram of the voltage waveform of the common electrode in Embodiment 1 of this application.

[0037] Figure 6 This is a schematic diagram of another row direction reversal control unit in Embodiment 1 of this application.

[0038] Figure 7 This is a schematic diagram of the structure and connection of the anomaly detection unit in Embodiment 1 of this application.

[0039] Figure 8 This is a schematic diagram of the connection of multiple column direction reversal control units in Embodiment 1 of this application.

[0040] Figure 9 This is a schematic diagram showing the connection of multiple row direction reversal control units in Embodiment 1 of this application.

[0041] Figure 10 This is a schematic diagram of the display device in Embodiment 2 of this application.

[0042] Explanation of reference numerals in the attached figures:

[0043] 10. Driver module; 100. Source driver chip; 200. Timing controller;

[0044] 300, Drive Module; 310, Polarity Partition Control Unit; 311, First Transistor; 312, Resistor; 320, Image Detection Unit; 330, Pixel Detection Unit; 331, First Detection Converter; 332, Ninth Transistor; 340, Column Direction Inversion Control Unit; 341, Second Transistor; 342, Third Transistor; 343, Frequency Converter; 350, Row Direction Inversion Control Unit; 351, Fourth Transistor; 352, Fifth Transistor; 353, Inverter; 354, Sixth Transistor; 355, Seventh Transistor; 356, Eighth Transistor; 360, Anomaly Detection Unit; 361, Second Detection Converter; 362, Tenth Transistor;

[0045] 410 Pull-down power supply; 420 Pull-up power supply; 430 First signal line; 440 Second signal line; 450 Third signal line; 460 Fourth signal line;

[0046] 500, Selector; 510, Eleventh Transistor; 520, Twelfth Transistor; 600, Selector Controller;

[0047] 20. Display panel; 21. Display zone; 211. First display sub-zone; 212. Second display sub-zone; 213. Data cable; 214. Sub-pixel. Detailed Implementation

[0048] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0049] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0050] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0051] Example 1

[0052] See Figures 1 to 4 As shown, in this embodiment, the drive module 10 includes multiple source drive chips 100 (including... Figure 1 The display panel 20 includes C1~C4), a timing controller 200 (TCON), and at least one drive module 300. Each drive module 300 controls one display partition 21 of the display panel 20. Each source driver chip 100 is connected to multiple rows of data lines 213 of the display panel 20, i.e., multiple source driver chips 100 form multiple rows.

[0053] The driving module 300 includes a polarity partition control unit 310, a screen detection unit 320, a pixel detection unit 330, a column direction inversion control unit 340, and a row direction inversion control unit 350. The source driver chips 100 of odd-numbered columns are connected to a pull-down power supply 410, which includes a ground terminal. The source driver chips 100 of even-numbered columns are connected to a pull-up power supply 420 via the polarity partition control unit 310, where the voltage of the pull-up power supply 420 is greater than the voltage of the pull-down power supply 410. The polarity partition control unit 310 controls the even-numbered column source driver chips 100 to connect to the pull-down power supply 410 to form a normal polarity mode, or it controls the even-numbered column source driver chips 100 to connect to the pull-up power supply 420 to form a symmetrical polarity mode.

[0054] The screen detection unit 320 is connected to the display partition 21 and the polarity partition control unit 310. The screen detection unit 320 outputs a first control signal S1 to control the polarity partition control unit 310 based on the display screen of the display partition 21. When the crosstalk level of the detected display screen exceeds a set value, the first control signal S1 output by the screen detection unit 320 is a high-level control signal, which controls the polarity partition control unit 310 to switch to a polarity symmetry mode. If the crosstalk level of the detected display screen does not exceed the set value, the first control signal S1 output by the screen detection unit 320 is a low-level control signal, which controls the polarity partition control unit 310 to switch to a normal polarity mode.

[0055] Taking the "Zigzag" architecture display panel 20 as an example, the display panel 20 includes multiple columns of data lines 213 and multiple sub-pixels 214 arranged in an array. Each column of sub-pixels 214 is located between two adjacent data lines 213. That is, there is one more column of data lines 213 than sub-pixels 214. The sub-pixels 214 in odd-numbered rows are connected to the data lines 213 on the first side of the adjacent data lines 213 in their respective columns, and the sub-pixels 214 in even-numbered rows are connected to the data lines 213 on the second side of the adjacent data lines 213 in their respective columns. For example, the first side is the right side and the second side is the left side. The sub-pixels 214 in odd-numbered rows are connected to the data lines 213 on the right side of the adjacent data lines 213 in their respective columns, and the sub-pixels 214 in even-numbered rows are connected to the data lines 213 on the left side of the adjacent data lines 213 in their respective columns. The polarity inversion method of the display panel 20 is dot inversion, that is, the polarity of the sub-pixels 214 alternates between positive and negative in both the row and column directions.

[0056] The default state is the normal polarity mode. The pull-down power supply 410 outputs a low-level control signal to the odd-numbered column source driver chips 100, and the polarity of the first display sub-area 211 controlled by the odd-numbered column source driver chips 100 is "+-+-". The polarity partition control unit 310 controls the even-numbered column source driver chips 100 to disconnect from the pull-up power supply 420, and the pull-down power supply 410 outputs a low-level control signal to the even-numbered column source driver chips 100, and the polarity of the second display sub-area 212 controlled by the even-numbered column source driver chips 100 is "+-+-", such as... Figure 2 As shown.

[0057] In polarity symmetry mode, the polarity of the first display sub-area 211 controlled by the source driver chip 100 of the odd-numbered columns remains unchanged. The polarity partition control unit 310 controls the source driver chip 100 of the even-numbered columns to be connected to the pull-up power supply 420. The pull-up power supply 420 outputs a high-level control signal to the source driver chip 100 of the even-numbered columns. The polarity of the second display sub-area 212 controlled by the source driver chip 100 of the even-numbered columns becomes "-+-+". The adjacent display sub-areas of the display panel 20 are polarity symmetrical, such as... Figure 3As shown. It should be understood that the adjacent first display sub-region 211 and second display sub-region 212 are polar symmetrical, and the data voltage and common voltage of the first display sub-region 211 and the second display sub-region 212 are coupled in opposite directions, which can cancel the coupling and improve or eliminate crosstalk.

[0058] See Figure 3 As shown, in the polarity symmetry mode, the pixel column at the junction of the first display sub-area 211 and the second display sub-area 212 will have the entire column being either positive or negative polarity. Meanwhile, the row and column direction sub-pixels 214 in other areas of the first display sub-area 211 and the second display sub-area 212 will have alternating positive and negative polarities, causing the pixel column at the junction to become brighter or darker than other areas, thus forming a bright-dark line, which affects the display effect of the display panel 20.

[0059] To reduce or eliminate bright and dark lines, this embodiment also includes a pixel detection unit 330, a column direction inversion control unit 340, and a row direction inversion control unit 350, which are used to control the polarity inversion interval of the column and row directions of the display partition 21.

[0060] The pixel detection unit 330 is connected to the display partition 21, the column direction inversion control unit 340, and the row direction inversion control unit 350. The pixel detection unit 330 outputs a second control signal S2 to control the column direction inversion control unit 340 and the row direction inversion control unit 350 based on the display screen of the display partition 21. When the pixel detection unit 330 detects that the display screen is not a full-pixel screen, the second control signal S2 output by the pixel detection unit 330 is a high-level control signal; when the display screen is a full-pixel screen, the second control signal S2 output by the pixel detection unit 330 is a low-level control signal. A full-pixel screen means that the red sub-pixel (R), green sub-pixel (G), and blue sub-pixel (B) are all illuminated; a non-full-pixel screen means that at least one of the red, green, and blue sub-pixels, 214, is not illuminated.

[0061] The column orientation inversion control unit 340 is connected to the timing controller 200, the screen detection unit 320, the pixel detection unit 330, and all the source driver chips 100 of the display partition 21. When the displayed screen is not a full-pixel screen, the pixel detection unit 330 controls the column orientation inversion control unit 340 to work, so that the polarity of the display partition 21 is reversed every two rows, that is, the polarity of each column of sub-pixels 214 alternates between "++--" (V2line).

[0062] The horizontal direction inversion control unit 350 is connected to the timing controller 200, the screen detection unit 320, the pixel detection unit 330, and all the source driver chips 100 of the display partition 21. When the display screen is a full-pixel screen, the pixel detection unit 330 controls the horizontal direction inversion control unit 350 to work, so that the polarity of the data lines 213 of the display partition 21 is reversed every two columns, that is, the polarity of each row of sub-pixels 214 alternates between "++--" (H-2dot).

[0063] The image detection unit 320 outputs a high-level control signal, switching display partition 21 to polarity symmetry mode. If the displayed image is not a full-pixel image, the pixel detection unit 330 outputs a high-level control signal, and the column direction inversion control unit 340 controls the display partition 21 to perform polarity inversion every two rows, that is, the polarity of each column of sub-pixels 214 alternates between "++" and "--", and the pixel columns at the boundary will show alternating positive and negative polarities, such as... Figure 4 As shown, this can weaken or eliminate the light and dark lines.

[0064] The column orientation reversal control unit 340 controls the display partition 21 to reverse the polarity every two rows. This provides good compensation for non-full-pixel images, but it can easily produce horizontal lines for full-pixel displays, affecting the display effect of the LCD. Therefore, if the displayed image is a full-pixel image, the pixel detection unit 330 outputs a low-level control signal to control the row orientation reversal control unit 350 to reverse the polarity of the data lines 213 of the display partition 21 every two columns. That is, the polarity of each row of sub-pixels 214 alternates between "++--", in order to reduce or eliminate horizontal lines and improve the display effect of the LCD.

[0065] It should be noted that although this embodiment uses a "Zigzag" architecture and a dot inversion method for polarity reversal in the display panel 20 for illustration, the driving module 10 in this embodiment can also be used to drive display panels 20 with other architectures and inversion methods. As long as there are display panels 20 with the same positive or negative polarity in the entire column of pixels at the boundary of adjacent display sub-areas in the polarity symmetry mode, the driving module 10 disclosed in this embodiment can be used for driving.

[0066] In this embodiment, the driving module 10 includes multiple source driver chips 100, a timing controller 200, and at least one driving module 300. Each source driver chip 100 is connected to multiple rows of data lines 213 of the display panel 20. The driving module 300 includes a polarity partition control unit 310, a screen detection unit 320, a pixel detection unit 330, a column direction inversion control unit 340, and a row direction inversion control unit 350. The screen detection unit 320 controls the polarity partition according to the crosstalk severity of the display partition 21 of the display panel 20. The control unit 310 operates to form a normal polarity mode and a polarity symmetry mode. In the polarity symmetry mode, if the displayed image is not a full-pixel image, the pixel detection unit 330 controls the column direction reversal control unit 340 to reverse the polarity of every two rows of the display partition 21, so as to reduce or eliminate bright and dark lines. If the displayed image is a full-pixel image, the pixel detection unit 330 controls the row direction reversal control unit 350 to reverse the polarity of every two columns of the data lines 213 of the display partition 21, so as to reduce or eliminate horizontal lines and improve the display effect of the display panel 20.

[0067] In some embodiments, under normal polarity mode, the pixel detection unit 330 controls the row direction inversion control unit 350 to operate, so that the polarity of each column of data lines 213 in the display partition 21 is inverted. Simultaneously, the pixel detection unit 330 controls the column direction inversion control unit 340 to operate, so that the polarity of each frame in the display partition 21 is inverted. For example, in the current frame, the polarity of the data signals output by multiple data lines 213 in the row direction is sequentially "+-+-", and in the next frame, the polarity of the data signals output by multiple data lines 213 in the row direction is sequentially "-+-+".

[0068] The polarity of each column of data lines 213 in display partition 21 is reversed. The polarity reversal method of display partition 21 is dot reversal, which can better suppress screen flicker. At the same time, the polarity of all sub-pixels 214 is reversed once every frame, alternating the direction of the electric field, which can effectively avoid the polarization of liquid crystal molecules.

[0069] In some embodiments, the polarity partition control unit 310 includes a first transistor 311 and a resistor 312. A first terminal of the first transistor 311 is connected to a pull-up power supply 420, and a second terminal of the first transistor 311 is connected to a pull-down power supply 410 via the resistor 312. The control terminal of the first transistor 311 is connected to the image detection unit 320. The first transistor 311 includes an N-type field-effect transistor.

[0070] When the crosstalk level of the detected display screen exceeds a set value, the screen detection unit 320 outputs a high-level control signal, the first transistor 311 turns on, and the voltage output of the pull-up power supply 420 is sent to the even-numbered source driver chips 100, thus pulling up the even-numbered source driver chips 100; when the crosstalk level of the detected display screen does not exceed the set value, the screen detection unit 320 outputs a low-level control signal, the first transistor 311 turns off, and the voltage output of the pull-down power supply 410 is sent to the even-numbered source driver chips 100, thus pulling down the even-numbered source driver chips 100.

[0071] Switching between conventional polarity mode and polarity symmetry mode is achieved by using a transistor and a resistor 312, which simplifies the structure of the polarity partition control unit 310 and reduces the manufacturing cost of the drive module 10.

[0072] In some embodiments, the screen detection unit 320 is a waveform recognition unit, which is connected to the common electrode and polarity partition control unit 310 of the display partition 21. The waveform recognition unit controls the polarity partition control unit 310 to switch to a polarity symmetry mode when the voltage of the common electrode exceeds a preset range. When the voltage of the common electrode does not exceed the preset range, the waveform recognition unit controls the polarity partition control unit 310 to switch to a normal polarity mode.

[0073] Crosstalk causes data voltage shifts, which can lead to voltage fluctuations in the common electrode (Vcom). The waveform recognition unit sets a range based on the common electrode voltage (Vcom), i.e., sets positive and negative trigger values ​​m1 and m2, respectively. Figure 5 As shown, when the voltage Vcom of the common electrode is detected to exceed the preset range (greater than m1 or less than m2, indicating severe crosstalk and poor image quality), a high-level control signal is output to the source driver chip 100 of the even-numbered column. Display partition 21 switches to polarity symmetry mode, and the data voltages of adjacent first display sub-regions 211 and second display sub-regions 212 are coupled in opposite directions to the common voltage, thereby canceling the coupling and improving or eliminating crosstalk. Conversely, when the voltage Vcom of the common electrode does not exceed the preset range, display partition 21 is in normal polarity mode.

[0074] When the display panel 20 displays special images, such as Excel images (images resembling Excel spreadsheets), alternating black and white columns, and TXT text documents, crosstalk can easily occur. The image detection unit 320 can also detect the severity of crosstalk based on parameters such as the type of image displayed and the area of ​​the image prone to crosstalk. Furthermore, the image detection unit 320 can be an additional detection unit, but it is not limited to this; the image detection unit 320 can also be integrated into the timing controller 200, depending on the specific circumstances.

[0075] The image detection unit 320 is a waveform recognition unit. The waveform recognition unit judges the severity of crosstalk based on the voltage fluctuation of the common electrode, which reduces the difficulty of recognizing the severity of crosstalk.

[0076] In some embodiments, the column direction inversion control unit 340 includes a second transistor 341, a third transistor 342, and a frequency converter 343. The second transistor 341 includes an N-type field-effect transistor, and the third transistor 342 includes a P-type field-effect transistor. The control terminals of the second transistor 341 and the third transistor 342 are both connected to the pixel detection unit 330. The first terminals of the second transistor 341 and the third transistor 342 are both connected to the timing controller 200. The second terminal of the second transistor 341 is connected to all the source driver chips 100 of the display partition 21 through the frequency converter 343, and the second terminal of the third transistor 342 is connected to all the source driver chips 100 of the display partition 21.

[0077] The horizontal direction inversion control unit 350 includes a fourth transistor 351, a fifth transistor 352, and an inverter 353. The fourth transistor 351 includes an N-type field-effect transistor, and the fifth transistor 352 includes a P-type field-effect transistor. The control terminals of the fourth transistor 351 and the fifth transistor 352 are both connected to the pixel detection unit 330. The first terminal of the fourth transistor 351 and the first terminal of the fifth transistor 352 are both connected to the timing controller 200. The second terminal of the fourth transistor 351 is connected to all the source driver chips 100 of the display partition 21, and the second terminal of the fifth transistor 352 is connected to all the source driver chips 100 of the display partition 21 through the inverter 353.

[0078] The image detection unit 320 outputs a low-level control signal, switching display partition 21 to normal mode. The second transistor 341 is turned off and the third transistor 342 is turned on. The first polarity inversion control signal S3 generated by the timing controller 200 is directly output to all source driver chips 100 of display partition 21, causing display partition 21 to invert polarity every frame. At the same time, the fourth transistor 351 is turned off and the fifth transistor 352 is turned on. The second polarity inversion control signal S4 generated by the timing controller 200 is either a high-level control signal or a low-level control signal. The second polarity inversion control signal S4 is output to all source driver chips 100 of display partition 21 through inverter 353, causing the data lines 213 of display partition 21 to invert polarity every two columns.

[0079] The image detection unit 320 outputs a high-level control signal, and the display partition 21 switches to polarity symmetry mode. If the displayed image is not a full-pixel image, the pixel detection unit 330 outputs a high-level control signal, the second transistor 341 turns on and the third transistor 342 turns off. The first polarity reversal control signal S3 generated by the timing controller 200 is frequency-converted by the frequency converter 343, generating a first polarity reversal control signal S3 with increased frequency, which is output to all source driver chips 100 of the display partition 21, causing the polarity of the display partition 21 to be reversed every two rows. At the same time, the fourth transistor 351 turns on and the fifth transistor 352 turns off, and the second polarity reversal control signal S4 generated by the timing controller 200 is directly output to all source driver chips 100 of the display partition 21, causing the polarity of the data lines 213 of the display partition 21 to be reversed every column.

[0080] The image detection unit 320 outputs a high-level control signal, switching display partition 21 to polarity symmetry mode. If the displayed image is a full-pixel image, the pixel detection unit 330 outputs a low-level control signal, the second transistor 341 is turned off and the third transistor 342 is turned on. The first polarity inversion control signal S3 generated by the timing controller 200 is directly output to all source driver chips 100 of display partition 21, causing display partition 21 to invert polarity every frame. At the same time, the fourth transistor 351 is turned off and the fifth transistor 352 is turned on. The second polarity inversion control signal S4 generated by the timing controller 200 is output to all source driver chips 100 of display partition 21 through inverter 353, causing the data lines 213 of display partition 21 to invert polarity every two columns.

[0081] Both the column direction reversal control unit 340 and the row direction reversal control unit 350 are implemented with two transistors, which simplifies the structure of the drive module 300 and reduces the manufacturing cost of the drive module 10.

[0082] In some embodiments, see Figure 6As shown, the horizontal direction inversion control unit 350 also includes a sixth transistor 354, a seventh transistor 355, and an eighth transistor 356. Both the sixth transistor 354 and the eighth transistor 356 are N-type field-effect transistors, and the seventh transistor 355 is a P-type field-effect transistor. The control terminal of the sixth transistor 354 is connected to the pixel detection unit 330. The first terminal of the sixth transistor 354 is connected to the second terminal of the fourth transistor 351, and the second terminal of the sixth transistor 354 is connected to all the source driver chips 100 of the display partition 21. The control terminal of the seventh transistor 355 is connected to the screen detection unit 320. The first terminal of the seventh transistor 355 is connected to the timing controller 200, and the second terminal of the seventh transistor 355 is connected to all the source driver chips 100 of the display partition 21. The control terminal of the eighth transistor 356 is connected to the screen detection unit 320. The first terminal of the eighth transistor 356 is connected to the second terminal of the fifth transistor 352, and the second terminal of the eighth transistor 356 is connected to the inverter 353.

[0083] The image detection unit 320 outputs a low-level control signal, switching display partition 21 to normal mode. The second transistor 341 is turned off and the third transistor 342 is turned on. The first polarity inversion control signal S3 generated by the timing controller 200 is directly output to all source driver chips 100 of display partition 21, causing display partition 21 to invert polarity every frame. At the same time, the fourth transistor 351, the sixth transistor 354, and the eighth transistor 356 are all turned off, and the seventh transistor 355 is turned on. The second polarity inversion control signal S4 generated by the timing controller 200 is directly output to all source driver chips 100 of display partition 21, causing the polarity of each column of data lines 213 of display partition 21 to invert polarity.

[0084] The image detection unit 320 outputs a high-level control signal, and the display partition 21 switches to polarity symmetry mode. If the displayed image is not a full-pixel image, the pixel detection unit 330 outputs a high-level control signal, the second transistor 341 turns on and the third transistor 342 turns off. The first polarity reversal control signal S3 generated by the timing controller 200 is frequency-converted by the frequency converter 343, generating a first polarity reversal control signal S3 with increased frequency, which is output to all source driver chips 100 of the display partition 21, causing the polarity of the display partition 21 to be reversed every two rows. At the same time, the fifth transistor 352 and the seventh transistor 355 turn off, and the fourth transistor 351 and the sixth transistor 354 turn on. The second polarity reversal control signal S4 generated by the timing controller 200 is directly output to all source driver chips 100 of the display partition 21, causing the polarity of the data lines 213 of the display partition 21 to be reversed every column.

[0085] The image detection unit 320 outputs a high-level control signal, switching display partition 21 to polarity symmetry mode. If the displayed image is a full-pixel image, the pixel detection unit 330 outputs a low-level control signal, the second transistor 341 is turned off and the third transistor 342 is turned on. The first polarity inversion control signal S3 generated by the timing controller 200 is directly output to all source driver chips 100 of display partition 21, causing display partition 21 to invert polarity every frame. At the same time, the sixth transistor 354 and the seventh transistor 355 are turned off, and the fourth transistor 351 and the eighth transistor 356 are turned on. The second polarity inversion control signal S4 generated by the timing controller 200 is output to all source driver chips 100 of display partition 21 through inverter 353, causing the data lines 213 of display partition 21 to invert polarity every two columns.

[0086] Adding a sixth transistor 354, a seventh transistor 355, and an eighth transistor 356 enables polarity reversal for each column of the data lines 213 of the display partition 21 in the normal polarity mode.

[0087] In some embodiments, the pixel detection unit 330 includes a first detection converter 331 and a ninth transistor 332, the ninth transistor 332 being an N-type field-effect transistor. The first detection converter 331 outputs a high-level control signal when it detects that the displayed image is not a full-pixel image, and outputs a low-level control signal when it detects that the displayed image is a full-pixel image. The control terminal of the ninth transistor 332 is connected to the first detection converter 331, the first terminal of the ninth transistor 332 is connected to the image detection unit 320, and the second terminal of the ninth transistor 332 is connected to the column direction inversion control unit 340 and the row direction inversion control unit 350.

[0088] When the screen detection unit 320 outputs a high-level signal and the display partition 21 is in polarity symmetry mode, the ninth transistor 332 turns on and uses the output signal of the screen detection unit 320 as the second control signal S2 to control the column direction reversal control unit 340 and the row direction reversal control unit 350, which can avoid the column direction reversal control unit 340 and the row direction reversal control unit 350 switching control signals in the normal polarity mode.

[0089] It should be noted that the control terminal of the ninth transistor 332 is connected to the first detection converter 331, the first terminal of the ninth transistor 332 is connected to the screen detection unit 320, and the second terminal of the ninth transistor 332 is connected to the column direction inversion control unit 340 and the row direction inversion control unit 350. However, it is not limited to this. The control terminal of the ninth transistor 332 is connected to the screen detection unit 320, the first terminal of the ninth transistor 332 is connected to the display partition 21, and the second terminal of the ninth transistor 332 is connected to the column direction inversion control unit 340 and the row direction inversion control unit 350 through the first detection converter 331.

[0090] The ninth transistor 332 controls whether the first detection converter 331 performs detection. The first detection converter 331 outputs a control signal as the second control signal S2 to control the column direction reversal control unit 340 and the row direction reversal control unit 350, which can avoid the column direction reversal control unit 340 and the row direction reversal control unit 350 switching control signals in the normal polarity mode.

[0091] In some embodiments, see Figure 7 As shown, the driving module 300 includes an anomaly detection unit 360, which includes a second detection converter 361 and a tenth transistor 362. The tenth transistor 362 includes an N-type field-effect transistor. The second detection converter 361 is connected to the display partition 21. The second detection converter 361 can determine the degree of brightness and darkness of the bright and dark lines based on the brightness and / or refresh rate of the display partition 21. When the degree of brightness and darkness of the bright and dark lines of the display partition 21 exceeds a preset value, the second detection converter 361 outputs a high-level control signal; when the degree of brightness and darkness of the bright and dark lines of the display partition 21 does not exceed the preset value, the second detection converter 361 outputs a low-level control signal. The control terminal of the tenth transistor 362 is connected to the second detection converter 361. The first terminal of the tenth transistor 362 is connected to the display partition 21, and the second terminal of the tenth transistor 362 is connected to the pixel detection unit 330.

[0092] In polar symmetry mode, not all images will produce bright and dark lines, and the brightness and darkness of the bright and dark lines produced by different images are different. For example, pure color low grayscale images are prone to producing bright and dark lines, and the higher the refresh rate of display zone 21, the more obvious the bright and dark lines are. The brightness and refresh rate are used to determine the brightness and darkness of the bright and dark lines. When the brightness is lower than the set value and / or the refresh rate is higher than the set value, the tenth transistor 362 is turned on. This can prevent the column direction inversion control unit 340 and the row direction inversion control unit 350 from switching control signals when no obvious bright and dark lines are produced.

[0093] In some embodiments, see Figure 8 and Figure 9 As shown, the drive module 10 includes multiple drive modules 300. The column direction inversion control unit 340 of each drive module 300 is connected to all the source drive chips 100 it controls via a first signal line 430. The timing controller 200 is connected to the column direction inversion control unit 340 via a second signal line 440. The row direction inversion control unit 350 of each drive module 300 is connected to all the source drive chips 100 it controls via a third signal line 450. The timing controller 200 is connected to the row direction inversion control unit 350 via a fourth signal line 460.

[0094] The drive module 10 includes multiple selectors 500 and a selection controller 600. Each selector 500 includes an eleventh transistor 510 and a twelfth transistor 520. The eleventh transistor 510 includes a P-type field-effect transistor, and the twelfth transistor 520 includes an N-type field-effect transistor.

[0095] The first and second terminals of the eleventh transistor 510 of the partial selector 500 are respectively connected to the first signal line 430 of the adjacent display partition 21, and the first and second terminals of the eleventh transistor 510 of the partial selector 500 are respectively connected to the third signal line 450 of the adjacent display partition 21. The first and second terminals of the twelfth transistor 520 of the partial selector 500 are respectively connected to the second signal line 440 of the adjacent display partition 21, and the first and second terminals of the twelfth transistor 520 of the partial selector 500 are respectively connected to the fourth signal line 460 of the adjacent display partition 21. One of the second signal lines 440 is connected to the timing controller 200, and one of the fourth signal lines 460 is connected to the timing controller 200.

[0096] The control terminals of the eleventh transistor 510 and the twelfth transistor 520 are both connected to the selection controller 600. The selection controller 600 can output a high-level control signal or a low-level control signal to control each display partition 21 individually by a drive module 300 or to control all display partitions 21 uniformly by a drive module 300.

[0097] When most display zones 21 are full-pixel or non-full-pixel images, the multiple display zones 21 of the entire display panel 20 can be uniformly controlled by a single drive module 300 to reduce the power consumption of the drive module 10; when the display zones 21 with full-pixel images are similar to those with non-full-pixel images, each display zone 21 is independently controlled by a single drive module 300 to achieve a better display effect.

[0098] In some embodiments, the driving module 10 includes at least three driving modules 300. A selection controller 600 is connected to the pixel detection unit 330 of each driving module 300. When the number of received high-level control signals or low-level control signals is greater than a preset value, the selection controller 600 outputs a high-level control signal to control all display zones 21 to be uniformly controlled by one driving module 300; otherwise, it outputs a low-level control signal so that each display zone 21 is controlled by one driving module 300 respectively. For example, the driving module 10 includes three driving modules 300. When the number of received high-level control signals or low-level control signals is greater than or equal to 2, the selection controller 600 outputs a high-level control signal to control all display zones 21 to be uniformly controlled by one driving module 300.

[0099] By determining whether to control uniformly or separately based on the control signal output by the pixel detection unit 330, the complexity of selecting the controller 600 can be reduced, and the manufacturing cost of the drive module 10 can be reduced.

[0100] Example 2

[0101] See Figure 10 As shown, the display device in this embodiment includes a display panel 20 and a driving module 10 disclosed in Embodiment 1, and the driving module 10 is connected to the display panel 20.

[0102] In this embodiment, the display device includes a driving module 10, which includes multiple source driver chips 100, a timing controller 200, and at least one driving module 300. Each source driver chip 100 is connected to multiple rows of data lines 213 of the display panel 20. The driving module 300 includes a polarity partition control unit 310, a screen detection unit 320, a pixel detection unit 330, a column direction inversion control unit 340, and a row direction inversion control unit 350. The screen detection unit 320 controls the crosstalk severity of the display partitions 21 of the display panel 20 according to the severity of the crosstalk. The polarity partition control unit 310 operates to form a normal polarity mode and a polarity symmetry mode. In the polarity symmetry mode, if the displayed image is not a full-pixel image, the pixel detection unit 330 controls the column direction reversal control unit 340 to reverse the polarity of every two rows of the display partition 21, so as to reduce or eliminate bright and dark lines. If the displayed image is a full-pixel image, the pixel detection unit 330 controls the row direction reversal control unit 350 to reverse the polarity of every two columns of the data lines 213 of the display partition 21, so as to reduce or eliminate horizontal lines and improve the display effect of the display panel 20 and the display device.

[0103] The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0104] In this application, unless otherwise expressly specified and limited, the terms "assembly," "connection," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0105] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0106] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A driving module comprising a plurality of source driver chips, each of the source driver chips being connected to multiple rows of data lines of a display panel, characterized in that, The source driver chips of the odd-numbered columns are connected to a pull-down power supply. The driver module also includes a timing controller and at least one driver module. Each driver module controls a display zone of the display panel. The driver module includes: The polarity partition control unit controls the even-numbered source driver chips to connect with the pull-down power supply to form a normal polarity mode, or controls the even-numbered source driver chips to connect with the pull-up power supply to form a polarity symmetry mode. A screen detection unit is connected to the display partition and the polarity partition control unit. When the crosstalk level of the detected display screen exceeds a set value, the screen detection unit controls the polarity partition control unit to switch to the polarity symmetry mode. A pixel detection unit is connected to the display partition. The pixel detection unit outputs a high-level control signal when it detects that the display screen is not a full-pixel screen, and outputs a low-level control signal when it detects that the display screen is a full-pixel screen. The column orientation reversal control unit is connected to all the source driver chips of the timing controller, the screen detection unit, the pixel detection unit and the display partition. When the display screen is not a full pixel screen, the pixel detection unit controls the column orientation reversal control unit to make the polarity of the display partition reverse every 2 rows. The horizontal direction reversal control unit is connected to the timing controller, the screen detection unit, the pixel detection unit, and all the source driver chips of the display partition. When the display screen is a full-pixel screen, the pixel detection unit controls the horizontal direction reversal control unit to make the polarity of the data lines of the display partition reverse every two columns.

2. The drive module according to claim 1, characterized in that, In the normal polarity mode, the pixel detection unit controls the column direction inversion control unit to operate, so that the polarity of the display partition is inverted every frame, and controls the row direction inversion control unit to operate, so that the polarity of the data lines of the display partition is inverted every column.

3. The drive module according to claim 1, characterized in that, The polarity partition control unit includes a first transistor and a resistor. The first transistor includes an N-type field-effect transistor. The first terminal of the first transistor is connected to the pull-up power supply, and the second terminal of the first transistor is connected to the pull-down power supply through the resistor. The control terminal of the first transistor is connected to the screen detection unit. The image detection unit includes a waveform recognition unit, which is connected to the common electrode of the display partition and the polarity partition control unit. The waveform recognition unit is used to output a high-level control signal when the voltage of the common electrode exceeds a preset range, thereby controlling the polarity partition control unit to switch to the polarity symmetry mode.

4. The drive module according to claim 1, characterized in that, The column direction inversion control unit includes a second transistor, a third transistor, and a frequency converter. The second transistor includes an N-type field-effect transistor, and the third transistor includes a P-type field-effect transistor. The control terminals of the second transistor and the third transistor are both connected to the pixel detection unit. The first terminals of the second transistor and the third transistor are both connected to the timing controller. The second terminal of the second transistor is connected to all the source driver chips of the display partition through the frequency converter. The second terminal of the third transistor is connected to all the source driver chips of the display partition. The horizontal direction inversion control unit includes a fourth transistor, a fifth transistor, and an inverter. The fourth transistor includes an N-type field-effect transistor, and the fifth transistor includes a P-type field-effect transistor. The control terminals of the fourth and fifth transistors are both connected to the pixel detection unit. The first terminals of the fourth and fifth transistors are both connected to the timing controller. The second terminal of the fourth transistor is connected to all the source driver chips of the display partition. The second terminal of the fifth transistor is connected to all the source driver chips of the display partition through the inverter.

5. The drive module according to claim 4, characterized in that, The horizontal direction inversion control unit includes a sixth transistor, a seventh transistor, and an eighth transistor. The sixth and eighth transistors are both N-type field-effect transistors, and the seventh transistor is a P-type field-effect transistor. The control terminal of the sixth transistor is connected to the pixel detection unit. The first terminal of the sixth transistor is connected to the second terminal of the fourth transistor. The second terminal of the sixth transistor is connected to all the source driver chips of the display partition. The control terminal of the seventh transistor is connected to the screen detection unit. The first terminal of the seventh transistor is connected to the timing controller. The second terminal of the seventh transistor is connected to all the source driver chips of the display partition. The control terminal of the eighth transistor is connected to the screen detection unit. The first terminal of the eighth transistor is connected to the second terminal of the fifth transistor. The second terminal of the eighth transistor is connected to the inverter.

6. The drive module according to claim 4 or 5, characterized in that, The pixel detection unit includes a first detection converter and a ninth transistor, the ninth transistor being an N-type field-effect transistor. The first detection converter outputs a high-level control signal when it detects a non-full-pixel display and outputs a low-level control signal when it detects a full-pixel display. The control terminal of the ninth transistor is connected to the first detection converter, the first terminal of the ninth transistor is connected to the image detection unit, and the second terminal of the ninth transistor is connected to the column direction inversion control unit and the row direction inversion control unit; or The control terminal of the ninth transistor is connected to the screen detection unit, the first terminal of the ninth transistor is connected to the display partition, and the second terminal of the ninth transistor is connected to the column direction inversion control unit and the row direction inversion control unit through the first detection converter.

7. The drive module according to claim 6, characterized in that, The driving module includes an anomaly detection unit, which includes a second detection converter and a tenth transistor. The tenth transistor includes an N-type field-effect transistor. The second detection converter is connected to the display partition. The second detection converter can determine the degree of brightness and darkness of the bright and dark lines based on the brightness and / or refresh rate of the display partition. When the degree of brightness and darkness of the bright and dark lines of the display partition exceeds a preset value, the second detection converter outputs a high-level control signal. The control terminal of the tenth transistor is connected to the second detection converter. The first terminal of the tenth transistor is connected to the display partition, and the second terminal of the tenth transistor is connected to the pixel detection unit.

8. The drive module according to claim 1, characterized in that, The drive module includes multiple drive modules. The column direction inversion control unit of each drive module is connected to all the source drive chips it controls via a first signal line. The timing controller is connected to the column direction inversion control unit via a second signal line. The row direction inversion control unit of each drive module is connected to all the source drive chips it controls via a third signal line. The timing controller is connected to the row direction inversion control unit via a fourth signal line. The driving module includes multiple selectors and a selection controller. Each selector includes an eleventh transistor and a twelfth transistor. The eleventh transistor is a P-type field-effect transistor, and the twelfth transistor is an N-type field-effect transistor. The first and second terminals of the eleventh transistor in some selectors are respectively connected to the first signal line of an adjacent display partition. The first and second terminals of the eleventh transistor in some selectors are respectively connected to the third signal line of an adjacent display partition. The first and second terminals of the twelfth transistor in some selectors are respectively connected to the second signal line of an adjacent display partition. The first and second terminals of the twelfth transistor in some selectors are respectively connected to the fourth signal line of an adjacent display partition. One of the second signal lines is connected to the timing controller, and one of the fourth signal lines is connected to the timing controller. The control terminals of the eleventh and twelfth transistors are both connected to the selection controller. The selection controller can output a high-level control signal or a low-level control signal to control each display partition individually or all display partitions uniformly controlled by one driving module.

9. The drive module according to claim 8, characterized in that, The driving module includes at least three driving modules. The selection controller is connected to the pixel detection unit of each driving module. When the number of received high-level control signals or low-level control signals is greater than a preset value, the selection controller outputs a high-level control signal to control all display zones to be uniformly controlled by one driving module.

10. A display device, characterized in that, include: Display panel; The driving module as described in any one of claims 1 to 9 is connected to the display panel.

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