Write-in control method of storage medium and controller

Abstract

The invention relates to the field of calculation, and particularly provides a storage medium write-in control method and a controller, the method comprises the following steps: a first heterogeneous core obtains a first request sent by a second heterogeneous core when the storage medium is in write protection, the first request is used for requesting to write in data, and the second heterogeneous core sends the first request to the second heterogeneous core; the type of the first heterogeneous core is different from that of the second heterogeneous core; sending a first reset signal to a storage medium, wherein the first reset signal is used for triggering the storage medium to relieve write protection; and under the condition that writing of the data of the second heterogeneous core into the storage medium is completed, starting write protection of the storage medium. In the technical scheme of the embodiment of the invention, the first heterogeneous core controls the use of the write-in permission of the storage medium, and once the write-in permission of the storage medium is occupied by the second heterogeneous core, other heterogeneous cores cannot write data into the storage medium, so that the uniqueness of the write-in permission of the storage medium is ensured, and the system security is effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of computing, and in particular to a storage medium write control method and controller. BACKGROUND

[0002] With the increasing complexity and diversity of computing services, heterogeneous multi-core design is becoming more and more common. Heterogeneous multi-core refers to setting multiple processing cores in the same hardware device, and different processing cores can be used for different systems. For example, a processing core for a Linux operating system and a processing core for other systems, such as a while (conditional) loop system, can be designed on a BMC (Baseboard Management Controller) chip. The processing core in the heterogeneous multi-core structure can also be referred to as a heterogeneous core.

[0003] Currently, multiple heterogeneous cores can share a storage medium, such as an EMMC (Embedded MultiMediaCard), a UFS (Universal Flash Storage), or a NorFlash (Not OR FlashMemory). Therefore, how to improve the write security of the storage medium in the heterogeneous multi-core scenario is a technical problem to be solved. SUMMARY

[0004] The embodiments of the present application provide a storage medium write control method and controller. When multiple heterogeneous cores exist in the controller, the write permission of the storage medium is managed by the heterogeneous core with the highest security permission, thereby improving the write security of the storage medium.

[0005] According to a first aspect of the embodiments of the present application, a storage medium write control method is provided, comprising: The first heterogeneous core acquires a first request sent by a second heterogeneous core in the case that the storage medium is in write protection, the first request being used to request writing data, and the first heterogeneous core and the second heterogeneous core being different in type.

[0006] A first reset signal is sent to the storage medium, the first reset signal being used to trigger the storage medium to release the write protection.

[0007] The write protection of the storage medium is started after determining that the data writing of the second heterogeneous core into the storage medium is completed.

[0008] In the embodiments of the present application, when multiple heterogeneous cores exist in the controller, whether the write protection of the storage medium is released is controlled by the first heterogeneous core. That is, the first heterogeneous core receives the first request sent by the second heterogeneous core when the storage medium is in the write protection state, and the first request is used to request writing data. In order to solve the write protection of the storage medium, a first reset signal can be sent to the storage medium to trigger the storage medium to release the write protection. Once the write protection of the storage medium is released, the data of the second heterogeneous core can be written into the storage medium, thereby ensuring the uniqueness of the write permission of the storage medium. When it is determined that the second heterogeneous core completes the data writing to the storage medium, the write protection of the storage medium is started to make the storage medium recover the write protection. The write protection of the storage medium is triggered to release and recover by the first heterogeneous core, which greatly improves the write security of the storage medium, effectively avoids the possibility of tampering with the firmware, and further improves the system security.

[0009] With reference to the first aspect, in some implementations of the first aspect, sending the first reset signal to the storage medium comprises: The first reset signal is sent to the storage medium through the first interface, and the first interface is a GPIO (General Purpose Input / Output) interface between the first heterogeneous core and the storage medium.

[0010] In the embodiments of the present application, the first interface between the first heterogeneous core and the storage medium is set to realize the exclusive communication channel of the first heterogeneous core and the storage medium, which can ensure that the release of the write protection of the storage medium can only be triggered by the first heterogeneous core, and further improve the write security of the storage medium.

[0011] With reference to the first aspect, in some implementations of the first aspect, the first heterogeneous core is the heterogeneous core with the highest security permission.

[0012] In the embodiments of the present application, the first heterogeneous core with the highest security permission is used to release and recover the write protection of the storage medium, so that the write permission of the storage medium is concentrated to the first heterogeneous core, the write permission of the storage medium is avoided to be dispersed, and the write security of the storage medium is further improved.

[0013] With reference to the first aspect, in some implementations of the first aspect, a hardware lock is arranged between the first heterogeneous core and the storage medium. Before the first reset signal is sent to the storage medium, the method further comprises: A configuration instruction is sent to the hardware lock, and the configuration instruction indicates that the hardware lock is occupied by the second heterogeneous core or the first heterogeneous core.

[0014] When the hardware lock is occupied by the first heterogeneous core, the data of the second heterogeneous core is written into the storage medium by the first heterogeneous core through the hardware lock.

[0015] In the case that the hardware lock is occupied by the second heterogeneous core, the data of the second heterogeneous core is written into the storage medium by the second heterogeneous core through the hardware lock.

[0016] Optionally, the hardware lock refers to a component that controls the write enable of the storage medium.

[0017] In the embodiments of the present application, the write permission of the storage medium is further controlled by the hardware lock between the first heterogeneous core and the storage medium. The physical control of the write permission of the storage medium is realized through the physical characteristics of the hardware lock, and the concurrent access conflict caused by the permission contention of different heterogeneous cores is eliminated from the physical layer, and the access security and stability of the storage medium are further improved.

[0018] In combination with the first aspect, in some implementation manners of the first aspect, the first request includes verification data, and sending the first reset signal to the storage medium includes: verifying the verification data in the first request to obtain a verification result; If the verification result is verification success, the first reset signal is sent to the storage medium.

[0019] In the embodiments of the present application, the verification data in the first request is verified to obtain a verification result, and if the verification result is verification success, the second heterogeneous core passes the security verification, and the first heterogeneous core can send the first reset signal to the storage medium, so as to configure the write permission of the storage medium to the second heterogeneous core. It is ensured that the heterogeneous core that obtains the write permission of the storage medium needs to pass the security verification, and the write security of the storage medium is further ensured.

[0020] In combination with the first aspect, in some implementation manners of the first aspect, the method further includes: If the verification result is verification failure, prompt information of the verification failure is sent to the second heterogeneous core.

[0021] In the embodiments of the present application, if the verification result is verification failure, it indicates that the second heterogeneous core does not pass the security verification, and the first heterogeneous core no longer sends the first reset signal. The second heterogeneous core cannot obtain the write permission of the storage medium in the case of security risk, so as to further ensure the write security of the storage medium. If the verification fails, the first heterogeneous core can also send the prompt information of the verification failure to the second heterogeneous core, which can prompt the second heterogeneous core to appear verification failure and security vulnerability in time, so that the second heterogeneous core responds in time to avoid more system vulnerabilities and further improve the system operation security.

[0022] In combination with the first aspect, in some implementation manners of the first aspect, the first request is sent to the shared memory by the second heterogeneous core, and the first request sent by the second heterogeneous core is obtained, including: The first request sent by the second heterogeneous core is read from the shared memory.

[0023] In the embodiments of the application, for communication between two heterogeneous cores, shared memory is used to complete, which can directly realize data interaction, reduces the difficulty of communication of heterogeneous cores with architecture difference, reduces the difficulty of data transmission, significantly reduces the delay of cross-core communication, and finally realizes efficient and flexible information transmission between heterogeneous cores, and improves the information transmission efficiency.

[0024] In combination with the first aspect, in some implementation manners of the first aspect, the method further includes: determining the to-be-stored data sent by the second heterogeneous core; sending the to-be-stored data to the storage medium, so that the storage medium stores the to-be-stored data.

[0025] In the embodiments of the application, after the second heterogeneous core obtains the write permission of the storage medium, the first heterogeneous core completes the writing of the to-be-stored data of the second heterogeneous core, which further limits the write permission of the second heterogeneous core, and effectively improves the write security of the storage medium.

[0026] In combination with the first aspect, in some implementation manners of the first aspect, during the write permission of the storage medium being occupied by the second heterogeneous core, the method further includes: obtaining a second request sent by another heterogeneous core, the another heterogeneous core being a heterogeneous core other than the first heterogeneous core and the second heterogeneous core; sending an occupation prompt to the another heterogeneous core, the occupation prompt being used to prompt the another heterogeneous core that the write permission of the storage medium has been occupied.

[0027] In the embodiments of the application, during the write permission of the storage medium being occupied by the second heterogeneous core, if the second request sent by the another heterogeneous core is received again, an occupation prompt is sent to the another heterogeneous core, the occupation prompt being used to prompt the another heterogeneous core that the write permission of the storage medium has been occupied, and the another heterogeneous core cannot obtain the write permission of the storage medium temporarily. The write permission of the storage medium is unique, that is, only one heterogeneous core can occupy the write permission in one period. Through the occupation prompt of the heterogeneous core, the another heterogeneous core can be processed in time, and occupation conflict can be avoided.

[0028] In combination with the first aspect, in some implementation manners of the first aspect, the method further includes: sending a second reset signal to the second heterogeneous core, the second reset signal being used to instruct the second heterogeneous core to suspend and instruct the second heterogeneous core to notify another heterogeneous core to suspend, the another heterogeneous core being a heterogeneous core other than the first heterogeneous core and the second heterogeneous core; alternatively, sending a second reset signal to the second heterogeneous core and the another heterogeneous core.

[0029] The data of the second heterogeneous core is written into the storage medium by the first heterogeneous core.

[0030] In the embodiments of the present application, the second reset signal is used to control the suspension of each second heterogeneous core, so as to ensure that the write permission of the storage medium is exclusively occupied by the first heterogeneous core for a period of time, avoid the write permission of the storage medium being impacted by other heterogeneous cores, and avoid the occurrence of permission conflicts, thereby eliminating potential conflicts and interference, and consolidating the uniqueness of the write permission of the storage medium, so as to provide safer access control for the storage medium.

[0031] With reference to the first aspect, in some implementations of the first aspect, the method further includes: sending a second reset signal to the other heterogeneous cores, the second reset signal being used to instruct the other heterogeneous cores to suspend; the data of the second heterogeneous core is written into the storage medium by the second heterogeneous core.

[0032] In the embodiments of the present application, the second reset signal is sent to the other heterogeneous cores, and the second reset signal is used to control the suspension of the other heterogeneous cores. At this time, the write permission of the storage medium is exclusively occupied by the second heterogeneous core. Suspending the other heterogeneous cores can avoid the write permission of the storage medium being impacted by the other heterogeneous cores, avoid the occurrence of permission occupation conflicts, eliminate the risk of data writing of the second heterogeneous core, consolidate the uniqueness of the write permission of the second heterogeneous core, and provide safer access control for the storage medium.

[0033] With reference to the first aspect, in some implementations of the first aspect, after determining that the second heterogeneous core completes the data writing into the storage medium, the write protection of the storage medium is started, and the method further includes: sending a notification signal to the other heterogeneous cores, the notification signal being used to notify the other heterogeneous cores that the write permission of the storage medium can be acquired.

[0034] In the embodiments of the present application, after determining that the second heterogeneous core completes the input writing into the storage medium, the write protection of the storage medium is started, and the notification signal can be sent to the other heterogeneous cores. The notification signal is used to notify the other heterogeneous cores that the write permission of the storage medium can be acquired, so as to timely remind the other heterogeneous cores that the write permission of the storage medium can be acquired for a long time, avoid disordered competition, and realize the orderly management of the write permission of the storage medium.

[0035] According to the second aspect of the embodiments of the present application, a controller is provided, including: a plurality of heterogeneous cores, the heterogeneous core with the highest security permission in the plurality of heterogeneous cores being a first heterogeneous core, the first heterogeneous core further being connected with a storage medium, the storage medium storing a computer program, and the computer program being called by the first heterogeneous core to execute any one of the storage medium write control methods.

[0036] With reference to the second aspect, in some implementations of the second aspect, the controller further includes a hardware lock, which is arranged between the first heterogeneous core and the storage medium. The hardware lock refers to a component that controls the write enable of the storage medium.

[0037] Optionally, the first heterogeneous core is connected with the hardware lock, and the hardware lock is connected with the storage medium. That is, the first heterogeneous core, the hardware lock, and the storage medium are sequentially connected.

[0038] Optionally, if the hardware lock receives the configuration instruction, the configuration instruction indicates that the first heterogeneous core or the second heterogeneous core occupies the hardware lock.

[0039] According to a third aspect of an embodiment of the present application, a computing device is provided, comprising a storage medium and a controller; the controller comprises a plurality of heterogeneous cores, and the storage medium is configured to store a computer program; a first heterogeneous core in the controller is configured to execute the computer program to implement any of the write control methods of the storage medium.

[0040] With reference to the third aspect, in some implementations of the third aspect, the computing device further comprises a hardware lock, which is arranged between the first heterogeneous core and the storage medium. The hardware lock refers to a component that controls the write enablement of the storage medium.

[0041] Optionally, the first heterogeneous core is connected with the hardware lock, and the hardware lock is connected with the storage medium. That is, the first heterogeneous core, the hardware lock, and the storage medium are sequentially connected.

[0042] Optionally, if the hardware lock receives the configuration instruction, the configuration instruction indicates that the first heterogeneous core or the second heterogeneous core occupies the hardware lock.

[0043] According to a fourth aspect of an embodiment of the present application, a communication device is provided, comprising a transceiver and a controller; the transceiver is configured to receive or send data, and the controller is configured to execute any of the write control methods of the storage medium.

[0044] According to a fifth aspect of an embodiment of the present application, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program; when the computer program is executed by a controller, any of the write control methods of the storage medium is implemented.

[0045] According to a sixth aspect of an embodiment of the present application, a computer product is provided, comprising a computer program; when the computer program is executed by a controller, the steps of any of the write control methods of the storage medium are implemented.

[0046] As will be described in detail below, the storage medium write control method provided by the embodiments of the present application controls whether the write protection of the storage medium is released by the first heterogeneous core when there are multiple heterogeneous cores in the controller. That is, the first heterogeneous core receives the first request sent by the second heterogeneous core when the storage medium is in write protection, and the first request is used to request writing data. In order to solve the write protection of the storage medium, a first reset signal can be sent to the storage medium to trigger the storage medium to release the write protection. Once the write protection of the storage medium is released, the data of the second heterogeneous core can be written into the storage medium, thereby ensuring the uniqueness of the write permission of the storage medium. When it is determined that the second heterogeneous core completes the data writing to the storage medium, the write protection of the storage medium is started to make the storage medium recover the write protection. The write protection of the storage medium is triggered by the first heterogeneous core to release and recover, which greatly improves the write security of the storage medium, effectively avoids the possibility of tampering with the firmware, and further improves the system security.

[0047] It is to be understood that both the foregoing general description and the following detailed description are exemplary and intended to provide further explanation of the subject technology claimed. BRIEF DESCRIPTION OF DRAWINGS

[0048] The above and other objects, features and advantages of the present application will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:

[0049] Figure 1 FIG. 1 shows a structural schematic diagram of a controller according to an embodiment of the present application; Figure 2 FIG. 2 shows a flow chart of a storage medium write control method according to an embodiment of the present application; Figure 3 FIG. 3 shows an example diagram of a communication scenario of multiple heterogeneous cores according to an embodiment of the present application; Figure 4 FIG. 4 shows a message structure schematic diagram of a first request according to an embodiment of the present application; Figure 5 FIG. 5 shows an example diagram of a storage medium write control method according to an embodiment of the present application; Figure 6 FIG. 6 shows another example diagram of a storage medium write control method according to an embodiment of the present application; Figure 7 FIG. 7 shows an example diagram of storage medium occupation release according to an embodiment of the present application; Figure 8 FIG. 1 illustrates another example diagram of a storage medium occupation release according to an embodiment of the present application; Figure 9 FIG. 1 illustrates another example diagram of a storage medium occupation release according to an embodiment of the present application; Figure 10 FIG. 1 illustrates another example diagram of a storage medium occupation release according to an embodiment of the present application; Figure 11 FIG. 1 illustrates another example diagram of a storage medium occupation release according to an embodiment of the present application; Figure 12 FIG. 1 illustrates another example diagram of a storage medium occupation release according to an embodiment of the present application; Figure 13 FIG. 1 illustrates another example diagram of a storage medium occupation release according to an embodiment of the present application; Figure 14 FIG. 1 illustrates another example diagram of a storage medium occupation release according to an embodiment of the present application; DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more obvious, the exemplary embodiments according to the embodiments of the present application will be described in detail below with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments of the present application, and it should be understood that the embodiments of the present application are not limited to the exemplary embodiments described herein.

[0051] The technical solutions of the embodiments of the present application can be applied to the field of computing. When the controller includes multiple heterogeneous cores, the write permission of the storage medium is controlled by the heterogeneous core with the highest security permission, so that the write permission of the storage medium is uniformly managed, and the write security of the storage medium is improved.

[0052] In related technologies, in a multiple heterogeneous core scenario, any heterogeneous core can release the write protection of the storage medium. Once the write protection of the storage medium is released, any heterogeneous core can write data to the storage medium, so that the storage medium has a write vulnerability, lacks security control, and can cause system security risks due to tampering with firmware.

[0053] To solve the above problems, in the embodiments of the present application, when the controller includes multiple heterogeneous cores, the write permission of the storage medium is controlled by the heterogeneous core with the highest security permission. Once the write permission of the storage medium is occupied by a certain heterogeneous core, other heterogeneous cores cannot write data to the storage medium, thereby ensuring the uniqueness of the write permission of the storage medium, greatly improving the write security of the storage medium, effectively avoiding the possibility of tampering with firmware, and further improving system security.

[0054] The technical solutions of the embodiments of the present application will be described in detail below with reference to the drawings.

[0055] As shown in Figure 1 FIG. 1 is a structural schematic diagram of a controller provided by an embodiment of the present application. The controller includes a plurality of heterogeneous cores 10, which can be connected with a storage medium 20. The plurality of heterogeneous cores 10 can include a first heterogeneous core 101, a second heterogeneous core 102, and other heterogeneous cores 103. The second heterogeneous core 102 or the other heterogeneous cores 103 can perform inter-core communication with the first heterogeneous core 101.

[0056] The first heterogeneous core 101 is the heterogeneous core with the highest security permission in the plurality of heterogeneous cores 10. The other heterogeneous cores 103 can be heterogeneous cores other than the first heterogeneous core 101 and the second heterogeneous core 102.

[0057] It can be understood that the first heterogeneous core 101 and the second heterogeneous core 102 are different in type, specifically, different in architecture, function, or performance characteristics.

[0058] The other heterogeneous cores 103 are different from the second heterogeneous core 102 in that the second heterogeneous core 102 is the heterogeneous core currently initiating the first request, and the other heterogeneous cores 103 are the heterogeneous cores that can initiate the first request but have not initiated the first request.

[0059] In addition, it can be understood that the other heterogeneous cores 103 can be the same in type as the second heterogeneous core 102. Specifically, the other heterogeneous cores 103 and the second heterogeneous core 102 are the same in architecture, function, or performance characteristics.

[0060] In a possible implementation, the first heterogeneous core 101 is the heterogeneous core with the highest security permission. The security permission of the second heterogeneous core 102 or the other heterogeneous cores 103 is lower than that of the first heterogeneous core 101.

[0061] The second heterogeneous core 102 can send the first request to the first heterogeneous core 101. As shown in Figure 1 The second heterogeneous core 102 can send the first request to the first heterogeneous core 101. The first request is used to request writing of data.

[0062] The first heterogeneous core 101 can execute the writing control method of the storage medium provided by an embodiment of the present application, such as receiving the first request sent by the second heterogeneous core 102 and sending a first reset signal to the storage medium 20. The first reset signal is used to trigger the storage medium to release the write protection. The first heterogeneous core 101 starts the write protection of the storage medium 20 in a case where it is determined that the second heterogeneous core 102 writes data into the storage medium.

[0063] During the data writing of the second heterogeneous core 102 to the storage medium, the other heterogeneous core 103 can no longer acquire the write permission of the storage medium 20 and write data to the storage medium 20.

[0064] Optionally, the controller can be a BMC (Baseboard Management Controller).

[0065] In the embodiments of the present application, the first heterogeneous core with the highest security permission is used to release and restore the write protection of the storage medium, so that the write permission of the storage medium is concentrated on the first heterogeneous core, avoiding the write permission of the storage medium being scattered, and further improving the write security of the storage medium.

[0066] As shown in FIG. 1, a flowchart of a write control method of a storage medium is provided in the embodiments of the present application. The method can include the following steps: Figure 2 S201, the first heterogeneous core acquires a first request sent by a second heterogeneous core in the case that the storage medium is under write protection, the first request being used to request writing data. The first heterogeneous core and the second heterogeneous core are of different types.

[0067] In a possible implementation, the first heterogeneous core refers to the heterogeneous core with the highest security permission, and the first heterogeneous core can be referred to as a secure core. The second heterogeneous core is any heterogeneous core except the first heterogeneous core among the plurality of heterogeneous cores. The security permission of the second heterogeneous core is lower than that of the first heterogeneous core. Optionally, the controller can include a plurality of heterogeneous cores, and each heterogeneous core can be provided with a corresponding security permission. The security permissions of different heterogeneous cores can be the same or different.

[0068] For example, a plurality of security permissions can be preset, and each heterogeneous core can be provided with any one of the plurality of security permissions. For example, three security permissions can be preset, i.e., a first security permission, a second security permission and a third security permission, and the permission levels are from high to low, i.e., the first security permission is the highest, and the third security permission is the lowest.

[0069] The security permission of the first heterogeneous core can be the highest level permission, such as the first security permission. The second heterogeneous core can be the second security permission or the third security permission. The other heterogeneous cores can be the second security permission or the third security permission.

[0070] ​Furthermore, the security coefficients corresponding to multiple heterogeneous cores can be obtained, and the heterogeneous core with the highest security coefficient can be identified as the first heterogeneous core. The security permissions of the first heterogeneous core can then be set to the highest level. The security coefficients of each heterogeneous core can be determined through dimensions such as the isolation level of the heterogeneous core, the strictness of permission management, and the security of inter-core communication. For details, please refer to the relevant technical documentation, which will not be elaborated upon here.

[0071] To facilitate communication between heterogeneous cores, shared memory can be configured between them to enable communication.

[0072] like Figure 3 The diagram shown is an example of a communication scenario with multiple heterogeneous cores. (Reference) Figure 3 The first heterogeneous core 301 and other heterogeneous cores 302 can perform inter-core communication through shared memory 303. For example, other heterogeneous cores 302 can send a TX (Transmit) signal to shared memory 303, and the first heterogeneous core 301 can read the TX signal from shared memory 303. Similarly, the first heterogeneous core 301 can send an RX signal to shared memory 303, and other heterogeneous cores can read the RX signal from shared memory 303. The first request can, for example, be a TX signal, enabling the first heterogeneous core to receive the first request.

[0073] Therefore, in Figure 3 Based on the illustrated embodiment, the first request is sent from the second heterogeneous core to the shared memory. Obtaining the first request sent by the second heterogeneous core includes: Read the first request sent by the second heterogeneous core from shared memory.

[0074] In this embodiment, communication between two heterogeneous cores is accomplished using shared memory, which enables direct data interaction. This reduces the communication difficulty between heterogeneous cores with different architectures, decreases data transmission difficulty, significantly reduces cross-core communication latency, and ultimately achieves efficient and flexible information transmission between heterogeneous cores, thereby improving information transmission efficiency.

[0075] S202, the first heterogeneous core sends a first reset signal to the storage medium, the first reset signal being used to trigger the storage medium to release write protection.

[0076] Optionally, the storage medium may include, but is not limited to, at least one of the following: EMMC, UFS, NorFlash.

[0077] It should be understood that before the first heterogeneous core sends the first reset signal to the storage medium, the storage medium is in a power-on protection state. In this state, no heterogeneous core can write input to the storage medium. After the first heterogeneous core sends the first reset signal to the storage medium, the storage medium can be de-protected by the first reset signal.

[0078] Optionally, the write protection of the storage medium can refer to the power-on write protection of the storage medium, that is, the write protection of the storage medium is realized by hardware circuit or firmware control. If the storage medium does not receive a reset signal, writing data is prohibited. If the storage medium receives a reset signal, power-on is triggered, the write protection is released, and data can be written.

[0079] In a possible design, the storage medium body can include a reset pin, and the first heterogeneous core sending a first reset signal to the storage medium can include: the first heterogeneous core sending the first reset signal to the reset pin of the storage medium. The first heterogeneous core and the storage medium can agree on the first reset signal in advance. If sending the first reset signal refers to sending a high-level signal to the reset pin of the storage medium. Alternatively, a low-level signal is sent to the reset pin of the storage medium instead of a high-level signal.

[0080] S203, the first heterogeneous core starts write protection of the storage medium in a case where data writing of the second heterogeneous core to the storage medium is completed.

[0081] Optionally, the first heterogeneous core starting the write protection of the storage medium can include: the first heterogeneous core sending a write protection signal to the storage medium and reconfiguring a write protection register of the storage medium to start the write protection of the storage medium. Correspondingly, the storage medium can receive the write protection signal sent by the first heterogeneous core, and start the write protection according to the write protection signal and the write protection register.

[0082] In a possible design, the storage medium body can include a write protection pin. The first heterogeneous core sending a write protection signal to the storage medium can include: the first heterogeneous core sending the write protection signal to the write protection pin of the storage medium. The first heterogeneous core and the storage medium can agree on the write protection signal in advance. If sending the first reset signal refers to sending a high-level signal to the write protection pin of the storage medium, or a low-level signal is sent to the write protection pin of the storage medium instead of a high-level signal.

[0083] Of course, the first reset signal or the write protection signal can also refer to a pre-set signal. In addition to the hardware signal described above, the first reset signal or the write protection signal can also be a software signal.

[0084] The write protection register address is 0x00001, and the reset signal register address is 0x00002.

[0085] Sending the first reset signal to the storage medium can refer to writing 1 to the register address 0x00002 of the reset signal of the storage medium, and then triggering the storage medium to read the data "1" in the register address 0x00002. The storage medium determines that the first reset signal is received.

[0086] The reconfiguring the write protection register of the storage medium can refer to writing 1 to the address 0x00001 of the write protection register of the storage medium, and then triggering the storage medium to read the data "1" in the address 0x00001 of the write protection register, so that the storage medium determines that the write protection register indicates write protection.

[0087] Of course, the above signal setting manners by software or hardware are only exemplary and do not constitute specific limitations.

[0088] In the embodiment of the application, when there are multiple heterogeneous cores in the controller, whether the write protection of the storage medium is released is controlled by the first heterogeneous core. That is, the first heterogeneous core receives the first request sent by the second heterogeneous core when the storage medium is in the write protection state, and the first request is used to request to write data. In order to solve the write protection of the storage medium, a first reset signal can be sent to the storage medium to trigger the storage medium to release the write protection. Once the write protection of the storage medium is released, the data of the second heterogeneous core can be written into the storage medium, so as to ensure the uniqueness of the write permission of the storage medium. When it is determined that the second heterogeneous core completes the data writing to the storage medium, the write protection of the storage medium is started, so that the storage medium restores the write protection. The write protection of the storage medium is triggered to release and restore by the first heterogeneous core, which greatly improves the write security of the storage medium, effectively avoids the possibility of tampering with the firmware, and further improves the system security.

[0089] In a possible design, the first heterogeneous core sending the first reset signal to the storage medium can include: sending the first reset signal to the storage medium through a first interface, and the first interface is a GPIO interface between the first heterogeneous core and the storage medium.

[0090] For example, the first interface can be a GPIO interface. The first reset signal can be a RST (Reset Signal, reset signal).

[0091] Further, the first interface can be a GPIO interface that can only be accessed by the first heterogeneous core, so as to ensure that only the first heterogeneous core can send the first reset signal.

[0092] For example, the RST signal can be a high-level signal, and the first heterogeneous core sends the RST signal to the first interface. The storage medium detects the RST signal, so as to determine that the first heterogeneous core sends the first reset signal, and thus the write protection is released.

[0093] In the embodiment of the application, by setting the first interface between the first heterogeneous core and the storage medium, a dedicated communication channel of the first heterogeneous core and the storage medium is realized, which can ensure that the release of the write protection of the storage medium can only be triggered by the first heterogeneous core, and further improve the write security of the storage medium.

[0094] In yet another possible design, the first request includes check data, and sending the first reset signal to the storage medium includes: checking the check data in the first request to obtain a check result; and sending the first reset signal to the storage medium if the check result is a check success.

[0095] As shown in Figure 4 , a first request message structure diagram provided by an embodiment of the present application.

[0096] Referring to Figure 4 , the first request can include: cmd (Command, communication instruction) 401, subcmd (Subcommand, sub-instruction) 402, check algorithm 403, data length 404, check data length 405, data 406, and check data 407.

[0097] The cmd 401 is a main command related header information, and the subcmd 402 is a sub-command related header information. The check algorithm 403 is an algorithm that needs to be used in data checking. The data length 404 is the length of the data 406. The check data length 405 is the length of the check data 407. The data 406 is the data to be stored. The check data 407 is the data participating in the security check, such as CRC (Cyclic Redundancy Check) check data.

[0098] It should be understood that the first request is used to request to write data. The main command indicated by the cmd 401 is to request to write data.

[0099] In the embodiment of the present application, the check data in the first request is checked to obtain a check result, and if the check result is a check success, the second heterogeneous core passes the security check, and the first heterogeneous core can send the first reset signal to the storage medium, so as to configure the write permission of the storage medium to the second heterogeneous core. The heterogeneous core that obtains the write permission of the storage medium needs to pass the security check, which further guarantees the write security of the storage medium.

[0100] Further, the method further includes: sending a check failure prompt information to the second heterogeneous core if the check result is a check failure.

[0101] The check process of the check data can refer to the description of related technologies, and will not be described here.

[0102] In the embodiment of the present application, if the verification result is a verification failure, it indicates that the second heterogeneous core fails to pass the security verification, the first heterogeneous core no longer sends the first reset signal, and the second heterogeneous core cannot obtain the write permission of the storage medium in the case of security risk, thereby further ensuring the write security of the storage medium. If the verification fails, the first heterogeneous core can also send prompt information of the verification failure to the second heterogeneous core, which can timely prompt the second heterogeneous core of the verification failure and the security vulnerability, so that the second heterogeneous core responds in time to avoid more system vulnerabilities and further improve the system operation security.

[0103] Based on Figure 1 As shown in the application scenario, after the write protection of the storage medium is released, the first heterogeneous core or the second heterogeneous core can obtain the write permission of the storage medium to write the data of the second heterogeneous core to the storage medium. When the data of the second heterogeneous core is written to the storage medium, there can be two cases. Case 1: In the case that the second heterogeneous core obtains the write permission of the storage medium, the data of the second heterogeneous core is written to the storage medium by the second heterogeneous core.

[0104] Based on the scenario of case 1, the following Figure 5 An example diagram of a storage medium write control method provided by an embodiment of the present application is shown, referring to Figure 5 , which can specifically include the following steps: S501, the second heterogeneous core sends a first request to the first heterogeneous core. Correspondingly, the first heterogeneous core receives the first request sent by the second heterogeneous core.

[0105] S502, the first heterogeneous core sends a first reset signal to the storage medium.

[0106] S503, the storage medium releases the write protection under the triggering of the first reset signal.

[0107] S504, the second heterogeneous core writes data to the storage medium.

[0108] Optionally, before the second heterogeneous core performs S504, it further includes determining to obtain the write permission of the storage medium.

[0109] Optionally, after the first heterogeneous core sends the first reset signal to the storage medium, it sends a reset signal to other heterogeneous cores, and the second reset signal is used to instruct other heterogeneous cores to suspend.

[0110] The data of the second heterogeneous core is written to the storage medium by the second heterogeneous core.

[0111] Optionally, in the case that the second heterogeneous core obtains the write permission of the storage medium, the data of the second heterogeneous core is written to the storage medium by the second heterogeneous core.

[0112] It can be understood that the write permission of the storage medium is monopolized by the second heterogeneous core at this time, and suspending other heterogeneous cores can avoid other heterogeneous cores from impacting the write permission of the storage medium by the second heterogeneous core, a permission occupation conflict, eliminating the risk of data writing of the second heterogeneous core, consolidating the uniqueness of the write permission of the second heterogeneous core, and providing safer access control for the storage medium.

[0113] The second heterogeneous core determining to obtain the write permission of the storage medium can include: in a case where the second heterogeneous core determines that the reset result sent by the first heterogeneous core is that the write permission of the storage medium has been obtained, the second heterogeneous core determines to obtain the write permission of the storage medium.

[0114] In a possible design, the reset result can be sent to the second heterogeneous core in the form of software or hardware.

[0115] For example, the reset result is sent in the form of hardware. The second heterogeneous core can set a reset result pin, and if the first heterogeneous core sends a high level to the reset result pin, it is determined that the write permission of the storage medium is obtained.

[0116] For example, the reset result is sent in the form of software. The first heterogeneous core and the second heterogeneous core can agree on a reset result command or signal in advance, such as a reset result signal or command being 1, which indicates that the write permission of the storage medium has been obtained, and a reset result signal or command being 0, which indicates that the write permission of the storage medium has not been obtained. After the second heterogeneous core receives the reset result signal or command, it can determine whether to obtain the write permission of the storage medium according to the value of the reset result signal or command.

[0117] In the embodiments of the present application, when there are multiple heterogeneous cores in the controller, the first heterogeneous core with the highest security permission controls the write permission of the storage medium. That is, the first heterogeneous core receives the first request sent by the second heterogeneous core, and under the action of the first request, sends a first reset signal to the storage medium to trigger the storage medium to release the write protection and obtain the access permission of the storage medium for the second heterogeneous core. Once the write permission of the storage medium is occupied by the second heterogeneous core, other heterogeneous cores cannot write data to the storage medium, thereby ensuring the uniqueness of the write permission of the storage medium, greatly improving the write security of the storage medium, effectively avoiding the possibility of firmware tampering, and further improving system security.

[0118] Case 2: In a case where the first heterogeneous core obtains the write permission of the storage medium, the data of the second heterogeneous core is written to the storage medium by the first heterogeneous core.

[0119] Based on the scenario of case 2, the following Figure 6 Another example of a storage medium write control method provided by the embodiments of the present application is shown in FIG. 6. Referring to FIG. 6, Figure 6may specifically include the following steps: S601, the second heterogeneous core sends a first request to the first heterogeneous core. Correspondingly, the first heterogeneous core receives the first request sent by the second heterogeneous core.

[0120] S602, the first heterogeneous core sends a first reset signal to the storage medium.

[0121] S603, the storage medium cancels the write protection under the triggering of the first reset signal.

[0122] S604, the first heterogeneous core sends the data of the second heterogeneous core to the storage medium, so as to write the data of the second heterogeneous core into the storage medium.

[0123] Optionally, the data of the second heterogeneous core can be carried in the first request. In this case, the first heterogeneous core obtains the data of the second heterogeneous core parsed from the first request.

[0124] Optionally, before the first heterogeneous core performs S604, the first heterogeneous core further includes determining to obtain the write permission of the storage medium. The second heterogeneous core sends data to the first heterogeneous core, and the data is the data to be written into the storage medium. Correspondingly, the first heterogeneous core receives the data sent by the second heterogeneous core.

[0125] In a possible design, a second reset signal is sent to the second heterogeneous core, and the second reset signal is used to instruct the second heterogeneous core to suspend and instruct the second heterogeneous core to notify other heterogeneous cores to suspend.

[0126] Alternatively, a second reset signal is sent to the first heterogeneous core and other heterogeneous cores.

[0127] The data of the second heterogeneous core is written into the storage medium by the first heterogeneous core.

[0128] Optionally, in the case where the first heterogeneous core obtains the write permission of the storage medium, the data of the second heterogeneous core is written into the storage medium by the first heterogeneous core.

[0129] It can be understood that the write permission of the storage medium is exclusively occupied by the first heterogeneous core, and suspending each second heterogeneous core can avoid the second heterogeneous cores from impacting the write permission of the storage medium by the first heterogeneous core, and can avoid the conflict of the write permission, eliminate the risk of writing the data of the second heterogeneous core, and consolidate the uniqueness of the write permission of the first heterogeneous core, so as to provide safer access control for the storage medium.

[0130] It should be understood that the other heterogeneous cores can include one or more. The write permission of the storage medium being locked can mean that the write permission of the storage medium has been locked by the second heterogeneous core, and the other heterogeneous cores cannot occupy the write permission of the storage medium any more, so as to ensure the uniqueness of the write permission of the storage medium.

[0131] In a possible design, the second reset signal can be an RST signal.

[0132] As shown in Figure 7 FIG. 1 shows an example diagram of storage medium occupation release provided by an embodiment of the present application.

[0133] The first heterogeneous core 101 can perform 701: sending a second reset signal to the second heterogeneous core 102 and other heterogeneous cores 103 respectively. The second reset signal is used to instruct the second heterogeneous core 102 and the other heterogeneous cores 103 to suspend.

[0134] Of course, when the hardware lock 30 exists between the first heterogeneous core 101 and the storage medium 20, the first heterogeneous core 101 can still perform: sending the second reset signal to the second heterogeneous core 102 and the other heterogeneous cores 103 respectively.

[0135] In yet another possible design, the second reset signal is sent to the second heterogeneous core, and the second reset signal is used to instruct the second heterogeneous core to suspend and instruct the second heterogeneous core to notify the other heterogeneous cores to suspend. That is, the second reset signal is further sent to the other heterogeneous cores by the second heterogeneous core.

[0136] As shown in Figure 8 FIG. 2 shows another example diagram of storage medium occupation release provided by an embodiment of the present application.

[0137] The first heterogeneous core 101 can perform 801: sending a second reset signal to the second heterogeneous core 102, and the second heterogeneous core 102 can perform 802: sending the second reset signal to the other heterogeneous cores 103. The second reset signal is used to instruct the second heterogeneous core 102 to release the occupation of the write permission of the storage medium 20, and instruct the other heterogeneous cores 103 to release the occupation of the write permission of the storage medium 20.

[0138] Of course, when the hardware lock 30 exists between the first heterogeneous core 101 and the storage medium 20, the first heterogeneous core 101 can still perform: sending the second reset signal to the second heterogeneous core 102 first, and then sending the second reset signal to the other heterogeneous cores by the second heterogeneous core.

[0139] In the embodiment of the present application, before sending the first reset signal to the storage medium to release the write protection of the storage medium, the second reset signal is sent to the other heterogeneous cores to trigger the other heterogeneous cores to release the occupation of the storage medium, so that the storage medium is in the write protection, the write permission of the storage medium is in the unoccupied state, the concurrent conflict after the write protection is released is avoided, the obstacle for the subsequent permission allocation of the storage medium is cleared, the potential conflict and interference are eliminated from the root, and the executability of the subsequent operation of the storage medium is consolidated, and the storage medium is provided with safer access control.

[0140] Optionally, the second heterogeneous core can resend the data to be written to the first heterogeneous core, or the data can be carried in the first request. For example... Figure 4 As shown, the data 406 in the first request can be, for example, the data of the second heterogeneous core.

[0141] In this embodiment, when the controller has multiple heterogeneous cores, the write access to the storage medium is controlled by the first heterogeneous core with the highest security privileges. Specifically, the first heterogeneous core receives a first request from the second heterogeneous core and, under the action of the first request, sends a first reset signal to the storage medium to trigger the storage medium to release write protection and grant the second heterogeneous core access to the storage medium. Since the first heterogeneous core completes the writing of the data to be stored by the second heterogeneous core, the write access of the second heterogeneous core is further restricted, effectively improving the write security of the storage medium.

[0142] like Figure 9 The diagram shown is yet another structural schematic of a controller provided in an embodiment of this application, and... Figure 1 The difference in the controller shown is that a hardware lock 30 is also provided between the first heterogeneous core 101 and the storage medium 20. The hardware lock 30 refers to the component that controls the write enable of the storage medium.

[0143] Furthermore, before the first heterogeneous core 101 sends the first reset signal to the storage medium 20, it also includes: A configuration command is sent to hardware lock 30, indicating that hardware lock 30 is occupied by the first heterogeneous core or the second heterogeneous core.

[0144] In this configuration, either the first heterogeneous core or the second heterogeneous core obtains write access to the storage medium via a hardware lock.

[0145] In this embodiment, a hardware lock located between the first heterogeneous core and the storage medium is used to further control the write permissions of the memory. By utilizing the physical characteristics of the hardware lock, physical control over the write permissions of the storage medium is achieved, which physically eliminates concurrent access conflicts caused by permission contention between different heterogeneous cores, thereby further improving the access security and stability of the storage medium.

[0146] based on Figure 9 In the application scenario shown, when hardware lock 30 is occupied by the second heterogeneous core 102, the second heterogeneous core 102 obtains write access to the storage medium. The second heterogeneous core 102 can then perform data write operations on the storage medium through hardware lock 30. When the second heterogeneous core 102 writes data to the storage medium 20, two scenarios can occur. Case 3: When the hardware lock 30 is occupied by the second heterogeneous core 102, the data of the second heterogeneous core 102 is written to the storage medium 20 by the second heterogeneous core 102 through the hardware lock 30.

[0147] Based on the scenario of case 3, the following Figure 10 An example diagram of a write control method of a storage medium provided by an embodiment of the application is shown, referring to Figure 10 , which can specifically include the following steps: S1001, the second heterogeneous core sends a first request to the first heterogeneous core. Accordingly, the first heterogeneous core receives the first request sent by the second heterogeneous core.

[0148] S1002, the first heterogeneous core sends a configuration instruction to the hardware lock. The configuration instruction instructs the hardware lock 30 to be occupied by the second heterogeneous core, and the second heterogeneous core obtains the write permission of the storage medium through the hardware lock.

[0149] S1003, the first heterogeneous core sends a first reset signal to the storage medium.

[0150] S1004, the storage medium is triggered by the first reset signal to remove the write protection.

[0151] S1005, the second heterogeneous core writes data to the storage medium through the hardware lock.

[0152] Optionally, the first heterogeneous core can allocate the write permission of the storage medium to the second heterogeneous core, and control the second heterogeneous core to occupy the hardware lock. Before the second heterogeneous core sends data to the first heterogeneous core, it further includes: the second heterogeneous core determines to obtain the write permission of the storage medium, and occupies the use permission of the hardware lock.

[0153] In the embodiment of the application, when there are multiple heterogeneous cores in the controller, the first heterogeneous core with the highest security permission is used to control the write permission of the storage medium. That is, the first heterogeneous core receives the first request sent by the second heterogeneous core, and under the action of the first request, first sends a configuration instruction to the hardware lock, and then sends a first reset signal to the storage medium, which not only releases the write function of the hardware lock to the storage medium, but also triggers the storage medium to remove the write protection, so that the second heterogeneous core obtains the access permission of the storage medium. The coordinated control of the hardware lock and the storage medium realizes the physical control of the write permission of the storage medium, which eliminates the concurrent access conflict caused by the permission contention of different heterogeneous cores from the physical layer, and further improves the access security and stability of the storage medium. After the second heterogeneous core determines to obtain the write permission of the storage medium, it can perform data write on the storage medium, thereby ensuring the uniqueness of the write permission of the storage medium, greatly improving the write security of the storage medium, effectively avoiding the possibility of firmware tampering, and further improving the system security.

[0154] Case 4, in the case where the hardware lock 30 is occupied by the first heterogeneous core 101, the data of the second heterogeneous core 102 is written to the storage medium 20 by the first heterogeneous core 101 through the hardware lock 30.

[0155] Based on the scenario of case 4, the following Figure 11 An example diagram of a write control method of a storage medium provided by an embodiment of the application is shown, referring to Figure 11 , which can specifically include the following steps: S1101, the second heterogeneous core sends a first request to the first heterogeneous core. Correspondingly, the first heterogeneous core receives the first request sent by the second heterogeneous core.

[0156] S1102, the first heterogeneous core sends a configuration instruction to the hardware lock. The configuration instruction instructs the hardware lock 30 to be occupied by the second heterogeneous core, and the second heterogeneous core obtains the write permission of the storage medium through the hardware lock.

[0157] S1103, the first heterogeneous core sends a first reset signal to the storage medium.

[0158] S1104, the storage medium releases the write protection under the triggering of the first reset signal.

[0159] S1105, the first heterogeneous core sends the data of the second heterogeneous core to the hardware lock, so that the hardware lock forwards the data of the second heterogeneous core to the storage medium, so that the storage medium stores the data of the second heterogeneous core.

[0160] Optionally, before the first heterogeneous core sends the data of the second heterogeneous core to the hardware lock, the first heterogeneous core further occupies the access permission of the storage medium and the use permission of the hardware lock.

[0161] Optionally, the second heterogeneous core can resend the to-be-stored data to the first heterogeneous core, or the to-be-stored data can be carried in the first request. As Figure 4 shown, the data 406 in the first request can be, for example, the data to be stored by the second heterogeneous core.

[0162] In the embodiment of the application, when there are multiple heterogeneous cores in the controller, the first heterogeneous core with the highest security permission is used to control the write permission of the storage medium. That is, the first heterogeneous core receives the first request sent by the second heterogeneous core, and under the action of the first request, first sends a configuration instruction to the hardware lock, and then sends a first reset signal to the storage medium, which not only releases the write function of the hardware lock to the storage medium, but also triggers the storage medium to release the write protection, so that the second heterogeneous core obtains the access permission of the storage medium. The cooperative control of the hardware lock and the storage medium realizes the physical control of the write permission of the storage medium, which eliminates the concurrent access conflict caused by the permission contention of different heterogeneous cores from the physical layer, and further improves the access security and stability of the storage medium. The first heterogeneous core and the hardware lock also complete the writing of the data of the second heterogeneous core, which further limits the write permission of the second heterogeneous core and effectively improves the write security of the storage medium.

[0163] As above, during the write permission of the storage medium is occupied by the second heterogeneous core, other heterogeneous cores cannot perform data write operation on the storage medium. In a possible design, during the write permission of the storage medium is occupied by the second heterogeneous core, further comprising: obtaining a second request sent by other heterogeneous cores, the other heterogeneous cores being the second heterogeneous cores other than the heterogeneous core occupying the write permission of the storage medium; sending an occupation prompt to the other heterogeneous cores, the occupation prompt being used to prompt the other heterogeneous cores that the write permission of the storage medium has been occupied.

[0164] Optionally, the message structure of the second request can be the same as that of the first request. The same message structure can specifically mean that the data types in the messages are the same. However, the message content of the second request is different from that of the first request, for example, the check data in the second request is different from that in the first request. The data in the second request is also different from that in the first request. Of course, the above different message contents are only exemplary and do not constitute specific limitation.

[0165] In the embodiment of the application, during the write permission of the storage medium is occupied by the second heterogeneous core, if the second request sent by other heterogeneous cores is received again, an occupation prompt is sent to the other heterogeneous cores, the occupation prompt being used to prompt the other heterogeneous cores that the write permission of the storage medium has been occupied, and the other heterogeneous cores cannot obtain the write permission of the storage medium temporarily. The write permission of the storage medium is unique, that is, only one heterogeneous core can occupy the write permission in a period. Through the occupation prompt of the heterogeneous core, the other heterogeneous cores can be processed in time, and occupation conflict can be avoided.

[0166] In a possible implementation, after determining that the second heterogeneous core completes data write on the storage medium, the write protection of the storage medium is started, and further comprising: sending a notification signal to the other heterogeneous cores, the notification signal being used to notify the other heterogeneous cores that the write permission of the storage medium can be obtained.

[0167] Optionally, the notification signal is 1, indicating that the other heterogeneous cores can obtain the write permission of the storage medium. The notification signal is 0, indicating that the other heterogeneous cores cannot obtain the write permission of the storage medium.

[0168] In the embodiment of the application, after determining that the second heterogeneous core completes input write on the storage medium, the write protection of the storage medium is started, and a notification signal can be sent to the other heterogeneous cores. The notification signal is used to notify the other heterogeneous cores that the write permission of the storage medium can be obtained, and timely remind the other heterogeneous cores that the write permission of the storage medium can be obtained for a long time, so as to avoid disorder competition and realize ordered management of the write permission of the storage medium.

[0169] As Figure 12As shown, a schematic diagram of a controller is provided. The controller 1201 may include: a first heterogeneous core 12011, a second heterogeneous core 12012, and other heterogeneous cores 12013. The other heterogeneous cores 12013 may be heterogeneous cores other than the first heterogeneous core 12011 and the second heterogeneous core 12012.

[0170] Optionally, the controller 1201 can be connected to the storage medium 1202. The storage medium 1202 can be located on the controller 1201 or on another substrate. For example, if the controller 1201 is a BMC, the storage medium 1202 can be located on the BMC or on another substrate.

[0171] As an example, the first heterogeneous core 12011 can execute: When the storage medium is under write protection, the first heterogeneous core receives a first request sent by the second heterogeneous core. The first request is used to request the writing of data. The first heterogeneous core and the second heterogeneous core are of different types. The first reset signal is sent to the storage medium to trigger the storage medium to release write protection. When the data of the second heterogeneous core is written to the storage medium, write protection of the storage medium is activated.

[0172] As another embodiment, the first heterogeneous core 12011 sends a first reset signal to the storage medium, specifically including: A first reset signal is sent to the storage medium through the first interface, which is a general-purpose input / output (GPIO) interface between the first heterogeneous core and the storage medium.

[0173] As another embodiment, the first heterogeneous core is the heterogeneous core with the highest security privileges.

[0174] As another embodiment, a hardware lock is provided between the first heterogeneous core and the storage medium. For example... Figure 13 As shown, another structural diagram of a controller is provided, which is similar to... Figure 12 The difference lies in that, optionally, the controller 1201 may also include a hardware lock 1203 connected to the first heterogeneous core 12011, and the hardware lock 1203 is connected to the storage medium 1202. A hardware lock refers to a component that controls the write enable of the storage medium.

[0175] The first heterogeneous core 12011 is also used to execute: Send a configuration command to the hardware lock, which indicates that the hardware lock is occupied by the second heterogeneous core or the first heterogeneous core; When the hardware lock is occupied by the first heterogeneous core, the data of the second heterogeneous core is written to the storage medium by the first heterogeneous core through the hardware lock; When the hardware lock is occupied by the second heterogeneous core, the data of the second heterogeneous core is written to the storage medium by the second heterogeneous core through the hardware lock.

[0176] As a further example, the first heterogeneous core is further configured to perform: send a second reset signal to the second heterogeneous core, the second reset signal being configured to instruct the second heterogeneous core to suspend and instruct the second heterogeneous core to notify other heterogeneous cores to suspend.

[0177] Or, send the second reset signal to the second heterogeneous core and the other heterogeneous cores, the second reset signal being configured to control the second heterogeneous core and the other heterogeneous cores to suspend.

[0178] Data of the second heterogeneous core is written into the storage medium by the first heterogeneous core.

[0179] As a further example, the first heterogeneous core is further configured to perform: send a second reset signal to the other heterogeneous cores, the second reset signal being configured to instruct the other heterogeneous cores to suspend.

[0180] Data of the second heterogeneous core is written into the storage medium by the second heterogeneous core.

[0181] As a further example, the first request includes verification data, and the first heterogeneous core 12011 sends the first reset signal to the storage medium, specifically including: verify the verification data in the first request to obtain a verification result; if the verification result is verification success, send the first reset signal to the storage medium.

[0182] As a further example, the first heterogeneous core 12011 is further configured to perform: if the verification result is verification failure, send prompt information of the verification failure to the second heterogeneous core.

[0183] As a further example, the first request is sent to the shared memory by the second heterogeneous core, and the first heterogeneous core 12011 obtains the first request sent by the second heterogeneous core, specifically including: read the first request sent by the second heterogeneous core from the shared memory.

[0184] As a further example, the first heterogeneous core 12011 is further configured to perform: obtain to-be-stored data required by the second heterogeneous core to be stored in the storage medium; send the to-be-stored data to the storage medium, so that the storage medium stores the to-be-stored data.

[0185] As a further example, during the write permission of the storage medium is occupied by the second heterogeneous core, the first heterogeneous core 12011 is further configured to perform: obtain a second request sent by the other heterogeneous core 12013; send an occupation prompt to the other heterogeneous core 12013, the occupation prompt being configured to prompt the other heterogeneous core 12013 that the write permission of the storage medium has been occupied.

[0186] As a further example, the first heterogeneous core 12011 is further configured to perform: sending a notification signal to the other heterogeneous core 12013, the notification signal being used to notify the other heterogeneous core 12013 that the write permission of the storage medium can be acquired.

[0187] It should be understood that the communication apparatus herein is embodied in the form of functional units. The term "unit" herein can refer to an application specific integrated circuit (ASIC), an electronic circuit, a controller (for example, a shared controller, a dedicated controller, or a group controller, etc.) and a storage medium for executing one or more software or firmware programs, a combination logic circuit, and / or other suitable components supporting the described functions.

[0188] In an optional example, the communication apparatus can be specifically the first processing unit or the second processing unit in the above-described embodiments, and the communication apparatus can be configured to perform the respective processes and / or steps corresponding to the first processing unit or the second processing unit in the above-described method embodiments. To avoid repetition, details are not described herein.

[0189] The communication apparatus of each of the above-described solutions has the function of implementing the respective steps performed by the first processing unit or the second processing unit in the above-described methods. The above-described functions can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described functions.

[0190] In the embodiments of the present application, Figure 12 or Figure 13 The controller in the above-described embodiments can also be a chip or a chip system, for example, a system on chip (SoC) or a BMC substrate.

[0191] Figure 14 The present application provides a hardware block diagram of a computing device. The computing device 1400 according to the embodiments of the present application at least includes a storage medium 1401 and a controller 1402, the storage medium 1401 is used to store a computer program, and the controller 1402 includes a plurality of heterogeneous cores, such as a first heterogeneous core 14021 and a second heterogeneous core 14022 and other heterogeneous cores 14023, the first heterogeneous core 14021 in the controller 1402 is used to execute the computer program to implement the write control method of the storage medium in any of the above-described embodiments.

[0192] In addition, the storage medium 1401 and the controller 1402 are electrically connected with a bus 1403. The computing device 1400 can further include a hardware lock 1404 connected with the bus 1403, and the hardware lock 1404 can be located between the first heterogeneous core and the storage medium 1401.

[0193] Further, the embodiment of the present application provides a computer readable storage medium for storing a computer program. The computer program is executed by the first heterogeneous core of the controller to implement the write control method of the storage medium according to any one of the preceding embodiments of the present application.

[0194] The computer readable storage medium includes, but is not limited to, for example, volatile storage medium and / or non-volatile storage medium. The volatile storage medium may, for example, include random access memory (RAM) and / or cache memory, etc. The non-volatile storage medium may, for example, include read only memory (ROM), hard disk, flash memory, optical disc, magnetic disc, etc.

[0195] The embodiment of the present application further provides a computer program product, including computer program / instruction, which is executed by the first heterogeneous core of the controller to implement the write control method of the storage medium according to any one of the preceding embodiments of the present application.

[0196] The above describes the basic principles of the embodiments of the present application in combination with specific embodiments, but it should be noted that the advantages, advantages, effects, etc. mentioned in the embodiments of the present application are only examples and are not limited, and these advantages, advantages, effects, etc. cannot be considered as the must-have of each embodiment of the present application. In addition, the above specific details are only for the purpose of example and for the purpose of understanding, and are not limited to the above specific details. The above specific details do not limit the embodiments of the present application to be implemented by the above specific details.

[0197] The block diagrams of the devices, apparatuses, equipment, systems involved in the embodiments of the present application are only illustrative examples and are not intended to require or imply that the connection, arrangement, configuration must be as shown in the block diagram. As those skilled in the art will recognize, these devices, apparatuses, equipment, systems can be connected, arranged, configured in any way. Words such as "include", "contain", "have", etc. are open-ended words, mean "include but not limited to", and can be used interchangeably. The words "or" and "and" used herein mean the word "and / or", and can be used interchangeably unless the context clearly indicates otherwise. The word "such as" used herein means the phrase "such as but not limited to", and can be used interchangeably.

[0198] In addition, as used herein, "or" used in the list of items starting with "at least one of indicates a separate list, so that, for example, "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e. A and B and C). In addition, the phrase "exemplary" does not mean that the described example is preferred or better than other examples.

[0199] It is also important to note that the systems and methods described in the embodiments of the present application can be capable of considerable variation and that the embodiments are thus not limited to what is described in the foregoing description. Rather, other alternative, modified and equivalent aspects can be used and practices within the scope of the described embodiments. Accordingly, the terms "comprises", "comprising", "includes", "including", "has", "having", "contains", "containing" or variants thereof are intended to mean a non-exclusive inclusion.

[0200] Various changes, modifications and alterations to the techniques described herein can be made without departing from the teachings of the attached claims. Moreover, the scope of the claims should not be limited to the particular aspects described in the embodiments of the present application. Rather, the scope of the claims should be understood to include all processes and methods that have similar applications, functions and / or results and which are within the scope of the claims. Accordingly, the attached claims are intended to cover all such alternatives, modifications and variations as falling within the true scope of the application.

[0201] The foregoing description of the disclosed aspects is provided as an enabling teaching of the aspects described herein. Various modifications will be apparent to those skilled in the art from this enabling teaching, and the general principles defined herein can be applied to other aspects. Therefore, the scope of the application is not intended to be limited to the aspects described herein and shown in the figures, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0202] The foregoing description has been presented for the purpose of illustration and description. Further, the description is not intended to limit the embodiments of the present application to the form disclosed herein. Although various example aspects and embodiments have been discussed, those skilled in the art will recognize that certain modifications, substitutions, changes, additions and rearrangements can be made without departing from the scope of the described embodiments.

Claims

1. A write control method of a storage medium, characterized by, The method comprises the following steps: In the case that the first heterogeneous core is in write protection of the storage medium, the first heterogeneous core acquires a first request sent by a second heterogeneous core, the first request being used for requesting writing data, the first heterogeneous core being different from the second heterogeneous core in type; A first reset signal is sent to the storage medium, the first reset signal being used for triggering the storage medium to cancel write protection; In the case that writing of the data of the second heterogeneous core into the storage medium is completed, write protection of the storage medium is started.

2. The method of claim 1, wherein, The step of sending the first reset signal to the storage medium comprises the following steps: The first reset signal is sent to the storage medium through a first interface, the first interface being a general input / output (GPIO) interface between the first heterogeneous core and the storage medium.

3. The method of claim 1, wherein, The first heterogeneous core is the heterogeneous core with the highest security authority.

4. The method according to any one of claims 1 to 3, characterized in that, A hardware lock is arranged between the first heterogeneous core and the storage medium. Before the step of sending the first reset signal to the storage medium, the following step is further included: A configuration instruction is sent to the hardware lock, the configuration instruction indicating that the hardware lock is occupied by the second heterogeneous core or the first heterogeneous core; In the case that the hardware lock is occupied by the first heterogeneous core, the data of the second heterogeneous core is written into the storage medium by the first heterogeneous core through the hardware lock; In the case that the hardware lock is occupied by the second heterogeneous core, the data of the second heterogeneous core is written into the storage medium by the second heterogeneous core through the hardware lock.

5. The method according to any one of claims 1 to 3, characterized in that, Before the step of sending the first reset signal to the storage medium, the following step is further included: A second reset signal is sent to the second heterogeneous core, the second reset signal being used for indicating that the second heterogeneous core is suspended and indicating that the second heterogeneous core notifies other heterogeneous cores of suspension, the other heterogeneous cores being heterogeneous cores other than the first heterogeneous core and the second heterogeneous core; Alternatively, the second reset signal is sent to the second heterogeneous core and the other heterogeneous cores, the second reset signal being used for indicating that the second heterogeneous core and the other heterogeneous cores are suspended; The data of the second heterogeneous core is written into the storage medium by the first heterogeneous core.

6. The method according to any one of claims 1 to 3, characterized in that, The following steps are further included: The second reset signal is sent to the other heterogeneous cores, the second reset signal being used for indicating that the other heterogeneous cores are suspended; The data of the second heterogeneous core is written into the storage medium by the second heterogeneous core.

7. The method according to any one of claims 1 to 5, characterized in that, The first request comprises verification data, and the step of sending the first reset signal to the storage medium comprises the following steps: Verification is performed on the verification data in the first request to obtain a verification result; If the verification result is verification success, the first reset signal is sent to the storage medium.

8. The method according to any one of claims 1 to 6, characterized in that, The first request is sent to a shared memory by the second heterogeneous core, and the step of acquiring the first request sent by the second heterogeneous core comprises the following step: The first request sent by the second heterogeneous core is read from the shared memory.

9. The method according to any one of claims 1 to 7, characterized in that, During the period that the write permission of the storage medium is occupied by the second heterogeneous core, the following step is further included: A second request sent by another heterogeneous core is acquired; An occupation prompt is sent to the other heterogeneous core, the occupation prompt being used for prompting the other heterogeneous core that the write permission of the storage medium has been occupied.

10. The method according to any one of claims 1 to 8, characterized in that, The following steps are further included: A notification signal is sent to other heterogeneous cores, which is used to inform that the other heterogeneous cores can acquire the write permission of the storage medium.

11. A controller, comprising: The application comprises: A plurality of heterogeneous cores, the heterogeneous core with the highest security permission is the first heterogeneous core, the first heterogeneous core is further connected with a storage medium, the storage medium stores a computer program, the computer program is called by the first heterogeneous core to execute the write control method of the storage medium in any one of claims 1-10.

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