W-band two-dimensional DBF microsystem based on AiP technology

Abstract

The invention discloses a W-band two-dimensional DBF microsystem based on an AiP technology, and belongs to the technical field of packaging antennas, the W-band two-dimensional DBF microsystem comprises an active array antenna module for realizing transceiving and frequency conversion of W-band signals, the active array antenna module is provided with a plurality of antenna units, and each antenna unit corresponds to a signal processing channel; the radio frequency direct acquisition transceiver module is used for multi-channel parallel sampling and transmitting and completing conversion between an analog radio frequency signal and a digital baseband signal; the digital beam former module is used for carrying out weighting, phase correction and delay control on each channel signal output by the radio frequency direct acquisition transceiver module so as to realize two-dimensional digital beam forming; and the active array antenna module, the radio frequency direct acquisition transceiver module and the digital beam former module are independently integrated on the integrated module to realize integral packaging. According to the invention, deep fusion of the AiP module and the DBF module is realized under the W-band condition.

Description

TECHNICAL FIELD

[0001] The application relates to a W-band two-dimensional DBF microsystem based on an AiP technology, and belongs to the technical field of packaged antennas. BACKGROUND

[0002] In recent years, with the rapid development of high-end application scenarios such as high-resolution imaging radars, unmanned system environment perception, millimeter wave communication and precision navigation, higher requirements are put forward for the detection accuracy, real-time response and system integration of millimeter wave band (especially W-band, 75-110 GHz) array radar systems. Digital beam forming (DBF) technology can flexibly realize spatial filtering, beam pointing adjustment and multi-target detection by controlling the amplitude and phase of the received channel signals, and is a key support means for improving the spatial resolution, anti-interference ability and multi-task processing performance of array systems. Compared with the traditional analog beam forming scheme, DBF has obvious advantages in scanning flexibility, system calibration, beam synthesis precision and the like, and is especially suitable for wide field of view, dynamic target detection and multi-beam simultaneous imaging tasks.

[0003] However, under the condition of the W-band high frequency, the system faces many challenges such as high dielectric loss, high interconnection loss, difficulty in controlling the consistency of radio frequency links, difficulty in device heat dissipation, and system layout complication, especially in realizing two-dimensional DBF, which requires integrating a large number of ADC / DAC, mixer, PA / LNA devices, and puts forward high requirements for channel consistency, package layout, intermodulation interference suppression and system-level integration scheme. In order to realize a high-density, multi-channel and low-loss millimeter wave transceiver array system, the Antenna-in-Package (AiP) technology has become one of the core trends of current millimeter wave system integration.

[0004] The AiP technology integrates antennas, radio frequency front ends, power distribution, and even part of the control and digital-to-analog conversion modules at the package level, significantly improves the system integration, reduces the interconnection loss, and is suitable for application in scenarios where the platform space is limited, such as unmanned aerial vehicles, satellites, small radar platforms and the like. Digital beam forming can realize amplitude, phase or time delay adjustment of multiple channels at the baseband, has high flexibility, multi-beam processing capability and good system reconfigurability. Two-dimensional DBF system can realize beam control in the azimuth and elevation directions, and is an important means to realize wide coverage and high resolution imaging. However, how to realize the deep integration of AiP and DBF modules under the condition of the W-band is still a key challenge in current technology development. SUMMARY

[0005] According to one aspect of the application, a W-band two-dimensional DBF microsystem based on an AiP technology is provided, which can realize the deep integration of AiP and DBF modules under the condition of the W-band.

[0006] The W-band two-dimensional DBF microsystem based on the AiP technology comprises: an active array antenna module for realizing the transmission and frequency conversion of W-band signals, the active array antenna module having a plurality of antenna units, each of the antenna units corresponding to a signal processing channel; a radio frequency direct sampling transceiver module for multi-channel parallel sampling and transmission and for completing the conversion between analog radio frequency signals and digital baseband signals; a digital beamformer module for weighting, phase correction and delay control of each channel signal output by the radio frequency direct sampling transceiver module to realize two-dimensional digital beamforming; an integrated module, the active array antenna module, the radio frequency direct sampling transceiver module and the digital beamformer module being independently integrated on the integrated module to realize overall packaging; the integrated module comprising: a local oscillator power division network for power division of an externally input local oscillator signal to provide stable and uniform local oscillator signals for the active array antenna module and the radio frequency direct sampling transceiver module; a power supply network for providing stable and reliable power supply for the system; a control signal distribution network for distributing and managing control signals in the system to realize accurate control and monitoring of the working state, parameter setting and the like of each module.

[0007] Further, the W-band two-dimensional DBF microsystem based on the AiP technology further comprises: an FPGA module for realizing system timing control, state management, high-speed data acquisition, caching and distribution, multi-channel signal real-time processing and reconstruction, configuration instruction analysis and delivery, and cooperative communication with external devices; a frequency synthesizer module for providing system clock signals and a variety of synchronization signals to realize multi-channel cooperation and high-precision time-frequency synchronization; the FPGA module and the frequency synthesizer module being integrated on the integrated module.

[0008] Further, the active array antenna module comprises: a millimeter wave array patch antenna located on the surface layer of a PCB board for transmitting or receiving signals; a millimeter wave power division network embedded in the inner layer of the PCB board to realize one-to-many signal distribution, comprising one input end and N output ends, N being a positive integer; a TR chip located on the bottom layer of the PCB board to realize electrical interconnection with the PCB board; the millimeter wave array patch antenna being connected to the output end of the millimeter wave power division network through a surface layer microstrip line, wherein a gradual transition structure is adopted between the microstrip line and the antenna unit; The input end of the millimeter wave power division network is interconnected with the output end of the TR chip through a buried hole; The output end of the millimeter wave power division network is transmitted to the surface layer of the PCB through a buried hole, and is connected to the corresponding antenna unit through a surface layer microstrip line; The millimeter wave power division network is electrically connected with the integrated module through BGA balls, so as to realize the connection of the active array antenna module and the integrated module.

[0009] Further, the digital beamformer comprises: The signal receiving module comprises a receiving channel processing module and a receiving beamforming module connected in sequence, the receiving channel processing module is used for converting the externally input radio frequency signal into a digital baseband signal, and the receiving beamforming module is used for performing delay, weighting and synthesis processing on the multi-channel digital baseband signal, and outputting a specific directional receiving beam; The signal transmitting module comprises a transmitting beamforming module and a transmitting channel processing module connected in sequence, the transmitting beamforming module is used for calculating multi-channel weighting coefficients and distributing baseband signals according to a target direction, and the transmitting channel processing module is used for converting the weighted digital signal into a radio frequency transmitting signal; The DDS module is connected with the receiving channel processing module and the transmitting channel processing module respectively, and is used for providing a down-conversion local oscillator signal for the signal receiving module, providing an up-conversion carrier signal for the signal transmitting module, and realizing frequency synchronization of the transceiving link; The consistency compensation module is integrated in the packaging channel and is coupled with the receiving channel processing module and the transmitting channel processing module respectively, and is used for correcting the error in the channel under the condition of the W waveband, maintaining the array consistency, and improving the pointing accuracy and sidelobe suppression capability of the DBF output beam.

[0010] Further, the receiving channel processing module is connected with the first compensation branch of the consistency compensation module; The receiving channel processing module comprises an ADC unit, a digital down-conversion unit, a low-pass filter unit and an extraction filter unit; The ADC unit is used for converting an analog radio frequency signal into a digital signal; The digital down-conversion unit is used for receiving the local oscillator signal output by the DDS module, and mixing the digital signal to reduce the high frequency signal to an intermediate frequency or a baseband; The low-pass filter unit is used for filtering out the image frequency components after mixing; The extraction filter unit is used for reducing the signal sampling rate, reducing the data amount for subsequent processing and suppressing aliasing noise; The first compensation branch is used for performing I / Q imbalance correction on the mixed frequency signal in the receiving channel, and correcting the amplitude imbalance and phase imbalance of the in-phase / quadrature branch in the digital down-conversion unit.

[0011] Further, the receiving beam forming module is connected with a second compensation branch of the consistency compensation module, and the second compensation branch is used for performing digital phase compensation on the multi-channel baseband signal before synthesis to correct phase deviation caused by package parasitic parameters.

[0012] Further, the transmitting beam forming module is connected with a third compensation branch of the consistency compensation module. The transmitting beam forming module comprises a weight calculation unit and a channel correction unit. The weight calculation unit is used for generating amplitude and phase weighting coefficients corresponding to single beam, multi-beam or anti-interception mode. The channel correction unit is used for compensating amplitude and phase errors of the multi-transmitting channel to avoid beam pointing deviation and side lobe level rise. The third compensation branch is used for performing gain drift suppression on the weighted transmitting signal to compensate channel gain fluctuation caused by temperature change and device aging in the package through digital feedback adjustment.

[0013] Further, the transmitting channel processing module is connected with a fourth compensation branch of the consistency compensation module. The transmitting channel processing module comprises an interpolation filter unit, a digital up-conversion unit, a DAC unit and a digital pre-distortion unit. The interpolation filter unit is used for inserting sampling points to improve signal data rate and adapt to the requirements of the DAC unit and the up-conversion. The digital up-conversion unit is used for receiving the carrier signal output by the DDS module to modulate the baseband signal to the transmitting carrier frequency. The digital pre-distortion unit is used for generating compensation signals to offset the nonlinear distortion of the subsequent power amplifier. The fourth compensation branch is used for performing I / Q imbalance correction again on the signal after digital up-conversion to suppress the secondary distortion products caused by the nonlinearity of the W-band mixer.

[0014] Further, the DDS module adopts any one of the following architectures: Centralized frequency source architecture, which provides the same source local oscillator / carrier signal for all transceiving channels through a power division network to ensure frequency consistency. Distributed frequency source architecture, which configures an independent DDS subunit for each transceiving channel and maintains the phase consistency of each subunit through a synchronization mechanism, with a frequency resolution of Hz level or mHz level.

[0015] Further, the microsystem further comprises an FPGA module and a frequency synthesizer module. The FPGA module and the frequency synthesizer module are independently integrated on the integrated module. The cold plate is further connected to the radio frequency direct sampling transceiver module, the digital beamformer module, the FPGA module and the frequency synthesizer module. A heat-conducting gasket is further arranged between the radio frequency direct sampling transceiver module and the cold plate. The integrated module is further independently integrated with a light module, a power connector and a radio frequency seat.

[0016] The application can produce beneficial effects, including: The W-band two-dimensional DBF microsystem based on the AiP technology provided by the application realizes efficient transceiving and frequency conversion of W-band signals through an active array antenna module, completes multi-channel parallel sampling and analog-digital signal conversion in cooperation with a radio frequency direct sampling transceiver module, and realizes accurate two-dimensional digital beamforming through a digital beamformer module. Meanwhile, the modules are independently integrated on an integrated module to realize overall packaging, and deep integration of the AiP and DBF modules is realized under the condition of the W-band. An internal local oscillator power division network guarantees stable and uniform distribution of local oscillator signals, a power network provides reliable power support, and a control signal distribution network realizes accurate control and monitoring of the modules. The system has high integration, complete functions, can significantly improve signal processing accuracy and efficiency, and enhance system stability and reliability, and has wide application prospects and significant advantages in the fields of radar and communication. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 A system diagram of the W-band two-dimensional DBF microsystem based on the AiP technology in an embodiment of the application; Figure 2 A structure of the W-band two-dimensional DBF microsystem based on the AiP technology in an embodiment of the application Figure One ; Figure 3 A structure of the W-band two-dimensional DBF microsystem based on the AiP technology in an embodiment of the application Figure Two ; Figure 4 A signal receiving module connection diagram of the W-band two-dimensional DBF microsystem based on the AiP technology in an embodiment of the application; Figure 5 A signal transmitting module connection diagram of the W-band two-dimensional DBF microsystem based on the AiP technology in an embodiment of the application; Component and reference numeral list: 1 - active array antenna module; 1.1 - millimeter wave array patch antenna; 1.2 - millimeter wave power division network; 1.3 - TR chip; 1.4 - BGA ball; 2 - radio frequency direct sampling transceiver module; 3 - digital beamformer module; 3.1 - signal receiving module; 3.1.1 - receiving channel processing module; 3.2 - signal transmitting module; 3.2.1 - transmitting beamforming module; 3.2.2 - transmitting channel processing module; 4 - integrated module; 4.1 - local oscillator power division network; 4.2 - power supply network; 4.3 - control signal distribution network; 5 - FPGA module; 6 - frequency synthesizer module; 7 - cold plate; 8 - heat-conducting gasket; 9 - optical module; 10 - power connector; 11 - radio frequency seat. DETAILED DESCRIPTION

[0018] The present application will be described in detail below with reference to examples, but the present application is not limited to these examples.

[0019] Reference Figures 1-5 , the W-band two-dimensional DBF microsystem based on the AiP technology, characterized in that it comprises: an active array antenna module 1 for realizing the transmission and reception and frequency conversion of W-band signals, the active array antenna module 1 having a plurality of antenna units, each of the antenna units corresponding to a signal processing channel; a radio frequency direct sampling transceiver module 2 for multi-channel parallel sampling and transmission and completing the conversion between analog radio frequency signals and digital baseband signals; a digital beamformer module 3 for weighting, phase correction and delay control of each channel signal output by the radio frequency direct sampling transceiver module 2 to realize two-dimensional digital beamforming; an integrated module 4, wherein the active array antenna module 1, the radio frequency direct sampling transceiver module 2 and the digital beamformer module 3 are independently integrated on the integrated module 4 to realize overall packaging; the integrated module 4 comprises: a local oscillator power division network 4.1 for power division of an externally input local oscillator signal to provide stable and uniform local oscillator signals for the active array antenna module 1 and the radio frequency direct sampling transceiver module 2; a power supply network 4.2 for providing stable and reliable power supply to the system; a control signal distribution network 4.3 for distributing and managing control signals in the system to realize accurate control and monitoring of the working state, parameter setting and the like of each module.

[0020] Specifically, the microsystem adopts AiP (Antenna-in-Package) technology to realize W-band (75-110 GHz) two-dimensional digital beamforming (DBF) through highly integrated design. Among them, the active array antenna realizes the transmission and frequency conversion of W-band signals, such as up-conversion to the transmission frequency band or down-conversion to the intermediate frequency / baseband, contains multiple antenna units (such as a 16x16 array), each unit corresponds to an independent signal processing channel, supports multi-beam parallel processing, the AiP technology integrates the antenna and the radio frequency circuit in the same package, reduces signal loss and improves system efficiency; the radio frequency direct sampling transceiver module samples the multi-channel analog radio frequency signals at high speed, such as ADC sampling rate≥10 GSPS, converts them into digital baseband signals, converts the digital baseband signals into analog radio frequency signals through DAC, supports multi-channel parallel transmission, adopts direct radio frequency sampling (Direct RF Sampling) technology, omits the traditional mixer, simplifies the architecture and reduces noise; the digital beamformer module weights, phase corrects and delays controls the signals of each channel to realize two-dimensional beamforming, such as beam scanning and spatial filtering, realizes real-time digital signal processing (DSP) through FPGA / ASIC, supports dynamic beam adjustment, and the algorithm includes adaptive beamforming (such as MVDR), beamforming, etc.; the integrated module realizes system-level packaging, integrates the above three modules, provides local oscillator signals, power supply and control signal distribution. The local oscillator power division network distributes the external local oscillator signal to each module through the power divider to ensure phase consistency, the power supply network adopts low dropout linear regulator (LDO) or switching power supply (DC-DC) to provide low-noise power supply for different modules, and the control signal distribution network realizes communication between modules through SPI / I2C bus, supports parameter configuration (such as gain, phase) and state monitoring.

[0021] Wherein, the AiP integration technology can adopt low-temperature co-fired ceramic or multi-layer organic substrate to realize low-loss transmission of high-frequency signals, vertical interconnection of antenna units and RF chips (such as through BGA or micro-bump), reduce parasitic effects, integrate heat dissipation layer or adopt flip-chip technology to improve thermal conductivity. According to the Nyquist criterion, the sampling rate needs to be ≥2xW highest frequency (such as 220 GSPS), and a multi-channel time-interleaved ADC / DAC is actually used to reduce the pressure of a single channel. A low-noise amplifier is used in combination with a digital domain noise suppression algorithm. A two-dimensional DBF algorithm adjusts the phase difference of each channel (Δφ = 2πd sinθ / λ) to realize azimuth (θ) and elevation (φ) scanning; space-time adaptive processing is used to suppress interference and improve signal-to-noise ratio. It is worth noting that in the manufacture of active array antenna modules, the AiP integration technology can adopt low-temperature co-fired ceramic or multi-layer organic substrate to realize low-loss transmission of high-frequency signals, vertical interconnection of antenna units and TR chips through BGA balls or micro-bumps to reduce parasitic effects; for ADC sampling of the RF direct sampling transceiver module, according to the Nyquist criterion, the sampling rate needs to be ≥2xW highest frequency (i.e. 220 GSPS), and a multi-channel time-interleaved ADC / DAC architecture is actually used to reduce the sampling pressure of a single channel.

[0022] Further, the system supports independent digital beamforming in horizontal (azimuth) and vertical (elevation) directions, can adjust the beam direction, gain and width of multiple beams in real time, realizes multi-target simultaneous tracking and dynamic radar imaging function, and is suitable for flight platforms and dynamic scenes.

[0023] Further comprising: An FPGA module 5 for realizing system timing control, state management, high-speed data acquisition, caching and distribution, multi-channel signal real-time processing and reconstruction, configuration instruction analysis and delivery, and cooperative communication with external devices; A frequency synthesis module 6 for providing system clock signals and various synchronization signals, realizing multi-channel cooperation and high-precision time-frequency synchronization; The FPGA module 5 and the frequency synthesis module 6 are integrated on an integrated module.

[0024] Specifically, on the basis of an active array antenna, a radio frequency direct sampling transceiver, a digital beamformer, and an integrated module, an FPGA module and a frequency synthesizer module are also provided and integrated in a system-in-package / integrated module. A signal flow is from antenna reception, radio frequency direct sampling (ADC), FPGA preprocessing, digital beamforming, FPGA post-processing, to a transmission link. A control flow is through external instructions, FPGA analysis, configuration of the frequency synthesizer module (clock / synchronization), control of radio frequency direct sampling / beamformer parameters, and finally feedback of a state to the outside. The power supply / signal distribution network of the FPGA and the frequency synthesizer ensures low-noise power supply and low-jitter clock transmission. A 3D packaging technology is used to realize high-density interconnection of the FPGA and the frequency synthesizer module, reducing signal delay. The FPGA module undertakes three core tasks of timing control, data processing, and communication interface, generates a distribution strategy of a system global clock (such as a 100 MHz reference clock), ensures synchronous start of each module, monitors the module state (such as temperature and voltage), and realizes fault self-recovery through a watchdog circuit. For example, in a radar mode, the sampling window of the radio frequency direct sampling module and the phase update timing of the beamformer are controlled. The receiving end is connected to the JESD204B / C interface of the radio frequency direct sampling module, supports multi-channel parallel data such as 16 channels x 14 bits x 10 GSPS, integrates a DDR4 / HBM controller, realizes data caching such as a cache depth ≥ 1 MB / channel, uses the AXI4-Stream protocol to reduce data transfer delay, and supports burst transmission mode. Digital down conversion reduces the intermediate frequency signal of the radio frequency direct sampling to baseband, compensates for the amplitude / phase inconsistency between antenna units, calculates the weighting coefficient of each channel (such as FFT-based beamforming), outputs single-beam or multi-beam data, generates a phase control word according to the beam pointing, and issues it to the DAC of the radio frequency direct sampling module. Compressed sensing or deep learning is supported to realize signal sparse reconstruction, SPI / I2C / UART instructions are analyzed, converted into internal register configuration, and runtime parameter update is supported. The high-speed interface is PCIe Gen4x8 (bandwidth ≥ 64 Gbps) or 100G Ethernet (for data backhaul), the low-speed interface is CAN / RS485 (for sensor data fusion), UDP / IP or a custom protocol is implemented, and multi-device networking (such as a distributed radar network) is supported. The frequency synthesizer module provides a unified clock reference and synchronization signal for the system, solves the problem of inconsistent time delay of multiple channels, and the main clock source uses a high-stability crystal oscillator or an atomic clock with a frequency stability ≤ 1 x 10 -12The PLL generates multi-frequency point clocks (such as a 100 MHz reference clock and a 10 GHz local oscillator signal), an integrated clock cleaner (such as an LMK04828), and reduces the phase noise to -150 dBc / Hz@10 kHz. A global trigger pulse is generated to synchronize the sampling time of the ADC / DAC of the radio frequency direct sampling module. A frame header mark is inserted to ensure the alignment of multi-channel data. The phases of each module are aligned through a 1PPS (pulse per second) signal to support distributed system clock synchronization. The deterministic delay calibration of the DAC / ADC is adopted to support the GPS / Beidou timing interface to realize cross-device time synchronization. The clock drift is monitored in real time through the FPGA to adjust the PLL parameters to maintain synchronization accuracy.

[0025] The active array antenna module 1 comprises: a millimeter wave array patch antenna 1.1 located on the surface layer of the PCB board for transmitting or receiving signals; a millimeter wave power division network 1.2 embedded in the inner layer of the PCB board to realize one-to-many distribution of signals, comprising one input end and N output ends, N being a positive integer and matching the number of antenna units of the active array antenna module; a TR chip 1.3 located on the bottom layer of the PCB board to realize electrical interconnection with the PCB board; The millimeter wave array patch antenna 1.1 is connected to the output end of the millimeter wave power division network 1.2 through a surface layer microstrip line, wherein a gradual transition structure is adopted between the microstrip line and the antenna unit; The input end of the millimeter wave power division network 1.2 is interconnected with the output end of the TR chip 1.3 through a buried hole; The output end of the millimeter wave power division network 1.2 is transmitted to the surface layer of the PCB through a buried hole and connected to the corresponding antenna unit through a surface layer microstrip line; The millimeter wave power division network 1.2 is electrically connected with the integrated module 4 through a BGA ball 1.4, thereby realizing the connection between the active array antenna module 1 and the integrated module 4.

[0026] Specifically, the active array antenna module adopts a multi-layer PCB integration technology to realize efficient signal transmission and electrical isolation through vertical interconnection. The millimeter wave array patch antenna adopts a microstrip patch antenna structure, and the substrate material is Rogers RT / duroid 5880 with a dielectric constant ε r= 2.2, loss tangent tan d < 0.0009 to reduce high frequency loss. Antenna element spacing is λ / 2 (about 1.95 mm in W-band), and beam symmetry is optimized by rotating symmetric layout. Exponential tapered line (length > 3λ) is used between the surface microstrip line and the antenna element to achieve impedance matching (50Ω to free space impedance 377Ω) and reduce reflection loss (S11 < -20 dB). For example, the tapered line has a starting width of 0.2 mm, a final width of 1.8 mm, and a length of 6 mm.

[0027] The millimeter wave power division network uses a tree-shaped one-to-many power divider, which supports 1 input and N output (N = 64 for example), and the cascading mode is two-dividers x 6 levels. The insertion loss of each power divider is < 0.5 dB (@ 80 GHz), the phase consistency is ± 2°, the input end is connected to the output end of the TR chip through a stepped buried hole, the buried hole diameter gradually changes from 0.2 mm to 0.1 mm to reduce parasitic inductance, and the output end transmits signals to the surface through a fan-shaped buried hole array, the fan angle is 120°, and signal crosstalk is reduced.

[0028] The output end of the power division network is interconnected with the pads of the integrated module 4 through a BGA ball array, wherein the BGA ball diameter is 500um, the PITCH is 800um, the height of the implanted ball after reflow is 330um~370um, the solder ball meets the SAC305 standard, SnAgCu, Ag 3%, Cu 0.5%, does not contain Pb, and reflow is 260℃. Sn-Ag-Cu lead-free solder with a melting point of 217℃ is used to ensure high temperature reliability (such as a working range of -55℃~+125℃).

[0029] The single-channel output power of the TR chip transmission channel is Psat=12.5dBm; the phase shift number is 6 bits; the phase shift range is 0-360°; the phase shift RMS error is 2.5°; the phase shift additional amplitude modulation is ± 0.8 dB; the noise figure of the receiving channel is NF=10dB; the input 1dB compression point is IP1dB= -25dBm; the phase shift number is 6 bits; the phase shift range is 0-360°; the phase shift RMS error is 2.5°; the attenuation number is 5 bits; the attenuation range is 15.5 dB; the attenuation step is 0.5 dB; and the attenuation additional phase shift is ± 2°. Flip-Chip technology is used to realize interconnection with the PCB bottom layer, the bonding pitch is < 50μm, and parasitic parameters are reduced. The ground layer uses a metallized via array (via pitch 0.8mm) to suppress high frequency ground bounce noise.

[0030] The digital beamformer 3 comprises: The signal receiving module 3.1 comprises a receiving channel processing module 3.1.1 and a receiving beam forming module 3.1.2 connected in sequence, the receiving channel processing module 3.1.1 is used for converting an externally input radio frequency signal into a digital baseband signal, and the receiving beam forming module 3.1.2 is used for performing delay, weighting and synthesis processing on a multi-channel digital baseband signal, and outputting a specific directional receiving beam; The signal transmitting module 3.2 comprises a transmitting beam forming module 3.2.1 and a transmitting channel processing module 3.2.2 connected in sequence, the transmitting beam forming module 3.2.1 is used for calculating multi-channel weighting coefficients and distributing baseband signals according to a target direction, and the transmitting channel processing module 3.2.2 is used for converting the weighted digital signals into radio frequency transmitting signals; A DDS (Direct Digital Synthesizer) module 3.3 is connected with the receiving channel processing module 3.1.1 and the transmitting channel processing module 3.2.2 respectively, and is used for providing a down-conversion local oscillator signal for the signal receiving module and an up-conversion carrier signal for the signal transmitting module, so as to realize frequency synchronization of a transceiving link; A consistency compensation module is integrated in a packaging channel and coupled with the receiving channel processing module 3.1.1 and the transmitting channel processing module 3.2.2 respectively, and is used for correcting channel internal errors under W waveband conditions, maintaining array consistency, and improving the pointing accuracy and sidelobe suppression capability of a DBF output beam.

[0031] Specifically, the receiving channel processing module radio frequency front end adopts a W waveband low noise amplifier (LNA) with a noise coefficient ≤ 3.5 dB and a gain ≥ 30 dB to suppress the noise of a receiving link; down-conversion mixing is performed through a passive mixer with a conversion loss ≤ 8 dB to convert a radio frequency signal, such as 77-81 GHz, to an intermediate frequency IF, such as 4 GHz; a high-speed ADC sampling adopts a 14-bit ADC with a sampling rate ≥ 5 GSPS and an effective bit number ENOB ≥ 10 bit to quantize an intermediate frequency signal with a dynamic range ≥ 60 dB. Digital down-conversion (DDC) realizes CIC filtering and HB filtering in an FPGA to reduce an intermediate frequency signal to a baseband with a bandwidth ≤ 200 MHz, thereby reducing the subsequent processing load. The receiving beam forming module realizes sub-sampling period delay through a fractional delay filter to compensate for the difference in propagation delay between channels, adopts a complex weighting coefficient, realizes multi-beam parallel processing through an FFT-based beam forming algorithm, supports a hybrid mode of mechanical scanning and electrical scanning, the electrical scanning angle range is ± 60°, and the step precision is 0.1°. The transmitting beam forming module dynamically adjusts the amplitude 0-31 dB and the phase 0-360° of each channel based on the least mean square error criterion, realizes 64-channel parallel distribution through a multi-core DSP, and supports beam hopping.

[0032] The transmit channel processing module digitally up-converts (DUC) the baseband signal to an intermediate frequency in the FPGA, reduces the DAC sampling rate requirement, uses a 14-bit DAC for conversion, has a sampling rate of ≥5 GSPS, and an SFDR of ≥70 dB, converts the digital intermediate frequency signal to an analog signal, up-converts the frequency through an active mixer to the W band, and uses a GaN power amplifier (PA) to meet the requirements of long-distance transmission.

[0033] The DDS module uses a direct digital frequency synthesis chip (such as AD9914) with an output frequency range of DC-4 GHz and a resolution of ≤1 μHz. The phase-locked loop (PLL) is multiplied to the W band (×20 multiplier), and the phase noise is ≤-110 dBc / Hz@1 MHz. A unified clock reference (such as a 100 MHz OCXO) is provided and distributed to each channel through a fan-out buffer, with a clock jitter of ≤50 fs. The transmit-receive link phase alignment is supported to ensure the spatial synchronization of the transmit beam and the receive beam.

[0034] Further, the channel amplitude inconsistency caused by the LNA / PA gain difference and the PCB loss unevenness, the channel phase inconsistency caused by the wiring length difference and the device group time delay fluctuation, and the channel time delay inconsistency caused by the digital signal processing delay difference are injected into each channel through the built-in test signal source, the error is measured and a compensation table is generated, the LMS algorithm is used to dynamically adjust the weighting coefficient, and the error is corrected in real time. In the PCB layout, the serpentine wiring is used to match the channel length and reduce the time delay difference.

[0035] The receive channel processing module 3.1.1 is connected to the first compensation branch of the consistency compensation module; The receive channel processing module 3.1.1 includes an ADC unit, a digital down-conversion unit, a low-pass filter unit, and a decimation filter unit. The ADC unit is configured to convert an analog radio frequency signal into a digital signal. The digital down-conversion unit is configured to receive a local oscillator signal output by the DDS module, and mix the digital signal to reduce the high frequency signal to an intermediate frequency or a baseband. The low-pass filter unit is configured to filter out the image frequency components after mixing. The decimation filter unit is configured to reduce the signal sampling rate, reduce the amount of subsequent processing data, and suppress aliasing noise. The first compensation branch is configured to perform I / Q imbalance correction on the mixed signal in the receive channel, and correct the amplitude imbalance and phase imbalance of the in-phase / quadrature branches in the digital down-conversion unit.

[0036] Specifically, the DC unit converts analog radio frequency signals, such as intermediate frequency signals after down-conversion of W-band 77-81 GHz, a typical value of 4 GHz, into digital signals, a sampling rate ≥ 5 GSPS, meeting the Nyquist sampling theorem, avoiding aliasing, a resolution of 14 bits, ENOB ≥ 10 bits, a dynamic range ≥ 60 dB, an input bandwidth ≥ 6 GHz, and supporting direct sampling of intermediate frequency signals of a superheterodyne receiver architecture. A time-interleaved ADC array, such as 4 channels x 1.25 GSPS, is used to achieve high-speed sampling by clock phase offset, reduce the difficulty of single-chip design, integrate an input buffer, such as an op-amp with SFDR ≥ 80 dB, and suppress the influence of analog front-end noise on the signal-to-noise ratio of the ADC.

[0037] The digital down-conversion unit receives the local oscillator signal output by the DDS module, such as 4 GHz, and mixes it with the digital signal output by the ADC to reduce the high-frequency signal to intermediate frequency IF or baseband BB. The linearity of the mixer IP3 ≥ 30 dBm avoids intermodulation distortion caused by strong interference signals. The resolution of the numerically controlled oscillator (NCO) is ≤ 1 μHz.

[0038] The mixing algorithm uses a complex multiplier (I / Q two-way parallel processing) to achieve signal spectrum shifting: I out =I ADC ·cos(2πf LO t)-Q ADC ·sin(2πf LO t); Q out =I ADC ·sin(2πf LO t)+Q ADC ·cos(2πf LO t); The NCO phase accumulator is 32 bits wide, supporting a maximum frequency synthesis range of half the sampling rate.

[0039] The low-pass filter unit filters out the image frequency components after mixing. The cutoff frequency is ≤ 200 MHz, matching the bandwidth of the subsequent beamforming module, and the stopband attenuation is ≥ 80 dB, suppressing image interference. A combination of cascaded integrator comb (CIC) and half-band (HB) filters is used. The CIC filter achieves a large decimation ratio, reducing computational complexity; the HB filter compensates for the passband attenuation of the CIC filter, optimizing the stopband characteristics.

[0040] The decimation filter unit reduces the signal sampling rate, reduces the amount of subsequent processing data and suppresses aliasing noise. The decimation factor is 16, which meets the data rate requirements of the beamforming module, the anti-aliasing attenuation is ≥60 dB, which ensures the signal quality, and a multi-stage filter cascade (such as CIC, HB, FIR) is used to reduce the sampling rate while maintaining signal integrity. The integrated dynamic bit width adjustment function automatically optimizes the data bit width according to the signal amplitude, reducing storage and transmission overhead.

[0041] Further, the amplitude imbalance and phase imbalance of the I / Q branch in the digital down-conversion unit are corrected, typical error amplitude imbalance ±1 dB, phase imbalance ±5°, wherein the I / Q path gain / phase inconsistency of the LNA / mixer causes analog front-end mismatch, and the ADC sampling clock offset and DDC mixer coefficient error cause digital processing mismatch.

[0042] The I / Q branch signal can be expressed as: I(t)=A I ·cos(ωt+Φ I ),Q(t)=A Q ·sin(ωt+Φ Q ); The amplitude imbalance ε and the phase imbalance Δφ are defined as: ε=20log 10 ( A I / A Q ),ΔΦ=Φ I -Φ Q -90°; The Q branch gain is adjusted by a multiplier: Q corr (t)=Q(t)· A I / A Q ; The Q branch phase is adjusted by a Hilbert transform or an all-pass filter: Qcorr(t)=Q(t)·cos(ΔΦ)-I(t)·sin(ΔΦ); The LMS algorithm is used to dynamically estimate the error parameters: w(n+1)=w(n)+μ·e(n)·x(n); Wherein, w is the error vector, μ is the step factor, and e(n) is the error signal.

[0043] The receiving beamforming module 3.1.2 is connected with the second compensation branch of the consistency compensation module, and the second compensation branch is used for performing digital phase compensation on the multi-channel baseband signal before synthesis, and correcting the phase deviation caused by packaging parasitic parameters.

[0044] Specifically, the receive beam forming module combines the signals received by multiple antennas into a directional beam, similar to focusing sunlight with a concave mirror, and is connected to the second compensation branch of the consistency compensation module. The second compensation branch corrects the signal delay introduced by the antenna packaging materials such as plastic, metal and circuit traces, similar to adjusting the time difference between multiple watches to ensure synchronization. In a 5G base station, if the signals of 8 antennas are phase-shifted by 5° due to packaging parasitic parameters, the beam direction will be offset, and after compensation, the beam can accurately point to the user's mobile phone.

[0045] The transmit beam forming module 3.2.1 is connected to the third compensation branch of the consistency compensation module; The transmit beam forming module 3.2.1 includes a weight calculation unit and a channel correction unit; The weight calculation unit is used to generate amplitude and phase weighting coefficients corresponding to single-beam, multi-beam or anti-interception mode; The channel correction unit is used to compensate the amplitude and phase errors of multiple transmit channels to avoid beam pointing deviation and side lobe level rise; The third compensation branch is used to perform gain drift suppression on the weighted transmit signal, and adjusts the channel gain fluctuation caused by temperature change and device aging in the package through digital feedback.

[0046] Specifically, the transmit beam forming module generates directional transmit signals such as radar beams or mobile phone signals. The weight calculation unit generates different beam modes according to requirements, single-beam = concentrated transmission, multi-beam = wide coverage, and anti-interception = frequency hopping transmission. The channel correction unit corrects the amplitude and phase errors of multiple transmit channels, such as a signal amplifier with a gain of 3dB higher than other channels. If not corrected, the beam will be skewed, the main lobe will be pointing in the wrong direction, and the side lobe energy will increase. The transmit beam forming module is connected to the third compensation branch of the consistency compensation module, and the third compensation branch dynamically adjusts the signal strength through digital feedback to compensate for temperature changes or device aging in the package.

[0047] The transmit channel processing module 3.2.2 is connected to the fourth compensation branch of the consistency compensation module; The transmit channel processing module 3.2.2 includes an interpolation filter unit, a digital up-conversion unit, a DAC unit, and a digital pre-distortion unit; The interpolation filter unit is used to insert sampling points to improve the signal data rate to adapt to the requirements of the DAC unit and up-conversion; The digital up-conversion unit is used to receive the carrier signal output by the DDS module and modulate the baseband signal to the transmit carrier frequency; The digital pre-distortion unit is used to generate a compensation signal to offset the non-linear distortion of the subsequent power amplifier; The fourth compensation branch is used for performing I / Q imbalance correction on the signal after digital up-conversion, so as to suppress the secondary distortion product caused by the nonlinearity of the W-band mixer.

[0048] Specifically, the interpolation filter unit inserts additional sampling points in the signal, such as increasing the sampling rate from 1 GHz to 4 GHz, so as to make the signal smoother and match the subsequent high-speed DAC and up-conversion requirements; the digital up-conversion unit moves the baseband signal (0 Hz~100 MHz) to the transmission frequency band; the DAC unit converts the digital signal to an analog signal for the RF circuit to process; and the digital pre-distortion unit generates a compensation signal in advance, which is opposite to the non-linear distortion of the power amplifier, such as stretching the amplitude in advance when the amplifier compresses the amplitude at high voltage.

[0049] The fourth compensation branch performs I / Q imbalance correction on the signal after digital up-conversion, and focuses on solving the nonlinearity problem of the W-band mixer. The W-band signal is extremely sensitive to hardware defects. The inconsistency of the I / Q path amplitude in the mixer, such as the I path gain being 2 dB higher than the Q path or the phase deviation, such as the Q path lagging 3°, will produce secondary distortion products, such as spurious signals at the target frequency ± 2 times the frequency. In vehicle-mounted radar, spurious signals may be misdetected as obstacles; in satellite communication, it will interfere with adjacent frequency bands. By dynamically adjusting the amplitude and phase of the I / Q signal, such as increasing the Q path gain by 2 dB and advancing the phase by 3°, the synthesized signal is pure. Adjust the left and right volume and delay of the dual-channel sound to eliminate echo interference.

[0050] JESD204C is a protocol for transceivers to connect digital processing devices through a serial interface. The JESD204C transmitter combines parallel data from the ADC into data frames and outputs serial data using 64B / 66B encoding and data scrambling techniques. The JESD204C receiver is the reverse process of the JESD204C transmitter. The JESD204C hardware data flow from sample input to physical output can be divided into transmission layer, data link layer and physical layer. The data frames assembled in the transmission layer are sent through the link in the form of 8 octet blocks. The data link layer is based on the 64B / 66B encoding scheme of IEEE802.3, which cooperates with the scrambling technique to maintain direct current balance and ensure sufficient data variation, so that the clock and data recovery (CDR) circuit in the JESD204C receiver can reliably recover the clock. The physical layer is composed of high-speed serialization circuits with a clock frequency of serial clock rate. In this layer, parallel data is converted into high-speed differential serial data of the channel.

[0051] The DDS module 3.3 adopts any one of the following architectures: The centralized frequency source architecture provides the same source LO / carrier signal for all transceiver channels through a power division network, ensuring frequency consistency. The distributed frequency source architecture configures an independent DDS subunit for each transceiving channel, and maintains the phase consistency of each subunit through a synchronization mechanism, and the frequency resolution reaches the Hz level or the mHz level, wherein the synchronization mechanism comprises a phase calibration mechanism based on a shared reference clock and a 1PPS synchronization pulse.

[0052] Specifically, the centralized frequency source architecture uses a single high-performance DDS chip to generate a local oscillator / carrier signal, and distributes the signal to all transceiving channels through a power division network. All channels share the same clock source, and the phase noise and frequency error are completely the same, such as phase noise <-120dBc / Hz@10kHz. Only one DDS chip and a power divider are required, which is low in cost and low in power consumption, and is suitable for scenarios with a large number of channels, such as 64T64R 5G base stations.

[0053] The distributed frequency source architecture configures an independent DDS subunit for each transceiving channel, and maintains the phase consistency of each subunit through a synchronization mechanism, and the frequency resolution reaches the Hz level or the mHz level, wherein the synchronization mechanism comprises a phase calibration mechanism based on a shared reference clock and a 1PPS synchronization pulse.

[0054] The radio frequency direct sampling transceiver module 2, the digital beamformer module 3, the FPGA module 5 and the frequency synthesizer module 6 are also connected with a cold plate 7; The radio frequency direct sampling transceiver module 2 and the cold plate 7 are also provided with a heat-conducting gasket 8; The integrated module 4 is also independently integrated with an optical module 9, a power connector 10 and a radio frequency seat 11.

[0055] Specifically, the cold plate acts as an active heat dissipation medium, and conducts the heat of the radio frequency direct sampling transceiver module, the digital beamformer module, the FPGA module and the frequency synthesizer module to an external heat sink through circulating cooling liquid such as ethylene glycol aqueous solution. The thermal resistance is <0.1°C / W, which ensures that the module temperature is stable below 65°C, the flow resistance is <50kPa, which is suitable for the pressure range of a micro pump, and the pressure resistance is >3MPa, which prevents the leakage of the cooling liquid.

[0056] The surface of the cold plate can be plated with nickel, and the module substrate can be adhered through heat-conducting glue, which is suitable for low-power scenarios such as the frequency synthesizer module; or a micron-level flow channel can be etched in the cold plate, such as 200μm wide x 500μm deep, to increase the heat exchange area, which is suitable for high-power modules such as the FPGA module, and the power consumption can reach 50W; or an embedded cold plate can be selected, which embeds the cold plate into the internal PCB of the module, such as below the ADC / DAC chip of the radio frequency direct sampling transceiver module, to realize local precise heat dissipation.

[0057] The thickness of the heat-conducting gasket of the radio frequency direct sampling module needs to be accurate to 0.5±0.1 mm, so as to avoid cracking of the ADC chip due to uneven pressure. A nano coating such as silicon dioxide is sprayed on the surface of the cold plate and the module to reduce the contact thermal resistance. The heat-conducting gasket is fixed by vacuum adsorption tooling to prevent air bubbles from being generated during assembly.

[0058] The optical module realizes high-speed data transmission, with a rate supporting 400Gbps (8x56Gbps PAM4) or 800Gbps (16x56Gbps PAM4), an interface standard being QSFP-DD or OSFP, and a power consumption being <15W. The radio frequency direct sampling module is connected with the digital beamformer to realize real-time transmission of 128-channel raw sampling data. The power connector realizes high-density power supply, with a current capacity supporting 100A per channel, meeting the peak power consumption demand of the FPGA module, an isolation voltage being >3kV to prevent digital ground and analog ground interference, a plugging life being >5000 times to adapt to fast maintenance scenarios. The radio frequency seat realizes low-loss signal transmission, with a frequency range being DC~40GHz, covering the 5G millimeter wave frequency band, an insertion loss being <0.5dB@28GHz, and a VSWR being <1.2:1 to ensure impedance matching. The MPC (Metal Post Connector) technology is used to integrate the radio frequency seat with the PCB, reducing parasitic capacitance.

[0059] The above is only a few embodiments of the present application, and does not limit the present application in any form. Although the preferred embodiments are disclosed above, the present application is not limited thereto. Any person skilled in the art can make some changes or modifications to the above disclosed technical content without departing from the scope of the present application, and such equivalent embodiments are also included in the scope of the present application.

Claims

1. A W-band two-dimensional DBF microsystem based on AiP technology, characterized in that, Comprise: Active array antenna module (1), realize W wave band signal transceiver and frequency conversion, the active array antenna module (1) has multiple antenna units, each antenna unit corresponds a signal processing channel; Radio frequency direct sampling transceiver module (2) is used for multi-channel parallel sampling and emission, and completes the conversion between analog radio frequency signal and digital baseband signal; Digital beamformer module (3) is used for weighting, phase correction and delay control to each channel signal output by the radio frequency direct sampling transceiver module (2), to realize two-dimensional digital beamforming; Integrated module (4), the active array antenna module (1), radio frequency direct sampling transceiver module (2) and digital beamformer module (3) are independently integrated on the integrated module (4) to realize overall packaging; The integrated module (4) comprises: Local oscillator power division network (4.1) is used for power distribution of external input local oscillator signal, to provide stable and uniform local oscillator signal for active array antenna module (1) and radio frequency direct sampling transceiver module (2); Power supply network (4.2) is used for providing stable and reliable power supply to the system; Control signal distribution network (4.3) is used for distributing and managing control signals in the system, to realize accurate control and monitoring of working state, parameter setting and the like of each module.

2. The W-band two-dimensional DBF microsystem based on the AiP technology according to claim 1, characterized in that, Further comprise: FPGA module (5) is used for realizing system timing control, state management, high-speed data acquisition, cache and distribution, multi-channel signal real-time processing and reconstruction, configuration instruction analysis and delivery, and collaborative communication with external equipment; Frequency synthesizer module (6) is used for providing system clock signal and various synchronous signals, to realize multi-channel cooperation and high-precision time-frequency synchronization; The FPGA module (5) and the frequency synthesizer module (6) are integrated on the integrated module.

3. The W-band two-dimensional DBF microsystem based on the AiP technology according to claim 1, characterized in that, The active array antenna module (1) comprises: Millimeter wave array patch antenna (1.1) is located on the surface layer of PCB board, and is used for transmitting or receiving signals; Millimeter wave power division network (1.2) is embedded in the inner layer of PCB board, to realize one-to-many distribution of signals, comprising one input end and N output ends, N is a positive integer, and matches the number of antenna units of the active array antenna module; TR chip (1.3) is located on the bottom layer of PCB board, to realize electrical interconnection with the PCB board; The millimeter wave array patch antenna (1.1) is connected with the output end of the millimeter wave power division network (1.2) through the surface layer microstrip line, wherein the microstrip line and the antenna unit adopt a gradual transition structure; The input end of the millimeter wave power division network (1.2) is interconnected with the output end of the TR chip (1.3) through a buried hole; The output end of the millimeter wave power division network (1.2) is transmitted to the surface layer of PCB through a buried hole, and is connected to the corresponding antenna unit through the surface layer microstrip line; The millimeter wave power division network (1.2) is electrically connected with the integrated module (4) through BGA ball (1.4), so as to realize the connection between the active array antenna module (1) and the integrated module (4).

4. The W-band two-dimensional DBF microsystem based on the AiP technology according to claim 1, characterized in that, The digital beamformer (3) comprises: The signal receiving module (3.1) comprises a receiving channel processing module (3.1.1) and a receiving beam forming module (3.1.2) connected in sequence, the receiving channel processing module (3.1.1) is used for converting an externally input radio frequency signal into a digital baseband signal, and the receiving beam forming module (3.1.2) is used for performing delay, weighting and synthesis processing on a multi-channel digital baseband signal and outputting a specific directional receiving beam; The signal transmitting module (3.2) comprises a transmitting beam forming module (3.2.1) and a transmitting channel processing module (3.2.2) connected in sequence, the transmitting beam forming module (3.2.1) is used for calculating multi-channel weighting coefficients according to a target direction and distributing a baseband signal, and the transmitting channel processing module (3.2.2) is used for converting a weighted digital signal into a radio frequency transmitting signal; The DDS module (3.3) is connected with the receiving channel processing module (3.1.1) and the transmitting channel processing module (3.2.2) respectively, is used for providing a down-conversion local oscillator signal for the signal receiving module, providing an up-conversion carrier signal for the signal transmitting module, and realizing frequency synchronization of a transceiving link; The consistency compensation module is integrated in a packaging channel, is coupled with the receiving channel processing module (3.1.1) and the transmitting channel processing module (3.2.2) respectively, is used for correcting channel internal errors under W wave band conditions, maintaining array consistency, and improving the pointing accuracy and sidelobe suppression capability of a DBF output beam.

5. The W-band two-dimensional DBF microsystem based on the AiP technology according to claim 4, characterized in that, The receiving channel processing module (3.1.1) is connected with a first compensation branch of the consistency compensation module; The receiving channel processing module (3.1.1) comprises an ADC unit, a digital down-conversion unit, a low-pass filter unit and an extraction filter unit; The ADC unit is used for converting an analog radio frequency signal into a digital signal; The digital down-conversion unit is used for receiving a local oscillator signal output by the DDS module, mixing the local oscillator signal with the digital signal to reduce a high frequency signal to an intermediate frequency or a baseband; The low-pass filter unit is used for filtering out an image frequency component after mixing; The extraction filter unit is used for reducing a signal sampling rate, reducing a subsequent processing data amount and suppressing aliasing noise; The first compensation branch is used for performing I / Q imbalance correction on a mixed frequency signal in the receiving channel, correcting amplitude imbalance and phase imbalance of in-phase / quadrature branches in the digital down-conversion unit.

6. The W-band two-dimensional DBF microsystem based on the AiP technology according to claim 4, characterized in that, The receiving beam forming module (3.1.2) is connected with a second compensation branch of the consistency compensation module, and the second compensation branch is used for performing digital phase compensation on a multi-channel baseband signal before synthesis, correcting phase deviation caused by packaging parasitic parameters.

7. The W-band two-dimensional DBF microsystem based on the AiP technology according to claim 4, characterized in that, The transmitting beam forming module (3.2.1) is connected with a third compensation branch of the consistency compensation module; The transmitting beam forming module (3.2.1) comprises a weight calculation unit and a channel correction unit; The weight calculation unit is used for generating amplitude and phase weighting coefficients corresponding to a single beam, a multi-beam or an anti-interception mode; The channel correction unit is used for compensating amplitude and phase errors of multiple transmitting channels, avoiding beam pointing deviation and side lobe level rising. The third compensation branch is used for performing gain drift suppression on the weighted transmit signal, and compensating for channel gain fluctuation caused by temperature change and device aging in the package through digital feedback adjustment.

8. The W-band two-dimensional DBF microsystem based on the AiP technology according to claim 4, characterized in that, The transmit channel processing module (3.2.2) is connected with the fourth compensation branch of the consistency compensation module; The transmit channel processing module (3.2.2) comprises an interpolation filter unit, a digital up-conversion unit, a DAC unit and a digital pre-distortion unit. The interpolation filter unit is used for inserting sampling points to improve the signal data rate and adapt to the requirements of the DAC unit and up-conversion; The digital up-conversion unit is used for receiving the carrier signal output by the DDS module, and modulating the baseband signal to the transmit carrier frequency; The digital pre-distortion unit is used for generating a compensation signal to offset the nonlinear distortion of the subsequent power amplifier; The fourth compensation branch is used for performing I / Q imbalance correction again on the signal after digital up-conversion, and suppressing the secondary distortion products caused by the nonlinearity of the W-band mixer.

9. The W-band two-dimensional DBF microsystem based on the AiP technology according to claim 4, characterized in that, The DDS module (3.3) adopts any one of the following architectures: A centralized frequency source architecture provides the same source LO / carrier signal for all transceiver channels through a power division network, ensuring frequency consistency; A distributed frequency source architecture configures an independent DDS subunit for each transceiver channel, and maintains the phase consistency of each subunit through a synchronization mechanism, with a frequency resolution of Hz or mHz.

10. The W-band two-dimensional DBF microsystem based on the AiP technology according to claim 2, characterized in that, The radio frequency direct sampling transceiver module (2), the digital beamformer module (3), the FPGA module (5) and the frequency synthesizer module (6) are further connected with a cold plate (7); A heat-conducting gasket (8) is further arranged between the radio frequency direct sampling transceiver module (2) and the cold plate (7); The integrated module (4) is further independently integrated with an optical module (9), a power connector (10) and a radio frequency seat (11).

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