Ethernet-based time synchronization acquisition method, device, equipment and medium

Abstract

The invention relates to the technical field of Ethernet communication and digital information transmission, and discloses an Ethernet-based time synchronization acquisition method, device and equipment and a medium, and the method comprises the steps: obtaining initial network time based on a network time protocol and a precise time protocol; recovering the synchronous clock signal from the Ethernet physical layer signal and generating a trigger pulse signal aligned with a second boundary to generate second-level reference time; the trigger pulse signal and the synchronous clock signal are used for executing high-frequency counting accumulation to generate nanosecond-level fine time; performing frequency division processing on the synchronous clock signal based on the sampling rate configuration parameter to obtain a sampling driving clock; the analog-to-digital conversion unit is triggered at the effective jump edge of the sampling driving clock to sample and latch nanosecond-level fine time to generate a sampling timestamp, and the sampling timestamp is output in combination with sampling data. According to the method, time recovery, time refinement and sampling time locking are realized through a unified time base, so that sampling action and time counting are accurately aligned, and the data synchronization precision and consistency of distributed acquisition nodes are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of Ethernet communication and digital information transmission, and in particular to an Ethernet-based time synchronization acquisition method, device, equipment and medium. BACKGROUND

[0002] A distributed synchronization acquisition system is usually composed of multiple acquisition nodes deployed at different locations, and each acquisition node needs to synchronously acquire physical quantities or signals under a unified time base. With the wide application of distributed systems in industrial monitoring, structural health monitoring, power system measurement and other scenarios, the synchronization accuracy of multiple nodes directly affects the consistency and reliability of the acquired data, and therefore higher requirements are put forward for high-precision time synchronization and high-consistency sampling control.

[0003] In existing time synchronization technologies, Network Time Protocol (NTP) and Simple Network Time Protocol (SNTP) are the most common network time service methods, but their synchronization accuracy can only reach the millisecond level, which cannot meet the demand for microsecond or even nanosecond time sequence consistency. Such protocols rely on message round-trip delay estimation, and when the network load fluctuates or the path changes, the time offset will significantly increase, resulting in perceptible time drift of distributed nodes.

[0004] GPS time service can achieve high synchronization accuracy, but it is easily affected by factors such as reception environment, electromagnetic interference, antenna deployment conditions, etc., and its stability is difficult to guarantee. In addition, the GPS scheme has high cost, and it cannot work stably in indoor, closed environments or specific industrial scenarios, which makes it have deployment limitations in many distributed acquisition applications.

[0005] IEEE1588v2 protocol can achieve sub-microsecond time synchronization through message mechanism, but the quality of time synchronization is still affected by network jitter, hardware timestamp precision and master-slave link stability. At the same time, this protocol mainly provides the alignment capability of time reference, and relies on external clock source in terms of frequency stability, and it is difficult to independently ensure high-stability synchronization clock for a long time.

[0006] Sync Ethernet (SyncE) can extract a high-stability frequency signal from the physical layer, which is beneficial to improving frequency consistency, but its mechanism itself does not provide phase synchronization capability, and cannot meet the scene demand for time stamp alignment and trigger consistency control. Since it only has frequency locking capability, the system still needs to rely on other mechanisms to supplement the alignment of absolute time and the control of millimicrosecond-level trigger precision. SUMMARY

[0007] The main purpose of the present application is to provide an Ethernet-based time synchronization acquisition method, device, equipment and storage medium, aiming to solve the technical problem that the prior art cannot obtain high-precision time synchronization and strictly aligned sampling actions among distributed acquisition nodes at the same time, resulting in difficulty in realizing nanosecond-level synchronous acquisition based on a unified time base.

[0008] To achieve the above-mentioned purpose, the present application provides an Ethernet-based time synchronization acquisition method, comprising: The data acquisition instrument communicates with the central control device based on the network time protocol, and interacts based on the precise time protocol to obtain an initial network time; The processing unit in the data acquisition instrument drives the physical layer interface unit to recover a synchronization clock signal from the Ethernet physical layer signal, and generates a trigger pulse signal aligned with the second boundary, and generates a second-level reference time based on the initial network time; The trigger pulse signal is used as a reset signal, and the synchronization clock signal is used as a counting driving source to perform high-frequency counting accumulation based on the second-level reference time to generate a nanosecond-level fine time; Receive a sampling rate configuration parameter, and perform frequency division processing on the synchronization clock signal based on the sampling rate configuration parameter to obtain a sampling driving clock; At the effective jump edge of the sampling driving clock, control the analog-digital conversion unit to perform a sampling action, and latch the nanosecond-level fine time to generate a sampling time stamp, and combine and output the sampling data and the sampling time stamp.

[0009] Further, to achieve the above-mentioned purpose, the present application provides an Ethernet-based time synchronization acquisition device, comprising: A time synchronization communication module is configured to communicate with the central control device based on the network time protocol through the data acquisition instrument, and interact based on the precise time protocol to obtain an initial network time; A physical layer clock recovery module is configured to drive the physical layer interface unit in the data acquisition instrument to recover a synchronization clock signal from the Ethernet physical layer signal through a processing unit, and generate a trigger pulse signal aligned with the second boundary, and generate a second-level reference time based on the initial network time; A high-precision timing module is configured to use the trigger pulse signal as a reset signal, and use the synchronization clock signal as a counting driving source to perform high-frequency counting accumulation based on the second-level reference time to generate a nanosecond-level fine time; A sampling clock generation module is configured to receive a sampling rate configuration parameter, and perform frequency division processing on the synchronization clock signal based on the sampling rate configuration parameter to obtain a sampling driving clock; A data acquisition and timestamp module is configured to perform a sampling action by controlling an analog-digital conversion unit at an effective jump edge of the sampling driving clock, and to latch a nanosecond-level fine time to generate a sampling timestamp, and to combine and output sampling data and the sampling timestamp.

[0010] Further, to achieve the above object, the present application also provides a computer device, which comprises a memory, a processor, and an Ethernet-based time synchronization acquisition program stored in the memory and executable on the processor, and the Ethernet-based time synchronization acquisition program, when executed by the processor, implements the steps of the above-described Ethernet-based time synchronization acquisition method.

[0011] Further, to achieve the above object, the present application also provides a computer readable storage medium, which stores an Ethernet-based time synchronization acquisition program, and the Ethernet-based time synchronization acquisition program, when executed by a processor, implements the steps of the above-described Ethernet-based time synchronization acquisition method.

[0012] Beneficial effects: The present application relates to the technical field of Ethernet communication and digital information transmission, and discloses an Ethernet-based time synchronization acquisition method, device, equipment and medium, which comprises the following steps: obtaining an initial network time based on a network time protocol and a precise time protocol; recovering a synchronization clock signal from an Ethernet physical layer signal and generating a trigger pulse signal aligned with a second boundary to generate a second-level reference time; performing high-frequency counting accumulation using the trigger pulse signal and the synchronization clock signal to generate nanosecond-level fine time; performing frequency division processing on the synchronization clock signal based on a sampling rate configuration parameter to obtain a sampling driving clock; triggering an analog-digital conversion unit to sample and latch the nanosecond-level fine time to generate a sampling timestamp at an effective jump edge of the sampling driving clock, and combining and outputting sampling data and the sampling timestamp. The present application realizes time recovery, time refinement and sampling time locking through a unified time base, accurately aligns the sampling action with the time counting, and improves the data synchronization precision and consistency of the distributed acquisition node. BRIEF DESCRIPTION OF DRAWINGS

[0013] The present application will be further described below in combination with the drawings and embodiments, and the drawings show: Figure 1 An application environment schematic diagram of an Ethernet-based time synchronization acquisition method in an embodiment of the present application; Figure 2 A flowchart of an Ethernet-based time synchronization acquisition method in an embodiment of the present application; Figure 3 A functional module schematic diagram of a preferred embodiment of an Ethernet-based time synchronization acquisition device of the present application; Figure 4 A structure schematic diagram of a computer device in an embodiment of the present application; Figure 5 Another structural schematic diagram of a computer device in an embodiment of the present application; Figure 6 A distributed precise synchronization acquisition system structural schematic diagram of an Ethernet-based time synchronization acquisition device in an embodiment of the present application; Figure 7 A functional schematic diagram of internal module composition of a data acquisition instrument in an embodiment of the Ethernet-based time synchronization acquisition device of the present application; Figure 8 A nanosecond-level fine time generation timing schematic diagram in an embodiment of the Ethernet-based time synchronization acquisition method of the present application. DETAILED DESCRIPTION

[0014] It should be understood that the specific embodiments described herein are merely illustrative of the present application and do not limit the present application.

[0015] The Ethernet-based time synchronization acquisition method provided by the embodiments of the present application can be applied in an application environment such as Figure 1 , wherein a client communicates with a server through a network. The server can obtain an initial network time based on a network time protocol and a precise time protocol through the client; a synchronization clock signal is recovered from an Ethernet physical layer signal and a trigger pulse signal aligned with a second boundary is generated to generate a second-level reference time; a high-frequency count accumulation is performed using the trigger pulse signal and the synchronization clock signal to generate a nanosecond-level fine time; a sampling driving clock is obtained by frequency dividing the synchronization clock signal based on a sampling rate configuration parameter; an analog-digital conversion unit is triggered and latched to sample the nanosecond-level fine time at an effective jump edge of the sampling driving clock to generate a sampling time stamp, and the sampling data and the sampling time stamp are combined and output. The present application realizes time recovery, time refinement and sampling time locking through a unified time base, accurately aligns the sampling action with the time count, and improves the data synchronization accuracy and consistency of the distributed acquisition nodes. The client can be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers and portable wearable devices. The server can be implemented by an independent server or a server cluster composed of multiple servers. The present application will be described in detail through specific embodiments.

[0016] Please refer to Figure 2 , Figure 2 The flow schematic diagram of an embodiment of the Ethernet-based time synchronization acquisition method provided by the present application. It should be noted that although the logical order is shown in the flowchart, in some cases, the steps shown or described can be performed in an order different from that herein.

[0017] As shown in Figure 2 , the Ethernet-based time synchronization acquisition method proposed by the present application includes the following steps: S10, the data acquisition instrument communicates with the central control device based on the network time protocol and interacts based on the precise time protocol to obtain an initial network time; In this embodiment, in the process that the data acquisition instrument communicates with the central control device based on the network time protocol and interacts based on the precise time protocol to obtain an initial network time, a communication link with the central control device is first established through an Ethernet interface. This interface is responsible for message transmission and reception, link state maintenance and data analysis, and provides basic support for subsequent time interaction. The network time protocol provides multiple time fields in communication for deriving propagation delay and local time offset. The processing unit reads these fields from the received message and derives the preliminary time offset based on the local counter state.

[0018] The precise time protocol is used to further improve the time interaction accuracy. This protocol relies on a hardware-level timestamp mechanism to record the actual time points of message arrival and sending. The timestamp is generally generated by a special timestamp engine inside the physical layer interface. The engine generates a time tag based on the boundary time of the frame and the relationship with the local clock count. The time tag value is directly related to the frequency stability of the local oscillator, so the local clock state needs to be considered before analysis.

[0019] The central control device acts as a time reference node in the precise time protocol interaction, and transmits reference time information to the acquisition instrument through bidirectional message exchange. The processing unit combines the request sending time, request receiving time, response sending time and response receiving time to derive the link delay, and calculates the offset of the local clock relative to the reference clock. The offset is corrected through frequency compensation and phase adjustment operations. The correction process can act on a digital clock synthesizer or a controllable oscillator to form a more stable local timing basis.

[0020] After completing delay compensation, frequency correction and phase adjustment, the processing unit fuses the corrected timestamp and the local timing state to generate a unified time reference value. This value serves as the initial network time for subsequent clock recovery and high-frequency counting, and contains link calibration information, delay compensation amount and local calibration result. The exchange device maintains a fixed delay during message forwarding, which helps to stabilize the calculation of the time tag, thereby improving the reliability of the initial network time.

[0021] This embodiment combines the rough time reference provided by the network time protocol with the hardware-level time tag of the precise time protocol, and forms a unified initial network time through delay compensation, frequency correction and phase adjustment, so that the acquisition instrument obtains a stable and reliable time reference, which facilitates the maintenance of cross-node consistency in subsequent synchronization recovery and fine timing links.

[0022] S20, recovering a synchronization clock signal from the Ethernet physical layer signal by a processing unit in the data acquisition instrument driving a physical layer interface unit, and generating a trigger pulse signal aligned with a second boundary based on the initial network time to generate a second-level reference time; In the embodiment, the process of recovering the synchronization clock signal from the Ethernet physical layer signal by the processing unit in the data acquisition instrument driving the physical layer interface unit is based on the configuration control capability of the processing unit to the physical layer interface. The processing unit first writes initialization control information to the physical layer interface unit, which contains the enable instruction of the clock recovery function, the register loading parameters and the link monitoring switch, so that the physical layer interface can extract the frequency component in the encoded stream when receiving the Ethernet data frame. After the Ethernet physical layer signal is digitally decoded, the internal bit stream converter uses the encoding characteristics to derive the frequency characteristics of the physical layer and recover a stable clock signal, which is used to build the subsequent timing system.

[0023] The timestamp engine in the physical layer interface performs periodic counting based on the recovered clock signal. The periodic counting can capture the rising edge position of the clock signal, and determine the corresponding position of the second boundary by the counter accumulation method. The second boundary is usually derived from the second information in the initial network time. After the processing unit loads the initial network time, the physical layer interface infers the second boundary time according to the trend of the second information, and outputs a trigger pulse signal at the corresponding position. The trigger pulse signal is composed of a fixed-width digital pulse, which is used to establish a unified second starting point in the time system and provide a synchronization reference for different modules.

[0024] After receiving the synchronization clock signal and the trigger pulse signal, the processing unit generates a second-level reference time by using the time sequence relationship of the two types of signals and combining the value of the initial network time. The generation process of the second-level reference time includes mapping the second count in the initial network time with the time position of the trigger pulse, incorporating the time advance rate provided by the synchronization clock signal into the calculation, and constructing a continuous time expression structure across the second by digital expression. The second-level reference time is used to provide a unified time starting point for subsequent high-frequency counting, and its structure includes second count information, cross-second state identification and displacement parameters associated with the synchronization clock frequency.

[0025] By recovering the synchronization clock from the physical layer signal and establishing a unified second boundary with the trigger pulse, and then generating a continuous and unified second-level reference time combined with the initial network time, the embodiment makes the time system have an accurate starting point and a stable advance rate, builds a reliable foundation for subsequent nanosecond-level timing, and realizes time consistency in a cross-node environment.

[0026] S30, using the trigger pulse signal as a reset signal and the synchronization clock signal as a counting driving source to perform high-frequency counting accumulation based on the second-level reference time, and generating a nanosecond-level fine time; In the embodiment, the use of the trigger pulse signal as a reset signal is derived from the second boundary jump extracted by the physical layer interface unit from the Ethernet physical layer signal. The pulse is sent into the counting circuit through the synchronizer or digital trigger logic in the hardware link, realizing the zeroing of the counting register structure and making the counting start point consistent with the whole second boundary. The reset mechanism can be realized by synchronous zeroing, asynchronous zeroing or edge-triggered zeroing, and is executed by register array, digital logic or timer internal unit according to the hardware structure.

[0027] The use of the synchronous clock signal as the counting driving source is based on the continuous high-frequency beat recovered by the physical layer, which is input to the clock end of the counting circuit after being stabilized by the clock tree or phase-locked loop. Each jump edge triggers the counting accumulation, and the second-in-second offset is incremented at a fixed frequency. The counting logic can be implemented in the synchronous counter of the FPGA, the timer channel or the on-chip counting module of the DSP, each of which can ensure the monotonic increment characteristic at a high frequency.

[0028] The high-frequency counting accumulation based on the second-level reference time involves establishing a mapping relationship between the coarse-grained time and the second-in-second offset. The second-level reference time is determined by the initial network time and the second boundary trigger event, providing an integer time reference for subsequent counting. The counting value as the offset needs to be processed by overflow detection and register update logic, and converted to nanoseconds according to the synchronous clock frequency.

[0029] The process of generating nanosecond-level fine time synthesizes the second-level reference time and the converted offset to a unified format, such as storing the second value in the high bit and the nanosecond offset in the low bit. The time field can use 64 bits or higher bit width, and the combination is completed by hardware or software according to uniform rules. The final time is recorded in the data output path for marking the acquisition timing. The above-mentioned links form a continuous link: the trigger pulse defines the starting point, the synchronous clock provides the stepping beat, the high-frequency counting generates the offset, and the second-level reference time and the offset are synthesized to obtain the nanosecond-level time.

[0030] The embodiment forms a stable nanosecond-level time recording capability by aligning the whole second time with the trigger pulse, generating a high-frequency offset with the synchronous clock, and accumulating on the second-level reference time, thereby realizing consistent time reference across devices. The system still maintains high precision and high consistency under different networks, different hardware architectures and different sampling conditions, meeting the needs of accurate timing marking for high-speed data acquisition.

[0031] S40, receiving a sampling rate configuration parameter, performing frequency division processing on the synchronous clock signal based on the sampling rate configuration parameter to obtain a sampling driving clock; In the present embodiment, receiving the sampling rate configuration parameter involves inputting a digitization configuration value given by an external control unit or an internal strategy module into the processing unit, which is used to define the target sampling rate. The sampling rate configuration parameter usually exists in the form of a register value, a communication message field, a configuration file parameter, or a runtime dynamic input, and its source can be a higher-level scheduling system, a sensor driving logic, or a task configuration module. After entering the processing unit, the sampling rate configuration parameter needs to undergo a legality check, such as a range judgment, a data bit width judgment, or a boundary limit processing, to avoid exceeding the hardware counting capability or generating a sampling period that cannot meet the synchronization requirements.

[0032] The synchronization clock signal, as the clock source to be divided, has a frequency output by a physical layer recovery circuit or stabilized by a phase-locked loop, and is the high-frequency beat basis of the entire acquisition system. This clock is usually significantly higher than the target sampling rate, so it must be reduced to a sampling drive clock used to control the sampling instant through frequency division logic. The input edge of the synchronization clock signal enters the frequency division calculation logic after passing through the input synchronization module, which is used to maintain phase stability and counting persistence.

[0033] The process of frequency division based on the sampling rate configuration parameter is essentially mapping the sampling rate to an integer or approximate integer multiple relationship of the synchronization clock frequency. To achieve this relationship, the processing unit calculates the frequency division coefficient according to the ratio of the synchronization clock frequency to the sampling rate configuration parameter and stores it in the hardware register structure or internal buffer structure. The frequency division coefficient determines the counting endpoint of the frequency division counter, which is reset when the counter reaches the endpoint value and outputs a sampling drive pulse. The calculated frequency division coefficient can be used as a direct counting endpoint in hardware, or it can be processed through correction logic to reduce errors caused by clock frequency drift or sampling rate changes.

[0034] The process of obtaining the sampling drive clock relies on the continuous counting of the frequency division counter on the synchronization clock signal. Each synchronization clock jump edge triggers the counter to increment, and when the counter reaches the value specified by the frequency division coefficient, a sampling drive edge is generated and the counter is reset. The sampling drive clock can be in the form of a pulse, a square wave with controllable duty cycle, or a trigger signal type defined by the downstream sampling module. The generation of the sampling drive clock needs to ensure period stability, phase continuity, and edge accuracy, so that the subsequent sampling action can be accurately associated with the nanosecond-level fine time.

[0035] The present embodiment achieves a stable relationship between the adjustable sampling rate and the high-frequency synchronization clock through the frequency division mapping of the sampling rate configuration parameter and the synchronization clock signal, so that the acquisition action and the time system remain synchronized. This mechanism makes the sampling period configurable and consistent with the time reference, avoiding sampling drift caused by clock drift or frequency mismatch.

[0036] S50, at the active transition edge of the sampling driving clock, a sampling action is performed by controlling the analog-digital conversion unit, and a nanosecond-level fine time generation sampling time stamp is latched, and the sampling data is combined with the sampling time stamp and output.

[0037] In the embodiment, the active transition edge of the sampling driving clock is the timing reference for triggering the sampling action. The transition edge usually comes from the sampling driving clock generated by the previous link, and can be a rising edge or a falling edge. The specific form is determined by hardware configuration. The active transition edge represents the unique mark of the sampling moment, so it needs to pass through the edge detection module before entering the sampling control circuit, and convert the continuous high and low levels into discrete transition events to ensure that the input signal does not produce multiple false triggers due to jitter.

[0038] After the active transition edge of the sampling driving clock appears, the sampling control circuit initiates a sampling action instruction to the analog-digital conversion unit. The sampling action is the process of the analog-digital conversion unit obtaining the instantaneous voltage from the analog input channel and performing quantization. The quantization process can rely on the sampling holding circuit or the internal sampling network to obtain a stable input signal, and then enter the comparator array or the successive approximation module to complete the digitization process. After the sampling action is completed, the original sampling data is output and written into the data path buffer structure waiting for time stamp binding.

[0039] The nanosecond-level fine time is generated by a high-frequency counting link, and its value is latched by a time stamp latch at the sampling time. The latching process is to capture the current nanosecond-level fine time into a fixed register structure, so that the time information generated during the sampling process will not change as the counter continues to accumulate. This latching behavior ensures that the sampling data and time information correspond one by one, and avoids time drift caused by processing delay.

[0040] The sampling time stamp generation process includes format conversion, which converts the latched nanosecond-level fine time into a unified time expression format used by the system, such as high bits for second count and low bits for nanosecond offset, or using a fixed length binary time field. The generated sampling time stamp has absolute and alignable properties, and can be compared with the time stamp of other nodes across devices.

[0041] The combined output of the sampling data and the sampling time stamp is to bind the two types of information together to form a transmissible data structure. The binding operation can be realized by parallel splicing, structured packaging or ring buffer writing, so that the collected data has complete timing properties before entering the transmission channel. The final product of the combined output is organized as a sampling data packet, which includes the sampling value, the sampling time stamp and the necessary identification field for subsequent channel identification.

[0042] The embodiment triggers the sampling action at the effective jump edge of the sampling driving clock, and latches the nanosecond-level fine time at the same time, so as to realize the completely synchronized collection output of time and data. The mechanism ensures that the sampling point strictly corresponds to the time reference, and avoids the error caused by the delay of the sampling action or the offset of the time latch.

[0043] In one embodiment, the above step S10 comprises: S101, receiving a power over Ethernet signal through an Ethernet interface in the data acquisition instrument, and converting the power over Ethernet signal to generate a working voltage by a power management unit, using the working voltage to make the data acquisition instrument enter a preparation working state; S102, initiating a network time protocol service through a central control device, and sending a time synchronization request to a network switch, and obtaining a coarse time reference by processing the time synchronization request through the network switch; S103, establishing a bidirectional dialogue with the network switch based on a precise time protocol through a processing unit in the data acquisition instrument, and performing request and response exchange of time messages using the coarse time reference; S104, forwarding related messages of the network time protocol and the precise time protocol through the network switch as an intermediate node, and calculating an intermediate path delay based on the request and response exchange of the time messages; S105, extracting timestamp information from the precise time protocol message through the processing unit, and correcting the frequency deviation and phase offset of the local clock using the timestamp information and the intermediate path delay to generate corrected time data; S106, determining a network transmission delay compensation value through multiple round-trip time measurements, and applying the delay compensation value to the corrected time data to generate compensated time data; S107, executing a time synchronization algorithm based on the compensated time data and the local clock state through the processing unit to generate an initial network time.

[0044] In the embodiment, when the data acquisition instrument communicates with the central control device based on the network time protocol and acquires the initial network time, it first accesses the wired network through the Ethernet interface. The Ethernet interface not only bears the data link but also can carry the power over Ethernet signal. The power over Ethernet signal transmits direct current energy and data signal through a differential line pair at the physical layer. The Ethernet interface isolates the line side from the device side through a transformer coupling and a magnetic device, and then introduces the power supply part into the power management unit. The power management unit internally includes a rectifier circuit, a DC / DC conversion unit, a voltage detection and power-on timing control logic, which converts the input power over Ethernet signal into multiple stable working voltages, such as providing a digital core voltage for the processing unit, an analog voltage for the physical layer interface, and independent voltage rails for the memory and clock chips. After detecting that each voltage meets the standard and remains stable, the power management unit releases the reset control of the processing unit and peripherals through the reset control logic, so that the data acquisition instrument enters the preparation state. In this state, the processing unit has completed the bootstrap and basic peripheral initialization, but has not yet executed the synchronous acquisition task.

[0045] The central control device usually deploys a time service program, and the network time protocol service listens to a preset port in the program to maintain a high-precision local clock or keep synchronization with an upstream time source. The central control device periodically or under external triggering constructs time synchronization request response logic, receives requests from multiple data acquisition instruments, and fills in the current time field and related timestamps in the response message according to the network time protocol format. The time synchronization request is sent from the data acquisition instrument to the network switch, which forwards it according to the forwarding table and may queue the message. After processing, the time synchronization request reaches the central control device and is parsed by the time service program. The central control device generates a response message with current time information according to the request content and arrival time, and then forwards it back to the data acquisition instrument through the network switch. The data acquisition instrument parses the response in the processing unit, compares the time field in the message with the local receiving time, and obtains a rough time reference, which generally reaches the millisecond to sub-millisecond level of accuracy, providing an initial time range for subsequent high-precision synchronization, and making the local time difference with the target time converge to a smaller interval.

[0046] The processing unit in the data acquisition instrument initiates the precision time protocol stack after obtaining the coarse time reference. The processing unit establishes a precision time protocol session with the network switch through socket or raw Ethernet frame, periodically sends synchronization and delay measurement messages according to the protocol specification, and receives the corresponding responses returned by the network switch. The coarse time reference is used to initialize the local timer, so that the precision time protocol operation is based on the time axis that has been aligned to the second level, thereby reducing the influence of large offset on timestamp calculation. The processing unit records the local sending time when sending the synchronization message each time, records the local receiving time when receiving the message returned by the network switch, and reads the opposite end timestamp carried in the message at the same time, forming a set of time message request and response exchange data for subsequent delay and deviation calculation.

[0047] The network switch plays the role of intermediary node in the whole time synchronization process. On the one hand, it forwards the network time protocol message to ensure that the coarse time reference link is unblocked, and on the other hand, it forwards the precision time protocol synchronization message and delay measurement message, and generates high-precision timestamps and inserts them into the message field when the message enters and leaves the port in the case of hardware timestamp capability. Through these timestamps, the intermediate path delay between the central control device and the data acquisition instrument can be calculated. The intermediate path delay calculation is usually based on the uplink and downlink path time difference and the symmetry assumption, and the processing unit combines the timestamps in the sending and receiving directions to obtain the link propagation time and queuing time component, so as to distinguish the propagation delay introduced by the network from the local clock deviation.

[0048] After obtaining the time message and the intermediate path delay, the processing unit deeply analyzes the precision time protocol message. The precision time protocol message contains multiple timestamp fields, such as the opposite end sending time, the local receiving time, the local sending delay request time, and the opposite end receiving delay request time. The processing unit substitutes these timestamps and the intermediate path delay into the clock deviation calculation model, in which the difference between the local clock reading and the reference clock reading can be decomposed into frequency deviation and phase offset. The frequency deviation corresponds to the proportional error between the local oscillator frequency and the target frequency, which can be compensated by adjusting the digital time reference count step or controlling the programmable oscillator control word. The phase offset corresponds to the instantaneous difference between the time readings at the current time, which can be corrected by one-time offset correction or segmented step-by-step alignment. The processing unit periodically updates the frequency parameter and the phase parameter in the control loop to form the corrected time data, which reflects that most of the static deviation and single propagation error have been stripped off on the time axis.

[0049] When the network is in a dynamic environment, the link queuing delay and switching processing delay fluctuate with the load changes. To further suppress this effect, the processing unit performs multiple round-trip time measurements, each of which includes sending a set of precise time protocol request messages and waiting for the corresponding responses, and after arrival, calculating a single round-trip time using the sending and receiving time stamps. A series of round-trip time values obtained by multiple measurements can be processed by statistical operations, such as using a sliding window average, a weighted average, a median filter, or a robust statistical method that excludes outliers, to determine a network transmission delay compensation value. The network transmission delay compensation value reflects the average propagation characteristics of the link in the current period of time, and can offset the deviation caused by some short-term congestion or queuing jitter. The processing unit applies the network transmission delay compensation value to the corrected time data obtained earlier, further corrects the dynamic error of the propagation path on the time axis, and obtains compensated time data.

[0050] The compensated time data needs to be further processed in combination with the local clock state. The local clock state can include the frequency stability of the local oscillator, the temperature drift estimate, the historical deviation statistics, and the current locking state, etc. The processing unit uses the compensated time data as an external reference and the local clock state as a control constraint in the time synchronization algorithm, and realizes time convergence through a discrete-time control law, a phase-locked loop structure, or a digital filter structure. The algorithm can introduce a limit slope to the time deviation to avoid large time jumps causing abnormal upper-layer services, and can dynamically adjust the convergence speed according to the quality of the local clock, relaxing the correction frequency under the condition of a high-quality oscillator, and increasing the correction frequency under the condition of a low-quality oscillator. Through continuous iterative adjustment, the local clock gradually approaches the compensated time data, and reaches a state where the steady-state deviation is within a preset threshold. In this state, the time reading given by the processing unit is the initial network time, which is used as a unified time reference for subsequent generation of second-level reference time, high-frequency count accumulation, and generation of sampling time stamps.

[0051] The time acquisition mechanism of the network time protocol and the precise time protocol is used in the embodiment. After power-on, the data acquisition instrument enters a stable preparation state quickly by using the power over Ethernet signal and the power management unit, and then obtains a rough time reference in a short time through the network time protocol, so that the local time axis falls into the target time interval. On this basis, the precise time protocol is used to exchange time messages with the network switch, the local clock frequency deviation and phase offset are separated from the timestamp information and the intermediate path delay, and correction is completed. At the same time, the network transmission delay compensation value is estimated through multiple round-trip time measurements and is applied to the corrected time data. Then, the initial network time is generated by combining the local clock state and executing the time synchronization algorithm. Therefore, under the condition of network jitter and link delay fluctuation, the initial network time with high precision, stability and consistency with the central control device can be obtained, which provides a reliable time reference for subsequent generation of the second-level reference time and calculation of the nanosecond-level fine time, and improves the synchronization accuracy and robustness of the distributed synchronous acquisition system in the multi-node scene.

[0052] In one embodiment, the above step S20 comprises: S201, sending a configuration instruction to a physical layer interface unit through a processing unit in the data acquisition instrument to start a clock recovery function; S202, extracting clock information from an Ethernet physical layer signal through the physical layer interface unit, and generating a synchronization clock signal based on the clock information; S203, monitoring the period count of the synchronization clock signal through a timestamp engine in the physical layer interface unit, and generating a trigger pulse signal aligned with the second boundary at the corresponding moment of the second boundary; S204, receiving the synchronization clock signal and the trigger pulse signal through the processing unit; S205, executing clock synchronization calculation to generate synchronization time data based on the initial network time, the synchronization clock signal and the trigger pulse signal through the processing unit; S206, applying a frequency calibration and phase adjustment algorithm to process the synchronization time data through the processing unit to generate a second-level reference time.

[0053] In this embodiment, when the processing unit in the data acquisition instrument drives the physical layer interface unit to recover the synchronization clock signal from the Ethernet physical layer signal, the processing unit needs to first issue a configuration instruction to activate the clock recovery function inside the physical layer interface unit. The configuration instruction is usually completed through the management interface in the register write mode. The processing unit determines whether the physical layer interface unit has completed the power-on self-test, link establishment and baseband initialization according to the internal state machine. When the configuration instruction takes effect, the physical layer interface unit enters the clock recovery state, in which the symbol boundary is extracted based on the voltage transition characteristics of the Ethernet differential signal, and a stable sampling clock is constructed through the phase-locked loop and clock recovery circuit. The source of the clock recovery function depends on the embedded clock structure in the Ethernet physical layer protocol. The bit stream on the differential line has sufficient transition information at the symbol level, so that the physical layer interface can derive an accurate clock frequency without an additional independent clock.

[0054] After the physical layer interface unit extracts the symbol-level time reference, it generates a synchronization clock signal through frequency multiplication, phase filtering and jitter suppression circuits. The frequency of the synchronization clock signal can reach hundreds of megahertz, and its stability is closely related to the divider ratio in the phase-locked loop structure, the characteristics of the voltage-controlled oscillator and the loop bandwidth. The synchronization clock signal has low period jitter and frequency drift after the link is stable, and can provide a reliable high-frequency driving source for subsequent time reference generation.

[0055] The timestamp engine inside the physical layer interface unit continuously counts when the synchronization clock signal is running stably. The timestamp engine records each clock rising edge or falling edge through the period counting method, and identifies the time corresponding to the second boundary based on the overflow rule of the count value. The second boundary usually comes from the second field in the precision time protocol message or the target time axis calculated. After the timestamp engine identifies the expected position of the second boundary, it generates a trigger pulse signal within a small time window before and after the counter reaches that position. The generation mechanism of the trigger pulse signal involves delay compensation, phase approximation control and count overflow prediction circuits, so that the trigger pulse signal can be strictly aligned with the second-level time axis.

[0056] After the processing unit outputs the synchronization clock signal and the trigger pulse signal from the physical layer interface unit, it connects these signals to the internal logic module through the high-speed input channel, and performs edge detection, time capture and signal consistency analysis. The synchronization clock signal and the trigger pulse signal are integrated by the processing unit as input sequences for time calculation. The processing unit determines the time starting point, count step and pulse validity according to these inputs, thereby constructing the reference time framework.

[0057] The processing unit establishes a mapping between the second-level and the synchronization clock cycle count when performing the clock synchronization calculation in combination with the initial network time, the synchronization clock signal and the trigger pulse signal. The initial network time provides an absolute time reference, the trigger pulse determines the position of the second-level boundary, and the count increment of the synchronization clock signal constitutes the time resolution within the second. The processing unit maps the cycle count to a continuous time value by combining the cycle count value with the initial network time. The clock synchronization calculation involves time offset estimation, phase matching function, cycle continuity check and jitter filtering to improve the stability and continuity of the time scale within the second. Due to the extremely high frequency of the synchronization clock signal, the calculation steps must use fixed-point arithmetic and hardware acceleration structure to process the cycle count to avoid time drift caused by accumulated errors.

[0058] After the generation of the synchronization time data, the processing unit further processes the synchronization time data by applying a frequency calibration and a phase adjustment algorithm. The frequency calibration is used to offset the time drift caused by the oscillator offset by adjusting the time accumulation rate for the slight frequency deviation of the synchronization clock signal. The phase adjustment algorithm is used to eliminate the slight time error caused by the incomplete alignment of the phase of the trigger pulse. By establishing a phase adjustment factor, the synchronization time data is remapped to a more accurate time axis, so that the time value remains absolutely consistent at the second boundary. Frequency calibration and phase adjustment usually use digital phase-locked loop, proportional-integral regulator or reference error feedback mechanism to keep the second-level reference time stable in long-term operation. The second-level reference time formed after frequency calibration and phase adjustment is the basis for subsequent nanosecond-level fine time, and determines the long-term consistency and cross-node synchronization of the entire distributed synchronization link.

[0059] The above-mentioned synchronization clock signal recovery and second boundary trigger pulse generation mechanism are used in the embodiment. The data acquisition instrument constructs the high-precision time scale of the entire system by means of the high-stability synchronization clock recovered by the physical layer. The second-level alignment capability of the trigger pulse enables the processing unit to update the time axis at the accurate boundary time, avoiding the accumulated error in the second switching process. The clock synchronization calculation in combination with the initial network time, the synchronization clock cycle count and the trigger pulse time enables the second-level reference time to have both absolute time reference and high-frequency time resolution. Under the joint action of frequency calibration and phase adjustment, the second-level reference time maintains high consistency among the distributed nodes in the entire network, providing a stable, accurate and cross-node consistent time basis for subsequent nanosecond-level time accumulation and sampling timestamp generation, thereby significantly improving the time synchronization performance and anti-interference ability of the distributed synchronous acquisition system under complex network conditions.

[0060] In one embodiment, the above step S30 comprises: S301, detecting the rising edge of the trigger pulse signal by the synchronization timer module, and initializing the counter register; S302, generating a count value by performing a count accumulation operation at each rising edge of the synchronous clock signal as a driving source of the counter register; S303, reading a current count value of the counter register and converting the count value into a nanosecond-level time offset; S304, generating an unverified nanosecond-level fine time by performing an arithmetic addition of the second-level reference time and the nanosecond-level time offset; S305, monitoring an abnormal condition in the count accumulation operation and performing a validity check on the unverified nanosecond-level fine time to generate a verified nanosecond-level fine time.

[0061] In the embodiment, when the trigger pulse signal is used as a reset signal, the rising edge of the trigger pulse signal needs to be detected by a synchronous timer module first. The trigger pulse signal is from a previous pulse generation logic based on a second-level time, and the level transition characteristic of the trigger pulse signal can present stable edge characteristics at the second-level position of the time axis. The synchronous timer module usually completes the capture of the rising edge through an edge detection circuit, and the edge detection circuit uses an asynchronous synchronous flip-flop chain and a special comparison logic to avoid the introduction of errors by metastability, and immediately executes an internal reset path after detecting the rising edge. The reset path initializes the counter register, clears the register or sets it to a defined starting value, so that the time counting starts again from the unified second-level boundary.

[0062] After the initialization of the counter register, the high-frequency count accumulation is performed with the synchronous clock signal as the driving source. The frequency of the synchronous clock signal is usually in the range of tens of megahertz to hundreds of megahertz, and its stability depends on the physical layer recovery mechanism and the post-stage filtering process. The counter register triggers the accumulation logic at each rising edge of the synchronous clock signal, so that the count value strictly increases according to the period of the synchronous clock signal. The accumulation process is performed by a hardware fixed-point adder, which ensures that the time precision is still determined under high-frequency conditions. The selection of the counter bit width is usually completed in the system design stage, which can cover the required count range in the second-level time period.

[0063] During the counting process, the current count value of the counter register needs to be read periodically and converted into a nanosecond-level time offset. The conversion process obtains the nanosecond-level time offset by multiplying the count value by the period of the synchronous clock signal or by table mapping. The period value of the synchronous clock signal is determined by the previous recovery mechanism, for example, if the frequency of the synchronous clock signal is 125MHz, the corresponding count step is about 8 nanoseconds. The conversion circuit maps the count value to the time offset through a multiplier or a hardware logic table, so that the periodic count can directly reflect the actual nanosecond-level time position in the second-level time period.

[0064] The arithmetic addition process of the second-level reference time and the nanosecond-level time offset constitutes unverified nanosecond-level fine time. The second-level reference time provides an absolute second-level starting point, and the nanosecond-level time offset provides high-resolution subdivision within a second. The two are combined to form a continuous time axis by means of addition mapping. The addition operation is generally based on fixed-point format to reduce numerical jitter, and the introduced time value needs to satisfy the cross-period continuity check to avoid time jumps caused by counter update lag or jitter.

[0065] In order to ensure the reliability of the nanosecond-level fine time, abnormal conditions in the high-frequency counting accumulation operation process need to be continuously monitored. The abnormalities include loss of synchronous clock signal, abnormal jitter of trigger pulse, counter register overflow, and count jump not conforming to period continuity. The monitoring module identifies abnormal conditions based on a logic comparator, a period prediction model, and a high-speed sampling feedback mechanism. If behavior inconsistent with the expected time axis is detected, the unverified nanosecond-level fine time needs to be investigated, and a consistency algorithm is used to verify whether the time value forms a continuous sequence with the second-level reference time, the period count, and the previous and subsequent time segments. The nanosecond-level fine time that passes the verification is generated after completing the above consistency check and can be used by the subsequent sampling timestamp module. The verification process combines edge time prediction, counter step comparison, and adjacent time difference verification mechanisms to ensure that the time value remains reliable under static and dynamic conditions.

[0066] The embodiment builds a high-frequency counting link through a trigger pulse and a synchronous clock, so that time counting can form a continuous, stable, and nanosecond-level resolution time scale based on a second-level reference time. Edge detection and counter initialization ensure the consistency of the time starting point at each second boundary, high-frequency accumulation ensures sufficient time resolution within a second, and the count value conversion mechanism provides nanosecond-level time precision. The abnormality monitoring and time verification mechanism further ensures that reliable time output can still be formed under electromagnetic interference, link jitter, or transient abnormal conditions.

[0067] In one embodiment, the above step S40 includes: S401, receiving a sampling rate configuration parameter from a central control device through a configuration interface; S402, calculating a frequency division coefficient according to the sampling rate configuration parameter and the frequency of the synchronous clock signal; S403, configuring the working parameters of the programmable frequency divider using the frequency division coefficient; S404, performing integer frequency division processing on the synchronous clock signal through the programmable frequency divider to generate a frequency-divided clock signal; S405, performing duty cycle optimization on the frequency-divided clock signal to generate an optimized clock signal; S406, monitoring the stability of the optimized clock signal in real time to generate a verified sampling driving clock; S407, distribute the verified sampling driving clock to each data acquisition channel.

[0068] In the embodiment, when the sampling rate configuration parameter is received through the configuration interface, it is necessary to ensure that the configuration interface can stably deliver the numerical value type parameter. The configuration interface is usually implemented based on a serial connection, an Ethernet management channel or a field programmable communication link, and includes an input buffer, a parameter analysis module and a data verification circuit in hardware. The sampling rate configuration parameter is essentially a control parameter defining the sampling period or sampling frequency, and its source is the operation management logic of the central control device. Necessary identification and verification fields are carried during transmission to ensure accurate analysis by the collected device. After receiving the parameter, the processing unit checks the numerical value range, format and sampling system capability to confirm that a reasonable frequency division relationship can be formed between the sampling rate and the frequency of the synchronization clock signal.

[0069] The calculation of the frequency division coefficient is based on the sampling rate configuration parameter and the frequency of the synchronization clock signal. The frequency of the synchronization clock signal is usually 125 MHz, 156.25 MHz or other high-frequency stable clock recovered by the physical layer. The calculation process relies on a fixed-point number operation unit or an embedded multiplier to generate a frequency division coefficient suitable for the control of the frequency divider through integer division, proportional conversion or fixed coefficient mapping. The calculation module needs to consider the integer ratio or approximate ratio relationship between the target output frequency corresponding to the sampling rate parameter and the frequency of the synchronization clock signal, and decide whether decimal frequency compensation is needed according to different hardware structures. After the calculation is completed, the frequency division coefficient is sent to the configuration path of the programmable frequency divider through the register.

[0070] The working parameters of the programmable frequency divider are determined by the frequency division coefficient. The programmable frequency divider usually includes multiple control registers, internal logic counter links and clock output buffer structures, which determine how many clock periods the synchronization clock signal needs to be divided into to output a complete sampling driving pulse according to the frequency division coefficient. The configuration process includes parameter writing, register updating, frequency division mode latching and output clock stability detection operations to ensure that the frequency divider enters the output state consistent with the calculation parameter. The programmable frequency divider strictly generates a new clock signal according to the internal counter loop during operation, so that the sampling driving clock remains consistent with the sampling rate configuration parameter in frequency.

[0071] The synchronous clock signal is subjected to integer frequency division in the frequency divider to generate a frequency-division clock signal with a lower frequency and a period consistent with the sampling rate. The signal needs to have a clear high-level duration and low-level duration in the timing structure, but the duty cycle of the initial frequency-division result may not meet the timing requirements of the sampling circuit, and therefore needs to be further optimized. The duty cycle optimization is implemented by a pulse width adjustment circuit, an asymmetric gate logic, or a duty cycle calibration module, so that the output clock forms a waveform structure between the high level and the low level that is more suitable for the analog front-end sampling circuit, the digital input circuit, or the analog-to-digital conversion driver, and reduces clock distortion and overshoot.

[0072] The optimized clock signal needs to be monitored for stability before being regarded as a sampling driving clock. The stability monitoring includes frequency stability analysis, duty cycle continuity evaluation, adjacent period consistency detection, and clock edge jitter analysis. The monitoring module obtains the clock parameters of consecutive periods through a time base measurer or a clock quality detection circuit, compares them with the expected values, and determines whether there is a sudden drift, an irregular jump of the edge, or an unstable duty cycle. The stability monitoring ensures that the clock can meet the time accuracy requirements of the sampling system, thereby forming a verified sampling driving clock.

[0073] The verified sampling driving clock needs to be distributed to multiple data acquisition channels. The distribution link usually relies on a clock tree structure, a low phase noise clock buffer, or a fan-out level driving circuit to output the same clock source to multiple sampling units with the same delay path. The delay difference between channels, the fan-out load capacity, the electromagnetic interference suppression, and the timing matching problem of cable or PCB wiring must be considered during the distribution process.

[0074] The present embodiment dynamically generates and maintains high stability of the sampling driving clock under different sampling rate requirements by analyzing the sampling rate configuration parameters, calculating the frequency division coefficient, configuring the programmable frequency divider, optimizing the clock duty cycle, monitoring the clock stability, and finally distributing. The sampling driving clock generated by the frequency division of the synchronous clock signal can meet the requirements of the sampling system in frequency, waveform, and phase characteristics, thereby keeping the acquisition channels consistent in time.

[0075] In one embodiment, the above step S402 includes: S4021, checking the rationality and effectiveness of the sampling rate configuration parameters by a parameter verification module to generate effective sampling rate parameters; S4022, performing integer division operation according to the effective sampling rate parameters and the frequency of the synchronous clock signal by a frequency division ratio calculation unit to generate a basic frequency division ratio; S4023, calculating a decimal frequency division compensation value based on the basic frequency division ratio; S4024, using the base frequency division ratio and the decimal frequency division compensation value, adding the base frequency division ratio and the decimal frequency division compensation value through an addition operation to generate a frequency division coefficient.

[0076] In this embodiment, the sampling rate configuration parameter is used to describe the expected sampling frequency or sampling period, generally in the form of a hertz value or a time interval, generated by the central control device according to the bandwidth requirement of the application scene, the signal spectrum characteristics and the data throughput capacity, and transmitted to the data acquisition side through the communication channel. The frequency of the synchronization clock signal is derived from the physical layer clock recovery circuit, which is the time reference of the entire acquisition system, and is usually a fixed high-frequency clock in the Ethernet environment, such as 125MHz, 156.25MHz, etc. After receiving the sampling rate configuration parameter, the parameter verification module will perform format checking, numerical range checking and hardware resource matching degree checking on the sampling rate configuration parameter according to the preset allowed sampling rate interval, the upper limit of the integer frequency division capability, the highest sampling frequency supported by the analog-to-digital conversion unit, and the relationship between the synchronization clock signal frequency and the sampling rate. For example, when the frequency of the synchronization clock signal is 125MHz, the parameter verification module will determine whether the sampling rate configuration parameter can be obtained through integer frequency division or decimal compensation frequency division, which can be analyzed by table lookup, interval judgment or inequality constraint. After verification, the valid sampling rate parameter is generated, and illegal parameters are marked as error state to block the subsequent frequency division calculation process.

[0077] The frequency division ratio calculation unit takes the valid sampling rate parameter and the frequency of the synchronization clock signal as input, and generates a base frequency division ratio through integer division operation. The integer division operation can be realized by hardware divider, shift-add structure or table lookup logic, and its calculation target is to determine how many synchronization clock signal periods to output one sampling driving pulse. The base frequency division ratio is an integer value, representing the approximate result of the ideal sampling frequency under the condition of only considering integer frequency division constraint. In actual application, the frequency of the synchronization clock signal and the target sampling rate are not necessarily strictly integer multiples, so using only integer frequency division will produce frequency error. In order to reduce this error, a decimal frequency division compensation value is needed. The decimal frequency division compensation value is calculated based on the residual between the base frequency division ratio and the target sampling rate, which can be obtained by comparing the target sampling frequency with the actual sampling frequency obtained by the base frequency division ratio, calculating the relative deviation between the two, and converting the deviation into a compensation parameter suitable for clock modulation or period interpolation. The compensation value can correspond to a period interpolation table of fixed length, or an increment value in a fractional frequency division accumulator, which is used to balance the sampling frequency in a long time scale, so that the average sampling rate approaches the target sampling rate.

[0078] The frequency division coefficient is obtained by combining the base frequency division ratio and the decimal frequency division compensation value through an addition operation. The addition operation is not limited to simple numerical addition, but also includes a cycle-by-cycle accumulation process in the hardware structure. The base frequency division ratio is responsible for defining the main frequency division rhythm of the counter, and the decimal frequency division compensation value periodically changes the output interval through an accumulation register or a phase accumulator, thereby adjusting the actual output frequency within a range of multiple frequency division cycles. The frequency division coefficient can be represented as a comprehensive control parameter containing an integer part and a decimal part, which is passed to the control unit in the programmable frequency divider or digital phase-locked loop.

[0079] The embodiment introduces a parameter verification module, a frequency division ratio calculation unit, and a decimal frequency division compensation calculation mechanism, and uses the frequency division coefficient as a unified control parameter to refine the relationship between the sampling rate configuration parameter and the frequency of the synchronization clock signal into a combination of the integer frequency division part and the decimal compensation part. Under the premise of ensuring that the sampling rate is within the range of hardware support, the frequency deviation between the synchronization clock signal frequency and the target sampling rate can be reduced, and the sampling drive clock can be closer to the expected sampling rate in long-term operation, thereby improving the consistency and frequency accuracy of the sampling time interval, and providing a stable and reliable time basis for subsequent high-precision synchronous acquisition and cross-node data alignment.

[0080] In one embodiment, the above step S50 comprises: S501, detecting the valid transition edge of the sampling drive clock through the sampling control circuit to generate a sampling trigger signal; S502, performing analog-to-digital conversion on the analog input signal under the control of the sampling trigger signal through the analog-to-digital conversion unit to generate raw sampling data; S503, latching the nanosecond-level fine time at the valid time of the sampling trigger signal through the time stamp latch to generate a raw time stamp; S504, storing the raw sampling data through the data buffer to generate buffered sampling data; S505, converting the raw time stamp into a standard format sampling time stamp, and binding the buffered sampling data with the standard format sampling time stamp to generate sampling data with a sampling time stamp; S506, verifying the correct association of the sampling data with a sampling time stamp, generating verified sampling data packets, and outputting the verified sampling data packets to the data transmission channel.

[0081] In the embodiment, the effective transition edge of the sampling drive clock refers to the level transition boundary selected as the trigger reference in the sampling drive clock waveform, which can be a rising edge from low to high or a falling edge from high to low, and is selected by a configuration register or a control instruction in the system initialization stage. The sampling control circuit receives the sampling drive clock signal, continuously judges the clock waveform through the edge detection unit, identifies the level change point by comparing the previous sampling value with the current sampling value, and immediately pulls up or flips a short pulse signal in the internal trigger logic when it matches the pre-set effective transition edge. The short pulse is the sampling trigger signal. The sampling trigger signal follows the effective transition edge of the sampling drive clock in time, and is distributed to the analog-to-digital conversion unit and the timestamp latch through the synchronous trigger path, so that both of them refer to the same trigger event at the same time.

[0082] After receiving the sampling trigger signal, the analog-to-digital conversion unit performs sample-and-hold and quantization conversion on the analog input signal during the effective period of the trigger signal. The front-end sample-and-hold circuit locks the instantaneous value of the analog input signal on the sampling capacitor when the trigger arrives, and then the internal comparator array or successive approximation structure divides the level interval according to the reference voltage to map the analog amplitude to the corresponding digital code, forming the original sampling data. The original sampling data can adopt a fixed word width format, such as 16 bits or 24 bits, and is output on the local bus according to the channel number and sampling order. In order to ensure the consistency between the sampling time and the timestamp, the trigger end of the analog-to-digital conversion unit and the sampling trigger signal generated by the sampling control circuit maintain a single source, avoiding additional gating or logic retiming.

[0083] The timestamp latch and the sampling control circuit maintain a time alignment relationship through the same sampling trigger signal. At the boundary of the effective period of the sampling trigger signal, the timestamp latch reads the current nanosecond-level fine time from the high-precision timing link, combines the second-level reference part and the nanosecond offset part output by the counter into a complete time value, and writes it into the latch register at one time. The latched data remains unchanged in the subsequent data packaging and output process, preventing time drift caused by subsequent counting. The value written into the latch register is the original timestamp, which can be stored in the second field and the nanosecond field, or in a unified fixed-width binary count value.

[0084] The data buffer is located between the output of the analog-to-digital conversion unit and the packing logic, and is used to receive raw sample data and form a sequential queue in the local storage medium. The data buffer can adopt a dual-port RAM, a ring buffer or a FIFO structure, and raw sample data is sequentially written in the write end according to the trigger sequence of the sample, and the buffered sample data is output in the read end in time sequence. The buffering mechanism absorbs the difference in data rate between the sampling side and the data transmission side, so that the sampling points will not be lost when the timestamp is bound and the integrity verification is performed, and the sampling sequence will not be disturbed due to the instantaneous blockage of the bus. The buffered sample data is internally attached with an address index or a sequence count value, which facilitates the establishment of a one-to-one correspondence with the corresponding timestamp record.

[0085] The original timestamp enters the format conversion path after the latch is completed, and in this process, the internal count representation is converted into a standard format sample timestamp. The standard format sample timestamp can adopt an encoding method consistent with the network time synchronization system, for example, the whole second field adopts unsigned integer representation, the number of seconds since the starting time is accumulated, and the nanosecond field adopts fixed-width integer representation of the nanosecond offset in the current second. It can also use a unified 64-bit or 96-bit extended time encoding to meet the large-scale time representation requirement in the long-time running scene. In the format conversion process, the system will perform carry normalization processing on the second field and the nanosecond field to avoid the overflow of the nanosecond field or the non-uniform encoding problem, and obtain a sample time reference that can be directly used for cross-node alignment and protocol interaction.

[0086] The sample data with sample timestamp is generated through the binding process. The binding logic reads the buffered sample data from the data buffer, and at the same time reads the standard format sample timestamp from the timestamp format conversion path, and combines a single sample value with the corresponding timestamp into a record according to the sequence index or internal label of the sample trigger event. The combination method can adopt a structured field arrangement, for example, a record contains channel identification, sample serial number, sample value and sample timestamp, or a binary frame structure, which places the timestamp field in the frame header and the sample data array in the frame body. After binding, the sample data with sample timestamp is obtained, which not only retains the original sample value, but also adds accurate time information.

[0087] The correlation verification process checks the sampling data with sampling time stamps to generate a sampling data packet. The verification logic can perform monotonicity judgment on the continuously recorded sampling time stamps to check whether the time is strictly increasing in the sampling order or meets the expected sampling interval range, or can check the mapping relationship between the channel identifier and the sampling time stamp to prevent time cross errors between different channels. It can also cross-compare the sampling trigger count, data buffer depth and local counter value to confirm that each trigger event produces corresponding sampling records and time stamp records. The verified data is reorganized into a sampling data packet, which can add a frame number, channel set identifier and brief verification field to the header to facilitate the data transmission channel to perform further link verification. The sampling data packet is output through the data transmission channel after passing the verification, and the data transmission channel can be an Ethernet interface, a high-speed serial interface or a backplane bus interface, which maintains the sampling data packet boundary during transmission to provide clear structure input for upper layer time alignment and cross-node analysis.

[0088] Example: In a distributed synchronous acquisition scene, the PC control machine, PoE&PTP switch and multiple data acquisition instruments form a physical interconnection structure through Ethernet. Each data acquisition instrument includes an RJ45 interface, a PHY chip supporting synchronous Ethernet and IEEE1588 protocol, a power supply unit, a SoC chip with embedded ARM and FPGA, and an ADC unit, which together constitute the time synchronization link, clock generation link and data acquisition link of the acquisition device. The embedded ARM has data transparent transmission, PTP service and timing trigger service functions, and the FPGA internally implements a synchronous timer module, a sampling clock generation module, a data acquisition module and a data processing module, which undertake the key logic in the subsequent synchronization and acquisition process.

[0089] After the system starts, the data acquisition instrument first receives the power over Ethernet signal through the RJ45 interface, that is, the power over Ethernet signal reaches the acquisition device through the network cable, and the power management unit converts the power signal into working voltage, so that the acquisition device enters the preparation state. Subsequently, the PC control machine initiates the network time protocol service to the PoE&PTP switch, and the switch obtains a rough time reference from the time synchronization request from the PC. The rough time is used as the initial time parameter for subsequent precise time protocol interaction. The processing unit in the data acquisition instrument, that is, the embedded ARM, establishes a two-way dialogue with the switch through the precise time protocol, and executes a complete time message interaction process including request and response messages. The switch acts as an intermediate node and forwards the network time protocol and precise time protocol related messages, so that the time message forms a round trip path between the PC, the switch and the acquisition device. The processing unit calculates the intermediate path delay according to the delay change between the message round trips. The processing unit extracts the timestamp information from the precise time protocol message, and corrects the frequency deviation and phase offset of the local clock in combination with the intermediate path delay, to obtain the corrected time data. Through multiple round trip time measurements, the processing unit further determines the network transmission delay compensation value, and applies the delay compensation value to the corrected time data, thereby generating the compensated time data. On the basis of the compensated time data, the processing unit executes the time synchronization algorithm in combination with the local clock state to obtain the initial network time, which is the starting reference for all subsequent time calculations of the system.

[0090] After the initial network time is obtained, the data acquisition instrument inside starts to drive the physical layer interface unit through the processing unit, that is, to drive the PHY chip to start the clock recovery function, to extract the frequency information used for synchronization from the Ethernet physical layer signal, and to recover and generate a synchronization clock signal Sync_clk. The timestamp engine inside the physical layer interface unit monitors the period count of the synchronization clock signal, and outputs a trigger pulse signal Trigger aligned with the second boundary when the position corresponding to the second boundary is detected, that is, a pulse is generated at the accurate time of second transition. After receiving the synchronization clock signal and the trigger pulse signal, the processing unit takes the initial network time as a reference, combines it with the two timing signals, and performs clock synchronization calculation to generate a second-level reference time through frequency calibration and phase adjustment, providing a stable second-level reference for subsequent nanosecond-level precise time calculation.

[0091] After obtaining the second-level reference time, the synchronization timer module in the FPGA starts running the counting process driven by the trigger pulse signal. The active transition of the trigger pulse signal, i.e., the active transition of the trigger, serves as a reset signal, causing the counter register to clear at the second boundary. The synchronization clock signal, i.e., the Sync_clk, serves as a driving source, triggering the counting accumulation operation at each rising edge, causing the count value to continuously increase, which is equivalent to the nanosecond-level time offset. When the count value recorded by the counter register is read, the count value is converted into a nanosecond-level time offset, and is arithmetically superimposed with the second-level reference time to generate an unverified nanosecond-level fine time. The synchronization timer module performs anomaly monitoring on the fine time, including counting transition integrity, synchronization clock continuity, and trigger boundary consistency. When the verification is passed, the nanosecond-level fine time is output as a time reference for subsequent sampling time stamp latching.

[0092] When the high-precision time link is stable, the processing unit receives the sampling rate configuration parameter from the central control device, and verifies the value range, resolution, and adaptability to the current synchronization clock signal frequency of the sampling rate parameter through the parameter verification module to obtain an effective sampling rate parameter. The frequency division ratio calculation unit performs integer division operation on the effective sampling rate parameter and the synchronization clock signal frequency to obtain a basic frequency division ratio, simultaneously calculates a decimal frequency division compensation value, and adds the two to generate a frequency division coefficient. The frequency division coefficient is written into the programmable frequency divider, causing the programmable frequency divider to work according to the frequency division coefficient and perform integer frequency division on the synchronization clock signal. The frequency- divided clock signal is adjusted for waveform symmetry and edge stability by the duty cycle optimization circuit, and the stable sampling drive clock is generated after stability detection. The sampling drive clock is distributed to each acquisition channel inside the data acquisition instrument, causing all channels to perform sampling based on a unified time reference.

[0093] After the sampling drive clock Samp_clk is stably output, the sampling control circuit generates a sampling trigger signal when detecting an effective edge at the active transition edge of Samp_clk, driving the analog-to-digital conversion unit to perform analog-to-digital conversion on the analog input signal to generate raw sampling data. The time stamp latch synchronously latches the nanosecond-level fine time at the active time of the sampling trigger signal to form a raw time stamp. The data buffer temporarily stores the sampling data, causing the data stream to automatically adapt to the subsequent binding process. The raw time stamp is converted into a standard format sampling time stamp, and is bound with the buffered sampling data to form a data structure with a time stamp. The system performs correlation verification to ensure that each sampling time stamp corresponds to the sampling data and the time link is continuous. The verified data is assembled into a sampling data packet and output to the data transmission channel.

[0094] Finally, the host computer software arranges the time series of multiple acquisition nodes according to the nanosecond-level fine time in the sampling data packet, realizes the synchronous acquisition between multiple nodes at the nanosecond level, and enables the distributed acquisition system to obtain the cross-node consistent time marking capability in the scenes of vibration monitoring, underwater sound detection, and ultra-high-speed industrial detection.

[0095] The embodiment generates a unified sampling trigger signal at the effective jump edge of the sampling driving clock, drives the analog-to-digital conversion unit to collect the analog input signal and drives the time stamp latch to read the nanosecond-level fine time under the same trigger event, and organizes the sampling data and the sampling time stamp into a structured sampling data packet through data buffering, standard format time stamp conversion, binding, and correlation verification. The sampling data packet can maintain the strict correspondence between the sampling time and the time reference under the conditions of high sampling rate and high data throughput, reduce the risk of mismatch between the sampling value and the time marking, improve the time alignment accuracy across channels and nodes, and provide a high-reliability time marking data basis for subsequent signal reconstruction, event positioning, and multi-node collaborative analysis in the distributed precise synchronous acquisition system.

[0096] In an embodiment, an Ethernet-based time synchronization acquisition device is provided, which corresponds to the Ethernet-based time synchronization acquisition method in the above embodiment. Referring to Figure 3 , Figure 3 A functional module schematic diagram of a preferred embodiment of the Ethernet-based time synchronization acquisition device of the present application is shown in FIG. 1. The functional modules include a time synchronization communication module 10, a physical layer clock recovery module 20, a high-precision timing module 30, a sampling clock generation module 40, and a data acquisition and time stamp module 50. The detailed descriptions of the functional modules are as follows: The time synchronization communication module 10 is configured to communicate with a central control device based on a network time protocol through a data acquisition instrument, and interact based on a precise time protocol to obtain an initial network time. The physical layer clock recovery module 20 is configured to drive a physical layer interface unit to recover a synchronization clock signal from an Ethernet physical layer signal through a processing unit in the data acquisition instrument, generate a trigger pulse signal aligned with a second boundary, and generate a second-level reference time based on the initial network time. The high-precision timing module 30 is configured to use the trigger pulse signal as a reset signal and use the synchronization clock signal as a counting driving source to perform high-frequency counting accumulation based on the second-level reference time, and generate a nanosecond-level fine time. The sampling clock generation module 40 is configured to receive a sampling rate configuration parameter, perform frequency division processing on the synchronization clock signal based on the sampling rate configuration parameter, and obtain a sampling driving clock. The data acquisition and timestamp module 50 is configured to perform sampling action by controlling the analog-digital conversion unit at the active jump edge of the sampling drive clock, and latch the nanosecond-level fine time generation sampling timestamp, and output the sampling data and the sampling timestamp.

[0097] The specific definitions of the Ethernet-based time synchronization acquisition device can refer to the aforementioned definitions of the Ethernet-based time synchronization acquisition method, which will not be described here. The various modules in the Ethernet-based time synchronization acquisition device described above can be realized by software, hardware, or a combination thereof. The various modules described above can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so that the processor can call and execute the operations corresponding to the various modules.

[0098] In one embodiment, a computer device is provided, which can be a server, and its internal structure diagram can be as shown in Figure 4 The computer device includes a processor, a memory, a network interface, and a database connected through a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile and / or volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The network interface of the computer device is configured to communicate with an external client through a network connection. The computer program is executed by the processor to implement the functions or steps of the server side of the Ethernet-based time synchronization acquisition method.

[0099] In one embodiment, a computer device is provided, which can be a client, and its internal structure diagram can be as shown in Figure 5 The computer device includes a processor, a memory, a network interface, a display screen, and an input device connected through a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The network interface of the computer device is configured to communicate with an external server through a network connection. The computer program is executed by the processor to implement the functions or steps of the client side of the Ethernet-based time synchronization acquisition method.

[0100] In one embodiment, an Ethernet-based time synchronization acquisition device is provided, which is deployed in a distributed precise synchronization acquisition system, and a structure diagram of the distributed precise synchronization acquisition system can be as shown inFigure 6 The schematic diagram of the distributed precise synchronization acquisition system structure of the Ethernet-based time synchronization acquisition device in an embodiment is shown. Referring to Figure 6 , Figure 6 The schematic diagram of the distributed precise synchronization acquisition system structure of the Ethernet-based time synchronization acquisition device in an embodiment is shown. The system connects the PC central controller, the PoE & PTP switch and multiple data acquisition instruments in the same network through Ethernet. The PC central controller is responsible for running the time service and the upper computer acquisition software, provides a unified time reference for the PoE & PTP switch, and centrally manages the acquisition results. The PoE & PTP switch provides working voltage for each data acquisition instrument through the power over Ethernet function, and provides time and frequency signals supporting IEEE1588 and synchronous Ethernet, forming a unified time reference and frequency reference on the network side. Multiple data acquisition instruments are distributed in different physical locations, access the PoE & PTP switch through network cables, perform synchronous sampling under the unified time reference, and return the acquisition data with sampling time stamps to the PC central controller through the network for subsequent display, storage and analysis.

[0101] In an embodiment, an Ethernet-based time synchronization acquisition device is provided, which can adopt the form of a data acquisition instrument, and the internal module structure schematic diagram can be as shown in Figure 7 Referring to Figure 7 , Figure 7The schematic diagram of the internal module of the data acquisition instrument in an embodiment of the Ethernet-based time synchronization acquisition device is shown. The data acquisition instrument includes an RJ45 interface for realizing the physical connection of Ethernet and data transceiving, a PHY chip integrating the functions of PoE, SyncE and PTP, a power supply unit for converting the power supply signal of Ethernet into multiple stable DC voltages, a SoC chip integrating an embedded ARM processing unit and an FPGA logic unit, and an ADC unit for acquiring analog signals. The RJ45 interface is connected with the PHY chip, introduces the differential signal from the external network side into the internal physical layer circuit through the Ethernet data link, and provides the necessary interface resources for the PHY chip; the PHY chip recovers the clock information from the network data stream, outputs the synchronous clock signal Sync_clk and the trigger pulse signal Trigger, and performs data interaction with the embedded ARM in the SoC chip through the MAC interface, and at the same time, delivers the power supply power to the power supply unit through the PoE port. The power supply unit obtains the input energy from the PoE power supply channel, and after the isolation, rectification and voltage stabilization links, provides the matching working voltage for the PHY chip, the SoC chip and the ADC unit respectively. The embedded ARM runs the time synchronization program, configures the PHY register and the FPGA register, and performs parameter issuing and working state management on the synchronization timer module, the sampling clock generation module and the data acquisition module in the FPGA, generates the time quantity corresponding to the second-level reference time in the time synchronization process, which is marked as Time1 in the figure. The FPGA side generates the nanosecond-level fine time according to the synchronous clock signal Sync_clk and the trigger pulse signal Trigger, which is marked as Time2 in the figure, and generates the sampling clock Samp_clk through the sampling clock generation module, drives the ADC unit to perform analog-digital conversion using Samp_clk, and outputs the digital sampling result through the ADC data channel. The data processing logic forms the acquisition time quantity with time stamp after completing the sampling time stamp binding, which is marked as Time3 in the figure, and then sends the acquisition data carrying Time3 to the embedded ARM for packaging and uploading.

[0102] In an embodiment, an Ethernet-based time synchronization acquisition method is provided for realizing nanosecond-level fine time generation. The timing schematic diagram of the nanosecond-level fine time generation can be as follows: Figure 8The figure shows. Time1 represents the second-level reference time axis, forming time intervals T11 and T12 between the rising edges of two adjacent Trigger pulses, where T11 corresponds to the duration of the first second, and T12 corresponds to the duration of the second second. Trigger is a trigger pulse signal that aligns the second boundary, and each rising edge marks the start of a new second. Sync_clk is a stable period output between two adjacent Triggers, represented by a square wave sequence. Time2 represents the nanosecond-level fine time axis, which is further divided into a plurality of finer time slices within each time interval of Time1. In the figure, T21, T22, T23…T2n represent this group of time slices, reflecting the continuous time points discretely divided according to the Sync_clk period within the same second. The synchronization timer module clears the internal counter register when the Trigger rising edge arrives, and stores the current second-level reference time Time1 as the start time of the second in the register unit. Then, at each Sync_clk rising edge, the counter is incremented, and the nanosecond-level time offset is calculated according to the proportional relationship between the count value and the Sync_clk period, and is superimposed on the corresponding T11 or T12 interval, thereby forming a series of nanosecond-level fine time outputs T21, T22, T23, and T2n on the Time2 axis, providing continuous and high-precision time reference for the generation of subsequent sampling timestamps.

Claims

1. An Ethernet-based time synchronization acquisition method, characterized in that, The method comprises the following steps: The data acquisition instrument communicates with the central control device based on the network time protocol and interacts based on the precise time protocol to obtain an initial network time; A processing unit in the data acquisition instrument drives a physical layer interface unit to recover a synchronization clock signal from an Ethernet physical layer signal and generates a trigger pulse signal aligned with a second boundary, and generates a second-level reference time based on the initial network time; The trigger pulse signal is used as a reset signal, and the synchronization clock signal is used as a counting driving source to perform high-frequency counting accumulation based on the second-level reference time to generate a nanosecond-level fine time; A sampling rate configuration parameter is received, and the synchronization clock signal is frequency-division processed based on the sampling rate configuration parameter to obtain a sampling driving clock; At an effective jump edge of the sampling driving clock, an analog-to-digital conversion unit is controlled to perform a sampling action, and the nanosecond-level fine time is latched to generate a sampling time stamp, and sampling data and the sampling time stamp are combined and output.

2. The Ethernet-based time synchronization collection method of claim 1, wherein, The data acquisition instrument communicates with the central control device based on the network time protocol and interacts based on the precise time protocol to obtain an initial network time, comprising: An Ethernet interface in the data acquisition instrument receives an Ethernet power supply signal, and a power management unit converts the Ethernet power supply signal to generate a working voltage, and the working voltage is used to make the data acquisition instrument enter a preparation working state; The central control device initiates a network time protocol service and sends a time synchronization request to a network switch, and a rough time reference is obtained by processing the time synchronization request through the network switch; A processing unit in the data acquisition instrument establishes a two-way dialogue with the network switch based on the precise time protocol, and uses the rough time reference to exchange request and response of time messages; The network switch acts as an intermediate node to forward related messages of the network time protocol and the precise time protocol, and calculates an intermediate path delay based on the request and response exchange of the time messages; The processing unit parses the precise time protocol message to extract timestamp information, and uses the timestamp information and the intermediate path delay to correct the frequency deviation and phase offset of the local clock to generate corrected time data; A network transmission delay compensation value is determined through multiple round-trip time measurements, and the delay compensation value is applied to the corrected time data to generate compensated time data; The processing unit generates an initial network time by executing a time synchronization algorithm based on the compensated time data and the state of the local clock.

3. The Ethernet-based time synchronization collection method of claim 1, wherein, The processing unit in the data acquisition instrument drives the physical layer interface unit to recover the synchronization clock signal from the Ethernet physical layer signal, and generates the trigger pulse signal aligned with the second boundary, and generates the second-level reference time based on the initial network time, comprising: The processing unit in the data acquisition instrument sends a configuration instruction to the physical layer interface unit to start the clock recovery function; The physical layer interface unit extracts clock information from the Ethernet physical layer signal and generates the synchronization clock signal based on the clock information; The period count of the synchronization clock signal is monitored by a timestamp engine in the physical layer interface unit, and a trigger pulse signal aligned with the second boundary is generated at the corresponding moment of the second boundary; The synchronization clock signal and the trigger pulse signal are received by the processing unit; The processing unit performs clock synchronization calculation based on the initial network time, the synchronization clock signal and the trigger pulse signal to generate synchronization time data; The processing unit applies frequency calibration and phase adjustment algorithms to process the synchronization time data to generate a second-level reference time.

4. The Ethernet-based time synchronization collection method of claim 1, wherein, Using the trigger pulse signal as a reset signal and the synchronization clock signal as a counting driving source, high-frequency counting accumulation is performed based on the second-level reference time to generate nanosecond-level fine time, including: The rising edge of the trigger pulse signal is detected by a synchronization timer module, and a counter register is initialized; The counter register uses the synchronization clock signal as a driving source to perform counting accumulation operation at each rising edge of the synchronization clock signal to generate a count value; The current count value of the counter register is read, and the count value is converted into a nanosecond-level time offset; The second-level reference time and the nanosecond-level time offset are arithmetically added to generate an unverified nanosecond-level fine time; Abnormal conditions in the counting accumulation operation process are monitored, and the unverified nanosecond-level fine time is checked for validity to generate a verified nanosecond-level fine time.

5. The Ethernet-based time synchronization collection method of claim 1, wherein, Receive a sampling rate configuration parameter, and perform frequency division processing on the synchronization clock signal based on the sampling rate configuration parameter to obtain a sampling driving clock, including: Receive a sampling rate configuration parameter from a central control device through a configuration interface; Calculate a frequency division coefficient according to the sampling rate configuration parameter and the frequency of the synchronization clock signal; Configure the working parameters of a programmable frequency divider using the frequency division coefficient; Perform integer frequency division processing on the synchronization clock signal through the programmable frequency divider to generate a frequency-divided clock signal; Optimize the duty cycle of the frequency-divided clock signal to generate an optimized clock signal; Real-time monitor the stability of the optimized clock signal to generate a verified sampling driving clock; Distribute the verified sampling driving clock to each data acquisition channel.

6. The Ethernet-based time synchronization collection method of claim 5, wherein, Calculate a frequency division coefficient according to the sampling rate configuration parameter and the frequency of the synchronization clock signal, including: Check the rationality and validity of the sampling rate configuration parameter through a parameter verification module to generate a valid sampling rate parameter; Perform integer division operation according to the valid sampling rate parameter and the frequency of the synchronization clock signal through a frequency division ratio calculation unit to generate a basic frequency division ratio; Calculate a decimal frequency division compensation value based on the basic frequency division ratio; Add the basic frequency division ratio and the decimal frequency division compensation value through addition operation using the basic frequency division ratio and the decimal frequency division compensation value to generate a frequency division coefficient.

7. The Ethernet-based time synchronization collection method of claim 1, wherein, At the effective jump edge of the sampling driving clock, control an analog-to-digital conversion unit to perform sampling action and latch the nanosecond-level fine time to generate a sampling timestamp, and combine and output the sampling data and the sampling timestamp, including: The sampling control circuit detects the effective jump edge of the sampling driving clock to generate a sampling trigger signal; The analog-to-digital conversion unit performs analog-to-digital conversion on the analog input signal under the control of the sampling trigger signal to generate original sampling data; The timestamp latch latches the nanosecond-level fine time at the effective moment of the sampling trigger signal to generate an original timestamp; The data buffer stores the original sampling data to generate buffered sampling data; The original timestamp is converted into a standard format sampling timestamp, and the buffered sampling data is bound with the standard format sampling timestamp to generate sampling data with a sampling timestamp; The correct association of the sampling data with the sampling timestamp is verified to generate verified sampling data packets, which are output to a data transmission channel.

8. An Ethernet-based time synchronization collection device, comprising: The Ethernet-based time synchronization acquisition device comprises: A time synchronization communication module is configured to communicate with a central control device based on a network time protocol and interact based on a precise time protocol to obtain an initial network time through a data acquisition instrument. A physical layer clock recovery module is configured to recover a synchronization clock signal from an Ethernet physical layer signal through a physical layer interface unit driven by a processing unit in the data acquisition instrument, and generate a trigger pulse signal aligned with a second boundary to generate a second-level reference time based on the initial network time. A high-precision timing module is configured to use the trigger pulse signal as a reset signal and use the synchronization clock signal as a counting driving source to perform high-frequency counting accumulation based on the second-level reference time to generate a nanosecond-level fine time. A sampling clock generation module is configured to receive a sampling rate configuration parameter, perform frequency division processing on the synchronization clock signal based on the sampling rate configuration parameter, and obtain a sampling driving clock. A data acquisition and timestamp module is configured to perform sampling action through a control analog-to-digital conversion unit at an effective jump edge of the sampling driving clock, latch the nanosecond-level fine time to generate a sampling timestamp, and combine and output sampling data and the sampling timestamp.

9. A computer device, comprising: The computer device comprises a memory, a processor, and an Ethernet-based time synchronization acquisition program stored on the memory and executable on the processor, and the Ethernet-based time synchronization acquisition program, when executed by the processor, implements the steps of the Ethernet-based time synchronization acquisition method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The storage medium stores an Ethernet-based time synchronization acquisition program, and the Ethernet-based time synchronization acquisition program, when executed by the processor, implements the steps of the Ethernet-based time synchronization acquisition method according to any one of claims 1-7.

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