Method for improving super junction power device IGSS failure

Abstract

The invention provides a method for improving a super junction power device IGSS failure, and relates to the technical field of power device super junction yield improvement. Comprising the following steps: determining that a failure parameter of a failure area is IGSS according to a wafer test or a wafer receiving test result; determining a plurality of failure reasons for the IGSS; according to the first failure reason, determining a plurality of corresponding formulated schemes, and executing the plurality of formulated schemes to determine a plurality of corresponding execution results; according to the silicon nails in the unit area, determining that the failure morphology has relevance with black silicon distribution generated by a preset etching process; obtaining an optimal etching process formula when correlation exists, and optimizing the bottom of the failed morphology according to the optimal etching process formula; by adjusting the gas ratio, the smooth and silicon-nail-free optimal morphology is obtained within the angle morphology within the preset range, and the EAS capability limit window of the optimal morphology is determined. In this way, IGSS 1V failure is improved, and the yield of mass production is greatly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of improving the yield of power devices with super junction (SJ), and in particular to a method for improving the failure of gate-source leakage current (IGSS) of a super junction power device. BACKGROUND

[0002] A super junction metal-oxide-semiconductor field-effect transistor (SJ MOS) with multiple epitaxial implantation processes must undergo multiple epitaxial layer growth and P-type ion implantation to form a matching p-type structure. The number of growth times is directly proportional to the cost. Although the multiple epitaxial implantation process is costly, it can control different implantation energies, implantation doses, critical dimensions (CD), and other parameters after each epitaxial growth, and form different p-type region distributions at different depths according to requirements. The SJ MOS mass production requires precise control of the charge balance of n-type and p-type, and how to accurately control the charge balance is of great significance to the mass production of SJ MOS, which significantly affects the breakdown voltage drain-source (BVDSS).

[0003] Currently, in the case of SJ MOS multi-layer epitaxial mass production, the circuit probing (CP) electrical parameters of the SJ MOS device wafer are strictly controlled, and the energy avalanche stress (EAS) is particularly prominent. Therefore, the CT si loss method is used to improve the EAS capability, but the problem that follows is that the contact etching etch over etch (CT etch OE) capability is not matched, resulting in a large area of IGSS 1V failure at the edge, which can affect up to 50% of the yield. This is obviously unacceptable for wafer mass production requirements, resulting in a low yield in mass production. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a method for improving the IGSS failure of a super junction power device, which solves the problem of insufficient EAS limit capability of the super junction product in wafer testing, resulting in IGSS 1V failure at the edge, and a low yield in mass production.

[0005] To solve the above technical problems, the embodiments of the present application provide the following technical solutions: The application provides a method for improving IGSS failure of a super-junction power device, comprising the following steps: According to wafer test or wafer acceptance test results, confirming that the failure parameter of the failure region is IGSS; A plurality of failure causes of IGSS are determined, and the plurality of failure causes include a first failure cause and a second failure cause; According to the first failure cause, a plurality of formulated solutions corresponding to the first failure cause are determined, and the plurality of formulated solutions are executed to determine a plurality of execution results corresponding to the plurality of formulated solutions, the plurality of formulated solutions are different solutions for improving IGSS failure, and the plurality of execution results include a failure morphology; According to the silicon spike of the unit region, it is determined that the failure morphology has relevance with a black silicon distribution generated by a preset etching process; When the relevance exists, an optimal etching process recipe is obtained, and a bottom of the failure morphology is optimized according to the optimal etching process recipe, so as to improve IGSS failure caused by the first failure cause; By adjusting the gas ratio, an optimal morphology that is smooth and free of silicon spikes is obtained within a preset range of angle morphology, and an EAS capability limit window of the optimal morphology is determined, so as to improve IGSS failure caused by the second failure cause.

[0006] In some embodiments, the first failure cause includes that the photoresist thickness does not meet a target thickness, and the second failure cause includes a contact hole deepening reason.

[0007] In some embodiments, the plurality of formulated solutions include a first formulated solution and a second formulated solution, and the plurality of execution results further include a target execution result, according to the first failure cause, a plurality of formulated solutions corresponding to the first failure cause are determined, and the plurality of formulated solutions are executed to determine a plurality of execution results corresponding to the plurality of formulated solutions, including: When the photoresist thickness does not meet the target thickness, it is determined that the corresponding first formulated solution is a solution for increasing the photoresist thickness, or it is determined that the corresponding second formulated solution is a solution for removing an aluminum layer on the surface of the failure region; The photoresist thickness is increased to the target thickness to obtain the target execution result, or the aluminum layer on the surface of the failure region is removed to obtain the failure morphology, and the target execution result is a result of improving IGSS failure.

[0008] In some embodiments, the target thickness is 2.4 μm.

[0009] In some embodiments, before the step of, when the relevance exists, obtaining an optimal etching process recipe and optimizing the bottom of the failure morphology according to the optimal etching process recipe to improve IGSS failure caused by the first failure cause, the method further comprises: When the relevance exists, the ratio of etching gas is adjusted to obtain a plurality of etching process recipes; In the plurality of etching process recipes, an optimal etching process recipe is determined.

[0010] In some embodiments, the etching gas is a mixed gas containing HBr, SF6, Cl2, and O2.

[0011] In some embodiments, before the IGSS failure caused by the second failure cause is improved, the method further comprises: Under the condition that the bias power or transformer coupled plasma power remains constant, the chamber pressure is adjusted to 10-60 mTorr, the flow rate of HBr is adjusted to 100-500 sccm, the flow rate of SF6 is adjusted to 20-200 sccm, the flow rate of Cl2 is adjusted to 0-160 sccm, and the flow rate of O2 is adjusted to 0-200 sccm.

[0012] In some embodiments, before the IGSS failure caused by the second failure cause is improved, the method further comprises: An optimal profile is obtained in a preset range of angle profiles by adjusting the proportion of HBr, SF6, Cl2, and O2; The depth of the optimal profile is process window biased, and the EAS capability limit window of the optimal profile is determined, and the EAS capability limit window of the optimal profile meets the production condition and the target production yield requirement.

[0013] In some embodiments, the preset range of angles is 95°-110°.

[0014] Compared with the prior art, the method for improving IGSS failure of the super junction power device provided by the application determines that the failure parameter of the failure area is IGSS according to wafer test or wafer acceptance test results; determines a plurality of failure causes of IGSS, the plurality of failure causes including a first failure cause and a second failure cause; determines a plurality of corresponding formulated solutions according to the first failure cause, and executes the plurality of formulated solutions to determine a plurality of corresponding execution results, the plurality of formulated solutions being different solutions for improving IGSS failure, and the plurality of execution results including failure morphology; determines that the failure morphology has relevance with black silicon distribution generated by a preset etching process according to silicon nails of a unit area; obtains an optimal etching process recipe when the relevance exists, and optimizes the bottom of the failure morphology according to the optimal etching process recipe to improve IGSS failure caused by the first failure cause; obtains a smooth and silicon-nail-free optimal morphology within a preset range of angle morphology by adjusting gas ratio, and determines an EAS capability limit window of the optimal morphology to improve IGSS failure caused by the second failure cause. In this way, different formulated solutions can be determined corresponding to different failure causes, the optimal etching process recipe is obtained, the bottom of the failure morphology is optimized according to the optimal etching process recipe to improve IGSS failure caused by the first failure cause, the smooth and silicon-nail-free optimal morphology within the preset range of angle morphology is obtained by adjusting the gas ratio, and the EAS capability limit window of the optimal morphology is determined to improve IGSS failure caused by the second failure cause, so that IGSS 1V failure is improved and the yield of mass production is greatly improved. BRIEF DESCRIPTION OF DRAWINGS

[0015] The above and other objects, features and advantages of the exemplary embodiments of the present application will be more apparent from the following detailed description read in conjunction with the accompanying drawings, in which several embodiments of the present application are shown by way of example, and wherein the same reference numerals refer to the same or similar components throughout the several views, in which: Figure 1 A flowchart of the method for improving IGSS failure of the super junction power device is schematically shown; Figure 2 A schematic diagram of IGSS 1V failure principle of the SJ MOS is schematically shown; Figure 3 A schematic diagram of the CT black silicon is schematically shown; Figure 4 A schematic diagram of the optimal morphology of the CT silicon loss is schematically shown. DETAILED DESCRIPTION

[0016] Exemplary embodiments of the present application will be described herein below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it is understood that the present application can be embodied in many forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

[0017] It should be noted that unless otherwise stated, technical or scientific terms used in the present application shall have their ordinary meaning as understood by a person skilled in the art to which the present application pertains.

[0018] The method in the embodiments of the present application will be described in detail below.

[0019] Figure 1 A flowchart of the method for improving IGSS failure of a super-junction power device in the embodiments of the present application is schematically shown in FIG. 1. Figure 1 As shown in FIG. 1, the method for improving IGSS failure of a super-junction power device can include the following steps. S101, confirming that the failure parameter of the failure region is IGSS according to wafer test or wafer acceptance test results.

[0020] Specifically, the specific position where the process procedure of IGSS failure occurs is first investigated. According to wafer test or wafer acceptance test (CP / WAT) results, it can be determined that the batches with edge failure of IGSS have been subjected to CT deepening, the batches without IGSS failure are Insulated Gate Bipolar Transistor (IGBT), and the SJ MOS of the other two batches has no CT deepening. It can be determined that the IGSS failure of SJ MOS is strongly related to CT deepening; then the CT etching process can be analyzed.

[0021] S102, determining multiple failure causes of IGSS.

[0022] The multiple failure causes include a first failure cause and a second failure cause. The first failure cause includes that the thickness of photoresist does not conform to the target thickness, and the second failure cause includes a contact hole deepening cause.

[0023] Specifically, a plurality of suspected failure causes are determined respectively: a suspected first failure cause is that: photoresist thickness is insufficient, the photoresist thickness does not conform to a target thickness, an in-plane photoresist (PR) distribution center is thick and an edge is thin, resulting in too much loss of CT photoresist when CT deepening is performed, an edge dielectric layer is damaged, resulting in IGSS failure. A suspected second failure cause is that: CT deepening results in that a contact hole corner plasma damage is relatively serious, resulting in metal along the corner has a drilling effect.

[0024] Figure 2 A schematic diagram of an IGSS 1V failure principle of an SJ MOS is schematically shown, referring to Figure 2 , Figure 2 is a typical wafer test distribution map (Chip Probing Mapping and Positioning, CP MAP) when black silicon occurs. Four process reasons causing IGSS failure are given: gate oxide (involving oxidation and etching process), polysilicon (involving etching morphology and residue), dielectric layer (involving film quality and hole etching anomaly), and metal layer (involving metal residue and barrier layer metal anomaly). Figure 2 Taking a vertical double-diffused metal-oxide-semiconductor (VDMOS) device as an example, the structure of the VDMOS device refers to the structure of the prior art, and it is mainly suspected that the metal layer anomaly causes IGSS short circuit.

[0025] S103, according to the first failure cause, a plurality of formulated schemes corresponding to the first failure cause are determined, and the plurality of formulated schemes are executed to determine a plurality of execution results corresponding to the plurality of formulated schemes.

[0026] Among them, the plurality of formulated schemes are different schemes for improving IGSS failure, and the plurality of execution results include failure topography. The plurality of formulated schemes include a first formulated scheme and a second formulated scheme, and the plurality of execution results further include a target execution result. The target thickness is 2.4 μm.

[0027] Specifically, according to the first failure cause, a plurality of formulated schemes corresponding to the first failure cause are determined, and the plurality of formulated schemes are executed to determine a plurality of execution results corresponding to the plurality of formulated schemes, including: Step A1: when the photoresist thickness does not conform to the target thickness, the corresponding first formulated scheme is determined to be a scheme of increasing the photoresist thickness, or the corresponding second formulated scheme is determined to be a scheme of removing the aluminum layer on the surface of the failure area.

[0028] Step A2: increase the thickness of the photoresist to the target thickness to obtain a target execution result, or remove the aluminum layer on the surface of the failed area to obtain a failed topography.

[0029] The target execution result is the result of improving IGSS failure.

[0030] Specifically, the thickness of the photoresist is increased to 2.4 μm to obtain a target execution result to ensure that the photoresist failure does not affect the quality of the inter layer dielectric (ILD) layer when the CT is deepened. Or, remove the aluminum layer on the surface of the failed area to obtain a failed topography.

[0031] For the target execution result obtained by increasing the thickness of the photoresist to 2.4 μm, the IGSS failure improvement of the thickened CT photoresist thickness is obvious, and the average IGSS failure is reduced by about 12.5%, and only a few wafers still have edge IGSS failure.

[0032] S104, according to the silicon nail of the unit area, determine that the failed topography has relevance with the black silicon distribution generated by the preset etching process.

[0033] Specifically, Figure 3 The schematic diagram of CT black silicon is schematically shown, see Figure 3 As shown, it is found that the SJ MOS edge failure is related to the black silicon distribution generated after the CT silicon loss of 5000A when analyzing the failed topography. Since there are silicon nails in the wafer center cutting path, the edge cutting path and the cell area, mainly the cell area, it can be determined that it is related to the etching process formula.

[0034] S105, when the relevance is obtained, the optimal etching process formula is obtained, and the bottom of the failed topography is optimized according to the optimal etching process formula to improve the IGSS failure caused by the first failure reason.

[0035] Specifically, when the relevance is obtained, the optimal etching process formula is obtained, and the bottom of the failed topography is optimized according to the optimal etching process formula to improve the IGSS failure caused by the first failure reason, the method further comprises: Step B1: when the relevance is obtained, adjust the ratio of etching gas to obtain a plurality of etching process formulas.

[0036] The etching gas is a mixed gas containing HBr, SF6, Cl2 and O2.

[0037] In the case of the association, that is, the silicon spike of the cell region etching the lower surface of the contact hole, a plurality of etching process recipes can be obtained by adjusting the ratio of the etching gas (HBr / SF6 / Cl2 / O2), which can be 10 etching process recipes. The number of etching process recipes can be various, and the number of etching process recipes is not specifically limited here.

[0038] Step B2: Among the plurality of etching process recipes, the optimal etching process recipe is determined.

[0039] Among the plurality of etching process recipes, the optimal etching process recipe is determined, and the specific operation of adjusting the depth to the position required for mass production can be referred to the prior art.

[0040] S106, by adjusting the gas ratio, the optimal morphology with smooth and no silicon spike is obtained within the preset range of angle morphology, and the EAS capability limit window of the optimal morphology is determined to improve the IGSS failure caused by the second failure reason.

[0041] Specifically, before the optimal morphology with smooth and no silicon spike is obtained within the preset range of angle morphology by adjusting the gas ratio, and the EAS capability limit window of the optimal morphology is determined to improve the IGSS failure caused by the second failure reason, the method further comprises: Under the condition that the bias power or transformer coupled plasma power (Bias Power / TCP Power) remains constant, the chamber pressure is adjusted to 10-60 mTorr, the flow rate of HBr is 100-500 sccm, the flow rate of SF6 is 20-200 sccm, the flow rate of Cl2 is 0-160 sccm, and the flow rate of O2 is 0-200 sccm.

[0042] Specifically, by adjusting the gas ratio, the optimal morphology with smooth and no silicon spike is obtained within the preset range of angle morphology, and the EAS capability limit window of the optimal morphology is determined to improve the IGSS failure caused by the second failure reason, comprising: Step C1: By adjusting the ratio of HBr, SF6, Cl2 and O2, the optimal morphology is obtained within the preset range of angle morphology.

[0043] Among them, the preset range of angle is 95°-110°.

[0044] While maintaining a constant bias power or transformer-coupled plasma power (Bias Power / TCP Power), adjust the ratios of HBr, SF6, Cl2, and O2 within the ranges of 10-60 mTorr chamber pressure, 100-500 sccm HBr flow rate, 20-200 sccm SF6 flow rate, 0-160 sccm Cl2 flow rate, and 0-200 sccm O2 flow rate. There can be 10 possible ratios of HBr, SF6, Cl2, and O2, and the number of possible ratios is not specifically limited here. Adjusting to these 10 ratios will yield 10 different angular morphologies.

[0045] For example, Table 1 shows the ratio of two gases, including Design of Experiments (DOE) 1 and DOE 2, bias power, TCP power, pressure, HBr flow rate, SF6 flow rate, Cl2 flow rate, O2 flow rate, and the presence and morphology of silica nails under microscopic examination.

[0046] Table 1. Combination ratio of two gases

[0047] Microscopic examination of the surface morphology at angles of 95°-110° reveals whether it is smooth and free of silica spikes, thus selecting the optimal morphology. The optimal morphology is one with a smooth surface and no silica spikes. The depth of each point in the morphology is measured to determine if it is consistent; inconsistency indicates irregularity, meaning the surface is not smooth, while consistency indicates a smooth surface. Figure 4 A schematic diagram illustrating the optimal morphology of CT silicon loss is shown below. Figure 4 As shown, Figure 4 The optimal morphology is one with a smooth surface and no silicon spikes. This ensures silicon failure without the presence of black silicon at the bottom, which could lead to IGSS failure.

[0048] Step C2: Adjust the process window for the depth of the optimal morphology to determine the EAS capability limit window of the optimal morphology.

[0049] Among them, the EAS capability limit window with the optimal morphology satisfies the mass production conditions and the target mass production yield requirements.

[0050] Specifically, the depth of the optimal morphology is adjusted by adjusting the process window to determine the EAS capability limit window of the optimal morphology, and the EAS capability limit window is checked to ensure that it meets the mass production conditions and target mass production yield requirements.

[0051] The application deepens the silicon loss in the SJ product CT etching process, the super junction structure in the super junction power device realizes charge balance through the alternating P / N column, improves the breakdown voltage (Breakdown Voltage, BV) of the device and reduces the on-resistance; the depth of the contact hole directly affects the carrier injection efficiency and the contact resistance, and at the same time, the difficulty of the technology lies in that the edge one circle IGSS 1V failure will be caused in the CT etching, which is caused by the existence of a large area of black silicon on the surface of the contact hole, and the etching process is improved to achieve the problem of no IGSS failure. Through the three-in-one strategy of precise control of etching depth + junction area protection design + efficient annealing repair, the silicon loss to yield can be minimized while deepening the contact hole and improving the performance. The process window needs to be controlled in the depth deviation <5%, and supplemented by reliability screening, the yield is expected to be improved by 8~12%. In actual execution, the process parameters need to be dynamically adjusted combined with online monitoring data to ensure that the integrity of the super junction structure in the super junction power device is always within the safety boundary.

[0052] The application can change the current path by deepening the silicon loss of the contact hole, thereby greatly optimizing the EAS limit capability of the product semiconductor device, improving the edge one circle product yield, reducing the yield loss caused by the contact hole black silicon, better realizing the stability of mass production process, reducing the fluctuation of wafer test electrical parameters, and reducing the economic loss caused by electrical parameter failure.

[0053] The method for improving IGSS failure of the super junction power device includes confirming that the failure parameter of the failure region is IGSS according to wafer test or wafer acceptance test result; determining a plurality of failure causes of IGSS, the plurality of failure causes including a first failure cause and a second failure cause; determining a plurality of formulated schemes corresponding to the first failure cause according to the first failure cause, and executing the plurality of formulated schemes to determine a plurality of execution results corresponding to the plurality of formulated schemes, the plurality of formulated schemes being different schemes for improving IGSS failure, and the plurality of execution results including failure morphology; determining that the failure morphology has relevance with black silicon distribution generated by a preset etching process according to silicon nails of a unit region; obtaining an optimal etching process recipe when the relevance exists, and optimizing a bottom of the failure morphology according to the optimal etching process recipe to improve IGSS failure caused by the first failure cause; obtaining a smooth and silicon-nail-free optimal morphology within a preset range of angle morphology by adjusting gas ratio, and determining an EAS capability limit window of the optimal morphology to improve IGSS failure caused by the second failure cause. In this way, different formulated schemes corresponding to different failure causes can be determined, the optimal etching process recipe is obtained, the bottom of the failure morphology is optimized according to the optimal etching process recipe to improve IGSS failure caused by the first failure cause, the smooth and silicon-nail-free optimal morphology within the preset range of angle morphology is obtained by adjusting the gas ratio, and the EAS capability limit window of the optimal morphology is determined to improve IGSS failure caused by the second failure cause, so that IGSS 1V failure is improved, and yield in mass production is greatly improved.

[0054] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method of improving the failure of an Insulated Gate Super Junction Semiconductor (IGSS) power device, comprising: The method comprises the following steps: According to the wafer test or wafer acceptance test result, it is confirmed that the failure parameter of the failure region is IGSS; A plurality of failure causes of the IGSS are determined, and the plurality of failure causes include a first failure cause and a second failure cause; According to the first failure cause, a plurality of corresponding formulated solutions are determined, and the plurality of formulated solutions are executed to determine a plurality of corresponding execution results, the plurality of formulated solutions are different solutions for improving IGSS failure, and the plurality of execution results include a failure morphology; According to the silicon nail of the unit region, it is determined that the failure morphology has relevance with a black silicon distribution generated by a preset etching process; When the relevance exists, an optimal etching process recipe is obtained, and a bottom of the failure morphology is optimized according to the optimal etching process recipe, so as to improve the IGSS failure caused by the first failure cause; By adjusting the gas ratio, an optimal morphology that is smooth and free of silicon nails is obtained within a preset range of angle morphology, and an EAS capability limit window of the optimal morphology is determined, so as to improve the IGSS failure caused by the second failure cause.

2. The method of claim 1, wherein the super junction power device is an IGSS device. The first failure cause includes that the photoresist thickness does not meet a target thickness, and the second failure cause includes a contact hole deepening reason.

3. The method of claim 2, wherein the super junction power device is an IGSS device. The plurality of formulated solutions include a first formulated solution and a second formulated solution, the plurality of execution results further include a target execution result, and the step of determining, according to the first failure cause, a plurality of corresponding formulated solutions and executing the plurality of formulated solutions to determine a plurality of corresponding execution results comprises the following steps: When the photoresist thickness does not meet the target thickness, it is determined that the corresponding first formulated solution is a solution of increasing the photoresist thickness, or it is determined that the corresponding second formulated solution is a solution of removing an aluminum layer on the surface of the failure region; The photoresist thickness is increased to the target thickness to obtain the target execution result, or the aluminum layer on the surface of the failure region is removed to obtain the failure morphology, and the target execution result is a result of improving IGSS failure.

4. The method of claim 3, wherein the super junction power device is an IGSS device. The target thickness is 2.4 μm.

5. The method of claim 1, wherein the super junction power device is an IGSS device. Before the step of obtaining, when the relevance exists, an optimal etching process recipe, and optimizing the bottom of the failure morphology according to the optimal etching process recipe, so as to improve the IGSS failure caused by the first failure cause, the method further comprises the following steps: When the relevance exists, the ratio of etching gas is adjusted to obtain a plurality of etching process recipes; Among the plurality of etching process recipes, the optimal etching process recipe is determined.

6. The method of claim 5, wherein the super junction power device is an IGSS device. The etching gas is a mixed gas containing HBr, SF6, Cl2 and O2.

7. The method of claim 1, wherein the super junction power device is an IGSS device. Before the step of obtaining, by adjusting the gas ratio, an optimal morphology that is smooth and free of silicon nails within a preset range of angle morphology, and determining an EAS capability limit window of the optimal morphology, so as to improve the IGSS failure caused by the second failure cause, the method further comprises the following steps: Under the condition that the bias power or transformer coupled plasma power is kept constant, the chamber pressure is adjusted to 10-60 mTorr, the flow rate of HBr is adjusted to 100-500 sccm, the flow rate of SF6 is adjusted to 20-200 sccm, the flow rate of Cl2 is adjusted to 0-160 sccm, and the flow rate of O2 is adjusted to 0-200 sccm.

8. The method of claim 7, wherein the super junction power device is an IGSS device. The optimal morphology is obtained in the preset range of angle morphology by adjusting the gas ratio, and the EAS capability limit window of the optimal morphology is determined to improve the IGSS failure caused by the second failure cause, and the method comprises the following steps: The optimal morphology is obtained in the preset range of angle morphology by adjusting the ratio of the HBr, the SF6, the Cl2 and the O2. The depth of the optimal morphology is process window pulled, the EAS capability limit window of the optimal morphology is determined, and the EAS capability limit window of the optimal morphology meets the production condition and the target production yield requirement.

9. The method of claim 1, wherein the super junction power device is an IGSS device. The preset range of angle is 95°-110°.

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