3D capacitor and method of manufacturing the same

Abstract

The application provides a 3D capacitor and a preparation method thereof, and belongs to the semiconductor field. The 3D capacitor comprises a silicon substrate; an insulating layer and a first metal layer are sequentially arranged above the silicon substrate; a plurality of vertically stacked functional layers are arranged above the first metal layer; each functional layer comprises at least a SiO2 layer formed with a plurality of grooves and a second metal layer located above the SiO2 layer from bottom to top; wherein, from bottom to top, a first lower electrode layer, a first dielectric layer and a first upper electrode layer are sequentially arranged in the SiO2 layer, the first lower electrode is connected with the first metal layer, and the top of the first upper electrode layer is connected with a first through hole; at least one side of the SiO2 layer is further provided with a second through hole; and the second metal layer of the lower functional layer is connected with the second metal layer of the upper adjacent functional layer. The 3D capacitor and the preparation method thereof can realize the increase of the capacitance of the capacitor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a 3D capacitor and a method for its fabrication. Background Technology

[0002] Capacitors are commonly used passive devices in integrated circuits. To improve capacitor capacitance, existing technologies mainly employ three approaches: First, using high dielectric constant materials as the dielectric layer, such as the piezoelectric materials used in multilayer ceramic capacitors. While this can increase capacitance to the microfarad level, it is prone to deformation under high voltage, affecting stability and causing a whistling phenomenon. Second, increasing the effective area of ​​the dielectric layer through deep-hole etching processes to form deep-hole structures with an aspect ratio of 50:1 on the substrate, combined with LPCVD or ALD processes to deposit thin films, can increase the effective capacitance by tens of times. However, as the aspect ratio increases, the process difficulty increases significantly, limiting further capacitance improvement. Third, using NAND technology to fabricate multilayer capacitor arrays. However, this process is complex, requires high precision control of the thin film, and may increase the equivalent series resistance, affecting high-frequency characteristics.

[0003] Therefore, there is an urgent need to study a new capacitor structure and manufacturing method to increase the capacitance value of capacitors. Summary of the Invention

[0004] In view of this, this application provides a 3D capacitor and a method for fabricating the same, which can increase the capacitance value of the capacitor by stacking multiple layers of trench capacitors.

[0005] Specifically, this application is implemented through the following technical solution:

[0006] A first aspect of this application provides a 3D capacitor, the 3D capacitor comprising:

[0007] silicon substrate;

[0008] An insulating layer and a first metal layer are sequentially disposed on the silicon substrate; a plurality of vertically stacked functional layers are disposed on the first metal layer.

[0009] Each of the functional layers includes, from bottom to top, at least a SiO2 layer with multiple trenches and a second metal layer above the SiO2 layer. In the SiO2 layer, a first lower electrode layer, a first dielectric layer and a first upper electrode layer are stacked sequentially from bottom to top. The first lower electrode layer is connected to the first metal layer, and the top of the first upper electrode layer is connected to a first via. The first via connects the first upper electrode layer and a first portion of the second metal layer.

[0010] At least one side of the SiO2 layer is further provided with a second through hole, the second through hole electrically connects the first metal layer to a second part of the second metal layer, the length of the second through hole is greater than that of the first through hole, and the first part and the second part are electrically isolated.

[0011] In this configuration, the second metal layer of the lower functional layer is connected to the second metal layer of the adjacent upper functional layer, and the capacitors in the multiple functional layers are connected in parallel.

[0012] A second aspect of this application provides a method for fabricating a 3D capacitor, the method comprising:

[0013] Provide a silicon substrate;

[0014] An insulating layer and a first metal layer are sequentially formed on the silicon substrate;

[0015] A first dielectric layer is formed on the first metal layer, and a plurality of first trenches are formed in the first dielectric layer by photolithography and etching processes;

[0016] Based on the first trench, a first lower electrode layer, a first dielectric layer and a first upper electrode layer are deposited sequentially.

[0017] The first lower electrode layer, the first dielectric layer and the first upper electrode layer are planarized and patterned, and then covered with an oxide layer for isolation.

[0018] A first through-hole and a second through-hole are formed in the oxide layer, wherein the etching depth of the second through-hole is greater than that of the first through-hole, the first through-hole is electrically connected to the first upper electrode layer, and the second through-hole is connected to the first metal layer.

[0019] A second metal layer is formed by depositing and patterning a metal layer, the second metal layer being patterned into a first portion and a second portion that are electrically isolated from each other, wherein the first portion is electrically connected to the first via and the second portion is electrically connected to the second via.

[0020] The operation from forming the first dielectric layer to forming the second metal layer is repeated, and at least one functional layer is formed on the second metal layer, wherein when forming the trench, the position of the trench opening is controlled to be offset from the trench opening in the adjacent lower functional layer.

[0021] The 3D capacitor and its fabrication method provided in this application significantly improve capacitance density by stacking multiple functional layers with deep trench structures in the vertical direction and staggering the trench opening positions of adjacent functional layers. This allows for a several-fold increase in the effective capacitance area within a limited chip planar area. Specifically, independent upper and lower electrode lead-out paths are constructed for each functional layer through a first via, a second via, and a first and second portion of a second metal layer patterned as electrically isolated from each other. This structure ensures that the capacitors of each layer are connected in parallel, ultimately forming a stable parallel structure and achieving effective superposition of the total capacitance value while avoiding interlayer signal crosstalk. Secondly, the electrodes at both ends of the capacitor are connected to low-resistivity metals (the first and second metal layers), effectively reducing parasitic resistance and lowering power consumption. Furthermore, by staggering the trench opening positions of adjacent functional layers, the trenches of each layer no longer completely overlap in the vertical direction during multi-layer stacking. This staggered layout avoids stress concentration in the vertical direction, improving the mechanical stability and process yield of the multilayer stacked structure. Furthermore, it allows each layer to create its own trenches on the blank areas of the functional layers below, maximizing the use of three-dimensional space and effectively increasing the number of capacitors per unit projected area. Finally, the second via is longer than the first via and is used to connect the lower electrode signal and extend it to the second part of this layer. This design allows the common signal of the lower electrode to vertically penetrate multiple functional layers with the shortest path, forming a low-resistance parallel bus. This not only simplifies the complexity of interlayer interconnection but also helps reduce the equivalent series resistance of the entire capacitor, ensuring the device's performance in high-frequency applications. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of the 3D capacitor provided in this application;

[0023] Figure 2 As shown in this application Figure 1 A partial schematic diagram;

[0024] Figure 3 This is a schematic diagram illustrating the formation of trenches in the SiO2 layer as shown in this application;

[0025] Figure 4 This is a schematic diagram of the filling trench shown in this application;

[0026] Figure 5 The object shown in this application Figure 4 A schematic diagram of the structure shown after graphical processing.

[0027] Figure 6 This is a schematic diagram illustrating the oxide layer coating process described in this application;

[0028] Figure 7This is a schematic diagram illustrating the formation of a first through-hole, a second through-hole, and a second metal layer as shown in this application;

[0029] Figure 8 This is a top view of the first, second, and third layers of the trench when the three functional layers are stacked as shown in this application;

[0030] Figure 9 This is a top view of the first, second, and third layers of the trench when another three-layer functional layer is stacked as shown in this application;

[0031] Figure 10 3D capacitors are arranged in a stacked structure as shown in this application;

[0032] Figure 11 A flowchart of Example 2 of the method for fabricating the 3D capacitor provided in this application;

[0033] Explanation of reference numerals in the attached figures:

[0034] Silicon substrate: 1;

[0035] Insulation layer: 2;

[0036] First metal layer: 3;

[0037] Functional layer: 4;

[0038] SiO2 layer: 5;

[0039] First lower electrode layer: 51;

[0040] First dielectric layer: 52;

[0041] First upper electrode layer: 53;

[0042] Second metal layer: 6;

[0043] The first part of the second metal layer: 61;

[0044] The second portion of the second metal layer: 62;

[0045] First through hole: 7;

[0046] Second through hole: 8;

[0047] Third through hole: 9. Detailed Implementation

[0048] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0049] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used herein are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0050] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0051] The following specific embodiments are given to illustrate the technical solution of this application in detail.

[0052] Example 1

[0053] Figure 1 This is a schematic diagram of the structure of the 3D capacitor provided in this application. Please refer to... Figure 1 The 3D capacitor provided in this embodiment includes:

[0054] Silicon substrate 1;

[0055] An insulating layer 2 and a first metal layer 3 are sequentially disposed on the silicon substrate 1; a plurality of vertically stacked functional layers 4 are disposed on the first metal layer.

[0056] Each of the functional layers 4 includes, from bottom to top, at least a SiO2 layer 5 with multiple trenches and a second metal layer 6 located on the SiO2 layer. In the SiO2 layer 5, a first lower electrode layer 51, a first dielectric layer 52 and a first upper electrode layer 53 are stacked from bottom to top. The first lower electrode layer 51 is connected to the first metal layer 3. The top of the first upper electrode layer 53 is connected to a first through hole 7. The first upper electrode layer 53 and a first portion 61 in the second metal layer are connected through the first through hole 7.

[0057] At least one side of the SiO2 layer is further provided with a second through hole 8, the second through hole 8 electrically connects the first metal layer 3 to the second part 62 in the second metal layer 6, the length of the second through hole 8 is greater than that of the first through hole 7, and the first part and the second part are electrically isolated.

[0058] In this configuration, the second metal layer of the lower functional layer is connected to the second metal layer of the adjacent upper functional layer, and the capacitors in the multiple functional layers are connected in parallel.

[0059] Figure 2 As shown in this application Figure 1 Please refer to the partial schematic diagram. Figure 2 An insulating layer 2, a first metal layer 3, and a SiO2 layer 5 are sequentially disposed on a silicon substrate 1. The lengths of the above layers are consistent in the horizontal direction, that is, the upper layer completely covers the lower layer.

[0060] It should be noted that the main function of the silicon substrate 1 is to serve as the basic support structure for the entire 3D capacitor, providing a physical platform and ensuring the basic environment for the mechanical stability and electrical performance of the entire 3D capacitor. The insulating layer 2 is used to achieve electrical insulation between the silicon substrate 1 and the upper first metal layer 3, reducing signal crosstalk between the device and the substrate. Its material is typically SiO2, which can be prepared through processes such as thermal oxidation or chemical vapor deposition (CVD). In some applications, the insulating layer 2 can also increase the adhesion of the deposited metal layer (such as copper). In some applications, the insulating layer 2 can be removed by selecting a different first metal layer. The main purpose of the first metal layer 3 is to connect the capacitor electrodes and serve as a barrier layer for subsequent etching. Its material can be a single layer of aluminum, copper, titanium, or titanium nitride, or an alloy thereof, or a multilayer composite film. The first metal layer 3 can be obtained through patterning operations (exposure and etching). Preferably, if copper is used as the first metal layer 3, it can be patterned using the damascus method.

[0061] Furthermore, a SiO2 layer 5 is deposited on the first metal layer 3. The SiO2 layer 5 serves as an insulating support layer for the functional layers. Compared to polysilicon, SiO2 has lower dielectric loss, which is beneficial for radio frequency signal transmission. The trenches formed within it are used to construct the electrode-dielectric layer-electrode structure of the capacitor, while also providing a deposition substrate for the first lower electrode layer, the first dielectric layer, and the first upper electrode layer, ensuring the structural stability and electrical isolation of each layer. To achieve a larger aspect ratio, the SiO2 layer is typically thicker, generally greater than 1 μm. Specifically, the oxide layer thickness is determined by the size and aspect ratio of the subsequent etched deep holes / deep trenches, and is not specifically limited here. The purpose of achieving a larger aspect ratio is to maximize the effective storage area of ​​the capacitor within a limited chip planar area, thereby increasing the capacitance density per unit area. This application achieves an increase in overall capacitance by stacking multiple deep trench capacitors. The aspect ratio of a single functional layer is the basis for increasing capacitance; if the aspect ratio of a single layer is insufficient, even with multiple layers stacked, the overall capacitance will be insufficient.

[0062] In addition, it should be noted that after the above-mentioned layer structure is formed, planarization can be performed as needed to obtain a flatter surface, providing a basis for consistent flatness in subsequent process steps, and ensuring the structural quality and electrical performance of the final 3D capacitor.

[0063] Figure 3 For a schematic diagram illustrating the formation of trenches in the SiO2 layer shown in this application, please refer to... Figure 3 After the SiO2 layer 5 is deposited on the first metal layer 3, a photolithography operation is performed on the surface of the SiO2 layer 5 to define the pattern of the trenches. Then, using the pattern formed by photolithography as a mask, the SiO2 layer 5 is etched using a dry etching process to form multiple parallel trenches.

[0064] It should be noted that the dry etching process is preferably anisotropic etching to achieve a trench structure with steep sidewalls and a high aspect ratio. Specifically, the trench diameter ranges from 50 nm to 200 nm, and the aspect ratio is greater than 10:1. Through the dry etching process, deep holes or trenches with precise dimensions and controllable morphology can be formed in the SiO2 layer 5, providing a basis for the subsequent deposition of the first lower electrode layer 51, the first dielectric layer 52, and the first upper electrode layer 53, thereby effectively increasing the capacitance area in three-dimensional space. In this example, the shape of the formed trench is an inverted trapezoid. In reality, the shape and number of trenches are set according to actual needs and are not limited in this application. Furthermore, the first metal layer also acts as an etching barrier layer.

[0065] Figure 4 For a schematic diagram of the filling trench shown in this application, please refer to... Figure 4 A first lower electrode layer 51, a first dielectric layer 52, and a first upper electrode layer 53 are sequentially deposited in the trenches, thereby forming an independent vertical capacitor structure within each trench. The first lower electrode layer 51 and the first upper electrode layer 53 can be made of metals (such as Ti, W), metal alloys, metal nitrides (such as TiN), or even polycrystalline silicon. The first dielectric layer 52 can be made of materials such as SiO2, SiN, Al2O3, HfO2, ZrO2, or combinations thereof. Through this design, the sidewalls and bottom surface of the trench are used to form the effective area of ​​the capacitor, allowing a significant increase in capacitor area within a limited planar area for a single functional layer. Furthermore, after filling, a planarization operation is also required to obtain a smooth surface.

[0066] Figure 5 The object shown in this application Figure 4 Please refer to the schematic diagram of the structure shown after graphical processing. Figure 5After completing trench filling and surface planarization, the stacked structure of the first upper electrode layer 53, the first dielectric layer 52 and the first lower electrode layer 51 is graphically processed to define independent capacitor regions.

[0067] It should be noted that the patterning operation here involves partially removing the multilayer thin film stack structure that originally completely covered the surface of the SiO2 layer through photolithography and etching processes. The capacitor region refers to the independent functional block that is retained, which includes the vertical capacitor structure in the trench and the surface electrode connection part. The purpose of the patterning operation here is to define the capacitor region. The area without capacitors will be used for the fabrication of vias.

[0068] Figure 6 This is a schematic diagram illustrating the oxide layer coating process shown in this application. Please refer to... Figure 6 After patterning the stacked structure of the first upper electrode layer 53, the first dielectric layer 52, and the first lower electrode layer 51, an oxide layer is applied and planarized. It should be noted that this oxide layer provides a stable substrate for subsequent via fabrication (first via, second via) and first metal layer deposition, while protecting the underlying electrode-dielectric layer-electrode stacked structure from physical damage by subsequent processes (such as etching and deposition), thus improving the structural stability and reliability of the device. It is important to note that the oxide layer material here can be the same as the SiO2 layer material, but it must be distinguished that this oxide layer is not a SiO2 layer. Furthermore, the flat and insulating oxide layer surface supports the fabrication of the upper functional layers, such as the SiO2 layer and electrode layers, ensuring the alignment accuracy and structural integrity of each layer during multilayer stacking, ultimately enabling the parallel connection of multiple capacitor layers to improve the overall capacity.

[0069] Figure 7 This application illustrates the formation of the first through-hole, the second through-hole, and the second metal layer. Please refer to the schematic diagram. Figure 7 A first through hole 7 is provided on the top of the first upper electrode layer 53 to connect the first upper electrode layer 53 and the first part 61 of the second metal layer; a second through hole 8 is also provided on at least one side of the SiO2 layer to extend the signal of the connected first metal layer 3 and first lower electrode layer 51 to the second part 62 of the second metal layer.

[0070] It should be noted that this step employs multiple (e.g., three) exposure processes to fabricate the first via, the second via, and the second metal layer separately. In some advanced processes, the second via and the second metal layer can be integrated in a single step using the double damask method. Referring to the example of three exposures above, it's important to clarify that "single integration" here means that the material of the second via is the same as the second metal, achieved through a single deposition, but the exposure is still three times. Specifically, three exposures refer to the three independent photolithography and etching processes used to pattern the three structures sequentially during the fabrication of the first via, the second via, and the second metal layer. This three-step approach allows for control over the patterning precision of each step, ensuring that the patterns of the first via, the second via, and the second metal layer are independent and accurate. The double damascene process is an integrated technology in semiconductor manufacturing that simultaneously fabricates vias and metal layers. Through a single photolithography-etching process, the patterns of vias (such as a second via) and metal layers (such as a second metal layer) are defined simultaneously, and then metal filling and planarization are completed. The double damascene process can reduce process complexity and cost, and the interface between the fabricated metal layer and the via is more tightly connected, with lower resistance and better electrical performance.

[0071] Please continue to refer to Figure 7 The first via 7 directly connects to the exposed area of ​​the first upper electrode layer 53, enabling the shortest path connection between the first upper electrode layer 53 and the first part 61 in the second metal layer, reducing signal transmission loss. Furthermore, it avoids the first lower electrode and the first dielectric layer structure inside and around the trench, preventing accidental connection with the first lower electrode that could cause a capacitor short circuit, thus ensuring the independence of the first upper electrode signal. The second via 8 is located away from the core capacitor area, does not occupy the effective area of ​​the trench, and does not affect the capacitance of a single layer capacitor (avoiding a reduction in the effective electrode area due to via occupancy). It is also far from the distribution area of ​​the first via 7, ensuring physical isolation between the two on the plane. This ensures electrical isolation between the first part (connected to the first via) and the second part (connected to the second via) of the second metal layer, preventing crosstalk between the upper and lower electrode signals. This layout provides a clear and consistent rule for the alignment and connection of upper and lower metal layers in multi-layer stacking, avoiding confusion in inter-layer signal routing.

[0072] Furthermore, the second via 8 directly penetrates the covering oxide layer and the SiO2 layer with multiple trenches, directly connecting the second portion 62 of the second metal layer to the first metal layer 3. Besides transmitting the signal from the first metal layer to the second portion of the second metal layer, it also leads out the signal from the first lower electrode (see reference). Figure 7The first bottom electrode deposited is directly connected to the first metal layer. This interconnection with the upper layer simplifies the process and ensures the uniformity of signal transmission of the bottom electrode, laying the foundation for parallel connection of bottom electrodes in multilayer capacitors. Based on this requirement, the number of layers penetrated by the second via is significantly greater than that of the first via; therefore, the length of the second via is also much greater than that of the first via.

[0073] It should be noted that, through the design of the via positions, connections, and length differences described above, firstly, the physical isolation design of the bottom vias avoids the risk of crosstalk for the upper interconnection; the shared connection between the second via and the first metal layer provides a unified signal interface for the upper layer; and the length adaptation ensures the efficiency of inter-layer signal transmission, together forming the basis for the feasibility of the upper interconnection; secondly, these designs are ultimately to support the parallel connection requirements of multilayer capacitors. The first vias of all upper functional layers can achieve homogeneous interconnection of upper electrode signals through the first part of the corresponding second metal layer, and the second vias can achieve homogeneous interconnection of lower electrode signals through the second part of the corresponding second metal layer, forming a complete parallel structure.

[0074] Dividing the second metal layer into a first part and a second part that are electrically isolated from each other can, on the one hand, completely separate the upper and lower electrode signals, avoid short circuits within the metal layer, and ensure the realization of the basic working principle of the capacitor; on the other hand, it can complete the signal aggregation of multiple trench capacitors within a single layer, forming a superposition effect of small parallel connections within the layer and large parallel connections between layers, ultimately improving the overall capacitance value; at the same time, this partitioning design can be completed in only one patterning process without the need to add additional electrodes or interconnect structures, which simplifies the process and further improves the electrical stability and high-frequency application reliability of the device.

[0075] It should be further explained that in the above multi-layer stacked structure, there is a reuse relationship in the electrical connections between the functional layers. For any functional layer (except the top layer), the second metal layer above it, while carrying the electrode connection function of the capacitor in this layer (i.e., the first part connects to the upper electrode, and the second part connects to the lower electrode), also provides a base connection function similar to the first metal layer for the adjacent functional layers above. Specifically, the first lower electrode layer of the capacitor in the upper functional layer makes electrical contact with the second metal layer through its own patterned structure, thereby realizing the continuation of the lower electrode signal; at the same time, the second metal layer also connects to the second via above through its patterned second part, continuing to transmit the common lower electrode signal upward. This functional reuse of metal layers constitutes a parallel bus of lower electrodes throughout the multi-layer structure, greatly simplifying the complexity of inter-layer interconnection.

[0076] Please continue to refer to Figure 1 The functional layer has a second through hole on at least one side, from Figure 1As can be seen from the exemplary overall structure, the second via of the bottommost functional layer is located on one side of this layer, while the second vias of the remaining upper functional layers are symmetrically located on both sides of their respective layers. This design is based on a comprehensive consideration of the interconnection requirements of multi-layer stacking, signal transmission efficiency, and process feasibility. In specific implementations, a reasonable design can be made according to actual needs, which will not be elaborated here. Figure 1 Taking this as an example, the core function of the second via is to lead the signals from the lower electrodes of each layer (via the first metal layer) to the second part of the second metal layer, and then connect the lower electrodes in parallel through the connection between the upper and lower second metal layers. The difference in the number of vias in different layers is to simplify the underlying process and optimize the flexibility of the upper layer interconnection while ensuring interconnect reliability.

[0077] It should be noted that the first metal layer 3 forms the underlying foundation of the entire 3D capacitor's lower electrode parallel bus. The first lower electrode layer 51 of all capacitors in the bottom functional layers achieves electrical connection and signal unification through this first metal layer 3. Therefore, in the lowest functional layer, only a second via 8 needs to be provided on one side to lead this unified lower electrode signal upwards to the second part 62 in the second metal layer. This single-sided lead-out design helps reduce the area occupied by vias at the edge of the bottom SiO2 layer 5, reduces the risk of damage to the bottom capacitor structure from the etching process, avoids signal redundancy caused by multiple vias, and simplifies the connection path between the bottom lower electrode signal and the upper interconnect and external circuits.

[0078] In contrast, the upper functional layer needs to be interconnected with the second metal layer of the lower functional layer through its own second via. The layout with vias on both sides offers several advantages. Firstly, the relatively symmetrical structure reduces high-frequency signal reflection and improves transmission efficiency. Secondly, this symmetrical layout allows for more uniform stress distribution on the second metal layer of the upper functional layer, especially during the planarization process after multi-layer stacking. This reduces localized stress concentration caused by vias on one side, preventing interlayer delamination or structural deformation.

[0079] In addition, for stacked structures with three or more layers, the vias on both sides of the middle functional layer can be connected to the second metal layers of the upper and lower layers respectively, so that the signals of the lower electrodes of each layer can be efficiently converged, ensuring that the lower electrodes of all layer capacitors are connected in parallel, and ensuring the superposition effect of the overall capacitance value.

[0080] Figure 8 This is a top view of the first, second, and third layers of the trench when the three functional layers are stacked as shown in this application; Figure 9 This is a top view of the first, second, and third layers of the trench in another three-layer functional layer stack as shown in this application. Please also refer to... Figure 8 and Figure 9The top view shape (such as circular or square) of the trench opening shown in the figure is mainly affected by the specific shape of the trench, and this application does not impose any restrictions on it. Observing its internal arrangement structure, it can be seen that in two adjacent functional layers, the orthographic projection of the trench opening located in the upper layer on a plane parallel to the surface of the silicon substrate is offset from the orthographic projection of the trench opening located in the lower layer.

[0081] It should be noted that the staggered arrangement here refers to the fact that the projection center of the upper trench opening does not fall directly on the projection area of ​​the lower trench opening, but rather falls directly above the gap area between the lower trench openings. This staggered relationship can be achieved in several ways, for example, by keeping the period and number of trenches in each layer constant and only shifting their positions; or by using different numbers or arrangement periods of trenches in different layers to form a staggered layout. Specifically, such as... Figure 8 As shown, the opening of the second layer of grooves is located directly above the gap of the opening of the first layer of grooves, and the opening of the third layer of grooves is located directly above the gap of the opening of the second layer of grooves, forming an alternating arrangement. Figure 9 The diagram shows another staggered arrangement, in which the second layer of grooves is offset relative to the first layer in both the horizontal and vertical directions, resulting in a more uniform stress distribution.

[0082] It should be noted that if the orthographic projections of the openings of adjacent trench layers overlap, multiple layers stacked together will waste usable vertical space due to the overlapping vertical structures (only one layer can be stacked below the overlapping area). A staggered arrangement allows each trench layer to be arranged without vertical overlap, for example... Figure 8 Below each trench in the first layer, the second layer has its own independent space for trench layout, and the third layer can be stacked in the gaps of the second layer. Thus, within a limited chip area, more trenches can be integrated through three-dimensional layering, directly increasing the number of capacitors per unit area and ultimately amplifying the total capacity.

[0083] Furthermore, multilayer stacked semiconductor structures are prone to stress concentration due to inconsistent thermal expansion and contraction between layers and material shrinkage. If the trench openings overlap, stress will continue to accumulate in the overlapping area, leading to interlayer delamination or cracking. Staggered trenches distribute stress evenly across the entire device area by dispersing the vertical projection of the trenches, avoiding excessive local stress, improving the structural stability of 3D capacitors during fabrication (such as high-temperature deposition and etching) and operation (such as voltage loading and temperature changes), and reducing the risk of failure.

[0084] It should also be noted that after the trench openings are staggered, the first and second through holes of each layer can be freely arranged in non-overlapping areas, avoiding process conflicts caused by overlapping through holes during interlayer interconnection. For example, the second through hole of the lower trench can extend independently in the edge area, and the first through hole of the upper trench can also be precisely connected at its own opening, without sacrificing the efficiency of the interconnection path to avoid the lower structure, ultimately ensuring the independent transmission of upper and lower electrode signals and the reliability of multi-layer parallel interconnection.

[0085] Figure 10 For another 3D capacitor stacked as shown in this application, please refer to... Figure 10 Trenches are formed directly within the silicon substrate using silicon etching, followed by the process mentioned above. Figure 4 Fill the trench to Figure 7 The process of forming the first via, the second via, and the second metal layer follows the same method described above after the formation of a functional layer. Please refer to [link to documentation]. Figure 10 The lower electrode layer within the bottom trench is in direct contact with the silicon substrate. This bottom electrode layer is directly connected to the second portion 62 of the second metal layer via the third via 9 on the side. The trenches in the upper structure remain within the SiO2 layer. By etching the bottom trenches directly onto the silicon substrate, the substrate can be further utilized, increasing capacitance density (unlike the methods described earlier where the silicon substrate itself was not utilized). It should be noted that... Figure 10 The third via 9 shown is located in the bottommost functional layer. Its function is similar to the second vias in the aforementioned functional layers: to lead the common signal of the lower electrode layer upwards and electrically connect it to the second portion of the second metal layer of the corresponding layer. The difference is that, since the bottommost lower electrode layer is formed directly in the trench of the silicon substrate, the third via 9 needs to directly contact the lower electrode layer in the silicon substrate trench and connect its signal to the second portion 62 in the second metal layer of that layer, so that the lower electrode of the capacitor in that layer can be connected to a common parallel bus. In actual manufacturing, this third via can be formed simultaneously with the first via in the same layer.

[0086] In addition, depending on the application scenario, the silicon substrate can be either high-resistivity silicon or heavily doped silicon, corresponding to scenarios where the capacitor electrode is located on one side of the substrate and on both sides of the substrate. For scenarios using high-resistivity silicon, an oxide layer will be deposited before depositing the lower electrode to reduce the parasitic capacitance of the silicon substrate. For details, please refer to the description of the relevant technology, which will not be repeated here.

[0087] The 3D capacitor provided in this embodiment constructs a clear parallel path for upper and lower electrodes by vertically stacking multiple functional layers with staggered trench openings and utilizing a second metal layer that is patterned and segmented, as well as first and second vias of different lengths. This achieves a doubling of capacitance density within a limited chip area, while avoiding interlayer signal crosstalk and stress concentration, thus ensuring the high-frequency performance and structural reliability of the device.

[0088] Example 2

[0089] Corresponding to the aforementioned 3D capacitor embodiment, this application also provides an embodiment of a method for fabricating a 3D capacitor.

[0090] Figure 11 This is a flowchart of Example 2 of the method for fabricating the 3D capacitor provided in this application. Please refer to... Figure 11 The preparation method provided in this embodiment includes:

[0091] S1101, Provide a silicon substrate.

[0092] S1102, An insulating layer and a first metal layer are sequentially formed on the silicon substrate.

[0093] S1103. A first dielectric layer is formed on the first metal layer, and a plurality of first trenches are formed in the first dielectric layer by photolithography and etching processes.

[0094] S1104. Based on the first trench, a first lower electrode layer, a first dielectric layer and a first upper electrode layer are deposited sequentially.

[0095] S1105. The first lower electrode layer, the first dielectric layer and the first upper electrode layer are patterned by a planarization process, and then an oxide layer is applied for isolation.

[0096] S1106. A first through-hole and a second through-hole are formed in the oxide layer, wherein the etching depth of the second through-hole is greater than that of the first through-hole, the first through-hole is electrically connected to the first upper electrode layer, and the second through-hole is connected to the first metal layer.

[0097] S1107. A second metal layer is deposited and patterned to form a metal layer, the second metal layer being patterned into a first portion and a second portion that are electrically isolated from each other, wherein the first portion is electrically connected to the first via and the second portion is electrically connected to the second via.

[0098] In some applications, the second metal layer and the short via can be achieved through the double damask process or through two independent exposures.

[0099] S1108. Repeat the operation from forming the first dielectric layer to forming the second metal layer, forming at least one functional layer on the second metal layer, wherein when forming the trench, the position of the trench opening is controlled to be offset from the trench opening in the adjacent lower functional layer.

[0100] The second metal layer of the lower functional layer is connected to the second metal layer of the upper functional layer through a second through-hole.

[0101] It should be noted that the specific process flow has been explained in detail above and will not be repeated here.

[0102] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A 3D capacitor, characterized in that, The 3D capacitor includes: silicon substrate; An insulating layer and a first metal layer are sequentially disposed on the silicon substrate; a plurality of vertically stacked functional layers are disposed on the first metal layer. Each of the functional layers includes, from bottom to top, at least a SiO2 layer with multiple trenches and a second metal layer above the SiO2 layer. In the SiO2 layer, a first lower electrode layer, a first dielectric layer and a first upper electrode layer are stacked sequentially from bottom to top. The first lower electrode layer is connected to the first metal layer, and the top of the first upper electrode layer is connected to a first via. The first via connects the first upper electrode layer and a first portion of the second metal layer. At least one side of the SiO2 layer is further provided with a second through hole, the second through hole electrically connects the first metal layer to a second part of the second metal layer, the length of the second through hole is greater than that of the first through hole, and the first part and the second part are electrically isolated. In this configuration, the second metal layer of the lower functional layer is connected to the second metal layer of the adjacent functional layer above, and the capacitors in the multiple functional layers are connected in parallel. For any second metal layer of a functional layer other than the topmost functional layer, in addition to carrying the electrode connection function of the capacitor of this layer, it also provides the same substrate connection function as the first metal layer for the adjacent functional layer above.

2. The 3D capacitor according to claim 1, characterized in that, In two adjacent vertically stacked functional layers, the second metal layer of the lower functional layer is connected to the second metal layer of the upper functional layer through the second through-hole of the upper functional layer. The second part of the second metal layer of the bottommost functional layer is also connected to the first metal layer through the second through-hole of the bottommost functional layer.

3. The 3D capacitor according to claim 1, characterized in that, The thickness of the SiO2 layer is greater than 1 μm; the diameter of the trench is 50 nm–200 nm, and the aspect ratio is greater than 10:

1.

4. The 3D capacitor according to claim 1, characterized in that, In two adjacent functional layers, the orthographic projection of the trench opening in the upper layer onto a plane parallel to the surface of the silicon substrate is offset from the orthographic projection of the trench opening in the lower layer.

5. The 3D capacitor according to claim 1, characterized in that, The second through hole is provided on at least one side of the functional layer.

6. The 3D capacitor according to claim 1, characterized in that, The silicon substrate has multiple trenches, and a lower electrode layer, a dielectric layer and an upper electrode layer are stacked in the trenches from bottom to top; the lower electrode is connected to a second part of the second metal layer through a third via; the functional layer is stacked on the second metal layer.

7. The 3D capacitor according to claim 1, characterized in that, An oxide layer is also provided between the first upper electrode layer and the second metal layer.

8. The 3D capacitor according to claim 1, characterized in that, The first and second vias are formed through multiple independent exposure processes, or the second via and the second metal layer are integrated in one step through a double damask process.

9. A method for fabricating a 3D capacitor, characterized in that, The method is used to prepare a 3D capacitor as described in any one of claims 1 to 8, the preparation method comprising: Provide a silicon substrate; An insulating layer and a first metal layer are sequentially formed on the silicon substrate; A first dielectric layer is formed on the first metal layer, and a plurality of first trenches are formed in the first dielectric layer by photolithography and etching processes; Based on the first trench, a first lower electrode layer, a first dielectric layer and a first upper electrode layer are deposited sequentially. The first lower electrode layer, the first dielectric layer, and the first upper electrode layer are planarized and patterned, and then covered with an oxide layer for isolation. A first through-hole and a second through-hole are formed in the oxide layer, wherein the etching depth of the second through-hole is greater than that of the first through-hole, the first through-hole is electrically connected to the first upper electrode layer, and the second through-hole is connected to the first metal layer. A second metal layer is formed by depositing and patterning a metal layer, the second metal layer being patterned into a first portion and a second portion that are electrically isolated from each other, wherein the first portion is electrically connected to the first via and the second portion is electrically connected to the second via. The operation from forming the first dielectric layer to forming the second metal layer is repeated, and at least one functional layer is formed on the second metal layer, wherein when forming the trench, the position of the trench opening is controlled to be offset from the trench opening in the adjacent lower functional layer.

10. The preparation method according to claim 9, characterized in that, The second metal layer of the lower functional layer is connected to the second metal layer of the upper functional layer through a second through-hole.

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