Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention relates to a solar cell, a preparation method thereof and a photovoltaic module. The solar cell comprises a semiconductor substrate which comprises a first surface and a second surface which are oppositely arranged; a plurality of passivation regions and a plurality of passivation contact regions are arranged on the semiconductor substrate, and the plurality of passivation regions and the plurality of passivation contact regions are alternately arranged along a first direction; the first direction is perpendicular to the thickness direction of the semiconductor substrate; the plurality of passivation contact structures are arranged on the second surface and are correspondingly distributed in the passivation contact regions; wherein the passivation contact structure comprises a conductive passivation layer; the dielectric layer at least covers and is positioned on the second surface of the passivation region; and a plurality of first electrodes, wherein at least one first electrode is arranged on one side, far away from the semiconductor substrate, of each passivation contact structure. According to the invention, the absorption of the passivation contact structure on long-wave-band light can be reduced, the current is increased, and the cell efficiency is improved.

Description

[0001] This application is a divisional application of the application with the application number: 202410956630X (invention name: solar cell and its preparation method, photovoltaic module, application date: July 17, 2024). TECHNICAL FIELD

[0002] The present application relates to the technical field of solar photovoltaic cells, in particular to a solar cell, a preparation method thereof and a photovoltaic module. BACKGROUND

[0003] With the continuous development of solar cell technology, people's requirements for cell photoelectric conversion efficiency are also getting higher and higher, but the improvement of the efficiency of the current industrialization cell still faces many challenges. Among them, the contact recombination of the metal and silicon contact area and the Auger recombination and deep level recombination caused by diffusion in the silicon matrix are the main factors restricting the improvement of the cell efficiency. The TOPCon (Tunnel Oxide Passivated Contact) cell reduces the recombination of surface carriers by setting a passivation contact structure on the back surface of the silicon substrate. How to further improve the efficiency of the TOPCon cell has become the research focus of the technical personnel in the field. SUMMARY

[0004] Therefore, it is necessary to provide a solar cell, a preparation method thereof and a photovoltaic module in view of the above problems.

[0005] In a first aspect, the embodiments of the present application provide a solar cell, comprising:

[0006] A semiconductor substrate comprising a first surface and a second surface arranged opposite to each other; a plurality of passivation regions and a plurality of passivation contact regions are provided on the semiconductor substrate, the plurality of passivation regions and the plurality of passivation contact regions are arranged alternately along a first direction; the first direction is perpendicular to the thickness direction of the semiconductor substrate;

[0007] A plurality of passivation contact structures are provided on the second surface and correspondingly distributed in each passivation contact region; wherein the passivation contact structure comprises a conductive passivation layer;

[0008] A dielectric layer covering at least the second surface of the passivation region; and

[0009] A plurality of first electrodes, at least one first electrode is provided on the side of each passivation contact structure away from the semiconductor substrate.

[0010] In one embodiment, the second surface of the passivation region has a first distance between the first surface, and the second surface of the passivation contact region has a second distance between the first surface;

[0011] The second distance is greater than the first distance.

[0012] In one embodiment, the difference between the second distance and the first distance is greater than 1 μm.

[0013] In one embodiment, the solar cell further comprises a plurality of first diffusion layers disposed in the semiconductor substrate, the plurality of first diffusion layers correspondingly distributed in the plurality of passivation contact regions, each of the first diffusion layers is in contact with the second surface.

[0014] In one embodiment, the difference between the second distance and the first distance is greater than or equal to a dimension of the first diffusion layer along a thickness direction of the semiconductor substrate.

[0015] In one embodiment, the second surface is a back surface.

[0016] In one embodiment, a roughness of the second surface in the passivation region is less than a roughness of the second surface in the passivation contact region.

[0017] In one embodiment, a plurality of pits are disposed on the second surface; a first pit is defined as a pit with the deepest depth in the passivation region, and a second pit is defined as a pit with the deepest depth in the passivation contact region.

[0018] The depth of the first pit is less than the depth of the second pit.

[0019] In one embodiment, an inner diameter of the first pit is greater than an inner diameter of the second pit.

[0020] In one embodiment, the second surface in the passivation region has a first distance from the first surface, and the second surface in the passivation contact region has a second distance from the first surface.

[0021] The second distance is greater than the first distance.

[0022] In one embodiment, in a direction from the second surface to the first surface, a dimension of the passivation contact structure along the first direction gradually decreases.

[0023] In one embodiment, the passivation contact structure further comprises a tunneling layer disposed between the conductive passivation layer and the semiconductor substrate.

[0024] In a direction from the second surface to the first surface, a dimension of the conductive passivation layer along the first direction gradually decreases.

[0025] In one of the embodiments, each of the passivation contact structures is provided with one of the first electrodes; a side surface of the conductive passivation layer close to the tunneling layer is a first surface, and a side surface of the conductive passivation layer away from the tunneling layer is a second surface;

[0026] The size of the first surface along the first direction, the size of the second surface along the first direction, and the size of the first electrode along the first direction satisfy the following relationship:

[0027]

[0028] In the above formula, W1 is the size of the first surface along the first direction, W2 is the size of the second surface along the first direction, and W3 is the size of the first electrode along the first direction.

[0029] In one of the embodiments, the dielectric layer also covers a surface of the passivation contact structure close to the passivation region.

[0030] In one of the embodiments, the second surface of the semiconductor substrate includes a first sub-surface, a second sub-surface, and a connecting surface; the first sub-surface is located in the passivation region, the second sub-surface is located in the passivation contact region, and the connecting surface connects the first sub-surface and the second sub-surface adjacent to each other.

[0031] The dielectric layer also covers the connecting surface.

[0032] In one of the embodiments, the second sub-surface includes a sub-contact surface and two non-contact surfaces, the two non-contact surfaces are located on both sides of the sub-contact surface along the first direction; the passivation contact structure is in contact with the sub-contact surface.

[0033] The dielectric layer also covers the non-contact surface.

[0034] In one of the embodiments, the dielectric layer includes one or more of aluminum oxide, silicon nitride, and silicon oxynitride.

[0035] In one of the embodiments, the conductive passivation layer includes a doped polysilicon layer, and the doped polysilicon layer is doped with N-type doping elements or P-type doping elements.

[0036] In one of the embodiments, the doped polysilicon layer is further doped with one or more of carbon, nitrogen, and oxygen.

[0037] In one of the embodiments, the conductive passivation layer further includes a silicon carbide layer, and the silicon carbide layer is arranged on a side of the doped polysilicon layer away from the semiconductor substrate.

[0038] In a second aspect, the embodiments of the present application provide a preparation method of a solar cell, including:

[0039] A semiconductor substrate is provided, which includes a first surface and a second surface arranged oppositely; a plurality of passivation regions and a plurality of passivation contact regions are arranged on the semiconductor substrate, and the plurality of passivation regions and the plurality of passivation contact regions are arranged alternately along a first direction; the first direction is perpendicular to a thickness direction of the semiconductor substrate;

[0040] A plurality of passivation contact structures are formed on the second surface; wherein the plurality of passivation contact structures are distributed in the passivation contact regions correspondingly; the passivation contact structure includes a conductive passivation layer;

[0041] A dielectric layer is formed on the semiconductor substrate; the dielectric layer covers at least the second surface of the passivation regions;

[0042] A plurality of first electrodes are formed on the plurality of passivation contact structures; at least one first electrode is arranged on a side of each passivation contact structure away from the semiconductor substrate.

[0043] In one embodiment, the forming of the plurality of passivation contact structures on the second surface and the forming of the plurality of first diffusion layers in the semiconductor substrate include:

[0044] A stacked tunneling material layer and a conductive passivation material layer are formed on the second surface;

[0045] A patterned mask layer is formed on the conductive passivation material layer;

[0046] The tunneling material layer and the conductive passivation material layer in the passivation regions are removed to form the passivation contact structures.

[0047] In one embodiment, after the forming of the stacked tunneling material layer and the conductive passivation material layer on the second surface, before the forming of the patterned mask layer on the conductive passivation material layer, the conductive passivation material layer is subjected to heat treatment to form an initial diffusion layer; or, after the forming of the patterned mask layer on the conductive passivation material layer, before the removing of the tunneling material layer and the conductive passivation material layer in the passivation regions to form the passivation contact structures, the conductive passivation material layer is subjected to heat treatment to form an initial diffusion layer.

[0048] After the removing of the tunneling material layer and the conductive passivation material layer in the passivation regions to form the passivation contact structures, the initial diffusion layer in the passivation regions is removed to form the first diffusion layer.

[0049] In a third aspect, an embodiment of the present application provides a photovoltaic module including the solar cell in the first aspect.

[0050] The solar cell and the preparation method thereof and the photovoltaic module provided by the embodiments of the present application have the following advantages. The passivation region and the passivation contact region are arranged alternately on the semiconductor substrate, and the plurality of passivation contact structures arranged on the second surface are distributed in the passivation contact regions. In this way, a plurality of spaced passivation contact structures are arranged on the second surface, the coverage area of the conductive passivation layer on the second surface is reduced compared with the conventional TOPCon cell, thereby reducing the absorption of the conductive passivation layer to the long-wave light, increasing the current, and improving the cell efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments or the exemplary embodiments of the present application, the drawings needed to be used in the description of the embodiments or the exemplary embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0052] Figure 1 A partial cross-sectional structure schematic diagram of a solar cell is provided for an embodiment of the present application.

[0053] Figure 2 A partial schematic diagram of a semiconductor substrate of the solar cell is shown. Figure 1

[0054] Figure 3 An enlarged view of part A in the above-mentioned solar cell is shown. Figure 2

[0055] Figure 4 An enlarged view of part B in the above-mentioned solar cell is shown. Figure 2

[0056] Figure 5 A structure schematic diagram of the semiconductor substrate and the passivation contact structure of the solar cell is shown. Figure 1

[0057] A flowchart schematic diagram of a preparation method of a solar cell is provided for an embodiment of the present application. Figure 6

[0058] A flowchart schematic diagram of S20 in the above-mentioned preparation method is shown. Figure 7 Figure 6 Another flowchart schematic diagram of S20 in the above-mentioned preparation method is shown.

[0059] Figure 8 Figure 6 Another flowchart schematic diagram of S20 in the above-mentioned preparation method is shown.

[0060] Figure 9 Another flowchart schematic diagram of S20 in the above-mentioned preparation method is shown. Figure 6 ​​​​​Schematic diagram of the partial cross-sectional structure of the semiconductor substrate after texturing in the process of the preparation method shown.

[0061] Figure 10 For Figure 6 Schematic diagram of the partial cross-sectional structure of the semiconductor substrate after polishing in the process of the preparation method shown.

[0062] Figure 11 For Figure 6 Schematic diagram of the partial cross-sectional structure of the tunneling material layer, the conductive passivation material layer and the oxide layer after formation in the process of the preparation method shown.

[0063] Figure 12 For Figure 6 Schematic diagram of the partial cross-sectional structure of the semi-finished product structure of the solar cell after heat treatment in the process of the preparation method shown.

[0064] Figure 13 For Figure 6 Schematic diagram of the partial cross-sectional structure of the patterned mask layer after formation in the process of the preparation method shown.

[0065] Figure 14 For Figure 6 Schematic diagram of the partial cross-sectional structure of the passivation contact structure after formation in the process of the preparation method shown.

[0066] Figure 15 For Figure 6 Schematic diagram of the partial cross-sectional structure of the dielectric layer after formation in the process of the preparation method shown.

[0067] Reference signs:

[0068] 1. Solar cell; 11, semiconductor substrate; 11a, passivation region; 11b, passivation contact region; 111, first face; 112, second face; 1121, first sub-face; 1122, second sub-face; 11221, sub-contact face; 11222, non-contact face; 1123, connecting face; 12, passivation contact structure; 121, tunneling layer; 122, conductive passivation layer; 13, dielectric layer; 14, first electrode; 15, first diffusion layer; 16, pit; 16a, first pit; 16b, second pit; 21, tunneling material layer; 22, conductive passivation material layer; 231, oxide layer; 232, patterned mask layer; 24, initial diffusion layer. DETAILED DESCRIPTION

[0069] In order to make the above objectives, features and advantages of the present application more clear and comprehensible, specific embodiments of the present application will be described below in detail with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be practiced in many different ways from those described herein without departing from the scope of the present application, and it is understood that similar improvements can be made by those skilled in the art in the art without departing from the scope of the present application, and therefore the present application is not limited to the specific embodiments disclosed below.

[0070] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0071] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to", or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0072] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. The terms "first", "second", "third", etc. do not necessarily indicate any ordinal, chronological or other sequence unless expressly so defined by the relative terms used herein.

[0073] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It should also be understood that the term "comprising" or "having" etc. specifies the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but does not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in the present description, the term "and / or" includes any and all combinations of the associated listed items.

[0074] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of ideal embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and a surface through which the implantation was made. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the application.

[0075] As described in the background section, the conventional TOPCon cell sets a full-area passivation contact structure on the back surface of the silicon substrate to reduce the recombination of surface carriers, however, the doped polysilicon layer in the passivation contact structure is easy to absorb long-wave band light to generate parasitic absorption phenomenon, thereby reducing the current and affecting the cell efficiency.

[0076] The related art 1 reduces the absorption of long-wave band light by the doped polysilicon layer by thinning the doped polysilicon layer, however, when the metal electrode is made, the metal paste is easy to burn through the passivation contact structure, affecting the passivation effect.

[0077] The related art 2 selectively sets the thickness of the doped polysilicon layer, the thickness of the doped polysilicon layer located in the metal electrode area is thicker, and the thickness of the doped polysilicon layer located in the non-metal electrode area is thinner. However, on the one hand, this structure still has a relatively serious parasitic absorption phenomenon; on the other hand, the preparation process of this structure is relatively complex and is not suitable for large-scale mass production.

[0078] In view of at least one of the above problems, the embodiments of the present application provide a solar cell and a preparation method thereof and a photovoltaic module. By arranging the passivation regions and the passivation contact regions alternately on the semiconductor substrate, and making the plurality of passivation contact structures arranged on the second surface correspond to the passivation contact regions, a plurality of spaced passivation contact structures are arranged on the second surface, which can reduce the coverage area of the passivation contact structures on the second surface compared with the conventional TOPCon cell, thereby reducing the absorption of long-wave light by the passivation contact structures, increasing the current, and improving the cell efficiency. In addition, compared with the related art I, the solar cell provided by the present application does not affect the passivation effect; compared with the related art II, the solar cell provided by the present application has low preparation difficulty and higher mass production.

[0079] In a first aspect, referring to Figure 1 The embodiments of the present application provide a solar cell 1, which can be a TOPCon cell. Specifically, the solar cell 1 includes a semiconductor substrate 11, a plurality of passivation contact structures 12, a dielectric layer 13, and a plurality of first electrodes 14.

[0080] The material of the semiconductor substrate 11 can be silicon. The semiconductor substrate 11 includes a first surface 111 and a second surface 112 arranged oppositely. Specifically, one of the first surface 111 and the second surface 112 can be a light-receiving surface, and the other can be a back surface. The semiconductor substrate 11 is provided with a plurality of passivation regions 11a and a plurality of passivation contact regions 11b, which are arranged alternately along a first direction X. The first direction X is perpendicular to the thickness direction of the semiconductor substrate 11. The plurality of passivation contact structures 12 are arranged on the second surface 112 and correspond to the passivation contact regions 11b. The passivation contact structure 12 includes a conductive passivation layer 122. Each passivation contact structure 12 is provided with at least one first electrode 14 away from one side of the semiconductor substrate 11. The dielectric layer 13 covers at least the second surface 112 of the passivation region 11a.

[0081] It should be noted that the passivation regions 11a and the passivation contact regions 11b can be arranged alternately in two passivation regions 11a and two passivation contact regions 11b, i.e., two passivation regions 11a form a group, two passivation contact regions 11b form a group, and the group of passivation regions 11a and the group of passivation contact regions 11b are arranged alternately. The passivation regions 11a and the passivation contact regions 11b can be arranged alternately in one passivation region 11a and one passivation contact region 11b, i.e., one passivation contact region 11b is arranged between any two adjacent passivation regions 11a, and one passivation region 11a is arranged between any two adjacent passivation contact regions 11b.

[0082] It should be noted that the plurality of passivation contact structures 12 can correspond to each passivation contact region 11b one by one, or 2, 3 or more passivation contact structures 12 correspond to one passivation contact region 11b. One, two or more first electrodes 14 can be arranged on each passivation contact structure 12. It should be noted that, since Figure 1 only one passivation contact region 11b is shown in FIG. 2, the passivation contact region 11b is not limited to one, and two or more passivation contact regions 11b can be arranged on the second surface 112. Figure 1 only one first diffusion layer 15 is shown in FIG. 2.

[0083] The embodiment of the present application provides a solar cell 1, which is equivalent to arranging the passivation contact structures 12 on the second surface 112 in a spaced arrangement. Compared with the traditional TOPCon cell, the passivation contact structures 12 are not arranged on the second surface 112 of the passivation region 11a, so that the coverage area of the passivation contact structures 12 (such as the conductive passivation layer 122) on the second surface 112 can be reduced, thereby facilitating the reduction of the absorption of long-wave light by the passivation contact structures 12 (such as the conductive passivation layer 122), increasing the absorption of current, and improving the cell efficiency.

[0084] In addition, compared with the related art 1, the solar cell 1 provided by the embodiment of the present application does not thin the thickness of the passivation contact structure 12 when the metal electrode is manufactured, so that the metal paste is not easy to burn through the passivation contact structure 12, thereby not affecting the passivation effect. Compared with the related art 2, the solar cell 1 provided by the embodiment of the present application needs to remove all the materials of the passivation contact structure 12 of the passivation region 11a in the preparation process, so that the manufacturing process window is relatively large, the preparation difficulty is reduced, and the mass production is higher.

[0085] In one of the embodiments, the solar cell 1 further includes a plurality of first diffusion layers 15 arranged in the semiconductor substrate 11, the plurality of first diffusion layers 15 correspond to the plurality of passivation contact regions 11b, and each first diffusion layer 15 is connected to the second surface 112.

[0086] In the embodiment of the present application, the region of the passivation region 11a in the semiconductor substrate 11 and adjacent to the second surface 112 is not provided with a diffusion layer, which is beneficial to reduce the recombination. The region of the passivation contact region 11b in the semiconductor substrate 11 and adjacent to the second surface 112 is provided with the first diffusion layer 15, which is beneficial to improve the carrier collection efficiency.

[0087] In one embodiment, the first surface 111 is the light-facing surface, and the second surface 112 is the backlight surface. This is equivalent to having spaced-apart passivation contact structures 12 on the backlight surface. Compared to a traditional TOPCon battery, the second surface 112, located in the passivation region 11a, does not have passivation contact structures 12. This reduces the coverage area of ​​the passivation contact structures 12 (such as the conductive passivation layer 122) on the second surface 112, thereby reducing the absorption of long-wavelength light by the passivation contact structures 12 (such as the conductive passivation layer 122), increasing current absorption, and improving battery efficiency.

[0088] In one embodiment, a first distance exists between the second surface 112 located in the passivation region 11a and the first surface 111, and a second distance exists between the second surface 112 located in the passivation contact region 11b and the first surface 111. The second distance is greater than the first distance. This can also be understood as the depth of the second surface 112 located in the passivation region 11a being greater than the depth of the second surface 112 located in the passivation contact region 11b.

[0089] The above configuration has several advantages. First, it facilitates the formation of spaced passivation contact structures 12 on the second surface 112. Second, it helps to remove the diffusion layer of the passivation region 11a, which reduces recombination. Third, during the fabrication process, pits 16 are formed on the second surface 112 of the semiconductor substrate 11. By making the depth of the second surface 112 in the passivation region 11a greater than the depth of the second surface 112 in the passivation contact region 11b, it is equivalent to etching the second surface 112 in the passivation region 11a deeper. This facilitates the formation of pits 16 with larger inner diameter and shallower depth, which in turn helps to reduce the roughness of the second surface 112 in the passivation region 11a and improve the reflectivity.

[0090] In one embodiment, the difference between the second distance and the first distance is greater than 1 μm. This ensures, on the one hand, that the diffusion layer of the passivation region 11a can be removed, which helps reduce recombination; on the other hand, during fabrication, the second surface 112 of the passivation region 11a can be etched deeper, which helps form pits 16 with larger inner diameters and shallower depths, thereby reducing the roughness of the second surface 112 of the passivation region 11a and improving the reflectivity.

[0091] In one embodiment, reference Figure 1 As shown, the difference between the second distance and the first distance is greater than or equal to the dimension of the first diffusion layer 15 along the thickness direction of the semiconductor substrate 11. It can be understood that the difference between the second distance and the first distance is equal to the depth of the second surface 112 located in the passivation region 11a, and the dimension of the first diffusion layer 15 along the thickness direction of the semiconductor substrate 11 is the thickness of the first diffusion layer 15.

[0092] By making the depth of the second surface 112 of the passivation region 11a not less than the thickness of the first diffusion layer 15, on one hand, the first diffusion layer 15 of the passivation region 11a can be completely removed, which is beneficial to reduce the recombination; on the other hand, the roughness of the second surface 112 of the passivation region 11a is smaller, so that the reflection effect is better and the passivation effect is better.

[0093] In one embodiment, the second surface 112 of the passivation region 11a can be a non-pyramid microstructure morphology, and the second surface 112 of the passivation contact region 11b can be a pyramid microstructure morphology.

[0094] In one embodiment, the roughness of the second surface 112 of the passivation region 11a is smaller than the roughness of the second surface 112 of the passivation contact region 11b. Here, the roughness can be the surface roughness.

[0095] In this way, the smoothness of the second surface 112 of the passivation region 11a is increased, so that the mirror reflection effect is increased. When the light of a fixed angle is incident, because the smoothness of the second surface 112 of the passivation region 11a is larger, the reflection effect of the second surface 112 of the passivation region 11a is better, and more long-wave band light can be reflected back into the semiconductor substrate 11, which is beneficial to increase the absorption of current, thereby improving the battery efficiency.

[0096] In the embodiment of the present application, the reflectivity of the second surface 112 of the passivation region 11a is greater than the reflectivity of the second surface 112 of the passivation contact region 11b. On one hand, because the roughness of the second surface 112 of the passivation region 11a is smaller than the roughness of the second surface 112 of the passivation contact region 11b; on the other hand, because the second surface 112 of the passivation region 11a is not covered by the passivation contact structure 12, so that the absorption of long-wave band light is smaller.

[0097] In one embodiment, as shown in Figure 2 , Figure 3 and Figure 4 , the second surface 112 is provided with a plurality of pits 16. Among them, the second surface 112 of the passivation region 11a is provided with a plurality of pits 16, and the second surface 112 of the passivation contact region 11b is also provided with a plurality of pits 16. It should be noted that Figure 2 is a schematic view of the second surface 112 of the semiconductor substrate 11 under a microscope.

[0098] The deepest recess 16 in the passivation region 11a is defined as a first recess 16a, and the deepest recess 16 in the passivation contact region lib is defined as a second recess 16b. The depth of the first recess 16a is shallower than the depth of the second recess 16b. Here, the dimension of the first recess 16a in the thickness direction of the semiconductor substrate 11 is the depth of the first recess 16a, and the dimension of the second recess 16b in the thickness direction of the semiconductor substrate 11 is the depth of the second recess 16b. As shown in FIG. 23, the dimension of the first recess 16a in the thickness direction of the semiconductor substrate 11 is Hl, and the dimension of the second recess 16b in the thickness direction of the semiconductor substrate 11 is H2. Figure 3

[0099] It should be noted that the initial surface of the semiconductor substrate 11 is polished to form the recesses. Since the diffusion layer in the passivation region 11a needs to be removed, the second surface 112 in the passivation region 11a needs to be further polished to remove the diffusion layer in this region. In the process of polishing, the depth of the recesses 16 on the second surface 112 in the passivation region 11a is reduced. In this way, the depth of most of the recesses 16 on the second surface 112 in the passivation region 11a is reduced. Further, the depth of the recesses 16 is related to the roughness. On the same surface, the smaller the difference between the depth of the deepest recess 16 and the depth of the shallowest recess 16, the smaller the roughness. Therefore, the above arrangement is beneficial to make the roughness of the second surface 112 in the passivation region 11a smaller than the roughness of the second surface 112 in the passivation contact region lib.

[0100] In one embodiment, the roughness of the second surface 112 in the passivation region 11a can be defined by the depth of all the recesses 16 on the second surface 112 in the passivation region 11a. Further, the standard deviation of the depth of all the recesses 16 on the second surface 112 in the passivation region 11a is the roughness of the second surface 112 in the passivation region 11a.

[0101] The roughness of the second surface 112 in the passivation contact region lib can be defined by the depth of all the recesses 16 on the second surface 112 in the passivation contact region lib. Further, the standard deviation of the depth of all the recesses 16 on the second surface 112 in the passivation contact region lib is the roughness of the second surface 112 in the passivation contact region lib.

[0102] Further, the standard deviation of the depth of all the recesses 16 on the second surface 112 in the passivation region 11a is smaller than the standard deviation of the depth of all the recesses 16 on the second surface 112 in the passivation contact region lib.

[0103] It should be noted that when calculating the standard deviation, the standard deviation of the depth of all the recesses 16 in a unit area can be calculated.

[0104] ​In one embodiment, the inner diameter of the first pits 16a is larger than the inner diameter of the second pits 16b. As shown in FIG. 1, the inner diameter of the first pits 16a is D1, and the inner diameter of the second pits 16b is D2. It is noted that if the pits 16 are circular pits 16, then the inner diameter of the pits 16 is the diameter of the circular pits 16. If the pits 16 are square pits 16, then the inner diameter of the pits 16 can be the side length of the square pits 16. If the pits 16 are rectangular pits 16, then the inner diameter of the pits 16 can be the largest side length of the rectangular pits 16. If the pits 16 are irregularly shaped pits 16, then the inner diameter of the pits 16 can be the largest inner diameter of the irregular shape. Figure 3 Figure 4 As shown in FIG. 1, the inner diameter of the first pits 16a is D1, and the inner diameter of the second pits 16b is D2. It is noted that if the pits 16 are circular pits 16, then the inner diameter of the pits 16 is the diameter of the circular pits 16. If the pits 16 are square pits 16, then the inner diameter of the pits 16 can be the side length of the square pits 16. If the pits 16 are rectangular pits 16, then the inner diameter of the pits 16 can be the largest side length of the rectangular pits 16. If the pits 16 are irregularly shaped pits 16, then the inner diameter of the pits 16 can be the largest inner diameter of the irregular shape.

[0105] It is appreciated that the inner diameter of the pits 16 is inversely proportional to the depth of the pits 16. During the polishing process to remove the diffusion layer of the passivation region 11a, the depth of the pits 16 on the second surface 112 of the passivation region 11a is reduced, and the inner diameter is increased. As such, the inner diameter of the first pits 16a is larger than the inner diameter of the second pits 16b.

[0106] In one embodiment, the inner diameter of each of the pits 16 on the second surface 112 of the passivation region 11a is larger than the inner diameter of the pit 16 (the second pit 16b) on the passivation contact region 11b having the largest inner diameter. As such, it is equivalent to that the depth of each of the pits 16 on the second surface 112 of the passivation region 11a is smaller than the depth of the pit 16 (the second pit 16b) on the passivation contact region 11b having the largest depth. It is beneficial to make the roughness on the second surface 112 of the passivation region 11a smaller than the roughness on the second surface 112 of the passivation contact region 11b.

[0107] In another embodiment, the inner diameter of a portion of the pits 16 on the second surface 112 of the passivation region 11a is larger than the inner diameter of the pit 16 (the second pit 16b) on the passivation contact region 11b having the largest inner diameter. As such, it is equivalent to that the depth of a portion of the pits 16 on the second surface 112 of the passivation region 11a is smaller than the depth of the pit 16 (the second pit 16b) on the passivation contact region 11b having the largest depth.

[0108] In one embodiment, the inner diameter of the first pits 16a is between 8 μm and 40 μm. Exemplarily, the inner diameter of the first pits 16a can be 8 μm, 15 μm, 23 μm, 30 μm, 35 μm, 40 μm, or between any two of the above values.

[0109] In one embodiment, the inner diameter of the second pits 16b is between 5 μm and 20 μm. Exemplarily, the inner diameter of the second pits 16b can be 5 μm, 10 μm, 15 μm, 20 μm, or between any two of the above values.​

[0110] In one embodiment, the depth of the first pit 16a is between 50nm and 800nm. Exemplarily, the depth of the first pit 16a can be 50nm, 200nm, 400nm, 600nm, 800nm, or between any two of the above values.

[0111] In one embodiment, the depth of the second pit 16b is between 200nm and 1000nm. Exemplarily, the depth of the second pit 16b can be 200nm, 400nm, 500nm, 700nm, 850nm, 1000nm, or between any two of the above values.

[0112] By ensuring that the dimensions (such as depth and inner diameter) of the first pit 16a and the second pit 16b are within the range described above, it is advantageous to form pits 16 of different sizes on the second surface 112 located in the passivation region 11a and the second surface 112 located in the passivation contact region 11b, thereby making the roughness of the second surface 112 located in the passivation region 11a less than the roughness of the second surface 112 located in the passivation contact region 11b.

[0113] In one embodiment, reference Figure 1 As shown, the size of the passivation contact structure 12 gradually decreases along the first direction X from the second surface 112 to the first surface 111. That is, the width of the passivation contact structure 12 gradually decreases from the second surface 112 to the first surface 111. For the same length, the surface area of ​​the passivation contact structure 12 facing away from the semiconductor substrate 11 is larger, and the surface area of ​​the passivation contact structure 12 facing closer to the semiconductor substrate 11 is smaller. This facilitates alignment during the fabrication of the first electrode 14, reducing the fabrication difficulty of the first electrode 14; furthermore, it reduces the contact area between the passivation contact structure 12 and the second surface 112, thereby reducing the absorption of long-wavelength light by the passivation contact structure 12.

[0114] In one embodiment, the passivation contact structure 12 further includes a tunneling layer 121 disposed between the conductive passivation layer 122 and the semiconductor substrate 11. From the second surface 112 to the first surface 111, the size of the conductive passivation layer 122 gradually decreases along the first direction X, that is, the width of the conductive passivation layer 122 gradually decreases. It is understood that the tunneling layer 121 can be made of silicon oxide, and the conductive passivation layer 122 can be made of polycrystalline silicon, microcrystalline silicon, or silicon carbide, and the conductive passivation layer 122 is doped with N-type or P-type dopants.

[0115] The inventor has found that the conductive passivation layer 122 (e.g. polysilicon) is easy to absorb long-wave light. The above arrangement makes the area of the conductive passivation layer 122 close to the side surface of the semiconductor substrate 11 smaller, which is conducive to reducing the absorption of long-wave light by the conductive passivation layer 122, and makes the area of the conductive passivation layer 122 away from the side surface of the semiconductor substrate 11 larger, which facilitates alignment when the first electrode 14 is made and reduces the difficulty of making the first electrode 14.

[0116] In one of the embodiments, a first electrode 14 is arranged on each passivation contact structure 12. The side surface of the conductive passivation layer 122 close to the tunneling layer 121 is a first surface, and the side surface of the conductive passivation layer 122 away from the tunneling layer 121 is a second surface. The size of the first surface along the first direction X, the size of the second surface along the first direction X, and the size of the first electrode 14 along the first direction X satisfy the following relationship.

[0117]

[0118] In the above relationship, W1 is the size of the first surface along the first direction X, W2 is the size of the second surface along the first direction X, and W3 is the size of the first electrode 14 along the first direction X.

[0119] The above arrangement makes the area of the conductive passivation layer 122 close to the side surface of the semiconductor substrate 11 smaller, which is conducive to reducing the absorption of long-wave light by the conductive passivation layer 122, and makes the area of the conductive passivation layer 122 away from the side surface of the semiconductor substrate 11 larger, which facilitates alignment when the first electrode 14 is made and reduces the difficulty of making the first electrode 14.

[0120] In one of the embodiments, the thickness of the tunneling layer 121 is between 0.5 nm and 2 nm. For example, the thickness of the tunneling layer 121 can be 0.5 nm, 1 nm, 1.5 nm, or 2 nm.

[0121] In one of the embodiments, the solar cell 1 further includes a dielectric layer 13 covering at least the second surface 112 of the passivation region 11a and the side surface of the passivation contact structure 12 away from the semiconductor substrate 11.

[0122] In the embodiments of the present application, the dielectric layer 13 is in direct contact with the second surface 112 of the passivation region 11a, and the roughness of the second surface 112 of the passivation region 11a is smaller (the flatness is better), which can make the passivation effect of the dielectric layer 13 better. In addition, the dielectric layer 13 covering the side surface of the passivation contact structure 12 away from the semiconductor substrate 11 can also make the passivation contact structure 12 have a better passivation effect.

[0123] In one embodiment, the thickness of the dielectric layer 13 is less than 30 nm. Exemplarily, the thickness of the dielectric layer 13 can be 25 nm, 20 nm, 10 nm, etc.

[0124] In one embodiment, the dielectric layer 13 also covers the surface of the passivated contact structure 12 near the passivation region 11a, that is, the dielectric layer 13 also covers the side surface of the passivated contact structure 12. In this way, the passivated contact structure 12 can have a better passivation effect.

[0125] In one embodiment, combined with Figure 5 As shown, the second surface 112 of the semiconductor substrate 11 includes a first sub-surface 1121, a second sub-surface 1122, and a connection surface 1123. The first sub-surface 1121 is located in the passivation region 11a, the second sub-surface 1122 is located in the passivation contact region 11b, and the connection surface 1123 connects adjacent first sub-surfaces 1121 and second sub-surfaces 1122. The dielectric layer 13 also covers the connection surface 1123. Figure 5 As shown, the second sub-surface 1122 and the connecting surface 1123 together form a step. In this way, a good passivation effect can be ensured at the side surface of the step.

[0126] In one embodiment, the second sub-surface 1122 includes a sub-contact surface 11221 and two non-contact surfaces 11222, with the two non-contact surfaces 11222 located on both sides of the sub-contact surface 11221 along a first direction X. The passivated contact structure 12 contacts the sub-contact surface 11221. The dielectric layer 13 also covers the non-contact surfaces 11222. Thus, the non-contact surfaces 11222 of the second sub-surface 1122 can also have a good passivation effect.

[0127] In one embodiment, reference Figure 1 As shown, a "fitting groove" is formed between the passivated contact structure 12 and the non-contact surface 11222, and the dielectric layer 13 is embedded in the fitting groove. In this way, the connection strength between the dielectric layer 13 and the semiconductor substrate 11 can be increased, thereby improving the structural stability of the solar cell 1.

[0128] In one embodiment, the dielectric layer 13 includes one or more of aluminum oxide, silicon nitride, silicon oxynitride, and silicon oxide.

[0129] In one example, the dielectric layer 13 includes an aluminum oxide layer that at least covers the second side 112 of the passivation region 11a. Thus, compared to the conductive passivation layer 122 (such as doped polysilicon) covering the second side 112 of the passivation region 11a in related technologies, the aluminum oxide layer can have a better passivation effect in the passivation region 11a, and this passivation effect is comparable to that of doped polysilicon.

[0130] In another example, the dielectric layer 13 includes a silicon nitride layer, which covers at least the second surface 112 of the passivation region 11a. In this way, the silicon nitride layer can have a better passivation effect on the passivation region 11a, thereby improving the performance of the solar cell 1.

[0131] It can be understood that the dielectric layer 13 can be a stack of at least two of an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The embodiments of the present application do not limit the specific structure of the dielectric layer 13.

[0132] In one of the embodiments, the conductive passivation layer 122 includes a doped polysilicon layer, which is doped with N-type or P-type doping elements. In this way, the passivation contact structure 12 can have better conductivity.

[0133] In one of the embodiments, the doped polysilicon layer is further doped with one or more of carbon, nitrogen, and oxygen. In this way, the band gap of the film layer can be increased, thereby further reducing light absorption and improving the efficiency of the solar cell 1.

[0134] It can be understood that the conductive passivation layer 122 can only include the doped polysilicon layer.

[0135] In one of the embodiments, the conductive passivation layer 122 can further include a doped microcrystalline silicon layer, which is doped with N-type or P-type doping elements.

[0136] In one of the embodiments, the conductive passivation layer 122 further includes a silicon carbide layer, which is disposed on the side of the doped polysilicon layer away from the semiconductor substrate 11. It can be understood that the silicon carbide layer can also be doped with N-type or P-type doping elements.

[0137] By disposing the silicon carbide layer, on the one hand, light absorption can be reduced, which is conducive to improving the efficiency of the solar cell 1; on the other hand, in the process of manufacturing the first electrode 14, metal ablation resistance can be achieved, which is conducive to reducing metal recombination. It should be noted that the first electrode 14 is in contact with at least one of the silicon carbide layer and the doped polysilicon layer.

[0138] In one of the embodiments, the material of the tunneling layer 121 includes at least one of silicon oxide, silicon nitride, intrinsic amorphous silicon, intrinsic polysilicon, aluminum oxide, aluminum nitride, phosphorus nitride, and titanium nitride.

[0139] In one of the embodiments, the material of the conductive passivation layer 122 includes at least one of polysilicon, microcrystalline silicon, and silicon carbide. Further, the conductive passivation layer 122 is doped with N-type or P-type doping elements.

[0140] In one of the embodiments, the solar cell 1 further comprises an emitter, a second electrode and a passivation layer. The emitter and the passivation layer are sequentially stacked on the first surface 111 of the semiconductor substrate 11, and the second electrode is electrically connected with the emitter through the passivation layer.

[0141] In one of the embodiments, the first electrode 14 comprises at least one of silver and aluminum. In one example, the first electrode 14 comprises silver and aluminum, and further, the first electrode can be made of silver aluminum paste.

[0142] In one of the embodiments, the second electrode comprises at least one of silver and aluminum. In one example, the second electrode comprises silver and aluminum, and further, the second electrode can be made of silver aluminum paste.

[0143] It should be noted that the applicant has respectively tested the conventional TOPCon cell and the solar cell provided in the embodiments of the present application, and the test results are as follows:

[0144] Comparison table of solar cell performance

[0145]

[0146] According to the above table, the solar cell provided in the embodiments of the present application can increase the short-circuit current by 0.19 mA / cm 2 , and the cell efficiency by 0.13%.

[0147] In a second aspect, referring to the manufacturing process of Figures 6-8 and combining the structural schematic diagram of Figures 9-15 , the present application provides a preparation method of a solar cell, which can be used to manufacture the solar cell 1 in the first aspect. The preparation method specifically comprises the following steps:

[0148] S10: providing a semiconductor substrate 11. The semiconductor substrate 11 comprises a first surface 111 and a second surface 112 arranged oppositely. The semiconductor substrate 11 is provided with a plurality of passivation regions 11a and a plurality of passivation contact regions 11b, and the plurality of passivation regions 11a and the plurality of passivation contact regions 11b are alternately arranged along a first direction X. The first direction X is perpendicular to the thickness direction of the semiconductor substrate 11. The semiconductor substrate 11 can be an N-type silicon substrate. It can be understood that in this step, as shown in Figure 9 , the semiconductor substrate 11 can be first textured, and after the texturing is completed, as shown in Figure 10 , an alkali solution can be used to polish the second surface 112 of the semiconductor substrate 11. After polishing, the second surface 112 of the semiconductor substrate 11 is formed with a pit 16.

[0149] S20: Form a plurality of passivation contact structures 12 on the second surface 112. The plurality of passivation contact structures 12 correspond to the distribution of each passivation contact region 11b. The passivation contact structure 12 includes a conductive passivation layer 122.

[0150] S30: Form a dielectric layer 13 on the semiconductor substrate 11. The dielectric layer 13 at least covers the second surface 112 of the passivation region 11a. The material of the dielectric layer 13 can include one or more of silicon oxide, aluminum oxide, silicon oxynitride, and silicon nitride. Exemplarily, the dielectric layer 13 can be made by an ALD (Atomic Layer Deposition) method, so that the dielectric layer 13 can be embedded in the "fitting groove" between the passivation contact structure 12 and the non-contact surface 11222 described above.

[0151] S40: Form a plurality of first electrodes 14 on the plurality of passivation contact structures 12. Each passivation contact structure 12 is provided with at least one first electrode 14 away from one side of the semiconductor substrate 11.

[0152] The preparation method of the solar cell provided by the embodiment of the present application is equivalent to arranging the passivation contact structures 12 on the second surface 112 in a spaced manner. Compared with the traditional TOPCon cell, the second surface 112 of the passivation region 11a is not provided with the passivation contact structure 12, so that the coverage area of the passivation contact structure 12 on the second surface 112 can be reduced, thereby facilitating the reduction of the absorption of long-wave light by the passivation contact structure 12, increasing the absorption of current, and improving the cell efficiency.

[0153] In addition, compared with the related art 1, the solar cell 1 provided by the embodiment of the present application does not thin the thickness of the passivation contact structure 12 when the metal electrode is made, so that the metal paste is not easy to burn through the passivation contact structure 12, thereby not affecting the passivation effect. Compared with the related art 2, the solar cell 1 provided by the embodiment of the present application needs to remove all the material of the passivation contact structure 12 of the passivation region 11a in the preparation process, so that the process window is relatively large, the preparation difficulty is reduced, and the mass production is higher.

[0154] In one of the embodiments, referring to FIG. 2, S20: forming a plurality of passivation contact structures 12 on the second surface 112, specifically including the following steps: Figure 7

[0155] ​S21: Forming a tunneling material layer 21 and a conductive passivation material layer 22 on the second surface 112. Exemplarily, the tunneling material layer 21 can be made of a dielectric material, such as silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, magnesium fluoride, amorphous silicon, polysilicon, silicon carbide, titanium oxide, etc. The conductive passivation material layer 22 can be made of amorphous silicon, polysilicon, microcrystalline silicon, silicon carbide, etc. It can be understood that the tunneling material layer 21 and the conductive passivation material layer 22 can be prepared by ALD (Atomic Layer Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PEALD (Plasma Enhanced Atomic Layer Deposition), LPCVD (Low Pressure Chemical Vapor Deposition), etc. The structure after forming the tunneling material layer 21 and the conductive passivation material layer 22 is shown in FIG. 2B. Figure 11

[0156] S23: Forming a patterned mask layer 232 on the conductive passivation material layer 22. The structure after forming the patterned mask layer 232 is shown in FIG. 2C. The patterned mask layer 232 can be made of silicon oxide. Specifically, the surface of the conductive passivation material layer 22 can be processed by laser or etching to form the patterned mask layer 232. It should be noted that the oxide layer 231 can be formed simultaneously in the process of S21. Figure 13

[0157] S24: Removing the tunneling material layer 21 and the conductive passivation material layer 22 in the passivation region 11a to form a passivation contact structure 12. The structure after forming the passivation contact structure 12 is shown in FIG. 2D. Exemplarily, the above-mentioned film layers can be removed by a wet etching process. Figure 14

[0158] It should be noted that after removing the tunneling material layer 21 and the conductive passivation material layer 22 in the passivation region 11a, the semiconductor substrate 11 in the passivation region 11a can be polished by an alkaline solution, so that the depth of the second surface 112 of the passivation region 11a is deeper than the depth of the second surface 112 of the passivation contact region 11b. In the process of polishing, the inner diameter of most of the pits 16, or even all of the pits 16 in the passivation region 11a can be enlarged, and the depth of the pits 16 can be reduced, so as to facilitate reducing the roughness of the second surface 112 of the passivation region 11a.

[0159] In one of the embodiments, refer to FIG. 1A. Figure 7 ​​​As shown, after S21: forming the stacked tunneling material layer 21 and the conductive passivation material layer 22 on the second surface 112, before S23: forming the patterned mask layer 232 on the conductive passivation material layer 22, the method further comprises the following steps:

[0160] S22: performing heat treatment on the conductive passivation material layer 22 to form an initial diffusion layer 24. As shown, after the heat treatment, the initial diffusion layer 24 is formed in the semiconductor substrate 11. Figure 12

[0161] It should be noted that the conductive passivation material layer 22 formed in S21 can contain doped elements or not. When the conductive passivation material layer 22 contains doped elements, the heat treatment in S22 can activate the doped elements and further crystallize the conductive passivation material layer 22. Further, as shown, when the conductive passivation material layer 22 formed in S21 contains doped elements, after S21 is completed, an oxide layer 231 is formed on the surface of the conductive passivation material layer 22. Figure 11

[0162] When the conductive passivation material layer 22 does not contain doped elements, during the heat treatment in S22, a doping source can be introduced to diffuse doped elements into the conductive passivation material layer 22 and further crystallize the conductive passivation material layer 22.

[0163] In one embodiment, as shown, after S24: removing the tunneling material layer 21 and the conductive passivation material layer 22 in the passivation contact structure 12a to form the passivation contact structure 12, the method further comprises the following steps: Figure 7

[0164] S25: removing the initial diffusion layer 24 in the passivation contact structure 12a to form a first diffusion layer 15. Specifically, an alkaline solution can be used to polish the semiconductor substrate 11 to remove the initial diffusion layer 24 in the passivation contact structure 12a. It should be understood that the initial diffusion layer 24 in the passivation contact structure 12a can also not be removed.

[0165] In one embodiment, as shown, after S20: forming a plurality of passivation contact structures 12 on the second surface 112, the method further comprises the following steps: Figure 8

[0166] ​​​​S201: Forming a tunneling material layer 21 and a conductive passivation material layer 22 on the second surface 112. The tunneling material layer 21 can be made of a dielectric material, such as silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, magnesium fluoride, amorphous silicon, polysilicon, silicon carbide, titanium oxide, etc. The conductive passivation material layer 22 can be an amorphous silicon layer. It can be understood that the tunneling material layer 21 and the conductive passivation material layer 22 can be prepared by ALD (Atomic Layer Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PEALD (Plasma Enhanced Atomic Layer Deposition), LPCVD (Low Pressure Chemical Vapor Deposition), etc. As shown in FIG. 2B, an oxide layer 231 can also be formed on the surface of the conductive passivation material layer 22 in this step. Figure 11

[0167] S202: Forming a patterned mask layer 232 on the conductive passivation material layer 22. The structure after forming the patterned mask layer 232 is shown in FIG. 2C. Specifically, the oxide layer 231 on the surface of the conductive passivation material layer 22 can be processed by laser or etching to form the patterned mask layer 232. Figure 13

[0168] S203: Performing a heat treatment on the conductive passivation material layer 22 to form an initial diffusion layer 24. It should be noted that a thin oxide film can be formed on the surface of the conductive passivation material layer 22 in the passivation region 11a in this step.

[0169] It should be noted that the conductive passivation material layer 22 formed in S201 can contain a doping element or not. When the conductive passivation material layer 22 contains a doping element, the heat treatment in S202 can activate the doping element and further crystallize the conductive passivation material layer 22. When the conductive passivation material layer 22 does not contain a doping element, a doping source can be introduced in the heat treatment in S203 to diffuse the doping element into the conductive passivation material layer 22 and further crystallize the conductive passivation material layer 22.

[0170] S204: Removing the tunneling material layer 21 and the conductive passivation material layer 22 in the passivation region 11a to form the passivation contact structure 12. The structure after forming the passivation contact structure 12 is shown in FIG. 2D. Figure 14 ​​The film layer can be removed by a wet etching process. It should be noted that, because of the thin oxide film on the surface of the conductive passivation material layer 22 of the passivation region 11a, the oxide film helps to control the rate of wet etching during the wet etching process, thereby improving the accuracy of the wet etching process.

[0171] S205: removing the initial diffusion layer 24 located in the passivation region 11a to form the first diffusion layer 15. Specifically, the semiconductor substrate 11 can be polished by using an alkaline solution to remove the initial diffusion layer 24 located in the passivation region 11a. It should be understood that the initial diffusion layer 24 located in the passivation region 11a can also not be removed.

[0172] In a third aspect, the embodiments of the present application provide a photovoltaic module, which comprises the solar cell in the first aspect.

[0173] The photovoltaic module comprises a plurality of solar cells, and the plurality of solar cells can be connected in series by using a solder strip, so that the electric energy generated by the single solar cell can be collected for subsequent transmission. Of course, the solar cells can be arranged at intervals, or can be stacked in a shingle form.

[0174] Further, the photovoltaic module further comprises an encapsulation layer and a cover plate. The encapsulation layer is used to cover the surface of the cell string, and the cover plate is used to cover the surface of the encapsulation layer away from the cell string. The solar cells are electrically connected in a whole piece or multiple pieces to form a plurality of cell strings, and the plurality of cell strings are electrically connected in series and / or parallel. Specifically, in some embodiments, the plurality of cell strings can be electrically connected by using a conductive strip. The encapsulation layer covers the surface of the solar cell. The encapsulation layer can be an organic encapsulation film such as an ethylene-vinyl acetate copolymer film, a polyethylene octene elastomer film, or a polyethylene terephthalate film. The cover plate can be a glass cover plate, a plastic cover plate, or a cover plate having a light transmission function.

[0175] It should be understood that, in the embodiments of the present application, at least one part of the steps in the drawings can comprise a plurality of steps or stages, which do not necessarily have to be executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least one part of other steps or stages.

[0176] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described, but as long as the combinations of the technical features do not contradict, they should be considered as within the scope of the present disclosure.

[0177] The above embodiments only express several implementation ways of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation to the patent scope of the application. It should be pointed out that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, which all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A solar cell, characterized by, The solar cell comprises: a semiconductor substrate comprising a first surface and a second surface arranged oppositely; a plurality of passivation regions and a plurality of passivation contact regions are arranged on the semiconductor substrate, the plurality of passivation regions and the plurality of passivation contact regions are arranged alternately along a first direction, and the first direction is perpendicular to a thickness direction of the semiconductor substrate; a plurality of passivation contact structures are arranged on the second surface and correspondingly distributed in the plurality of passivation contact regions, and the passivation contact structure comprises a conductive passivation layer; a dielectric layer at least covers the second surface of the passivation region; and a plurality of first electrodes, each passivation contact structure is provided with at least one first electrode on a side away from the semiconductor substrate; the second surface of the passivation region has a first distance from the first surface, and the second surface of the passivation contact region has a second distance from the first surface, and the second distance is greater than the first distance; the solar cell further comprises a plurality of first diffusion layers arranged in the semiconductor substrate, the plurality of first diffusion layers are correspondingly distributed in the plurality of passivation contact regions, and each first diffusion layer is connected to the second surface; the difference between the second distance and the first distance is greater than or equal to the size of the first diffusion layer along the thickness direction of the semiconductor substrate.

2. The solar cell according to claim 1, characterized in that, The difference between the second distance and the first distance is greater than 1 μm.

3. The solar cell of claim 1, wherein The second surface is a back light surface.

4. The solar cell of claim 1, wherein The roughness of the second surface of the passivation region is less than the roughness of the second surface of the passivation contact region.

5. The solar cell of claim 1, wherein The second surface is provided with a plurality of pits; the deepest pit in the passivation region is defined as a first pit, and the deepest pit in the passivation contact region is defined as a second pit; The depth of the first pit is less than the depth of the second pit.

6. The solar cell according to claim 5, characterized in that, The inner diameter of the first pit is greater than the inner diameter of the second pit.

7. The solar cell of claim 1, wherein In the direction from the second surface to the first surface, the size of the passivation contact structure along the first direction gradually decreases.

8. The solar cell of claim 7, wherein, The passivation contact structure further comprises a tunneling layer arranged between the conductive passivation layer and the semiconductor substrate; In the direction from the second surface to the first surface, the size of the conductive passivation layer along the first direction gradually decreases.

9. The solar cell of claim 8, wherein, Each passivation contact structure is provided with one first electrode; the side surface of the conductive passivation layer close to the tunneling layer is a first surface, and the side surface of the conductive passivation layer away from the tunneling layer is a second surface; The size of the first surface along the first direction, the size of the second surface along the first direction, and the size of the first electrode along the first direction satisfy the following relationship: wherein W1 is the size of the first surface along the first direction, W2 is the size of the second surface along the first direction, and W3 is the size of the first electrode along the first direction.

10. The solar cell of claim 1, wherein, The dielectric layer further covers the side surface of the passivation contact structure away from the semiconductor substrate.

11. The solar cell of claim 10, wherein, The second surface of the semiconductor substrate comprises a first sub-surface, a second sub-surface and a connecting surface; the first sub-surface is located in the passivation region, the second sub-surface is located in the passivation contact region, and the connecting surface connects the first sub-surface and the second sub-surface; The dielectric layer also covers the connecting surface.

12. The solar cell of claim 11, wherein, The second sub-surface comprises a sub-contact surface and two non-contact surfaces, and the two non-contact surfaces are located on both sides of the sub-contact surface along the first direction; the passivation contact structure is in contact with the sub-contact surface; The dielectric layer also covers the non-contact surface.

13. The solar cell of claim 1, wherein, The dielectric layer comprises one or more of aluminum oxide, silicon nitride and silicon oxynitride.

14. The solar cell of claim 1, wherein, The conductive passivation layer comprises a doped polysilicon layer, and the doped polysilicon layer is doped with N-type or P-type doping elements.

15. The solar cell of claim 14, wherein, The doped polysilicon layer is also doped with one or more of carbon, nitrogen and oxygen.

16. The solar cell of claim 14, wherein, The conductive passivation layer further comprises a silicon carbide layer, and the silicon carbide layer is located on the side of the doped polysilicon layer away from the semiconductor substrate.

17. The solar cell of claim 1, wherein, The first electrode comprises at least one of silver and aluminum.

18. A method for preparing a solar cell, characterized in that, Comprise: A semiconductor substrate is provided; the semiconductor substrate comprises a first surface and a second surface arranged oppositely; A plurality of passivation regions and a plurality of passivation contact regions are arranged on the semiconductor substrate, and the plurality of passivation regions and the plurality of passivation contact regions are arranged alternately along a first direction; the first direction is perpendicular to the thickness direction of the semiconductor substrate; A plurality of passivation contact structures are formed on the second surface; wherein the plurality of passivation contact structures are distributed correspondingly in each passivation contact region; the passivation contact structure comprises a conductive passivation layer; A dielectric layer is formed on the semiconductor substrate; the dielectric layer at least covers the second surface located in the passivation region; A plurality of first electrodes are formed on the plurality of passivation contact structures; at least one first electrode is arranged on the side of each passivation contact structure away from the semiconductor substrate.

19. The method of producing a solar cell according to claim 18, wherein The plurality of passivation contact structures formed on the second surface comprises: A layer of tunneling material and a layer of conductive passivation material are formed on the second surface in a stack; A patterned mask layer is formed on the conductive passivation material layer; The tunneling material layer and the conductive passivation material layer located in the passivation region are removed to form the passivation contact structure.

20. The method of producing a solar cell according to claim 19, wherein After the layer of tunneling material and the layer of conductive passivation material are formed on the second surface in a stack, before the patterned mask layer is formed on the conductive passivation material layer, the conductive passivation material layer is subjected to heat treatment to form an initial diffusion layer; or, after the patterned mask layer is formed on the conductive passivation material layer, before the tunneling material layer and the conductive passivation material layer located in the passivation region are removed to form the passivation contact structure, the conductive passivation material layer is subjected to heat treatment to form an initial diffusion layer; After the tunneling material layer and the conductive passivation material layer located in the passivation region are removed to form the passivation contact structure, the initial diffusion layer located in the passivation region is removed to form a first diffusion layer.

21. A photovoltaic module, characterized by, The solar cell comprises any one of claims 1-17.

Images