Liphome circuit

Abstract

The invention discloses a Liphome circuit. The Liphome circuit comprises a digital self-locking circuit, an analog circuit, a first digital operation circuit, a second digital operation circuit, a data latch circuit, a first output control circuit and a second output control circuit. The digital self-locking circuit is responsible for performing signal conditioning on the digital signal and the digital switch control quantity to obtain two conditioning signals. The first digital operation circuit completes digital calculation based on the conditioning signal and the digital signal to generate a first group of operation results. The analog circuit respectively conditions the digital signals and the analog switch control quantity, and the second digital operation circuit combines the signals to carry out digital operation so as to generate a second group of operation results. The data latch circuit performs state latching according to the two groups of operation results and outputs corresponding digital signals, and then the first output control circuit and the second output control circuit convert the received corresponding digital signals into corresponding driving signals. The invention provides a failure protection scheme which not only has state latching and circuit memory capabilities, but also meets a higher-level security guarantee requirement.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of automobile electronic safety control, and in particular to a Liphome circuit. BACKGROUND

[0002] A body domain controller is responsible for managing the control of multiple execution loads in a vehicle, coordinating various functions of the body electronic system, realizing centralized control and communication of light, door lock, wiper, air conditioner and other subsystems, and improving the intelligence and safety performance of the vehicle. In order to ensure that the key load can still maintain basic functions when the controller fails, a limp-home mode (Limp-home Mode, Liphome) circuit is introduced in the design.

[0003] The Liphome circuit for protecting the body domain controller will adopt different implementation schemes according to the safety requirements of different control functions in the design. For the main control circuit part, the Liphome circuit can effectively improve the fault tolerance of the system through perfect redundancy design and state detection mechanism, thereby supporting a higher functional safety level, which can reach ASILD at most.

[0004] And for auxiliary control circuits such as ignition lockout (Ignition Lockout, IGN lockout), wiper and low beam, the Liphome circuit adopts a relatively simplified single-fault protection mode, only provides input signal detection and output control functions, and lacks state latching and circuit memory capability, so its safety level can only reach ASIL B, and it is difficult to realize higher level safety protection within the cost range.

[0005] Therefore, how to improve the safety protection level of the Liphome circuit for the auxiliary control circuit while ensuring the low cost of the Liphome circuit is a technical problem that technicians in the field urgently need to solve. SUMMARY

[0006] Based on the above problems, the application provides a Liphome circuit which can provide a failure protection scheme that has both state latching and circuit memory capability and meets higher level safety protection requirements.

[0007] To solve the above problems, the technical scheme provided by the embodiments of the application is as follows:

[0008] A Liphome circuit, the circuit comprising: a digital self-locking circuit, an analog circuit, a first digital operation circuit, a second digital operation circuit, a data latching circuit, a first output control circuit and a second output control circuit.

[0009] An output end of the digital self-locking circuit is connected with an input end of the first digital operation circuit; an output end of the first digital operation circuit is connected with the data latching circuit; a first output end of the data latching circuit is connected with an input end of the first output control circuit; an output end of the analog circuit is connected with an input end of the second digital operation circuit; an output end of the second digital operation circuit is connected with the data latching circuit; a second output end of the data latching circuit is connected with an input end of the second output control circuit;

[0010] The digital self-locking circuit is configured to perform signal conditioning on a digital signal and a digital switch control quantity respectively to obtain a first digital conditioning signal and a second digital conditioning signal; the digital signal is subjected to logical operation by a microcontroller unit (MCU) on the digital switch control quantity;

[0011] The first digital operation circuit is configured to perform digital operation on the first digital conditioning signal and the second digital conditioning signal, and on the digital signal and the digital switch control quantity to obtain a first operation result signal group;

[0012] The analog circuit is configured to perform signal conditioning on the digital signal and an analog switch control quantity respectively to obtain a third digital conditioning signal and a fourth digital conditioning signal;

[0013] The second digital operation circuit is configured to perform digital operation on the third digital conditioning signal and the fourth digital conditioning signal, and on the digital signal and the analog switch control quantity to obtain a second operation result signal group;

[0014] The data latching circuit is configured to latch and output the first operation result signal group to obtain a first digital output signal, and to latch and output the second operation result signal group to obtain a second digital output signal;

[0015] The first output control circuit is configured to drive and adapt the first digital output signal to obtain a first high-side drive signal or a first low-side drive signal;

[0016] The second output control circuit is configured to drive and adapt the second digital output signal to obtain a second high-side drive signal or a second low-side drive signal.

[0017] In a possible implementation, the first digital operation circuit includes a first OR operation circuit and a second OR operation circuit; an output terminal of the first OR operation circuit is connected with a first data input terminal of the data latch circuit; an output terminal of the second OR operation circuit is connected with a first clock input terminal of the data latch circuit; the first data input terminal and the first clock input terminal of the data latch circuit have a clock-triggered latch corresponding relationship with the first output terminal; the first operation result signal group includes a first operation result signal and a second operation result signal;

[0018] The first OR operation circuit is configured to perform OR operation on the first digital conditioning signal and the second digital conditioning signal to obtain the first operation result signal.

[0019] The second OR operation circuit is configured to perform OR operation on the digital signal and the digital switch control quantity to obtain the second operation result signal.

[0020] In a possible implementation, the circuit further includes a voltage comparator; an output terminal of the voltage comparator is connected with an input terminal of the second digital operation circuit.

[0021] The voltage comparator is configured to perform comparison processing on the analog switch control quantity to obtain a digital comparison result.

[0022] In a possible implementation, the second digital operation circuit includes a third OR operation circuit and a fourth OR operation circuit; an input terminal of the third OR operation circuit is connected with the analog circuit; an output terminal of the third OR operation circuit is connected with a second data input terminal of the data latch circuit; one input terminal of the fourth OR operation circuit is connected with the voltage comparator; an output terminal of the fourth OR operation circuit is connected with a second clock input terminal of the data latch circuit; the second data input terminal and the second clock input terminal of the data latch circuit have a clock-triggered latch corresponding relationship with the second output terminal; the second operation result signal group includes a third operation result signal and a fourth operation result signal.

[0023] The third OR operation circuit is configured to perform OR operation on the third digital conditioning signal and a fourth digital conditioning signal to obtain the third operation result signal.

[0024] The fourth OR operation circuit is configured to perform OR operation on the digital signal and the digital comparison result to obtain the fourth operation result signal.

[0025] In a possible implementation, the data latch circuit is specifically configured to:

[0026] When the second operation result signal is a valid signal, the circuit is configured to latch the second operation result signal and the first operation result signal, and when the first operation result signal is a valid signal, the first operation result signal is transmitted to the first output terminal for output, otherwise the second operation result signal is transmitted to the first output terminal for output.

[0027] In a possible implementation, the data latch circuit is specifically configured to:

[0028] When the fourth operation result signal is a valid signal, the circuit is configured to latch the fourth operation result signal and the third operation result signal, and when the third operation result signal is a valid signal, the third operation result signal is transmitted to the second output terminal for output, otherwise the fourth operation result signal is transmitted to the second output terminal for output.

[0029] In a possible implementation, the data latch circuit includes a double D flip-flop unit composed of D flip-flops.

[0030] In a possible implementation, the circuit further includes a power conversion circuit, and the power conversion circuit is connected to each functional module in the Liphome circuit.

[0031] The power conversion circuit is configured to supply power to each functional module in the Liphome circuit when receiving a Liphome trigger signal.

[0032] In a possible implementation, the power conversion circuit is specifically configured to:

[0033] When receiving a Liphome trigger signal, the power conversion circuit is configured to receive a vehicle-mounted VBAT battery voltage, stabilize and filter the VBAT battery voltage to obtain a low-voltage direct current voltage, and supply power to each functional module in the Liphome circuit through the low-voltage direct current voltage.

[0034] In a possible implementation, the or operation circuit includes a diode or gate composed of two diodes.

[0035] Compared with the prior art, the present application has the following beneficial effects:

[0036] The application provides a Liphome circuit, which comprises a digital self-locking circuit, an analog circuit, a first digital operation circuit, a second digital operation circuit, a data latch circuit, a first output control circuit and a second output control circuit. The digital self-locking circuit is used for accurately processing a digital signal obtained by performing a logic operation on a digital switch control quantity by a microcontroller unit (MCU) and the digital switch control quantity based on the digital switch control quantity, to obtain a first digital processed signal and a second digital processed signal. Further, the first digital operation circuit is used for processing the above digital processed signal, the digital signal and the digital switch control quantity, to realize complex and flexible digital calculation and generate a first operation result signal group with high reliability. Meanwhile, the analog circuit is used for processing the digital signal and an analog switch control quantity, and the second digital operation circuit is used for performing operation on the digital and analog signals to output a second operation result signal group, so as to realize consideration and processing of diversified signals. The key data latch circuit is used for latching and outputting the above two groups of operation result signals respectively, to effectively compensate for the short board of lacking state memory in traditional circuit design, ensure stability and continuity of the signals, and thus greatly improve fault tolerance and self-recovery capability of the Liphome circuit. Finally, the first and second output control circuits are used for converting the latched digital output signal into corresponding high-side or low-side driving signals, to provide accurate and reliable control instructions for performing a load.

[0037] The application not only significantly improves the functional safety level and failure protection capability of the auxiliary control circuit, but also balances low cost and high safety performance, breaks through the technical bottleneck that the traditional Liphome circuit is difficult to balance cost and high-level safety protection, and effectively improves the intelligent management level and safety performance of the whole body domain controller. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0039] Figure 1 A structure diagram of a Liphome circuit provided by the embodiment of the present application;

[0040] Figure 2 Another structure diagram of a Liphome circuit provided by the embodiment of the present application;

[0041] Figure 3 A structure diagram of one operation circuit provided by the embodiment of the present application. DETAILED DESCRIPTION

[0042] To make the technical solutions provided by the embodiments of the present application easy to understand, the background art related to the embodiments of the present application will be described first.

[0043] The body domain controller (Body Domain Controller) is responsible for coordinating and managing multiple execution loads in the vehicle, realizing centralized control and communication of light, door lock, windshield wiper, air conditioner and other subsystems, thereby improving the intelligent level and safety performance of the whole vehicle. In order to ensure that the key functions can maintain basic operation even when the controller fails, a limp-home mode (Limp-home Mode, Liphome) circuit is introduced in the design.

[0044] According to the safety requirements of different control functions, the Liphome circuit adopts a differentiated design strategy. The main control circuit part improves the system fault tolerance through redundancy and state detection mechanism, and supports the highest ASIL D level of functional safety. The auxiliary control circuit, such as IGN lock, windshield wiper and low beam, adopts a simplified single-path protection scheme, only has input detection and output control functions, and lacks state latching and memory capability, so its safety level is usually limited to ASIL B, and it is difficult to achieve a higher safety level within the cost allowed range. In addition, the conventional Liphome circuit is only suitable for digital signal input and output control, and cannot realize the control requirements of analog signal and multi-path logic system.

[0045] To solve this problem, a Liphome circuit is provided in the embodiments of the present application, which realizes more perfect signal conditioning and processing capability by integrating digital self-locking circuit, analog circuit, double digital operation circuit, data latching circuit and double output control circuit. Specifically, the circuit uses a digital self-locking circuit to finely condition digital signals and digital switch control quantities, wherein the digital self-locking circuit is based on digital switch control quantities and obtained by MCU executing logic operation. The analog circuit is used to condition digital signals and analog switch control quantities respectively. Then the first and second digital operation circuits are used to finely condition multiple groups of digital and analog signals respectively, forming two groups of high-reliability operation results. Subsequently, the data latching circuit performs state latching and stable output based on these results, effectively overcoming the shortcoming of lacking memory and latching function in traditional design, and improving the fault tolerance and continuous operation capability of the system. Finally, the two output control circuits convert the latched signals into adaptive high-side or low-side drive signals, providing precise and reliable control instructions for vehicle execution loads. The Liphome circuit of the present application provides significant advantages in redundancy design, differentiated protection and system simplification, not only meeting the functional guarantee under high safety requirements, but also ensuring the continuous operation of key functions under the premise of cost control, improving the reliability and scalability of the system.

[0046] In addition, the Liphome circuit of the present application realizes efficient control of complex multi-path logic and analog signals through integration of digital and analog signal processing, multi-stage digital operation and state latching, and significantly improves the adaptability and reliability of the system.

[0047] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the Liphome circuit embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0048] Referring to Figure 1 , Figure 1 A structural diagram of a Liphome circuit provided by the embodiments of the present application is shown.

[0049] As Figure 1 shown, the circuit comprises a digital self-locking circuit 110, an analog circuit 120, a first digital operation circuit 130, a second digital operation circuit 140, a data latching circuit 150, a first output control circuit 160 and a second output control circuit 170.

[0050] The output end of the digital self-locking circuit 110 is connected with the input end of the first digital operation circuit 130; the output end of the first digital operation circuit 130 is connected with the data latching circuit 150; the first output end of the data latching circuit 150 is connected with the input end of the first output control circuit 160; the output end of the analog circuit 120 is connected with the input end of the second digital operation circuit 140; the output end of the second digital operation circuit 140 is connected with the data latching circuit 150; and the second output end of the data latching circuit 150 is connected with the input end of the second output control circuit 170.

[0051] The digital self-locking circuit 110 in the Liphome circuit first performs signal conditioning on the input digital signals and digital switch control quantities respectively to generate first and second digital conditioning signals, which ensures the quality and stability of the input signals and facilitates subsequent processing. Among them, the MCU performs logic operation on the digital switch control quantity based on the digital signals, which enhances the response capability of the system to complex control logic. Then, the first digital operation circuit 130 comprehensively utilizes the first and second digital conditioning signals, as well as the original digital signals and digital switch control quantities, to perform multi-dimensional digital calculation, and finally generates a first group of operation result signals, which provides accurate basis for subsequent state latching and output.

[0052] Meanwhile, the analog circuit 120 performs signal conditioning on the digital signal and the analog switch control quantity respectively, and converts them into third and fourth digital conditioning signals, so as to realize effective detection and preprocessing of the analog signal. The second digital operation circuit 140 obtains a second set of operation result signals through digital operation based on the two sets of conditioning signals, in combination with the digital signal and the analog switch control quantity, so as to ensure support for control requirements in the analog and digital mixed signal environment. The data latch circuit 150 completes state latching and stable output respectively based on the first and second sets of digital operation result signals, and obtains two stable digital output signals, thereby enhancing the fault tolerance of the system and the reliability of the output signal.

[0053] Finally, the first output control circuit 160 performs driving adaptation on the first digital output signal, and generates a first high-side driving signal (High Side Driver single) or a first low-side driving signal (Low Side Driver single) capable of driving a high-side or low-side load. Similarly, the second output control circuit 170 performs similar driving conversion on the second digital output signal, and outputs a second set of high-side or low-side driving signals.

[0054] In a possible implementation, the signal conditioning of the digital self-latching circuit 110 on the digital signal and the digital switch control quantity includes but is not limited to filtering and denoising (i.e., filtering out noise), clamping and limiting the signal level (i.e., limiting the level range), dividing and stabilizing the signal amplitude (i.e., stabilizing the signal amplitude), and buffering and amplifying the signal (i.e., enhancing the driving capability) to avoid transmission attenuation, etc.

[0055] In a possible implementation, the signal conditioning of the analog circuit 120 on the digital signal includes but is not limited to filtering and suppressing spurs (i.e., filtering out spurs), shaping the signal waveform to eliminate jitter (i.e., shaping and eliminating jitter), and clamping and adapting the signal level (i.e., adapting the target level).

[0056] In a possible implementation, the signal conditioning of the analog circuit 120 on the analog switch control quantity includes but is not limited to preamplification of weak signals (i.e., amplifying the signal amplitude), suppression of interference through a band-pass filter network (i.e., suppressing out-of-band interference), dividing and converting the signal level, and linear correction of the signal (i.e., correcting signal distortion) to compensate for distortion, etc.

[0057] In a possible implementation, the driving adaptation actions of the first output control circuit 160 and the second output control circuit 170 include but are not limited to dividing and adjusting the output level through a resistance network (i.e., adjusting the driving level), and filtering with a capacitor (i.e., stabilizing the output signal) to stabilize the output signal, so as to adapt the driving requirements of the load.

[0058] Through the organic combination of the modules, the Liphome circuit realizes comprehensive processing of digital and analog signals, multi-channel logic operation and precise and stable output control, significantly improving the functional flexibility and safety performance of the system.

[0059] Referring to Figure 2 , Figure 2 Another structure diagram of the Liphome circuit provided by the embodiment of the present application is shown in Figure 2 The first digital operation circuit 130 described in the embodiment includes a first OR operation circuit 131 and a second OR operation circuit 132, which work together to realize logic processing of digital signals.

[0060] Specifically, the first OR operation circuit 131 receives the first digital conditioning signal and the second digital conditioning signal processed by the digital self-locking circuit 110, and generates a first operation result signal through logic OR operation, which reflects the logic state when any of the two input signals is high, and helps to capture the active signal characteristics. At the same time, the second OR operation circuit 132 performs similar logic OR operation on the unconditioned digital signal and the digital switch control quantity, generating a second operation result signal, which focuses on the joint logic relationship of the original signal and the switch control quantity.

[0061] The two operation result signals together constitute a first operation result signal group, the output ends of which are respectively connected to different input ports of the data latch circuit 150: the output of the first OR operation circuit 131 is connected to the first data input end of the data latch circuit 150, and the output of the second OR operation circuit 132 is connected to the first clock pulse input end of the data latch circuit 150 as a clock pulse signal. Based on the clock-triggered correspondence relationship between the two input ends, the data latch circuit 150 realizes synchronous latching of the first operation result signal, that is, under the action of the clock pulse provided by the second OR operation circuit 132, the data latch circuit 150 can stably capture the output of the first OR operation circuit 131, thereby ensuring the timing correctness and data integrity in the signal processing process.

[0062] Through the above design, not only can the information of multiple digital signal sources be effectively integrated, but also the clock control mechanism can be used to avoid signal aliasing and loss, thereby improving the response speed and stability of the entire Liphome circuit in a complex digital logic environment. This structured logic operation combined with clock latching lays a solid foundation for subsequent signal processing and control output, making the processing of digital signals efficient, safe and reliable.

[0063] In a possible implementation, the Liphome circuit also integrates a voltage comparator 180, as shown in Figure 2As shown in the figure, the voltage comparator is marked as 180. The output of the voltage comparator 180 is directly connected to the input of the second digital arithmetic circuit 140, thereby passing the comparison result to the subsequent digital arithmetic module for processing.

[0064] Specifically, the voltage comparator 180 is mainly used for real-time monitoring and comparison of analog switch control quantities. By comparing its input voltage with a preset reference voltage, it realizes the function of determining the threshold of the analog signal. When the voltage of the analog switch control quantity exceeds or falls below the set reference value, the voltage comparator 180 outputs a corresponding digital comparison result signal. This digital signal can be effectively identified and processed by the second digital processing circuit 140.

[0065] By introducing voltage comparator 180, not only is the processing capability for analog signals expanded, but accurate conversion from analog to digital signals is also achieved. This allows analog switch control quantities to participate in digital logic operations, improving the flexibility and precision of the overall control circuit. Therefore, the close cooperation between voltage comparator 180 and the second digital arithmetic circuit 140 achieves seamless integration of analog and digital signals, providing a more complete and efficient signal processing solution for the Liphome circuit.

[0066] In one possible implementation, the second digital arithmetic circuit 140 includes a third OR operation circuit 141 and a fourth OR operation circuit 142. For example... Figure 2 As shown in the figure, the circuit marked 141 is the third OR operation circuit, while 142 represents the fourth OR operation circuit.

[0067] The input of the third OR operation circuit 141 is directly connected to the analog circuit 120. It receives the third and fourth digital conditioning signals output from the analog circuit 120, processes these two sets of signals through a logical OR operation, and generates the third operation result signal. This signal reflects the overall state of the analog signal after conditioning, which helps to capture the effective characteristics of the analog switch control quantity and related digital signals.

[0068] Meanwhile, one input of the fourth OR operation circuit 142 is connected to the voltage comparator 180 to receive its output digitized comparison result signal, while the other input is connected to the original digital signal. By performing a logical OR operation on these two signals, the fourth OR operation circuit 142 generates a fourth operation result signal, which combines the decision information from the comparison between the digital and analog signals, enriching the system's ability to determine the signal state. The output of this fourth operation result signal is further connected to the second clock pulse input of the data latch circuit 150, while the output of the third OR operation circuit 141 is connected to the second data input of the data latch circuit 150.

[0069] The data latch circuit 150 realizes synchronous capture and stable output of the third and fourth operation result signals based on the clock trigger latch relationship between the second data input end and the second clock pulse input end, ensuring that the second output end can obtain accurate and timely digital control signals. This structural design not only improves the data processing efficiency in the mixed environment of analog and digital signals, but also guarantees the timing consistency and anti-interference ability of the signals through the clock trigger mechanism. As can be seen, the second digital operation circuit 140, through the cooperative work of the third or operation circuit 141 and the fourth or operation circuit 142, organically fuses the analog signal conditioning result and the digital signal and voltage comparison result, significantly improving the response speed and control accuracy of the Liphome system in complex application scenarios.

[0070] In a possible implementation, the data latch circuit 150 undertakes the key functions of data synchronization and selection output, and its working mechanism is based on the effectiveness judgment and timing control of the first operation result signal and the second operation result signal. The data latch circuit 150 is specifically used for:

[0071] When the second operation result signal is in the effective state, the data latch circuit 150 will preferentially perform a latch operation on the second operation result signal and the first operation result signal at the same time, ensuring that the two groups of signals are stably saved at the same time for subsequent processing or decision-making. The latch process uses a clock trigger mechanism to ensure the accuracy and timing consistency of signal capture, effectively avoiding data errors caused by interference or delay during signal transmission.

[0072] Subsequently, the data latch circuit 150 makes an output selection according to the effectiveness of the first operation result signal: if the first operation result signal is determined to be effective, it is directly transmitted to the first output end as the final output signal, thereby preferentially reflecting the calculation result of the first digital operation circuit 130; otherwise, if the first operation result signal is invalid, the previously latched second operation result signal is automatically switched and transmitted to the first output end for output. Through this logical judgment and switching mechanism, the data latch circuit 150 can dynamically respond to the state changes of different operation results, ensuring the continuity and correctness of the system output signal.

[0073] As can be seen, the data latch circuit 150 not only realizes efficient latching of multiple groups of digital operation results, but also has intelligent output selection capability, maximizing the adaptability and reliability of the Liphome system in complex signal environments. This design ensures that the system can flexibly allocate output resources when facing multiple source signal inputs, avoiding signal conflicts and false outputs, and improving the stable operation and application safety of the entire circuit.

[0074] In a possible implementation, the data latch circuit 150 also undertakes the core function of synchronously latching and intelligently outputting the third operation result signal and the fourth operation result signal, and the data latch circuit 150 is specifically configured to:

[0075] When it is detected that the fourth operation result signal is a valid signal, the data latch circuit 150 simultaneously performs latching operations on the fourth operation result signal and the third operation result signal, to ensure that the two groups of signals are stably saved at the same time, thereby guaranteeing that the subsequent processing link can obtain accurate and consistent data states. This latching process is usually based on a clock trigger mechanism, so that the signal capture has good timing synchronization and stability, effectively avoiding data errors caused by signal delay or interference.

[0076] Subsequently, the data latch circuit 150 makes an intelligent judgment according to the validity of the third operation result signal: if the third operation result signal is determined to be valid, the signal is preferentially transmitted to the second output end as the final output of the system, reflecting the comprehensive judgment result after analog and digital signal conditioning; if the third operation result signal is invalid, the system automatically switches, and the previously latched fourth operation result signal is transmitted to the second output end for output, ensuring that the output end always maintains meaningful control signals. Through this dynamic selection mechanism, the data latch circuit 150 realizes flexible management of multiple signals, enhancing the system's ability to cope with complex signal environments.

[0077] As can be seen, the data latch circuit 150 not only completes the key signal synchronous latching task, but also realizes intelligent priority output control through the validity discrimination of different operation results, greatly improving the reliability and stability of the Liphome system. This design ensures that in the application scenario of multiple signal input interlacing, the system can continuously output valid signals that meet actual needs, avoiding signal conflicts and misoperations, and providing a solid foundation for the entire control circuit.

[0078] In a possible implementation, the data latch circuit 150 includes a double-D flip-flop unit composed of a double-D flip-flop integrated device. The double-D flip-flop unit realizes synchronous sampling and hierarchical latching of multiple input signals through two independent and cooperative D flip-flops, thereby guaranteeing the stability and timing accuracy of the signals.

[0079] In the working process, the first D flip-flop receives the operation result signal from the operation circuit as the data input to be latched, while the second D flip-flop can be used to receive other related signals. The clock pulse signal drives the two flip-flops, so that they can accurately capture and latch the corresponding input signals at the clock active edge (for example, the rising edge).

[0080] In addition, if the output of the first D flip-flop is used as the clock or data input of the second D flip-flop to realize a two-stage latching structure, the anti-jitter and anti-interference capabilities of the signal can be further enhanced, achieving the effect of "second stabilization". This design effectively suppresses the occurrence of metastability and improves the reliability of the latch; at the same time, the double-D flip-flop unit ensures the timing consistency between multiple digital signals, avoiding the phenomenon of incorrect latching caused by transmission delay or noise.

[0081] As can be seen, the data latch circuit 150 constructed based on the double-D flip-flop integrated device not only has good timing capture capability and anti-interference performance, but also can flexibly manage multiple channel signals and achieve precise timing control, providing stable and non-jittered latch output for the system. This scheme provides a solid hardware foundation for signal processing and running stability of the Liphome circuit in complex environments, significantly improving the performance of the entire system.

[0082] In a possible implementation, the circuit further includes a power conversion circuit connected to each functional module in the Liphome circuit. The main function of the power conversion circuit is to provide stable and adaptive power supply for each functional module in the Liphome circuit when receiving the Liphome trigger signal, ensuring that each module can operate normally under the required voltage and current conditions. By reasonably designing the power conversion circuit, the power supply of different circuit parts can be effectively isolated, the influence of power noise on signal processing can be reduced, and the stability and reliability of the entire system can be improved. At the same time, the power conversion circuit can also realize power optimization and protection functions, ensuring that the system can maintain excellent performance in various working environments.

[0083] In a possible implementation, the power conversion circuit is specifically used for:

[0084] When receiving the Liphome trigger signal, the vehicle-mounted VBAT battery voltage is received, and the VBAT battery voltage is stabilized and filtered to obtain a stable low-voltage direct current voltage. Then, the low-voltage direct current voltage is used to provide reliable power supply for each functional module in the Liphome circuit. Through the voltage stabilization function, the power conversion circuit can effectively suppress the interference caused by the fluctuation of the battery voltage, ensuring that the downstream circuit obtains constant and clean voltage input; and the filtering operation further reduces the high-frequency noise and peak signals in the power supply, thereby improving the power quality and working stability of the entire system. This design ensures that the data latch circuit 150 and the analog circuit 120 can stably and efficiently operate in a complex vehicle-mounted environment.

[0085] In a possible implementation, the or operation circuit includes a diode or gate composed of two diodes. As Figure 3As shown, the diode or gate realizes the logical "or" operation function of the input signals by connecting the two input signals to the respective diodes respectively, and connecting the other end of the diodes to the common output terminal.

[0086] When any one of the input signals is high, the high level is transmitted to the output terminal through the corresponding diode; only when all the input signals are low, the output terminal remains in the low level state. This structure realizes simple and efficient logical or operation by using the unidirectional conduction characteristic of the diode, and has the advantages of fast response speed, less occupation of hardware resources, etc.

[0087] It should be noted that the embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can be mutually referred to.

[0088] It should be understood that in the present application, "at least one" means one or more, and "multiple" means two or more. "And / or" is used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, "A and / or B" can represent three cases: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the front and rear associated objects. "At least one of the following" or similar expressions means any combination of these items, including single item or any combination of multiple items. For example, at least one of a, b or c, can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0089] It should also be noted that in this paper, relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, article or device. Without more limitations, the element defined by the statement "including a…" does not exclude the presence of another identical element in the process, article or device including the element.

Claims

1. A Liphome circuit, characterized by, The circuit comprises a digital self-locking circuit, an analog circuit, a first digital operation circuit, a second digital operation circuit, a data latch circuit, a first output control circuit and a second output control circuit; An output end of the digital self-locking circuit is connected with an input end of the first digital operation circuit; an output end of the first digital operation circuit is connected with the data latch circuit; a first output end of the data latch circuit is connected with an input end of the first output control circuit; an output end of the analog circuit is connected with an input end of the second digital operation circuit; an output end of the second digital operation circuit is connected with the data latch circuit; a second output end of the data latch circuit is connected with an input end of the second output control circuit; The digital self-locking circuit is used for signal conditioning of a digital signal and a digital switch control quantity respectively to obtain a first digital conditioning signal and a second digital conditioning signal; the digital signal is subjected to logical operation on the digital switch control quantity by a micro controller unit (MCU); The first digital operation circuit is used for digital operation on the first digital conditioning signal and the second digital conditioning signal, and on the digital signal and the digital switch control quantity to obtain a first operation result signal group; The analog circuit is used for signal conditioning of the digital signal and an analog switch control quantity respectively to obtain a third digital conditioning signal and a fourth digital conditioning signal; The second digital operation circuit is used for digital operation on the third digital conditioning signal and the fourth digital conditioning signal, and on the digital signal and the analog switch control quantity to obtain a second operation result signal group; The data latch circuit is used for latching and outputting based on the first operation result signal group to obtain a first digital output signal, and latching and outputting based on the second operation result signal group to obtain a second digital output signal; The first output control circuit is used for driving and adapting the first digital output signal to obtain a first high-side driving signal or a first low-side driving signal; The second output control circuit is used for driving and adapting the second digital output signal to obtain a second high-side driving signal or a second low-side driving signal.

2. The circuit of claim 1, wherein, The first digital operation circuit comprises a first OR operation circuit and a second OR operation circuit; an output end of the first OR operation circuit is connected with a first data input end of the data latch circuit; an output end of the second OR operation circuit is connected with a first clock pulse input end of the data latch circuit; wherein the first data input end and the first clock pulse input end of the data latch circuit have a clock-triggered latching corresponding relationship with the first output end; the first operation result signal group comprises a first operation result signal and a second operation result signal; The first OR operation circuit is used for OR operation on the first digital conditioning signal and the second digital conditioning signal to obtain the first operation result signal; The second OR operation circuit is used for OR operation on the digital signal and the digital switch control quantity to obtain the second operation result signal.

3. The circuit of claim 1, wherein, The circuit further comprises a voltage comparator; an output terminal of the voltage comparator is connected with an input terminal of the second digital operation circuit; The voltage comparator is used for comparing and processing the analog switch control quantity to obtain a digital comparison result.

4. The circuit of claim 3, wherein, The second digital operation circuit comprises a third OR operation circuit and a fourth OR operation circuit; an input terminal of the third OR operation circuit is connected with the analog circuit; an output terminal of the third OR operation circuit is connected with a second data input terminal of the data latch circuit; one input terminal of the fourth OR operation circuit is connected with the voltage comparator; an output terminal of the fourth OR operation circuit is connected with a second clock pulse input terminal of the data latch circuit; wherein the second data input terminal and the second clock pulse input terminal of the data latch circuit have a clock triggered latch corresponding relationship; the second operation result signal group comprises a third operation result signal and a fourth operation result signal; The third OR operation circuit is used for performing OR operation on the third digital conditioning signal and the fourth digital conditioning signal to obtain the third operation result signal; The fourth OR operation circuit is used for performing OR operation on the digital signal and the digital comparison result to obtain the fourth operation result signal.

5. The circuit of claim 2, wherein, The data latch circuit is specifically used for: When the second operation result signal is a valid signal, the data latch circuit is used for latching the second operation result signal and the first operation result signal, and when the first operation result signal is a valid signal, the first operation result signal is transmitted to the first output terminal for output, otherwise the second operation result signal is transmitted to the first output terminal for output.

6. The circuit of claim 4, wherein, The data latch circuit is specifically used for: When the fourth operation result signal is a valid signal, the data latch circuit is used for latching the fourth operation result signal and the third operation result signal, and if the third operation result signal is a valid signal, the third operation result signal is transmitted to the second output terminal for output, otherwise the fourth operation result signal is transmitted to the second output terminal for output.

7. The circuit of claim 1, 2, 4, 5, or 6, wherein, The data latch circuit comprises a double D flip-flop unit composed of D flip-flops.

8. The circuit of claim 1, wherein, The circuit further comprises a power conversion circuit; the power conversion circuit is connected with each functional module in the Liphome circuit respectively; The power conversion circuit is used for supplying power for each functional module in the Liphome circuit when receiving a Liphome trigger signal.

9. The circuit of claim 8, wherein, The power conversion circuit is specifically used for: When receiving a Liphome trigger signal, receiving a vehicle-mounted VBAT battery voltage, stabilizing and filtering the VBAT battery voltage to obtain a low-voltage direct current voltage, and supplying power for each functional module in the Liphome circuit through the low-voltage direct current voltage.

10. The circuit of claim 1 or 4, wherein, The OR operation circuit comprises a diode OR gate composed of two diodes.

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