An instruction processing method, apparatus, electronic device, and readable storage medium

Abstract

This application provides an instruction processing method, apparatus, electronic device, and readable storage medium. After the instruction renaming stage, the source logic register number corresponding to the consumer instruction is determined. Based on the source logic register number, the source logic register storage structure is queried to determine whether the producer instruction corresponding to the source logic register number has been renamed within a preset period. If the producer instruction corresponding to the source logic register number has been renamed within the preset period, a target control signal is generated to prevent early wake-up operations during the instruction dispatch stage, and the instruction state of the consumer instruction is determined to be in an unready state. The consumer instruction is then stored in the issue queue according to the determined instruction state. This reduces the query operations on hardware units, reduces power consumption waste during processor processing, and thus improves the processor's energy efficiency and processing efficiency.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an instruction processing method, apparatus, electronic device, and readable storage medium. Background Technology

[0002] During instruction processing, to dynamically adjust the instruction execution order and improve performance, the processor may use out-of-order execution to process multiple instructions. Instructions are executed based on their data readiness state rather than the original program order, thereby improving circuit utilization and reducing pipeline congestion. A simplified out-of-order execution pipeline flow for a processor can be: fetch -> decode -> register renaming -> dispatch -> execute -> write back -> commit. In the dispatch stage, different instructions can be assigned to an issue queue, allowing the instructions in the queue to be processed sequentially, thus completing the entire processing flow.

[0003] In existing technologies, to maximize instruction issue bandwidth, instructions typically undergo an "early wake-up" operation during the dispatch phase before entering the issue queue. This operation aims to determine in advance whether the source operands of the instruction are ready, thereby determining its initial state after entering the issue queue. During the lookup process, each instruction needs to perform a hardware lookup. With a large number of instructions, this can easily lead to a significant amount of unnecessary and redundant power consumption, resulting in low processor energy efficiency and impacting processor processing efficiency. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide an instruction processing method, apparatus, electronic device, and readable storage medium that can query the source logic register storage structure according to the source logic register number corresponding to the consumer instruction after the instruction renaming stage is completed. For consumer instructions whose producer instructions corresponding to the source logic register number have been renamed within a preset period, the early wake-up operation will no longer be performed, which can reduce the query operation of hardware units, reduce power consumption waste during processor processing, and thus improve the processor's energy efficiency ratio and processing efficiency.

[0005] In a first aspect, embodiments of this application provide an instruction processing method applied to a server; the instruction processing method includes:

[0006] After the instruction renaming phase is completed, the source logic register number corresponding to the consumer instruction is determined;

[0007] Based on the source logic register number, query the source logic register storage structure to determine whether the producer instruction corresponding to the source logic register number has been renamed within a preset period;

[0008] If the producer instruction corresponding to the source logic register number is renamed within a preset period, a target control signal is generated to control the early wake-up operation not to be performed during the instruction dispatch stage, and the instruction status of the consumer instruction is determined to be in an unready state.

[0009] The control consumer commands are entered into the launch queue according to the determined command status.

[0010] In one possible implementation, the source logic register storage structure includes a preceding producer prediction table; the producer instruction corresponding to the source logic register number is renamed within a preset period through the following steps:

[0011] Based on the source logical register number, the index determines whether the corresponding logical register in the preceding producer dependency local vector of the preceding producer prediction table is pulled high; wherein, the logical register is pulled high when the position corresponding to the logical register in the preceding producer dependency local vector is assigned a value of 1;

[0012] If the corresponding logic register is pulled high, the producer instruction corresponding to the source logic register number is renamed within a preset period.

[0013] In one possible implementation, the instruction processing method further includes:

[0014] Construct an initial producer prediction table; the initial producer prediction table includes at least one entry, and each entry corresponds to at least one bit;

[0015] Obtain at least one producer instruction within a preset period, and determine the destination logic register and delay period information corresponding to the producer instruction;

[0016] For each producer instruction, if the producer instruction is located within a preset period according to the corresponding delay period information, the corresponding bit of the destination logic register of the producer instruction is assigned a value of 1 in the initial producer prediction table;

[0017] After assigning values ​​to the corresponding bits in the initial producer prediction table based on the destination logic register corresponding to each producer instruction, the preceding producer prediction table is obtained.

[0018] In one possible implementation, the preceding producer dependency local vector is determined through the following steps:

[0019] Perform a bitwise OR operation on at least one bit corresponding to all entries in the preceding producer prediction table to obtain the preceding producer dependency local vector.

[0020] In one possible implementation, the instruction processing method further includes:

[0021] The source logic register storage structure is updated based on the destination logic register and delay period information of the consumer instruction.

[0022] In one possible implementation, the source logic register storage structure includes content-addressable memory; the producer instruction corresponding to the source logic register number is renamed within a preset period through the following steps:

[0023] Based on the source logical register number, compare it with the destination logical register number corresponding to at least one producer instruction stored in the content addressing memory, and detect whether there is a destination logical register number in the content addressing memory that is consistent with the source logical register number;

[0024] If a destination logical register number with the same source logical register number exists in the content-addressable memory, it is determined that the producer instruction corresponding to the source logical register number will be renamed within a preset period.

[0025] In one possible implementation, the source logic register storage structure includes a storage queue; the producer instruction corresponding to the source logic register number is renamed within a preset period through the following steps:

[0026] Based on the source logic register number, compare it with the destination logic register number corresponding to at least one producer instruction recorded in the storage queue, and detect whether there is a destination logic register number in the storage queue that matches the source logic register number;

[0027] If a destination logical register number that matches the source logical register number exists in the storage queue, it is determined that the producer instruction corresponding to the source logical register number will be renamed within a preset period.

[0028] Secondly, embodiments of this application also provide an instruction processing device applied to a server; the instruction processing device includes:

[0029] The register number determination module is used to determine the source logic register number corresponding to the consumer instruction after the instruction renaming stage is completed;

[0030] The storage structure query module is used to query the storage structure of the source logical register based on the source logical register number, and determine whether the producer instruction corresponding to the source logical register number has been renamed within a preset period.

[0031] The instruction status determination module is used to generate a target control signal if the producer instruction corresponding to the source logic register number is renamed within a preset period, so as to control the early wake-up operation not to be performed during the instruction dispatch stage through the target control signal, and to determine the instruction status of the consumer instruction as not ready.

[0032] Queue entry is used to control the consumer command to enter the launch queue according to the determined command state.

[0033] Thirdly, embodiments of this application also provide an electronic device, including: a processor, a storage medium, and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the machine-readable instructions to perform the steps of the instruction processing method as described in any of the first aspects.

[0034] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the instruction processing method as described in any of the first aspects.

[0035] The instruction processing method, apparatus, electronic device, and readable storage medium provided in this application, after the instruction renaming phase, determine the source logic register number corresponding to the consumer instruction; based on the source logic register number, query the source logic register storage structure to determine whether the producer instruction corresponding to the source logic register number has been renamed within a preset period; if the producer instruction corresponding to the source logic register number has been renamed within the preset period, generate a target control signal to control the instruction dispatch phase from performing an early wake-up operation, and determine the instruction state of the consumer instruction as not ready; store the consumer instruction in the issue queue according to the determined instruction state. In this way, after the instruction renaming phase ends, the source logic register storage structure can be queried based on the source logic register number corresponding to the consumer instruction. For consumer instructions whose producer instructions corresponding to the source logic register number have been renamed within the preset period, an early wake-up operation will no longer be performed, reducing query operations on hardware units, reducing power consumption waste during processor processing, and thereby improving the processor's energy efficiency ratio and processing efficiency.

[0036] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 A flowchart illustrating an instruction processing method provided in an embodiment of this application;

[0039] Figure 2 This is a schematic diagram of processor pipeline processing in the prior art provided in the embodiments of this application;

[0040] Figure 3 A schematic diagram of the preceding producer prediction table provided in the embodiments of this application;

[0041] Figure 4 This is a schematic diagram of the instruction processing flow provided in the embodiments of this application;

[0042] Figure 5 This is a schematic diagram of the structure of an instruction processing device provided in an embodiment of this application;

[0043] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. Based on the embodiments of this application, every other embodiment obtained by those skilled in the art without inventive effort falls within the scope of protection of this application.

[0045] First, the applicable scenarios for this application will be introduced. This application can be applied to the field of computer technology.

[0046] During instruction processing, to dynamically adjust the instruction execution order and improve performance, the processor may use out-of-order execution to process multiple instructions. Instructions are executed based on their data readiness state rather than the original program order, thereby improving circuit utilization and reducing pipeline congestion. A simplified out-of-order execution pipeline flow for a processor can be: fetch -> decode -> register renaming -> dispatch -> execute -> write back -> commit. In the dispatch stage, different instructions can be assigned to an issue queue, allowing the instructions in the queue to be processed sequentially, thus completing the entire processing flow.

[0047] In existing technologies, to maximize instruction issue bandwidth, instructions typically undergo an "early wake-up" operation during the dispatch phase before entering the issue queue. This operation aims to determine in advance whether the source operands of the instruction are ready, thus determining its initial state after entering the issue queue. During the lookup process, each instruction needs to perform a hardware lookup, regardless of the distance between the producer and consumer instructions. Each instruction must unconditionally execute the entire early wake-up lookup process during dispatch. Large, high-speed storage and comparison structures such as lookup result caches, bypass networks, and general-purpose registers trigger numerous transistor flips, generating significant dynamic power consumption. This easily leads to a large amount of unnecessary and redundant power waste, resulting in low processor energy efficiency and impacting processor processing efficiency.

[0048] Based on this, embodiments of this application provide an instruction processing method to reduce power consumption waste during processor processing, thereby improving the processor's energy efficiency ratio and processing efficiency.

[0049] Please see Figure 1 , Figure 1 This is a flowchart illustrating an instruction processing method provided in an embodiment of this application. Figure 1 As shown in the embodiments of this application, the instruction processing method includes:

[0050] S101. After the instruction renaming stage is completed, determine the source logic register number corresponding to the consumer instruction.

[0051] S102. Based on the source logic register number, query the source logic register storage structure to determine whether the producer instruction corresponding to the source logic register number has been renamed within a preset period.

[0052] S103. If the producer instruction corresponding to the source logic register number is renamed within a preset period, a target control signal is generated to control the early wake-up operation not to be performed during the instruction dispatch stage, and the instruction status of the consumer instruction is determined to be in an unready state.

[0053] S104. Control the consumer command to enter the launch queue according to the determined command state.

[0054] The instruction processing method provided in this application embodiment can query the source logic register storage structure according to the source logic register number corresponding to the consumer instruction after the instruction renaming stage ends. For consumer instructions whose producer instructions corresponding to the source logic register number have been renamed within a preset period, the early wake-up operation will no longer be performed. This can reduce the query operation of hardware units, reduce power consumption waste during processor processing, and thus improve the processor's energy efficiency ratio and processing efficiency.

[0055] The exemplary steps of the embodiments of this application are described below:

[0056] S101. After the instruction renaming stage is completed, determine the source logic register number corresponding to the consumer instruction.

[0057] In the embodiments of this application, during the processor's instruction processing, in order to dynamically adjust the instruction execution order to improve performance, multiple instructions are processed through out-of-order execution technology. The instructions are executed according to the data ready state rather than the original program order, thereby improving circuit utilization and reducing pipeline blockage.

[0058] Here, the simplified pipeline flow for out-of-order execution of the processor can be fetch -> decode -> register renaming -> dispatch -> execute -> write back -> commit; in the dispatch stage, different instructions can be dispatched to the issue queue so that the instructions in the queue can be processed in order through the issue queue, thereby completing the entire processing flow.

[0059] In existing technologies, to maximize instruction issuance bandwidth, instructions typically undergo an "early wake-up" operation during the dispatch phase before entering the issuance queue. The purpose of this operation is to determine in advance whether the source operands of the instruction are ready, thereby determining its initial state after entering the issuance queue; for example, please refer to... Figure 2 , Figure 2 This is a schematic diagram of processor pipeline processing in the prior art provided in the embodiments of this application, such as... Figure 2As shown, after a micro-operation of an instruction completes register renaming, it enters the instruction dispatch stage from the register renaming stage. In the instruction dispatch stage, the early wake-up logic needs to determine whether the source operands (src0, src1) of the instruction are ready. It initiates parallel query requests to multiple hardware units (main result cache, bypass network, and general-purpose register status table) through logic circuits to cover all possible locations where operands may exist. The dispatch logic determines the state when the instruction enters the issue queue based on these query results. In the above query process, each instruction needs to perform a hardware query process once. For instructions that are unlikely to have query results, it is easy to cause a lot of unnecessary and redundant power consumption waste, resulting in low processor energy efficiency and affecting the processor's processing efficiency.

[0060] Based on this, in this embodiment, after the instruction renaming stage ends, the source logic register storage structure can be queried according to the source logic register number corresponding to the consumer instruction. For consumer instructions whose producer instructions corresponding to the source logic register number have been renamed within a preset period, the early wake-up operation will no longer be performed, thereby reducing the query operation on the hardware unit, reducing power consumption waste during processor processing, and thus improving the processor's energy efficiency ratio and processing efficiency.

[0061] Here, during out-of-order execution, if one instruction needs the calculation result of another instruction, then this instruction can be called the consumer instruction, and the other instruction that provides the calculation result can be called the producer instruction.

[0062] In one possible implementation, the register renaming phase is the process of replacing all source (read) and destination (write) logical registers in the instruction with their corresponding physical registers. The destination logical register for the producer instruction is the same as the source logical register for the consumer instruction. Therefore, after determining that the instruction renaming phase for the consumer instruction has ended, the source logical register number corresponding to the consumer instruction can be determined. Then, the source logical register number can be used as an index to query the source logical register storage structure to determine whether the producer instruction corresponding to the source logical register number has been renamed within a preset period.

[0063] S102. Based on the source logic register number, query the source logic register storage structure to determine whether the producer instruction corresponding to the source logic register number has been renamed within a preset period.

[0064] Here, the source logic register storage structure is integrated into a data dependency locality prediction device hardware structure. By integrating the prediction device hardware structure after the processor register instruction renaming stage and before the instruction dispatch stage, the prediction is completed in advance.

[0065] In one possible implementation, the source logic register storage structure may include a preceding producer prediction table. By indexing the preceding producer dependency local vector in the preceding producer prediction table through the source logic register number, it can be determined that the producer instruction corresponding to the source logic register number is renamed within a preset period.

[0066] Specifically, the following steps are used to determine that the producer instruction corresponding to the source logic register number is renamed within a preset period:

[0067] a1: Based on the source logic register number, index whether the logic register corresponding to the preceding producer dependency local vector in the preceding producer prediction table is pulled high; wherein, the logic register is pulled high when the position corresponding to the logic register in the preceding producer dependency local vector is assigned a value of 1.

[0068] a2: If the corresponding logic register is pulled high, the producer instruction corresponding to the source logic register number is renamed within a preset period.

[0069] In one possible implementation, the preceding producer prediction table is a low-overhead data structure that records information about producer instructions within a preset period. The preceding producer prediction table can be constructed based on the preset number of periods and the number of processor logic registers.

[0070] Specifically, the instruction processing method further includes:

[0071] c1: Construct an initial producer prediction table; the initial producer prediction table includes at least one entry, and each entry corresponds to at least one bit.

[0072] c2: Obtain at least one producer instruction within a preset period, and determine the destination logic register and delay period information corresponding to the producer instruction.

[0073] c3: For each producer instruction, if the producer instruction is located within a preset period according to the corresponding delay period information, the corresponding bit of the destination logic register of the producer instruction is assigned a value of 1 in the initial producer prediction table.

[0074] c4: After assigning values ​​to the corresponding bits in the initial producer prediction table based on the destination logic register corresponding to each producer instruction, the preceding producer prediction table is obtained.

[0075] Here, the time window of the initial producer prediction table can be set according to the specific processing requirements of the processor. For example, if it is determined that the producer information that has been renamed for 1-3 cycles needs to be recorded, then the initial producer prediction table can include 3 entries, each corresponding to a different cycle, indicating that the corresponding subsequent consumer instructions need to be delayed for the corresponding cycle to wake up.

[0076] Here, the number of bits corresponding to each entry can be determined according to the CPU's instruction set architecture. For example, the x86 architecture has 8 general-purpose logic registers, so each entry corresponds to eight bits; the ARM64 architecture has 32 general-purpose logic registers, so each entry corresponds to thirty-two bits.

[0077] In one possible implementation, the initial producer prediction table may only cover integer registers or floating-point registers, further simplifying the number of data queries in the prediction table and further improving processor processing efficiency.

[0078] Furthermore, after determining the initial producer prediction table, the assignment result of the corresponding bit can be determined based on whether the destination logic register corresponding to each producer instruction is renamed within a preset period. Specifically, if the producer instruction indicates that it is within the preset period according to the corresponding delay period information, the bit corresponding to the destination logic register of the producer instruction in the initial producer prediction table is assigned a value of 1; if the producer instruction indicates that it is not within the preset period according to the corresponding delay period information, the bit corresponding to the destination logic register of the producer instruction in the initial producer prediction table is assigned a value of 0.

[0079] For example, if it is determined that producer instruction A needs to be delayed by two cycles, and the bit corresponding to the destination logic register where producer instruction A is located is 30, then the 30th bit in entry 2 of the initial producer prediction table needs to be assigned the value 1.

[0080] After assigning values ​​to the corresponding bits in the initial producer prediction table according to the destination logic register of each producer instruction, the preceding producer prediction table is obtained.

[0081] In one possible implementation, after assigning values ​​to the corresponding bits in the initial producer prediction table according to the destination logic register corresponding to each producer instruction, a bitwise OR operation can be performed on at least one bit corresponding to the table entry to obtain the preceding producer dependency local vector.

[0082] Specifically, the preceding producer dependency local vector is determined through the following steps:

[0083] d1: Perform a bitwise OR operation on at least one bit corresponding to all entries in the preceding producer prediction table to obtain the preceding producer dependency local vector.

[0084] In one possible implementation, the bitwise OR operation means that if at least one bit in each bit has a value of 1, then the value at the corresponding position in the preceding producer-dependent local vector is 1.

[0085] For example, in the above example, if the bit corresponding to the destination logic register where producer instruction A is located is 30, then the 30th bit in entry 2 of the initial producer prediction table needs to be assigned the value 1. After bitwise OR operation, the 30th bit in the preceding producer dependency local vector is assigned the value 1.

[0086] For example, please refer to Figure 3 , Figure 3 A schematic diagram of the preceding producer prediction table provided in the embodiments of this application, as shown below. Figure 3 As shown, the preceding producer prediction table includes three entries, indicating that a delay of 1-3 cycles is required. Each entry corresponds to 32 bits, which are bits 0-31 respectively. After performing a bitwise OR operation on the three entries, a 32-bit preceding producer dependency local vector is obtained.

[0087] Furthermore, after determining the source logic register number corresponding to the consumer instruction, it is detected whether the logic register corresponding to the preceding producer dependency local vector in the preceding producer prediction table indexed by the source logic register number is pulled high. If the logic register is pulled high, it is determined that the producer instruction corresponding to the source logic register number is renamed within a preset period.

[0088] Here, pulling a logic register high usually means that its output level is forced to be set to a high level (logic 1), that is, the position in the preceding producer dependency local vector corresponding to the logic register is assigned a value of 1.

[0089] For example, in the above example, if the bit corresponding to the destination logic register where producer instruction A is located is 30, then the 30th bit in entry 2 of the initial producer prediction table needs to be set to 1. After the bitwise OR operation, the 30th bit in the preceding producer dependency local vector is set to 1. If consumer instruction C depends on the calculation result of producer instruction A, then the source logic register number corresponding to consumer instruction C is bit 30. After comparing it with the preceding producer dependency local vector, it is determined that the 30th bit in the preceding producer dependency local vector is set to 1. That is, the logic register corresponding to the preceding producer dependency local vector is pulled high, and the producer instruction corresponding to the source logic register number is renamed within a preset period.

[0090] In another possible implementation, the source logic register storage structure can also be a content-addressable memory. By searching in the content-addressable memory according to the source logic register number, it can be determined whether the producer instruction corresponding to the logic register number has been renamed within a preset period.

[0091] Specifically, the following steps are used to determine that the producer instruction corresponding to the source logic register number is renamed within a preset period:

[0092] e1: Based on the source logical register number, compare it with the destination logical register number corresponding to at least one producer instruction stored in the content-addressable memory, and detect whether there is a destination logical register number in the content-addressable memory that is consistent with the source logical register number.

[0093] e2: If a destination logical register number with the same number as the source logical register exists in the content addressing memory, determine that the producer instruction corresponding to the source logical register number is renamed within a preset period.

[0094] Here, Content Addressed Memory (CAM) is a type of memory that accesses data by storing content rather than physical addresses. CAM can store the destination logic register numbers corresponding to producer instructions that have been renamed within a preset period. As mentioned earlier, the destination logic register corresponding to the producer instruction is the same as the source logic register corresponding to the consumer instruction. The CAM can be queried based on the source logic register number and compared with the destination logic register number corresponding to at least one producer instruction stored in the CAM. If a destination logic register number that matches the source logic register number exists in the CAM, it is determined that the producer instruction corresponding to the source logic register number has been renamed within the preset period.

[0095] In another possible implementation, the source logic register storage structure can also be a storage queue. By searching in the storage queue according to the source logic register number, it can be determined whether the producer instruction corresponding to the logic register number has been renamed within a preset period.

[0096] Specifically, the following steps are used to determine that the producer instruction corresponding to the source logic register number is renamed within a preset period:

[0097] f1: Based on the source logic register number, compare it with the destination logic register number corresponding to at least one producer instruction recorded in the storage queue, and detect whether there is a destination logic register number in the storage queue that matches the source logic register number.

[0098] f2: If there is a destination logical register number in the storage queue that is consistent with the source logical register number, determine that the producer instruction corresponding to the source logical register number is renamed within a preset period.

[0099] In one possible implementation, a first-in-first-out (FIFO) storage queue can be used to record the destination logic register number corresponding to at least one producer instruction within a preset period. As mentioned earlier, the destination logic register corresponding to the producer instruction and the source logic register corresponding to the consumer instruction are the same. The source logic register number can be queried in the storage queue and compared with the destination logic register number corresponding to at least one producer instruction stored in the storage queue. If there is a destination logic register number in the storage queue that matches the source logic register number, it is determined that the producer instruction corresponding to the source logic register number has been renamed within the preset period.

[0100] Here, the very existence of a register in the queue implies that it is "recent," and its position in the queue reflects the time it was renamed. The earlier a destination logic register is in the storage queue, the further back in time its renaming occurred.

[0101] Furthermore, if the producer instruction corresponding to the source logic register number is renamed within a preset period, and the result of the producer instruction has not yet been generated, it is meaningless to query the calculation result of the producer instruction through the early wake-up operation. A target control signal needs to be generated so that the early wake-up operation can be skipped in the instruction dispatch stage and the instruction status of the consumer instruction can be determined as not ready.

[0102] S103. If the producer instruction corresponding to the source logic register number is renamed within a preset period, a target control signal is generated to control the early wake-up operation not to be performed during the instruction dispatch stage, and the instruction status of the consumer instruction is determined to be in an unready state.

[0103] In one possible implementation, the target control signal can be a high-level signal that disables the clock enable of the device that was woken up early. During the instruction dispatch phase, this enable signal is used to gate and disable the circuitry of the query result cache, bypass network, and general-purpose registers, thereby saving power.

[0104] In another possible implementation, if it is determined that the producer instruction corresponding to the source logic register number has not been renamed within a preset period, the result corresponding to the producer instruction may have already been generated. The calculation result of the producer instruction can be queried through an early wake-up operation, so that no target control signal is generated. In order to perform the early wake-up operation in the instruction dispatch stage, the target instruction status of the consumer instruction can be determined.

[0105] Specifically, after the step of "determining whether the producer instruction corresponding to the source logic register number has been renamed within a preset period", the instruction processing method further includes:

[0106] g1: If the producer instruction corresponding to the source logic register number is not renamed within a preset period, no target control signal is generated, and an early wake-up operation is performed during the instruction dispatch stage to determine the target instruction state of the consumer instruction; the target instruction state includes a ready state and a not ready state.

[0107] In one possible implementation, when the source logic register storage structure may include a preceding producer prediction table, if it is a source logic register number, the preceding producer dependency local vector in the preceding producer prediction table is indexed. If the logic register corresponding to the preceding producer dependency local vector in the preceding producer prediction table is not pulled high, it is determined that the producer instruction corresponding to the source logic register number has not been renamed within a preset period or there is no producer instruction prediction information. Therefore, no target control signal is generated to perform an early wake-up operation during the instruction dispatch stage to determine the target instruction state of the consumer instruction.

[0108] For example, if consumer instruction D depends on the calculation result of producer instruction B, then the source logic register number corresponding to consumer instruction D is bit 02. After comparing it with the previous producer dependency local vector, it is determined that bit 02 in the previous producer dependency local vector is assigned a value of 0. That is, the logic register corresponding to the previous producer dependency local vector has not been pulled high, and the producer instruction corresponding to the source logic register number has not been renamed within the preset period.

[0109] In another possible implementation, when the source logic register storage structure includes a content-addressable memory, the source logic register number is compared with the destination logic register number corresponding to at least one producer instruction stored in the content-addressable memory. If there is no destination logic register number in the content-addressable memory that matches the source logic register number, it is determined that the producer instruction corresponding to the source logic register number has not been renamed within a preset period or that there is no producer instruction prediction information. Therefore, no target control signal is generated to perform an early wake-up operation during the instruction dispatch stage to determine the target instruction state of the consumer instruction.

[0110] In another possible implementation, when the source logic register storage structure includes a storage queue, the source logic register number is compared with the destination logic register number corresponding to at least one producer instruction recorded in the storage queue. If there is no destination logic register number in the storage queue that matches the source logic register number, it is determined that the producer instruction corresponding to the source logic register number has not been renamed within a preset period or there is no producer instruction prediction information. Therefore, no target control signal is generated to perform an early wake-up operation during the instruction dispatch stage to determine the target instruction status of the consumer instruction.

[0111] Here, the early wake-up operation requires querying multiple hardware units through logic circuits to ensure coverage of all possible locations where the producer instruction's calculation result may exist. Specifically, it needs to query the main result cache to check whether the producer instruction's calculation result is the most recently calculated result that has not yet been written back to the register file; it also needs to query the bypass network to check whether the producer instruction's calculation result is being calculated by a functional unit further upstream of the current pipeline; and it also needs to query the general-purpose register status table or a similar structure to check whether the producer instruction's calculation result is in the physical register file and valid.

[0112] Furthermore, based on the query results during the early wake-up operation, the target instruction status of the consumer instruction can be determined. Specifically, if the calculation result of the corresponding producer instruction is found at any location in the main result cache, bypass network, or general-purpose register status table or similar structure, the target instruction status of the consumer instruction is determined to be in a ready state. If the calculation result of the corresponding producer instruction is not found at any location in the main result cache, bypass network, or general-purpose register status table or similar structure, the target instruction status of the consumer instruction is determined to be in a not-ready state, that is, it needs to wait for the producer's calculation result.

[0113] Furthermore, during the instruction dispatch phase, consumer instructions can be stored in the launch queue for subsequent processing.

[0114] S104. Control the consumer command to enter the launch queue according to the determined command state.

[0115] In one possible implementation, for consumer instructions that are in a ready state when entering the launch queue, the launch queue can process them directly without performing a wake-up operation; however, for consumer instructions that are in a not-ready state when entering the launch queue, the launch queue needs to perform subsequent operations on them based on the calculation result of the producer instruction. After determining that the calculation result of the producer instruction has been completed, the launch queue performs a wake-up operation on the consumer instruction and then performs subsequent processing.

[0116] Furthermore, after the query process is completed, the preceding producer prediction table can be updated.

[0117] Specifically, the instruction processing method further includes:

[0118] h1: Update the source logic register storage structure based on the destination logic register and delay period information of the consumer instruction.

[0119] In one possible implementation, when the source logic register storage structure is a preceding producer prediction table, if it is determined that the current consumer instruction is also the producer instruction of a subsequent instruction, the preceding producer prediction table can be updated based on the destination logic register and delay period information determined during the register renaming stage.

[0120] For example, if the current instruction is determined to be a 0-cycle instruction based on the delay cycle information, its calculation result can be used directly without waiting, and the preceding producer prediction table does not need to be updated; if the current instruction is determined to be a 1-cycle instruction based on the delay cycle information, the bit corresponding to its destination register is set to '1' in the first entry of the prediction table (representing 1 future cycle). This information will be automatically cleared by the shifter after 1 cycle; if the current instruction is determined to be a long-delay instruction based on the delay cycle information, such as a load instruction or an instruction with RAW dependency, the bit corresponding to its destination register is set to '1' in the second or third entry of the prediction table (representing 2 or 3 future cycles) based on its expected delay, providing a longer "non-essential lookup" prediction window.

[0121] Furthermore, if the source operand of an instruction hits the Nth entry of the prediction table, then the instruction itself, as a producer, will also pass on its "not ready" state. When updating in the next cycle, the update logic will also set its destination register in the (N-1)th entry of the prediction table, forming a prediction chain to ensure the accuracy of subsequent instruction processing.

[0122] In one possible implementation, as the processor cycle progresses, the data in the entries of the preceding producer prediction table is also updated automatically. Specifically, each cycle, entry n moves to entry n-1.

[0123] Here, if the processor experiences a pipeline flush, that is, clearing incomplete instructions and ensuring that the pipeline restarts the execution of new instructions, it is necessary to clear all data information recorded in the preceding producer prediction table so that the preceding producer prediction table can be re-determined based on the re-executed new instructions.

[0124] In another possible implementation, when the source logic register storage structure is content-addressable memory, if it is determined that the current consumer instruction is also the producer instruction of a subsequent instruction, the corresponding destination logic register can be stored in the content-addressable memory according to the destination logic register and delay period information determined in the register renaming stage, and the content-addressable memory can be updated.

[0125] In another possible implementation, when the source logic register storage structure is a storage queue, if it is determined that the current consumer instruction is also the producer instruction of a subsequent instruction, then the corresponding destination logic register can be stored in the storage queue according to the destination logic register and delay period information determined in the register renaming stage, and the storage queue can be updated.

[0126] The instruction processing procedure in the embodiments of this disclosure will be illustrated below through specific examples:

[0127] Please see Figure 4 , Figure 4 This is a schematic diagram of the instruction processing flow provided in the embodiments of this application, such as... Figure 4 As shown, after instruction decoding is completed, the register renaming stage begins, followed by prediction in the integrated data dependency locality prediction device. Specifically, based on the source logic register number corresponding to the consumer instruction, the source logic register storage structure is queried to determine whether the producer instruction corresponding to the source logic register number has been renamed within a preset period. If it has been renamed, a clock gating signal is generated, and no early wake-up operation is performed during the instruction dispatch stage, controlling the consumer instruction to enter the issue queue. If it has not been renamed, an early wake-up operation is performed during the instruction dispatch stage, and after querying the result cache, bypass network, and general-purpose register status table, the consumer instruction is controlled to enter the issue queue.

[0128] Thus, in this embodiment, a very small prediction table (e.g., 3x31 bits) consumes significantly less power than the large lookup circuits described above. This invention utilizes this low-power prediction table to accurately identify premature wake-up queries that are "certainly doomed to fail" in scenarios with close data dependencies (i.e., producer and consumer instructions are close together). By clock-gating or disabling these high-power lookup circuits, this invention transforms the unconditional, continuous high-power operation of the prior art into a conditional, intermittent operation, thereby significantly reducing the processor's average dynamic power consumption and significantly improving its energy efficiency without affecting functionality. Prediction is performed after the register renaming stage, and since there is ample time between the register renaming stage and the instruction dispatch stage, it will not become a new bottleneck in the pipeline, thus not increasing instruction processing latency and not affecting processor efficiency.

[0129] The instruction processing method provided in this application, after the instruction renaming phase, determines the source logic register number corresponding to the consumer instruction; based on the source logic register number, queries the source logic register storage structure to determine whether the producer instruction corresponding to the source logic register number has been renamed within a preset period; if the producer instruction corresponding to the source logic register number has been renamed within the preset period, a target control signal is generated to control the instruction dispatch phase from performing an early wake-up operation, and the instruction state of the consumer instruction is determined to be in an unready state; the consumer instruction is stored in the issue queue according to the determined instruction state. In this way, after the instruction renaming phase ends, the source logic register storage structure can be queried based on the source logic register number corresponding to the consumer instruction. For consumer instructions whose producer instructions corresponding to the source logic register number have been renamed within the preset period, an early wake-up operation will no longer be performed, reducing the query operations on hardware units, reducing power consumption waste during processor processing, and thus improving the processor's energy efficiency and processing efficiency.

[0130] Based on the same inventive concept, this application also provides an instruction processing device corresponding to the instruction processing method. Since the principle of the device in this application to solve the problem is similar to the instruction processing method described above in this application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0131] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of an instruction processing device provided in an embodiment of this application. Figure 5 As shown, the instruction processing device 500 includes:

[0132] Register number determination module 510 is used to determine the source logic register number corresponding to the consumer instruction after the instruction renaming stage is completed;

[0133] The storage structure query module 520 is used to query the storage structure of the source logical register based on the source logical register number, and determine whether the producer instruction corresponding to the source logical register number has been renamed within a preset period.

[0134] The instruction status determination module 530 is used to generate a target control signal if the producer instruction corresponding to the source logic register number is renamed within a preset period, so as to control the early wake-up operation not to be performed in the instruction dispatch stage through the target control signal, and to determine the instruction status of the consumer instruction as not ready.

[0135] The queue entry module 540 is used to control the consumer instruction to enter the launch queue according to a determined instruction state.

[0136] In one possible implementation, the source logic register storage structure includes a preceding producer prediction table; the storage structure query module 520 is used to determine, through the following steps, that the producer instruction corresponding to the source logic register number is renamed within a preset period:

[0137] Based on the source logical register number, the index determines whether the corresponding logical register in the preceding producer dependency local vector of the preceding producer prediction table is pulled high; wherein, the logical register is pulled high when the position corresponding to the logical register in the preceding producer dependency local vector is assigned a value of 1;

[0138] If the corresponding logic register is pulled high, the producer instruction corresponding to the source logic register number is renamed within a preset period.

[0139] In one possible implementation, the instruction processing apparatus 500 further includes a preceding producer prediction table construction module (not shown in the figure), the preceding producer prediction table construction module being used for:

[0140] Construct an initial producer prediction table; the initial producer prediction table includes at least one entry, and each entry corresponds to at least one bit;

[0141] Obtain at least one producer instruction within a preset period, and determine the destination logic register and delay period information corresponding to the producer instruction;

[0142] For each producer instruction, if the producer instruction is located within a preset period according to the corresponding delay period information, the corresponding bit of the destination logic register of the producer instruction is assigned a value of 1 in the initial producer prediction table;

[0143] After assigning values ​​to the corresponding bits in the initial producer prediction table based on the destination logic register corresponding to each producer instruction, the preceding producer prediction table is obtained.

[0144] In one possible implementation, the preceding producer prediction table construction module is used to determine the preceding producer dependency local vector through the following steps:

[0145] Perform a bitwise OR operation on at least one bit corresponding to all entries in the preceding producer prediction table to obtain the preceding producer dependency local vector.

[0146] In one possible implementation, the instruction processing apparatus 500 further includes a source logic register storage structure update module (not shown in the figure), the source logic register storage structure update module being used for:

[0147] The source logic register storage structure is updated based on the destination logic register and delay period information of the consumer instruction.

[0148] In one possible implementation, the source logic register storage structure includes a content-addressable memory; the storage structure query module 520 is used to determine, through the following steps, that the producer instruction corresponding to the source logic register number has been renamed within a preset period:

[0149] Based on the source logical register number, compare it with the destination logical register number corresponding to at least one producer instruction stored in the content addressing memory, and detect whether there is a destination logical register number in the content addressing memory that is consistent with the source logical register number;

[0150] If a destination logical register number with the same source logical register number exists in the content-addressable memory, it is determined that the producer instruction corresponding to the source logical register number will be renamed within a preset period.

[0151] In one possible implementation, the source logic register storage structure includes a storage queue; the storage structure query module 520 is used to determine, through the following steps, that the producer instruction corresponding to the source logic register number has been renamed within a preset period:

[0152] Based on the source logic register number, compare it with the destination logic register number corresponding to at least one producer instruction recorded in the storage queue, and detect whether there is a destination logic register number in the storage queue that matches the source logic register number;

[0153] If a destination logical register number that matches the source logical register number exists in the storage queue, it is determined that the producer instruction corresponding to the source logical register number will be renamed within a preset period.

[0154] In one possible implementation, the instruction processing device 500 further includes an early wake-up operation determination module (not shown in the figure), the early wake-up operation determination module being used for:

[0155] If the producer instruction corresponding to the source logic register number is not renamed within a preset period, no target control signal is generated, and an early wake-up operation is performed during the instruction dispatch stage to determine the target instruction state of the consumer instruction; the target instruction state includes a ready state and a not ready state.

[0156] The instruction processing apparatus provided in this application, after the instruction renaming phase, determines the source logic register number corresponding to the consumer instruction; based on the source logic register number, it queries the source logic register storage structure to determine whether the producer instruction corresponding to the source logic register number has been renamed within a preset period; if the producer instruction corresponding to the source logic register number has been renamed within the preset period, a target control signal is generated to control the instruction dispatch phase from performing an early wake-up operation, and the instruction state of the consumer instruction is determined to be in an unready state; the consumer instruction is stored in the issue queue according to the determined instruction state. In this way, after the instruction renaming phase ends, the source logic register storage structure can be queried based on the source logic register number corresponding to the consumer instruction. For consumer instructions whose producer instructions corresponding to the source logic register number have been renamed within the preset period, an early wake-up operation will no longer be performed, reducing the query operations on hardware units, reducing power consumption waste during processor processing, and thereby improving the processor's energy efficiency ratio and processing efficiency.

[0157] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 6 As shown, the electronic device 600 includes a processor 610, a memory 620, and a bus 630.

[0158] The memory 620 stores machine-readable instructions executable by the processor 610. When the electronic device 600 is running, the processor 610 and the memory 620 communicate via the bus 630. When the machine-readable instructions are executed by the processor 610, they can perform the operations described above. Figure 1 The steps of the instruction processing method in the method embodiment shown are described in detail in the method embodiment, and will not be repeated here.

[0159] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can perform the above-described actions. Figure 1 The steps of the instruction processing method in the method embodiment shown are described in detail in the method embodiment, and will not be repeated here.

[0160] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0161] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0162] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0163] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0164] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0165] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An instruction processing method, characterized by, The application is applied to a server, and the instruction processing method comprises: After the instruction renaming stage ends, the source logical register number corresponding to the consumer instruction is determined; Based on the source logical register number, the source logical register storage structure is queried to determine whether the producer instruction corresponding to the source logical register number is renamed within a preset period; If the producer instruction corresponding to the source logical register number is renamed within the preset period, a target control signal is generated to control that the early wake-up operation is not performed in the instruction dispatch stage through the target control signal, and the instruction state of the consumer instruction is determined as an unready state; The consumer instruction is controlled to enter the emission queue according to the determined instruction state.

2. The instruction processing method of claim 1, wherein, The source logical register storage structure comprises a preceding producer prediction table; The producer instruction corresponding to the source logical register number is determined to be renamed within the preset period by the following steps: Based on the source logical register number, it is indexed whether the corresponding logical register in the preceding producer dependent local vector in the preceding producer prediction table is pulled high; wherein the logical register is pulled high, that is, the position corresponding to the logical register in the preceding producer dependent local vector is assigned as 1; If the corresponding logical register is pulled high, the producer instruction corresponding to the source logical register number is renamed within the preset period.

3. The instruction processing method of claim 2, wherein, The instruction processing method further comprises: An initial producer prediction table is constructed; the initial producer prediction table comprises at least one table item, and each table item corresponds to at least one bit; At least one producer instruction within a preset period is acquired, and the destination logical register and the delay period information corresponding to the producer instruction are determined; For each producer instruction, if the producer instruction is indicated to be located within the preset period according to the corresponding delay period information, the corresponding bit of the destination logical register of the producer instruction in the initial producer prediction table is assigned as 1; After the assignment of the corresponding bit of the destination logical register of each producer instruction to the initial producer prediction table ends, the preceding producer prediction table is obtained.

4. The instruction processing method of claim 3, wherein, The preceding producer dependent local vector is determined by the following steps: The at least one bit corresponding to all table items in the preceding producer prediction table is subjected to a bitwise OR operation to obtain the preceding producer dependent local vector.

5. The instruction processing method of claim 1, wherein, The instruction processing method further comprises: Based on the destination logical register and the delay period information of the consumer instruction, the source logical register storage structure is updated.

6. The instruction processing method of claim 1, wherein, The source logical register storage structure comprises a content addressable memory; The producer instruction corresponding to the source logical register number is determined to be renamed within the preset period by the following steps: Based on the source logical register number, the destination logical register number corresponding to at least one producer instruction stored in the content addressable memory is compared to detect whether there is a destination logical register number consistent with the source logical register number in the content addressable memory; If there is a destination logical register number consistent with the source logical register number in the content addressable memory, it is determined that the producer instruction corresponding to the source logical register number is renamed within a preset period.

7. The instruction processing method of claim 1, wherein, The source logical register storage structure includes a storage queue; the source logical register number corresponding to the producer instruction is determined to be renamed within a preset period by the following steps: Based on the source logical register number, the destination logical register number corresponding to at least one producer instruction recorded in the storage queue is compared to detect whether there is a destination logical register number consistent with the source logical register number in the storage queue; If there is a destination logical register number consistent with the source logical register number in the storage queue, it is determined that the producer instruction corresponding to the source logical register number is renamed within a preset period.

8. An instruction processing apparatus, characterized by, The application is applied to a server; the instruction processing device includes: A register number determination module is configured to determine the source logical register number corresponding to the consumer instruction after the end of the instruction renaming stage; A storage structure query module is configured to query the source logical register storage structure based on the source logical register number to determine whether the producer instruction corresponding to the source logical register number is renamed within a preset period; An instruction state determination module is configured to generate a target control signal to control that the advance wake-up operation is not performed in the instruction dispatch stage through the target control signal if the producer instruction corresponding to the source logical register number is renamed within a preset period, and determine the instruction state of the consumer instruction as an unready state; A queue entry is configured to control the consumer instruction to enter the launch queue according to the determined instruction state.

9. An electronic device, comprising: It includes: A processor, a memory and a bus, the memory stores machine readable instructions executable by the processor, when the electronic device is running, the processor and the memory communicate through the bus, the processor executes the machine readable instructions to execute the steps of the instruction processing method in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, which is executed by the processor to execute the steps of the instruction processing method in any one of claims 1 to 7.

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