A thread scheduling method and device, electronic equipment and storage medium

Abstract

This application provides a thread scheduling method, apparatus, electronic device, and storage medium, relating to the field of hardware testing technology. The specific solution is as follows: Obtaining the importance representation information of each target LLC to a target process, where the target LLC is the LLC occupied by threads running in the target process; determining the recommended LLC corresponding to the target process from the obtained importance representation information; in response to scheduling the target threads in the target process, determining the CPU core based on the load state of the CPU cores sharing the recommended LLC, and scheduling the target threads to the determined CPU cores for execution. Applying the solution provided in this application can improve the cache hit rate for scheduling threads in the same process to CPU cores sharing the same LLC and improve the operating efficiency of multi-core CPUs.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a thread scheduling method, apparatus, electronic device, and storage medium. Background Technology

[0002] To improve the performance of multi-core CPUs, current computer systems typically employ NUMA (Non-Uniform Memory Access) architecture to manage memory. In NUMA architecture, the computer system divides memory into multiple relatively independent memory units, each corresponding to a NUMA node. A NUMA node also includes one or more CPU cores and one or more LLC (Last-Level Cache). The CPU cores in a NUMA node are directly connected to the memory units, and some or all CPU cores share a single LLC.

[0003] In related technologies, when scheduling threads within a process, the CPU core is typically selected based on the principle of CPU core load balancing, and then the thread is scheduled to run on the selected CPU core. However, in a NUMA architecture, CPU cores may be distributed across different NUMA nodes, and the shared LLC may also be different. Therefore, when applying the above-mentioned technologies for thread scheduling, a low cache hit rate may occur. Summary of the Invention

[0004] The purpose of this application is to provide a thread scheduling method, apparatus, electronic device, and storage medium to improve the cache hit rate of scheduling threads in the same process to run on CPU cores sharing the same LLC, and to improve the operating efficiency of multi-core CPUs. The specific technical solution is as follows:

[0005] According to one aspect of the embodiments of this application, a thread scheduling method is provided, the method comprising:

[0006] Obtain the importance representation information of each target LLC to the target process, wherein the target LLC is: the LLC occupied by the thread in the target process during its execution;

[0007] Based on the obtained importance representation information, the recommended LLC corresponding to the target process is determined from the target LLCs;

[0008] In response to scheduling the target thread in the target process, based on the load status of the CPU cores sharing the recommended LLC, the CPU core is determined, and the target thread is scheduled to run on the determined CPU core.

[0009] In one embodiment of this application, obtaining the importance representation information of each target LLC to the target process includes:

[0010] The runtime of each thread in the target process on each target CPU core, wherein the target CPU core is the CPU core in which the threads in the target process run;

[0011] Based on the runtime of each thread on the target CPU core sharing the same target LLC, information representing the importance of each target LLC to the target process is obtained.

[0012] In one embodiment of this application, obtaining the importance representation information of each target LLC to the target process based on the runtime of each thread on the target CPU core sharing the same target LLC includes:

[0013] The runtime of each thread on the target CPU core sharing the same target LLC is summed to obtain the importance information of each target LLC to the target process;

[0014] or

[0015] Based on the runtime of each thread on the target CPU core sharing the same target LLC, the importance of each target LLC to each thread is represented by information; based on the importance of each target LLC to each thread, the importance of each target LLC to the target process is represented by information.

[0016] In one embodiment of this application, obtaining the importance representation information of each target LLC to each thread based on the runtime of each thread on the target CPU core sharing the same target LLC includes:

[0017] Based on the first additional information of the target CPU core, a first weight coefficient corresponding to the target CPU core is determined, wherein the first additional information includes at least one of the following: CPU core performance parameters, CPU core load status, and CPU core scheduling weight; based on the runtime of each thread in the target CPU core sharing the same target LLC and the first weight coefficient corresponding to the target CPU core, the importance representation information of each target LLC to each thread is obtained.

[0018] or

[0019] For each thread, the runtime of that thread on the target CPU core sharing the same target LLC is accumulated to obtain information representing the importance of each target LLC to that thread.

[0020] In one embodiment of this application, obtaining the importance representation information of each target LLC to the target process based on the importance representation information of each target LLC to each thread includes:

[0021] Based on the second additional information of each target LLC, a second weight coefficient corresponding to each target LLC is determined, wherein the second additional information includes at least one of the following: the load status of the target LLC, the weight of the target LLC, and the performance parameters of the CPU cores sharing the target LLC; according to the importance representation information of each target LLC to each thread and the second weight coefficient corresponding to each target LLC, the importance representation information of each target LLC to the target process is obtained.

[0022] or

[0023] The importance representation information of each target LLC to each thread is accumulated to obtain the importance representation information of each target LLC to the target process.

[0024] In one embodiment of this application, determining the recommended LLC corresponding to the target process from the target LLCs based on the obtained importance characterization information includes:

[0025] Based on the third additional information, recommended LLCs are determined from the target LLCs in descending order of importance represented by the acquired importance characterization information. The third additional information includes at least one of the following: the latest time when the thread in the target process occupies the target LLC, the load status of the target LLC, the cumulative number of times the thread in the target process occupies the target LLC, the target NUMA node to which the target LLC belongs, and the status of the target NUMA node.

[0026] In one embodiment of this application, the recommended LLC value is determined based on the ratio between the number of threads in the target process and the number of CPU cores in the LLC.

[0027] According to another aspect of the embodiments of this application, a thread scheduling apparatus is provided, the apparatus comprising:

[0028] The importance acquisition module is used to acquire the importance representation information of each target LLC to the target process, wherein the target LLC is: the LLC occupied by the thread in the target process during its execution;

[0029] A recommended cache determination module is used to determine the recommended LLC corresponding to the target process from the target LLCs based on the obtained importance representation information;

[0030] The thread scheduling module is used to schedule the target thread in the target process, determine the CPU core based on the load status of the CPU cores sharing the recommended LLC, and schedule the target thread to run on the determined CPU core.

[0031] In one embodiment of this application, the importance acquisition module includes:

[0032] The runtime timing unit is used to time the runtime of each thread in the target process on each target CPU core, wherein the target CPU core is the CPU core in which the threads in the target process run;

[0033] The importance acquisition unit is used to obtain the importance representation information of each target LLC to the target process based on the runtime of each thread on the target CPU core sharing the same target LLC.

[0034] In one embodiment of this application, the importance acquisition unit includes: a duration accumulation subunit, used to accumulate the runtime of each thread on the target CPU core sharing the same target LLC to obtain importance representation information of each target LLC to the target process; or an importance acquisition subunit, used to obtain importance representation information of each target LLC to each thread based on the runtime of each thread on the target CPU core sharing the same target LLC; and to obtain importance representation information of each target LLC to the target process based on the importance representation information of each target LLC to each thread.

[0035] In one embodiment of this application, the importance determination subunit is specifically used to determine a first weight coefficient corresponding to a target CPU core based on first additional information of the target CPU core, wherein the first additional information includes at least one of: CPU core performance parameters, CPU core load status, and CPU core scheduling weight; to obtain importance representation information of each target LLC to each thread based on the runtime of each thread on the target CPU core sharing the same target LLC and the first weight coefficient corresponding to the target CPU core; or, for each thread, to accumulate the runtime of the thread on the target CPU core sharing the same target LLC to obtain importance representation information of each target LLC to the thread.

[0036] In one embodiment of this application, the importance determination subunit is specifically used to determine a second weighting coefficient corresponding to each target LLC based on second additional information of each target LLC, wherein the second additional information includes at least one of: the load status of the target LLC, the weight of the target LLC, and the performance parameters of the CPU cores sharing the target LLC; to obtain the importance representation information of each target LLC to the target process based on the importance representation information of each target LLC to each thread and the second weighting coefficient corresponding to each target LLC; or to accumulate the importance representation information of each target LLC to each thread to obtain the importance representation information of each target LLC to the target process.

[0037] In one embodiment of this application, the recommended cache determination module is specifically used to determine recommended LLCs from the target LLCs according to the third additional information, in descending order of importance represented by the obtained importance characterization information. The third additional information includes at least one of the following: the latest time when the thread in the target process occupies the target LLC, the load status of the target LLC, the cumulative number of times the thread in the target process occupies the target LLC, the target NUMA node to which the target LLC belongs, and the status of the target NUMA node.

[0038] In one embodiment of this application, the recommended LLC value is determined based on the ratio between the number of threads in the target process and the number of CPU cores in the LLC.

[0039] According to another aspect of the embodiments of this application, an electronic device is provided, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0040] Memory, used to store computer programs;

[0041] When a processor executes a program stored in memory, it implements any of the thread scheduling methods described above.

[0042] According to another aspect of the embodiments of this application, a computer-readable storage medium is provided, wherein a computer program is stored therein, and the computer program, when executed by a processor, implements any of the thread scheduling methods described above.

[0043] According to another aspect of the embodiments of this application, a computer program product containing instructions is provided, which, when run on a computer, causes the computer to perform any of the thread scheduling methods described above.

[0044] Beneficial effects of the embodiments in this application:

[0045] As can be seen from the above, in the thread scheduling method provided in this application embodiment, the target LLC is the LLC occupied by the thread in the target process during its execution. The importance representation information of each target LLC to the target process can represent the importance of each target LLC to the thread in the target process. The recommended LLC corresponding to the target process determined based on the above importance representation information is also the recommended LLC corresponding to the thread in the target process. When scheduling the target thread in the target process, the CPU core is determined based on the load state of the CPU core sharing the recommended LLC, and the target thread is scheduled to run on the CPU core. The CPU core determined in this way shares the recommended LLC. When scheduling each thread in the target process, the recommended LLC of the target process is used. In this way, the probability of each thread in the target process being scheduled to run on the CPU core sharing the recommended LLC can be increased, so that each thread in the same process is scheduled to run on the CPU core sharing the same LLC as much as possible, thereby improving the cache hit rate of scheduling each thread in the same process to run on the CPU core sharing the same LLC.

[0046] Furthermore, by increasing the probability that each thread in the target process is scheduled to run on a CPU core sharing the recommended LLC, if other threads in the target process have already been scheduled to run on the same CPU core, the recommended LLC will store the data used by those other threads during CPU core execution. The target thread in the target process can reuse this data stored in the recommended LLC during CPU core execution. This reduces the need to read the data required by the target thread from memory during CPU core execution. Reading the data from the recommended LLC allows for more efficient data retrieval, improving the efficiency of each thread running on the CPU core and enhancing the overall efficiency of multi-core CPUs.

[0047] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0049] Figure 1a This is a schematic diagram of the structure of a CPU chip provided in an embodiment of this application;

[0050] Figure 1bA flowchart illustrating a thread scheduling method provided in an embodiment of this application;

[0051] Figure 1c A schematic diagram illustrating the correspondence between a CPU chip and a memory unit, provided as an embodiment of this application;

[0052] Figure 2 A flowchart illustrating a method for obtaining importance characterization information provided in an embodiment of this application;

[0053] Figure 3 A flowchart illustrating another method for obtaining importance characterization information provided in an embodiment of this application;

[0054] Figure 4 This is a schematic diagram of the structure of a thread scheduling device provided in an embodiment of this application;

[0055] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0056] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0057] The execution subject of the embodiments of this application will be described below.

[0058] The solutions provided in this application can be applied to various electronic devices such as servers, computers, mobile phones, and tablets. For ease of description, the execution subject of the thread scheduling method provided in this application will be collectively referred to as the thread scheduling device.

[0059] The following is combined Figure 1a The target CPU core and the target LLC are described.

[0060] Target CPU core: The CPU core on which the threads in the target process run.

[0061] The target LLC is the LLC occupied by the thread in the target process during its execution.

[0062] A multi-core CPU chip is an independent circuit unit cut from a whole silicon wafer. A single CPU chip can include multiple CPU cores and multiple LLCs. For example, see [link to documentation]. Figure 1a A schematic diagram of a CPU chip structure is provided. Figure 1aThe CPU chip shown includes 8 CPU cores and two LLCs.

[0063] Assuming that thread 1 in the target process runs on CPU core 1, then CPU core 1 is the CPU core on which thread 1 in the target process runs, and CPU core 1 is also the target CPU core. Figure 1a In the CPU chip shown, CPU core 1, CPU core 2, CPU core 3 and CPU core 4 share LLC1. Thread 1 in the target process needs to occupy LLC1 to store data when running in CPU core 1. Therefore, LLC1 is the LLC occupied by thread 1 in the target process during its operation, and LLC1 is also the target LLC.

[0064] Similarly, if thread 2 in the target process runs in CPU core 2, CPU core 2 is also the target CPU core. CPU core 1 and CPU core 2 share LLC1, and LLC1 is still the target LLC.

[0065] If thread 3 in the target process runs on CPU core 5, and CPU core 5 is also the target CPU core, then... Figure 1a In the CPU chip shown, CPU cores 5, 6, 7, and 8 share LLC2. Thread 3 in the target process runs in CPU core 5 and does not occupy LLC1, but needs to occupy LLC2 to store data. Therefore, LLC2 is the LLC occupied by thread 3 in the target process during its operation, and LLC2 is also the target LLC.

[0066] Assuming that the threads in the target process have not occupied CPU cores 3, 4, 6, 7, and 8, then CPU cores 3, 4, 6, 7, and 8 are not the target CPU cores.

[0067] The thread scheduling method provided in the embodiments of this application will be described in detail below.

[0068] In one embodiment of this application, see Figure 1b A flowchart of a thread scheduling method is provided, which includes the following steps S101-S103.

[0069] Step S101: Obtain the information representing the importance of each target LLC to the target process.

[0070] The importance representation information may include: the identifier of each target LLC and information representing the degree of importance of each target LLC to the target process. For example, the target LLCs can be sorted to record the order of their importance to the target process from highest to lowest.

[0071] The implementation method of step S101 will be described in the following embodiments, and will not be detailed here.

[0072] Step S102: Based on the obtained importance representation information, determine the recommended LLC corresponding to the target process from the target LLCs.

[0073] The recommended LLCs can include information on the importance of the recommended LLCs to the target process. For example, the recommended LLCs can be recorded in descending order of their represented importance.

[0074] In one implementation, the thread scheduling device, based on the acquired importance representation information, determines a first number of target LLCs, ranked from highest to lowest importance to the target process, as the recommended LLCs corresponding to the target process. The order of importance of the recommended LLCs to the target process is the same as the order of importance of the recommended LLCs to the target process when the importance representation information was acquired.

[0075] The following explains how to determine the recommended LLC value.

[0076] In one embodiment of this application, the recommended LLC value is determined based on the ratio between the number of threads in the target process and the number of CPU cores in the LLC. When determining the recommended LLC corresponding to the target process in step S102, a target LLC of the aforementioned recommended LLC value can be selected as the recommended LLC. For example, the first quantity in the above implementation can be the number of recommended LLC values.

[0077] In one approach, the thread scheduling device can divide the ratio between the number of threads in the target process and the number of CPU cores in the LLC by a preset multiple to obtain a quotient. If the quotient is an integer, it is used as the recommended LLC value; if the quotient is not an integer, it is converted to an integer and used as the recommended LLC value. The multiple can be any value between 2 and 10.

[0078] Alternatively, a maximum value for the recommended LLC can be set. If the thread scheduling device determines that the obtained quotient exceeds the maximum value for the recommended LLC, then the maximum value for the recommended LLC is selected as the recommended LLC value.

[0079] For example, Figure 1aThe CPU chip shown has 4 CPU cores in an LLC. Assuming the target process has 100 threads and the multiplier is 10, the ratio of the number of threads in the target process to the number of CPU cores in the LLC is 100 / 4 = 25. Then, we calculate 25 / 10 = 2.5. In this case, the quotient is not an integer. We can use rounding to convert the quotient to 3 as the recommended LLC value. Alternatively, we can directly take the integer part of the quotient and convert it to 2 as the recommended LLC value.

[0080] As can be seen from the above, by determining an appropriate number of recommended LLCs based on the number of threads in the target process, the threads in the target process can be scheduled into an appropriate number of recommended LLCs, so that the threads in the target process are concentrated in an appropriate number of recommended LLCs as much as possible, thereby further improving the cache hit rate of scheduling the threads in the same process to run on the CPU cores that share the same LLC.

[0081] Another implementation of step S102 will be described in the following embodiments, and will not be detailed here.

[0082] Steps S101 and S102 can be executed periodically. For example, step S101 can be executed periodically while the target process's thread is running on the CPU core, and then step S102 can be executed periodically at set time intervals. Alternatively, steps S101 and S102 can be executed periodically at set time intervals, such as 0.2s, 0.5s, 1s, and 2s. When it is necessary to schedule the target thread in the target process, the thread scheduling device executes step S103.

[0083] Step S103: In response to scheduling the target thread in the target process, based on the load status of the CPU cores of the shared recommended LLC, determine the CPU cores and schedule the target thread to run on the determined CPU cores.

[0084] The following explains the situation where scheduling of the target thread in the target process is required.

[0085] In one scenario, when a thread in the target process enters the running state, such as when a thread in the target process needs to be scheduled to run on a CPU core after it has moved from a blocked state to a ready state, then the thread in the target process is identified as the target thread, and the target thread needs to be scheduled.

[0086] In another scenario, where it's necessary to schedule threads from a target process in the processing queue of a CPU core to other CPU cores, then the thread in the target process is identified as the target thread, and scheduling of the target thread is required. For example, in a thread balancing scenario within the processing queue of a CPU core, it's necessary to schedule threads from the CPU core's processing queue to other CPU cores.

[0087] The method for determining the CPU core in step S103 is explained below.

[0088] In one implementation, the thread scheduling device can select the recommended LLC with the highest importance to the target process as the first LLC, determine the CPU core with the lowest workload among the CPU cores sharing the first LLC based on the load status of the CPU cores sharing the first LLC, and then schedule the target thread to run on the determined CPU core.

[0089] In another implementation, the thread scheduling device can determine the CPU core with the lowest load among the CPU cores sharing various recommended LLCs, and schedule the target thread to run on the determined CPU core.

[0090] As can be seen from the above, in the thread scheduling method provided in this application embodiment, the target LLC is the LLC occupied by the thread in the target process during its execution. The importance representation information of each target LLC to the target process can represent the importance of each target LLC to the thread in the target process. The recommended LLC corresponding to the target process determined based on the above importance representation information is also the recommended LLC corresponding to the thread in the target process. When scheduling the target thread in the target process, the CPU core is determined based on the load state of the CPU core sharing the recommended LLC, and the target thread is scheduled to run on the CPU core. The CPU core determined in this way shares the recommended LLC. When scheduling each thread in the target process, the recommended LLC of the target process is used. In this way, the probability of each thread in the target process being scheduled to run on the CPU core sharing the recommended LLC can be increased, so that each thread in the same process is scheduled to run on the CPU core sharing the same LLC as much as possible, thereby improving the cache hit rate of scheduling each thread in the same process to run on the CPU core sharing the same LLC.

[0091] Furthermore, by increasing the probability that each thread in the target process is scheduled to run on a CPU core sharing the recommended LLC, if other threads in the target process have already been scheduled to run on the same CPU core, the recommended LLC will store the data used by those other threads during CPU core execution. The target thread in the target process can reuse this data stored in the recommended LLC during CPU core execution. This reduces the need to read the data required by the target thread from memory during CPU core execution. Reading the data from the recommended LLC allows for more efficient data retrieval, improving the efficiency of each thread running on the CPU core and enhancing the overall efficiency of multi-core CPUs.

[0092] The NUMA architecture is explained below.

[0093] In a NUMA architecture, a computer system divides memory into multiple relatively independent memory units, each corresponding to a NUMA node. A NUMA node can correspond to one memory unit or multiple memory units.

[0094] The following is combined Figure 1c The correspondence between NUMA nodes and memory units is explained.

[0095] For example, suppose a NUMA node includes a CPU chip, and the structure of the CPU chip is as follows: Figure 1a As shown, a NUMA node can include 8 CPU cores and 2 LLCs from a CPU chip. See [link / reference] Figure 1c This document provides a schematic diagram illustrating the correspondence between CPU chips and memory units. Each CPU chip can connect to two memory units via two shared memory channels. In this configuration, one NUMA node corresponds to two memory units. For example, NUMA node 1 of CPU chip 1 corresponds to memory units 1 and 2; NUMA node 2 of CPU chip 2 corresponds to memory units 3 and 4; NUMA node 3 of CPU chip 3 corresponds to memory units 5 and 6; and NUMA node 4 of CPU chip 4 corresponds to memory units 7 and 8. In this scenario, the CPU core and LLC in CPU chip 1 belong to NUMA node 1, the CPU core and LLC in CPU chip 2 belong to NUMA node 2, the CPU core and LLC in CPU chip 3 belong to NUMA node 3, and the CPU core and LLC in CPU chip 4 belong to NUMA node 4.

[0096] The target NUMA node is described below.

[0097] The target NUMA node is the NUMA node to which the target LLC belongs, and also the NUMA node to which the target CPU core belongs. (As mentioned above...) Figure 1a and Figure 1c For example, if the thread in the target process runs on CPU core 1 in CPU chip 1, then CPU core 1 is the target CPU core, LLC1 is the target LLC, and NUMA node 1 is the target NUMA node.

[0098] The importance information of each target LLC to the target process obtained by the thread scheduling device can also determine the dependence of the target process on the target LLC. Based on this importance information, the recommended LLC is determined, and the target thread of the target process is scheduled to run on the CPU core sharing the recommended LLC. In this way, the threads of the target process can be concentrated as much as possible on the CPU cores sharing the recommended LLCs, reducing the possibility of the threads of the target process being scheduled to run on the CPU cores sharing other LLCs. In a NUMA architecture, because the threads of the target process run primarily on CPU cores sharing the recommended LLCs, the data required by the target process during CPU core execution is concentrated within the LLCs of one or more NUMA nodes to which the recommended LLCs belong. This reduces the need to schedule threads of the target process to run on CPU cores of other NUMA nodes, thus reducing cross-NUMA node access. In cases of cross-NUMA node access, threads of the target process running on CPU cores of other NUMA nodes need to access the LLCs or memory units of the recommended LLCs to read data, which is inefficient. Therefore, in a NUMA architecture, the solution provided in this application reduces cross-NUMA node access by reading data directly from the memory units or LLCs of the recommended LLCs within the one or more NUMA nodes to which the recommended LLCs belong during CPU core execution, improving the efficiency of each thread running on the CPU core and enhancing the overall efficiency of multi-core CPUs.

[0099] The following explains the recommended LLC method for determining the target process in step S102.

[0100] In one embodiment of this application, the thread scheduling device may determine the recommended LLC in the following manner: based on third additional information, the recommended LLC is determined from the target LLCs in descending order of importance represented by the obtained importance characterization information.

[0101] The third additional information includes at least one of the following: the latest time that the thread in the target process occupies the target LLC, the load status of the target LLC, the cumulative number of times the thread in the target process occupies the target LLC, the target NUMA node to which the target LLC belongs, and the status of the target NUMA node.

[0102] In one approach, the thread scheduling device can determine, based on third additional information, the target LLCs that cannot be used as recommended LLCs, obtain the target LLCs that can be used as recommended LLCs, and then select the first number of target LLCs that can be used as recommended LLCs in descending order of importance represented by the obtained importance representation information, and use them as recommended LLCs.

[0103] The following explains how to identify target LLCs that cannot be recommended LLCs based on third additional information.

[0104] 1. The latest time that the thread in the target process occupies the target LLC.

[0105] The thread scheduling device can determine the time difference between the current time and the latest time when a thread in the target process last occupied the target LLC. If the time difference is greater than a preset expiration time threshold, the target LLC is determined not to be a recommended LLC. In this way, if a relatively long time has passed since the target LLC was last occupied by a thread in the target process, it will no longer be considered a recommended LLC, which can reduce the possibility of data in the target LLC that can be reused by threads in the target process being overwritten.

[0106] II. Load Status of the Target LLC

[0107] The thread scheduling device can compare the load status of a target LLC with a preset LLC load threshold. If the load status of the target LLC indicates that its load exceeds the LLC load threshold, then the target LLC cannot be used as a recommended LLC. This prevents the target LLC from being used as a recommended LLC when its available cache space is limited or when it is difficult to store the data required by threads in the target process that are currently using the target LLC. This reduces the likelihood of threads running inefficiently on CPU cores due to excessive load on the target LLC.

[0108] III. The cumulative number of times the target LLC is occupied by threads in the target process

[0109] The thread scheduling device can compare the cumulative number of times threads in the target process occupy the target LLC with a preset LLC occupancy threshold. If the cumulative number is less than the LLC occupancy threshold, the target LLC is determined not to be a recommended LLC. This indicates that threads in the target process rarely occupy the target LLC, meaning that most threads in the target process are likely on other target LLCs. Therefore, this target LLC is no longer recommended, which can improve the cache hit rate of scheduling threads in the same process to run on CPU cores sharing the same LLC.

[0110] IV. The target NUMA node to which the target LLC belongs

[0111] The thread scheduling device can determine the target NUMA node to which each target LLC belongs. If there is only one target NUMA node, each target LLC can be considered a recommended LLC. If there are multiple target NUMA nodes, the target NUMA node with the most target LLCs is selected as the available target NUMA node. Target LLCs other than those included in the available target NUMA nodes are not considered recommended LLCs. This approach maximizes the number of target LLCs belonging to the same target NUMA node as recommended LLCs, minimizing the possibility of recommended LLCs belonging to different NUMA nodes.

[0112] V. Status of the target NUMA node

[0113] The state of a target NUMA node can include the load state of the memory unit corresponding to the target NUMA node, the load state of the CPU cores included in the target NUMA node, and the load state of the LLCs included in the target NUMA node. If at least one of these load states exceeds the corresponding load state threshold, then the target LLC under that target NUMA node cannot be used as a recommended LLC. This reduces the likelihood of low thread processing efficiency on CPU cores due to excessive load on the target NUMA node.

[0114] The following describes another implementation method for determining the recommended LLC.

[0115] When the third additional information includes the target NUMA node to which the target LLC belongs and the status of the target NUMA node, the thread scheduling device can determine the available target NUMA node according to the method for determining the available target NUMA node described above. The status of the target NUMA node can include the load status of other LLCs in the target NUMA node besides the target LLC. The load status of other LLCs of the available target NUMA node is obtained from the status of each target NUMA node. If the load status of other LLCs of the target NUMA node is less than or equal to the preset LLC load threshold, then the other LLCs of the available target NUMA node are recommended LLCs.

[0116] Alternatively, if the recommended LLC cannot be identified from the target LLC in step S102, the target thread in the target process can be scheduled according to the existing thread scheduling method.

[0117] In this way, when determining the recommended LLC, the latest time and cumulative number of times threads in the target process have occupied the target LLC can be used to assess the likelihood that data within the target LLC can be used by threads in the target process. This further improves the cache hit rate of scheduling threads in the same process to run on CPU cores sharing the same LLC, and reduces the need to read data required by the target thread from memory when running on the CPU core. The load status of the target LLC can be used to assess the available cache space of the target LLC, and thus the processing efficiency of threads in the target process on CPU cores sharing the target LLC. Furthermore, the target NUMA node to which the target LLC belongs and the status of the target NUMA node can be used to assess the likelihood of threads in the same process being processed on CPU cores under the same target NUMA node. When it is difficult to schedule threads in the same process to run on CPU cores sharing the same LLC, this increases the likelihood of scheduling threads in the same process to CPU cores under the same NUMA node, further reducing the likelihood of accessing memory corresponding to other NUMA nodes across NUMA nodes, and improving the operating efficiency of multi-core CPUs.

[0118] The following explains how to obtain importance representation information in step S101.

[0119] In one embodiment of this application, see Figure 2 A flowchart of a method for obtaining importance characterization information is provided, the method including the following steps S201-S202.

[0120] Step S201: Time the runtime of each thread in the target process on each target CPU core.

[0121] The target CPU core refers to the CPU core on which the threads in the target process run.

[0122] In one implementation, a cache context can be set for each thread in the target process, and the runtime of the thread on each target CPU core can be recorded in the cache context. Specifically, the cache context can record the thread identifier, the identifier of the CPU core in which the thread runs, and the runtime of the thread on that CPU core.

[0123] For example, if the target process includes thread 1, and thread 1 runs on CPU core 1 for 1 second, then the identifier of CPU core 1 and the information that the thread ran on CPU core 1 for 1 second are recorded in the cache context 1 corresponding to thread 1. Specifically, the cache context 1 can be identified as the cache context 1 corresponding to thread 1 by recording the identifier of thread 1.

[0124] If thread 1 runs on CPU core 2 for 1 second, then the identifier of CPU core 2 and the information that the thread runs on CPU core 2 for 1 second are recorded in cache context 1.

[0125] If thread 1 runs on CPU core 1 again for 1 second, then you can add a record of the CPU core 1 identifier and the information that the thread runs on CPU core 1 for 1 second in cache context 1. Alternatively, you can modify the information already recorded in cache context 1, such as the CPU core 1 identifier and the information that the thread runs on CPU core 1 for 1 second, to: the CPU core 1 identifier and the information that the thread runs on CPU core 1 for 2 seconds.

[0126] Additionally, the cache context can also record the latest execution time of a thread on each CPU core.

[0127] Step S202: Based on the runtime of each thread on the target CPU core sharing the same target LLC, obtain the importance representation information of each target LLC to the target process.

[0128] In one implementation, the runtime of each thread on the target CPU core sharing the same target LLC is accumulated to obtain information representing the importance of each target LLC to the target process.

[0129] In one approach, for each target LLC, the thread scheduling device can accumulate the runtime of the thread on each CPU core sharing the target LLC to obtain information representing the importance of the target LLC to the target process.

[0130] In another approach, the thread scheduling device can obtain the runtime of each thread in the target process on each target CPU core, and accumulate the runtime of each thread on the target CPU core to obtain the cumulative runtime of threads on the target CPU core. Then, for each target LLC, it can determine the cumulative runtime of threads on each target CPU core sharing the target LLC, and accumulate the cumulative runtime of threads on each target CPU core to obtain the cumulative time occupied by each thread in the target process for the target LLC. The obtained cumulative time occupied by each thread in the target process for the target LLC is used as the information representing the importance of the target LLC to the target process.

[0131] For example, suppose the target process includes thread 1 and thread 2, in order to Figure 1a For example, if thread 1 runs for 5 seconds on CPU core 1, 6 seconds on CPU core 2, 2 seconds on CPU core 5, 3 seconds on CPU core 2, and 1 second on CPU core 5, then, for CPU core 1, the cumulative runtime of each thread in the target process on CPU core 1 is 5 seconds; for CPU core 2, the cumulative runtime is 6 seconds + 3 seconds = 9 seconds; and for CPU core 5, the cumulative runtime is 2 seconds + 1 second = 3 seconds. Since CPU cores 1 and 2 share LLC1, the cumulative runtime of each thread in the target process occupying LLC1 is 5 seconds + 9 seconds = 14 seconds, and the cumulative runtime of each thread in the target process occupying LLC2 is 3 seconds.

[0132] In this way, based on the runtime of each thread on each target CPU core, the dependence of the target process on the target LLC and the importance of each target LLC to the target process can be obtained quickly and accurately through cumulative calculation. The applicability of the importance representation information of each target LLC to the target process obtained by accumulating runtime is more extensive, and the computational resources occupied by obtaining importance representation information can also be reduced through a simple calculation method.

[0133] Alternatively, the method for obtaining importance representation information in step S202 can also be described below. Figure 3 The provided implementation examples are not detailed here.

[0134] As can be seen from the above, by timing the runtime of each thread in the target process on each target CPU core, the dependence of each thread in the target process on each target CPU core can be accurately recorded. In this way, the runtime of the target CPU cores sharing the same target LLC can be accumulated, and the dependence of each thread in the target process on each target CPU core can be converted into the dependence of each thread in the target process on the target LLC. This allows for the accurate acquisition of the importance representation information of each target LLC to the target process.

[0135] The implementation method of step S202 will be explained below.

[0136] In one embodiment of this application, see Figure 3 A flowchart of another method for obtaining importance characterization information is provided, which includes the following steps S2021-S2022.

[0137] Step S2021: Based on the runtime of each thread on the target CPU core sharing the same target LLC, obtain the importance representation information of each target LLC to each thread.

[0138] Step S2021 can be achieved through either step A1 or step A2.

[0139] Step A1: Based on the first additional information of the target CPU core, determine the first weight coefficient corresponding to the target CPU core. Based on the runtime of each thread on the target CPU core sharing the same target LLC and the first weight coefficient corresponding to the target CPU core, obtain the importance representation information of each target LLC to each thread.

[0140] The first additional information includes at least one of the following: CPU core performance parameters, CPU core load status, and CPU core scheduling weight.

[0141] The following describes one implementation method for step A1.

[0142] The method for determining the first weighting coefficient is explained below.

[0143] In one approach, an information type weight can be set for each first additional information. For each target CPU core, the weighted value of the information value of the first additional information of the target CPU core and the information type weight corresponding to the first additional information can be calculated, and the sum of each weighted value can be used as the first weight coefficient of the target CPU core.

[0144] In another approach, an information type weight can be set for each first additional information. For each group of target CPU cores sharing the same target LLC, the weighted value of the information value of the first additional information of the target CPU cores sharing the target LLC and the information type weight corresponding to the first additional information can be calculated. The sum of the weighted values ​​of the target CPU cores sharing the target LLC can be used as the first weight coefficient of the target CPU cores sharing the target LLC.

[0145] After obtaining the first weight coefficient of each target CPU core, for each thread, the thread scheduling device can determine the importance representation information of each target LLC to that thread in the following way:

[0146] In each target CPU core, the first target CPU core corresponding to the thread is determined. In each first target CPU core, each target CPU core group that shares the same target LLC is determined. For each target LLC, that is, for each target CPU core group, the sum of the runtime of the thread in the target CPU core in the target CPU core group and the weighted value of the first weight coefficient corresponding to the target CPU core is calculated as the importance representation information of the target LLC to the thread, thus obtaining the importance representation information of each target LLC to the thread.

[0147] For example, with Figure 1a For example, if the first target CPU cores corresponding to the thread include CPU core 1, CPU core 2, CPU core 3, CPU core 5, and CPU core 6, then CPU core 1, CPU core 2, and CPU core 3 are target CPU core groups sharing the same target LLC (LLC1), and CPU core 5 and CPU core 6 are target CPU core groups sharing the same target LLC (LLC2). For LLC1, the weighted value 1 of the thread's runtime on CPU core 1 and the first weight coefficient corresponding to CPU core 1, the weighted value 2 of the thread's runtime on CPU core 2 and the first weight coefficient corresponding to CPU core 2, and the weighted value 3 of the thread's runtime on CPU core 3 and the first weight coefficient corresponding to CPU core 3 are calculated. Then, the sum of weighted value 1, weighted value 2, and weighted value 3 is used as the information representing the importance of LLC1 to the thread. For LLC2, calculate the weighted value 5 of the thread's runtime on CPU core 5 and the first weight coefficient corresponding to CPU core 5, and the weighted value 6 of the thread's runtime on CPU core 6 and the first weight coefficient corresponding to CPU core 6. Then, the sum of the weighted value 5 and the weighted value 6 is used as the representation information of the importance of LLC2 to the thread.

[0148] Among them, the performance parameters of the CPU core can be the CPU core frequency, the load status of the CPU core can be the CPU core utilization, and the scheduling weight of the CPU core can be a preset weight value. The scheduling weight of the CPU core can also be a weight value adjusted according to the state of the CPU core. For example, the scheduling weight of the CPU core can be adjusted according to the temperature of the CPU core. When the CPU core temperature is high, the scheduling weight of the CPU core is reduced, and when the CPU core temperature is low, the scheduling weight of the CPU core is increased.

[0149] In this way, based on the first additional information of each target CPU core, the specific situation of the CPU core can be analyzed from the CPU core performance, CPU core load and CPU scheduling priority. The importance of the CPU core under the shared target LLC to each thread can be analyzed from different perspectives, thereby more accurately determining the importance representation information of each target LLC to each thread.

[0150] Step A2: For each thread, sum the runtime of the thread on the target CPU core sharing the same target LLC to obtain the importance information of each target LLC to the thread.

[0151] In one implementation, the importance representation information of each target LLC to the thread can be determined as follows: In each target CPU core, determine the first target CPU core corresponding to the thread; in the first target CPU core, determine the target CPU core group sharing the same target LLC; for each target LLC, that is, for each target CPU core group, calculate the sum of the runtime of the thread on each target CPU core in that target CPU core group, and use this as the importance representation information of the target LLC to the thread, thus obtaining the importance representation information of each target LLC to the thread.

[0152] In this way, by accumulating the runtime of each thread on the target CPU core sharing the same target LLC, the applicability of the importance representation information of each target LLC to the target process is more extensive, and the computational resources occupied in obtaining the importance representation information can also be reduced through a simple calculation method.

[0153] In steps A1 and A2, after obtaining the importance representation information of each target LLC to a thread, the thread scheduling device can normalize the importance representation information of each target LLC to the thread on a thread-by-thread basis, and use the normalized value as the importance representation information of each target LLC to the thread.

[0154] Step S2022: Based on the importance representation information of each target LLC to each thread, obtain the importance representation information of each target LLC to the target process.

[0155] Step S2022 can be achieved through either step B1 or step B2.

[0156] Step B1: Based on the second additional information of each target LLC, determine the second weight coefficient corresponding to each target LLC. Based on the importance representation information of each target LLC to each thread and the second weight coefficient corresponding to each target LLC, obtain the importance representation information of each target LLC to the target process.

[0157] The second additional information includes at least one of the following: the load status of the target LLC, the weight of the target LLC, and the performance parameters of the CPU cores sharing the target LLC.

[0158] The following describes one implementation method for step B1.

[0159] You can set the information type weight corresponding to each first additional information. For each target LLC, calculate the weighted value of the information value of the second additional information of the target LLC and the information type weight corresponding to the second additional information. The sum of each weighted value is used as the second weight coefficient of the target LLC.

[0160] After obtaining the second weighting coefficients for each target LLC, the thread scheduling device can obtain the importance representation information of each target LLC to each thread in the following manner:

[0161] For each target LLC, the importance representation information of the target LLC to each thread is accumulated to obtain the sum value corresponding to the target LLC. Then, the second weight coefficient corresponding to the target LLC is calculated and weighted with the sum value corresponding to the target LLC to obtain the weighted value corresponding to the target LLC. The obtained weighted values ​​corresponding to the target LLC are summed and the sum value is used as the importance representation information of the target LLC to the target process.

[0162] For example, if the target process includes thread 1 and thread 2, and the target LLC includes LLC1 and LLC2, and in step S2021, the importance representation information 1 of LLC1 to thread 1, the importance representation information 2 of LLC2 to thread 1, the importance representation information 3 of LLC1 to thread 2, and the importance representation information 4 of LLC2 to thread 2 can be obtained, then, for LLC1, the weighted value 1 of the importance representation information 1 and the corresponding second weight coefficient of LLC1 can be calculated, the weighted value 2 of the importance representation information 3 and the corresponding second weight coefficient of LLC1 can be calculated, and the weighted values ​​1 and 2 are summed to obtain the importance representation information of LLC1 to the target process. For LLC2, the weighted value 3 of the importance representation information 2 and the corresponding second weight coefficient of LLC2 can be calculated, the weighted value 4 of the importance representation information 4 and the corresponding second weight coefficient of LLC2 can be calculated, and the weighted values ​​3 and 4 are summed to obtain the importance representation information of LLC2 to the target process.

[0163] Among them, the information value of the load status of the target LLC can be the LLC utilization rate, the information value of the performance parameters of the CPU cores sharing the target LLC can be the frequency of each CPU core sharing the target LLC, and the information value of the weight of the target LLC can be a preset weight value.

[0164] In this way, based on the second additional information of each target LLC, the load status, weight, and priority of the target LLC can be analyzed to determine the specific situation of the target LLC. The importance of the target LLC to each thread can be analyzed from different perspectives, thereby more accurately determining the importance representation information of each target LLC to each target process.

[0165] Step B2: Accumulate the importance representation information of each target LLC to each thread to obtain the importance representation information of each target LLC to the target process.

[0166] In one implementation, the importance representation information of each target LLC to each thread can be determined in the following way: For each target LLC, the sum of the importance representation information of the target LLC to each thread is calculated as the importance representation information of the target LLC to the target process, thus obtaining the importance representation information of each target LLC to the target process.

[0167] In this way, the information on the importance of each target LLC to the target process obtained by accumulating the importance representation information of each target LLC to each thread has a wider applicability, and the computational resources occupied in obtaining the importance representation information can also be reduced through a simple calculation method.

[0168] In this embodiment of the application, steps S2021 and S2022 can be implemented in the following ways: Method 1: Step S2021 is implemented via step A1, and step S2022 is implemented via step B1. Method 2: Step S2021 can be implemented via step A1, and step S2022 can be implemented via step B2. Method 3: Step S2021 can be implemented via step A2, and step S2022 can be implemented via step B1. Method 4: Step S2021 can be implemented via step A2, and step S2022 can be implemented via step B2.

[0169] If step S2021 is implemented through step A1 and step S2022 is implemented through step B1, the second additional information may not include the performance parameters of the CPU core of the shared target LLC.

[0170] In steps B1 and B2, after obtaining the importance representation information of each target LLC to the target process, the thread scheduling device can normalize the importance representation information of each target LLC to the target process on a per-target-process basis, and use the normalized values ​​as the importance representation information of each target LLC to the target process.

[0171] As can be seen from the above, by analyzing the thread's runtime on the target CPU core and the thread's dependence on the target LLC, we can analyze the importance representation information of each target LLC to the target process from both the target CPU core and target LLC perspectives, thereby improving the accuracy of the obtained importance representation information.

[0172] Corresponding to the above thread scheduling method, this application also provides a thread scheduling device.

[0173] In one embodiment of this application, see Figure 4 A schematic diagram of a thread scheduling device is provided, the device comprising:

[0174] Importance acquisition module 401 is used to acquire the importance representation information of each target LLC to the target process, wherein the target LLC is: the LLC occupied by the thread in the target process during its execution.

[0175] The recommended cache determination module 402 is used to determine the recommended LLC corresponding to the target process from the target LLCs based on the obtained importance representation information.

[0176] The thread scheduling module 403 is used to schedule the target thread in the target process, determine the CPU core based on the load status of the CPU core sharing the recommended LLC, and schedule the target thread to run on the determined CPU core.

[0177] As can be seen from the above, in the thread scheduling method provided in this application embodiment, the target LLC is the LLC occupied by the thread in the target process during its execution. The importance representation information of each target LLC to the target process can represent the importance of each target LLC to the thread in the target process. The recommended LLC corresponding to the target process determined based on the above importance representation information is also the recommended LLC corresponding to the thread in the target process. When scheduling the target thread in the target process, the CPU core is determined based on the load state of the CPU core sharing the recommended LLC, and the target thread is scheduled to run on the CPU core. The CPU core determined in this way shares the recommended LLC. When scheduling each thread in the target process, the recommended LLC of the target process is used. In this way, the probability of each thread in the target process being scheduled to run on the CPU core sharing the recommended LLC can be increased, so that each thread in the same process is scheduled to run on the CPU core sharing the same LLC as much as possible, thereby improving the cache hit rate of scheduling each thread in the same process to run on the CPU core sharing the same LLC.

[0178] Furthermore, by increasing the probability that each thread in the target process is scheduled to run on a CPU core sharing the recommended LLC, if other threads in the target process have already been scheduled to run on the same CPU core, the recommended LLC will store the data used by those other threads during CPU core execution. The target thread in the target process can reuse this data stored in the recommended LLC during CPU core execution. This reduces the need to read the data required by the target thread from memory during CPU core execution. Reading the data from the recommended LLC allows for more efficient data retrieval, improving the efficiency of each thread running on the CPU core and enhancing the overall efficiency of multi-core CPUs.

[0179] In one embodiment of this application, the importance acquisition module includes:

[0180] The runtime timing unit is used to time the runtime of each thread in the target process on each target CPU core, wherein the target CPU core is the CPU core in which the threads in the target process run;

[0181] The importance acquisition unit is used to obtain the importance representation information of each target LLC to the target process based on the runtime of each thread on the target CPU core sharing the same target LLC.

[0182] As can be seen from the above, by timing the runtime of each thread in the target process on each target CPU core, the dependence of each thread in the target process on each target CPU core can be accurately recorded. In this way, the runtime of the target CPU cores sharing the same target LLC can be accumulated, and the dependence of each thread in the target process on each target CPU core can be converted into the dependence of each thread in the target process on the target LLC. This allows for the accurate acquisition of the importance representation information of each target LLC to the target process.

[0183] In one embodiment of this application, the importance acquisition unit includes: a duration accumulation subunit, used to accumulate the runtime of each thread on the target CPU core sharing the same target LLC to obtain importance representation information of each target LLC to the target process; or an importance acquisition subunit, used to obtain importance representation information of each target LLC to each thread based on the runtime of each thread on the target CPU core sharing the same target LLC; and to obtain importance representation information of each target LLC to the target process based on the importance representation information of each target LLC to each thread.

[0184] In this way, based on the runtime of each thread on each target CPU core, the dependency of the target process on the target LLC and the importance of each target LLC to the target process can be quickly and accurately calculated through cumulative calculation. The importance representation information of each target LLC to the target process obtained by accumulating runtime has wider applicability, and the computational resources occupied in obtaining the importance representation information can be reduced through a simple calculation method. By analyzing the dimensions of thread runtime on the target CPU core and the dependency of each thread on the target LLC, the importance representation information of each target LLC to the target process can be analyzed from two perspectives: the target CPU core and the target LLC, thus improving the accuracy of the obtained importance representation information.

[0185] In one embodiment of this application, the importance determination subunit is specifically used to determine a first weight coefficient corresponding to a target CPU core based on first additional information of the target CPU core, wherein the first additional information includes at least one of: CPU core performance parameters, CPU core load status, and CPU core scheduling weight; to obtain importance representation information of each target LLC to each thread based on the runtime of each thread on the target CPU core sharing the same target LLC and the first weight coefficient corresponding to the target CPU core; or, for each thread, to accumulate the runtime of the thread on the target CPU core sharing the same target LLC to obtain importance representation information of each target LLC to the thread.

[0186] In this way, based on the initial additional information of each target CPU core, the specific situation of the CPU core can be analyzed from the perspectives of CPU core performance, CPU core load, and CPU scheduling priority. This allows for analysis of the importance of CPU cores sharing a target LLC to each thread from different angles, thus more accurately determining the importance representation information of each target LLC to each thread. The applicability of the importance representation information of each target LLC to the target process obtained by accumulating the runtime of each thread on the target CPU core sharing the same target LLC is broader, and the computational resources required to obtain the importance representation information can be reduced through a simple calculation method.

[0187] In one embodiment of this application, the importance determination subunit is specifically used to determine a second weighting coefficient corresponding to each target LLC based on second additional information of each target LLC, wherein the second additional information includes at least one of: the load status of the target LLC, the weight of the target LLC, and the performance parameters of the CPU cores sharing the target LLC; to obtain the importance representation information of each target LLC to the target process based on the importance representation information of each target LLC to each thread and the second weighting coefficient corresponding to each target LLC; or to accumulate the importance representation information of each target LLC to each thread to obtain the importance representation information of each target LLC to the target process.

[0188] In this way, based on the second additional information of each target LLC, the load status, weight, and priority of the target LLC can be analyzed to understand its specific situation. This allows for analysis of the importance of each target LLC to each thread from different perspectives, thus more accurately determining the importance representation information of each target LLC to each target process. By accumulating the importance representation information of each target LLC to each thread, the applicability of the obtained importance representation information of each target LLC to the target process is broader, and the simple calculation method can also reduce the computational resources required to obtain the importance representation information.

[0189] In one embodiment of this application, the recommended cache determination module is specifically used to determine recommended LLCs from the target LLCs according to the third additional information, in descending order of importance represented by the obtained importance characterization information. The third additional information includes at least one of the following: the latest time when the thread in the target process occupies the target LLC, the load status of the target LLC, the cumulative number of times the thread in the target process occupies the target LLC, the target NUMA node to which the target LLC belongs, and the status of the target NUMA node.

[0190] In this way, when determining the recommended LLC, the latest time and cumulative number of times threads in the target process have occupied the target LLC can be used to assess the likelihood that data within the target LLC can be used by threads in the target process. This further improves the cache hit rate of scheduling threads in the same process to run on CPU cores sharing the same LLC, and reduces the need to read data required by the target thread from memory when running on the CPU core. The load status of the target LLC can be used to assess the available cache space of the target LLC, and thus the processing efficiency of threads in the target process on CPU cores sharing the target LLC. Furthermore, the target NUMA node to which the target LLC belongs and the status of the target NUMA node can be used to assess the likelihood of threads in the same process being processed on CPU cores under the same target NUMA node. When it is difficult to schedule threads in the same process to run on CPU cores sharing the same LLC, this increases the likelihood of scheduling threads in the same process to CPU cores under the same NUMA node, further reducing the likelihood of accessing memory corresponding to other NUMA nodes across NUMA nodes, and improving the operating efficiency of multi-core CPUs.

[0191] In one embodiment of this application, the recommended LLC value is determined based on the ratio between the number of threads in the target process and the number of CPU cores in the LLC.

[0192] As can be seen from the above, by determining an appropriate number of recommended LLCs based on the number of threads in the target process, the threads in the target process can be scheduled into an appropriate number of recommended LLCs, so that the threads in the target process are concentrated in an appropriate number of recommended LLCs as much as possible, thereby further improving the cache hit rate of scheduling the threads in the same process to run on the CPU cores that share the same LLC.

[0193] This application also provides an electronic device, such as... Figure 5 As shown, it includes a processor 501, a communication interface 502, a memory 503, and a communication bus 504, wherein the processor 501, the communication interface 502, and the memory 503 communicate with each other through the communication bus 504.

[0194] Memory 503 is used to store computer programs;

[0195] When the processor 501 executes the program stored in the memory 503, it implements any of the thread scheduling methods described above.

[0196] The communication bus mentioned in the above electronic devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0197] The communication interface is used for communication between the aforementioned electronic devices and other devices.

[0198] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0199] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0200] In another embodiment provided in this application, a computer-readable storage medium is also provided, which stores a computer program that, when executed by a processor, implements the steps of any of the above-described thread scheduling methods.

[0201] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute any of the thread scheduling methods described above.

[0202] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0203] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0204] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of apparatus, electronic devices, storage media, and computer program products are basically similar to the method embodiments, so the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0205] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A thread scheduling method, characterized by, The method includes: The runtime of each thread in the target process on each target CPU core, wherein the target CPU core is the CPU core in which the threads in the target process run; Based on the runtime of each thread on the target CPU core sharing the same target LLC, the importance of each target LLC to the target process is obtained, wherein the target LLC is: the LLC occupied by the thread in the target process during its execution. Based on the obtained importance representation information, the recommended LLC corresponding to the target process is determined from the target LLCs; In response to scheduling the target thread in the target process, based on the load status of the CPU cores sharing the recommended LLC, the CPU core is determined, and the target thread is scheduled to run on the determined CPU core. The method of obtaining the importance representation information of each target LLC to the target process based on the runtime of each thread on the target CPU core sharing the same target LLC includes: The importance of each target LLC to the target process is represented by summing the runtime of each thread on the target CPU core sharing the same target LLC; or the importance of each target LLC to each thread is represented by the runtime of each thread on the target CPU core sharing the same target LLC; and the importance of each target LLC to the target process is represented by the runtime of each thread on the target CPU core sharing the same target LLC. The step of obtaining the importance representation information of each target LLC to the target process based on the importance representation information of each target LLC to each thread includes: Based on the second additional information of each target LLC, a second weighting coefficient corresponding to each target LLC is determined, wherein the second additional information includes at least one of the following: the load status of the target LLC, the weight of the target LLC, and the performance parameters of the CPU cores sharing the target LLC; according to the importance representation information of each target LLC to each thread and the second weighting coefficient corresponding to each target LLC, the importance representation information of each target LLC to the target process is obtained; or the importance representation information of each target LLC to each thread is accumulated to obtain the importance representation information of each target LLC to the target process.

2. The method according to claim 1, characterized in that, The method of obtaining the importance information of each target LLC to each thread based on the runtime of each thread on the target CPU core sharing the same target LLC includes: Based on the first additional information of the target CPU core, a first weight coefficient corresponding to the target CPU core is determined, wherein the first additional information includes at least one of the following: CPU core performance parameters, CPU core load status, and CPU core scheduling weight; based on the runtime of each thread in the target CPU core sharing the same target LLC and the first weight coefficient corresponding to the target CPU core, the importance representation information of each target LLC to each thread is obtained. or For each thread, the runtime of that thread on the target CPU core sharing the same target LLC is accumulated to obtain information representing the importance of each target LLC to that thread.

3. The method according to claim 1 or 2, characterized in that, The step of determining the recommended LLC corresponding to the target process from the target LLCs based on the acquired importance representation information includes: Based on the third additional information, recommended LLCs are determined from the target LLCs in descending order of importance represented by the acquired importance characterization information. The third additional information includes at least one of the following: the latest time when the thread in the target process occupies the target LLC, the load status of the target LLC, the cumulative number of times the thread in the target process occupies the target LLC, the target NUMA node to which the target LLC belongs, and the status of the target NUMA node.

4. The method according to claim 1 or 2, characterized in that, The recommended LLC value is determined based on the ratio between the number of threads in the target process and the number of CPU cores in the LLC.

5. A thread scheduling device, characterized in that, The device includes: The importance acquisition module is used to acquire the importance representation information of each target LLC to the target process, wherein the target LLC is: the LLC occupied by the thread in the target process during its execution; A recommended cache determination module is used to determine the recommended LLC corresponding to the target process from the target LLCs based on the obtained importance representation information; The thread scheduling module is used to respond to the scheduling of the target thread in the target process, determine the CPU core based on the load status of the CPU core sharing the recommended LLC, and schedule the target thread to run on the determined CPU core. The importance assessment module includes: The runtime timing unit is used to time the runtime of each thread in the target process on each target CPU core, wherein the target CPU core is the CPU core in which the threads in the target process run; the importance acquisition unit is used to obtain the importance representation information of each target LLC to the target process based on the runtime of each thread on the target CPU core sharing the same target LLC. The importance determination unit includes: a duration accumulation subunit, used to accumulate the runtime of each thread on the target CPU core sharing the same target LLC to obtain importance representation information of each target LLC to the target process; or an importance determination subunit, used to obtain importance representation information of each target LLC to each thread based on the runtime of each thread on the target CPU core sharing the same target LLC; and to obtain importance representation information of each target LLC to the target process based on the importance representation information of each target LLC to each thread. The importance determination subunit is specifically used to determine the second weight coefficient corresponding to each target LLC based on the second additional information of each target LLC, wherein the second additional information includes at least one of: the load status of the target LLC, the weight of the target LLC, and the performance parameters of the CPU cores sharing the target LLC; to obtain the importance representation information of each target LLC to the target process based on the importance representation information of each target LLC to each thread and the second weight coefficient corresponding to each target LLC; or to accumulate the importance representation information of each target LLC to each thread to obtain the importance representation information of each target LLC to the target process.

6. The apparatus according to claim 5, characterized in that, The importance determination subunit is specifically used to determine a first weight coefficient corresponding to a target CPU core based on first additional information of the target CPU core, wherein the first additional information includes at least one of the following: CPU core performance parameters, CPU core load status, and CPU core scheduling weight; to obtain importance representation information of each target LLC to each thread based on the runtime of each thread on the target CPU core sharing the same target LLC and the first weight coefficient corresponding to the target CPU core; or, for each thread, to accumulate the runtime of the thread on the target CPU core sharing the same target LLC to obtain importance representation information of each target LLC to the thread. and / or The recommended cache determination module is specifically used to determine recommended LLCs from the target LLCs according to the third additional information, in descending order of importance represented by the obtained importance representation information. The third additional information includes at least one of the following: the latest time when the thread in the target process occupies the target LLC, the load status of the target LLC, the cumulative number of times the thread in the target process occupies the target LLC, the target NUMA node to which the target LLC belongs, and the status of the target NUMA node. and / or The recommended LLC value is determined based on the ratio between the number of threads in the target process and the number of CPU cores in the LLC.

7. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, when executing a program stored in memory, implements the method of any one of claims 1-4.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method described in any one of claims 1-4.

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