A method and system for chip interconnection communication based on manchester coding

Abstract

The application belongs to the field of chip interconnection communication, and particularly discloses a chip interconnection communication method and system based on Manchester coding, which comprises the following steps: a master control device generates and sends a communication frame, the physical layer of which adopts Manchester coding, logic 1 is high-to-low transition, and logic 0 is low-to-high transition, and the frame start / end is defined by a specific high-low level sequence; the data link layer of the communication frame comprises a synchronization code, an address field, a control field, a data field and an end code, the control field comprises pin intervals and quantity identification, and a clock is sent simultaneously to synchronize the slave device; the slave device decodes the received signal, determines the target pin range according to the identification when the address is matched, and sets the pin level according to the data field. The application improves the communication rate and efficiency, simplifies the wiring, and adapts to the chip interconnection requirements in multiple scenes.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip interconnection communication, in particular to a chip interconnection communication method and system based on Manchester coding. BACKGROUND

[0002] In the field of chip interconnection communication, data transmission methods are mainly divided into two categories: serial bus and parallel bus. Both types of buses have technical defects that are difficult to reconcile in actual application, and cannot meet the flexible and variable chip interconnection scene requirements.

[0003] Among them, the serial bus covers low-speed and high-speed interfaces: low-speed interfaces such as I2C, SPI, UART, although they have the advantages of low hardware cost, simple communication protocol, and short development cycle, but the data transmission bandwidth is extremely low, for example, the standard communication rate of UART is only 115200bps (14.4KB / s), and the rate of I2C fast mode is only 400Kbps (50KB / s), and the transmission efficiency is poor, UART needs an additional start bit and end bit for every 1 byte transmission, the efficiency is only 80%, I2C needs 29bit total transmission for every 1 byte effective data transmission, the efficiency is only 27.5%, and the pin usage is large, SPI needs to add 1 chip selection pin for every 1 slave device, and UART needs to add 2 FPGA pins for every 1 CPLD; high-speed interfaces such as USB, PCIe, Aurora, although they have high bandwidth and low delay, but the hardware implementation cost is high, the communication protocol is complex, and the development difficulty is great.

[0004] Parallel buses such as SDRAM and DDR have extremely high data transmission bandwidth and are mainly used for CPU and external DDR connection, but the pin consumption is large, the hardware design difficulty is high, and the power consumption is high, which further limits its application scenarios.

[0005] In actual test scenarios, for example, using Xilinx Zynq7000 series FPGA and 8 board cards, each board containing 8 pieces of Lattice MachXO series CPLD communication, 2680 CPLD pins need to be controlled, and the ideal time consumption of traditional protocols such as I2C to control all pins of 8 Pin cards is 7680us, which is extremely low and difficult to meet the efficient control requirements. SUMMARY

[0006] The purpose of the present application is to provide a chip interconnection communication method and system based on Manchester coding to solve the problems raised in the background art.

[0007] According to one aspect of the present application, a Manchester coding-based chip interconnection communication method is provided, which is applied to a chip interconnection system including one master device and at least one slave device, and includes the following method steps: S1, the master device generates and sends a communication frame, a physical layer signal of the communication frame is modulated by Manchester coding, wherein a frame start and a frame end are defined by a high level lasting two effective data widths followed by a mark sequence of two low levels; the communication frame includes the following fields arranged in sequence at a data link layer: a synchronization code, an address field, a control field, a data field, and an end code; wherein the address field is used for addressing a specific slave device, the control field includes at least pin interval identification and interval number identification, the pin interval identification is used for specifying one pin control interval inside the slave device, each pin control interval corresponds to a group of continuous input / output pins, the interval number identification is used for specifying the number of continuously controlled pin intervals in one transmission, and each bit of the data field corresponds to the level state of a specific pin in a specified pin control interval; the master device provides a clock signal used by Manchester coding data to the slave device for signal synchronization and decoding while sending the communication frame; S2, the slave device receives the clock signal and Manchester coding signal, decodes the Manchester coding signal by using the clock signal, parses the address field, the control field, and the data field after recognizing the frame start mark; when the address field matches the own address, the range of target pins is determined according to the pin interval identification and the interval number identification, and corresponding level setting operations are performed on the target pins according to the content of the data field.

[0008] Preferably, the control field further includes a read-back enabling bit, when the read-back enabling bit is set to be valid, the addressed slave device assembles the address field and the control field into a response frame after receiving the address field and the control field of the communication frame, sets the read-back enabling bit and a read / write bit in the response frame to preset values, and sends the response frame back to the master device by Manchester coding.

[0009] Preferably, the control field further includes a read / write bit, when the read / write bit is set to be in a read state, the addressed slave device reads the current level state of the corresponding pin interval according to the pin interval identification and the interval number identification after receiving the communication frame, and encapsulates the read level state data into a response frame and sends the response frame back to the master device.

[0010] Preferably, the address field is further divided into a board card address and a chip select address, wherein the board card address is used for selecting a target board card in multiple board cards, and the chip select address is used for selecting a target slave device in multiple slave devices on the target board card.

[0011] Preferably, on the hardware link, the unipolar Manchester coding signal and the clock signal sent by the master device are first converted into differential signals by a unipolar-to-differential chip and then transmitted, and the differential-to-unipolar chip is used to restore the unipolar signal at the receiving end of the slave device.

[0012] Preferably, the clock signal is embedded in the Manchester coding data, and the slave device restores the clock signal from the received data stream by using a digital phase-locked loop to achieve synchronization.

[0013] Preferably, the master device sets the interval number identifier to a value greater than or equal to zero to continuously control multiple pin intervals in one communication frame transmission, and the length of the data field is dynamically determined according to the interval number identifier.

[0014] Preferably, when sending a response frame, the slave device first sends a header containing the address field and the control field, wherein the read-write bit is set to a state indicating that the slave device writes to the master device, and then sends the read level state data.

[0015] Preferably, the master device dynamically adjusts the clock rate of the Manchester coding signal, including that the master device sends a back-reading test frame to the target slave device at an initial clock rate before initiating formal data transmission; if no correct response from the slave device is received within a preset timeout, the master device automatically reduces the clock rate by one level and re-sends the back-reading test frame until a correct response is received or the minimum rate threshold is reached.

[0016] Preferably, when setting the interval number identifier, the master device makes a logical judgment according to the actual change of the state of the pin to be controlled this time; if the judgment result is that the state of all pins to be controlled this time has not changed compared with the current state, the master device cancels the sending of this communication frame; if the judgment result is that only the state of part of the pin intervals has changed, the master device dynamically adjusts the pin interval identifier and the interval number identifier, and only the pin intervals and their data that have changed are encapsulated into a communication frame for sending.

[0017] Another aspect of the present application also provides a Manchester coding-based chip interconnection communication system, comprising: a master device and a slave device, wherein the master device is configured to generate and send a communication frame, a physical layer signal of the communication frame being modulated by Manchester coding, wherein a frame start and a frame end are defined by a high level lasting two valid data widths followed by a two-low-level flag sequence; the communication frame comprises, in a data link layer, sequentially arranged fields of: a synchronization code, an address field, a control field, a data field, and an end code; wherein the address field is configured to address a specific slave device, the control field comprises at least pin interval identification and interval number identification, the pin interval identification is configured to specify one pin control interval in the slave device, each pin control interval corresponds to a group of continuous input / output pins, the interval number identification is configured to specify a number of continuously controlled pin intervals in one transmission, and each bit of the data field corresponds to a level state of a specific pin in a specified pin control interval; the master device provides a clock signal used by Manchester coding data to the slave device for signal synchronization and decoding while sending the communication frame; wherein the slave device is configured to receive the clock signal and Manchester coding signal, decode the Manchester coding signal by using the clock signal, identify a frame start flag, and analyze the address field, the control field, and the data field; when the address field matches a self address, a range of target pins is determined according to the pin interval identification and the interval number identification, and a corresponding level setting operation is performed on the target pins according to content of the data field.

[0018] The present application improves the anti-interference capability by using Manchester coding and a clock signal, and cooperates with differential signal transmission, has a high transmission rate, is two orders of magnitude higher than UART and I2C; the self-defined frame structure contains pin interval and number identification, supports burst transmission, has low pin card pin control time consumption, is one order of magnitude lower than I2C, and has higher transmission efficiency. Full-duplex communication is realized by only 3 wires, 64 nodes are supported, the wiring complexity is greatly reduced, and the adaptive clock adjustment and pin state judgment optimization functions are simultaneously provided, the compatibility, stability, and low power consumption are taken into account, and the chip interconnection demand in multiple scenes is adapted. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0020] Figure 1A flow chart of a chip interconnection communication method based on Manchester coding is provided for the embodiment of the present application.

[0021] Figure 2 An IP framework schematic diagram of a master device end DTP Master is provided for the embodiment of the present application.

[0022] Figure 3 A timing diagram when a Manchester coding mode is used to modulate a signal is provided for the embodiment of the present application.

[0023] Figure 4 An IP framework schematic diagram of a slave device end DTP Slave is provided for the embodiment of the present application.

[0024] Figure 5 A schematic diagram of a chip interconnection communication system based on Manchester coding is provided for the embodiment of the present application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0026] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0027] As Figure 1As shown, the embodiment of the present application discloses a chip interconnection communication method 100 based on Manchester coding, comprising the following method steps: S1, a master device generates and sends a communication frame, the physical layer signal of the communication frame is modulated by Manchester coding, wherein the frame start and frame end are defined by a high level lasting two effective data widths followed by a two-low-level mark sequence; the communication frame contains the following fields arranged in sequence at the data link layer: synchronization code, address field, control field, data field and end code; wherein the address field is used for addressing a specific slave device, the control field at least includes pin interval identification and interval number identification, the pin interval identification is used to specify a pin control interval inside the slave device, each pin control interval corresponds to a group of continuous input / output pins, the interval number identification is used to specify the number of continuously controlled pin intervals in one transmission, each bit of the data field corresponds to the level state of a specific pin in a specified pin control interval; the master device provides a clock signal used by Manchester coding data to the slave device at the same time of sending the communication frame, so that the slave device performs signal synchronization and decoding; S2, the slave device receives the clock signal and Manchester coding signal, decodes the Manchester coding signal using the clock signal, identifies the frame start mark, and analyzes the address field, control field and data field; when the address field matches the own address, the range of the target pin is determined according to the pin interval identification and interval number identification, and the target pin is executed corresponding level setting operation according to the content of the data field.

[0028] In some embodiments, for step S1, according to the embodiment of the present application, the master device needs to complete the construction of the communication frame, the physical layer modulation and the sending of the synchronous clock, and specifically, the implementation of each link is as follows.

[0029] For the construction of the communication frame data link layer field, specifically, the master device first constructs the communication frame in the data link layer in the order of "synchronization code-address field-control field-data field-end code".

[0030] Among them, regarding the construction of the synchronization code, exemplarily, the synchronization code length is set to 4 bits, and its value needs to be consistent with the frame start mark sequence, that is, corresponding to the logic state of "high level lasting two effective data widths followed by two low levels". In actual implementation, the master device pre-sets the synchronization code to a fixed value through the internal register, such as write_cmd register associated field, for example, when the logic level corresponding to the effective data width is 1 bit, the 4-bit value of the synchronization code is 1100, that is, the high level corresponds to logic 1 and the low level corresponds to logic 0, so as to ensure that the slave device can accurately identify the starting position of the frame.

[0031] Regarding the construction of the address field, for example, the address field is used to address a specific slave device, and its length needs to be determined according to the number of slave devices. In a preferred embodiment of the present invention, if the chip interconnect system includes 8 boards, and each board contains 8 slave devices, then the address field is divided into 3 bits for the board address and 3 bits for the chip select address, for a total of 6 bits.

[0032] Specifically, the master control device reads the addressing instructions issued by the host computer and converts the board address and chip select address into corresponding binary values ​​in its internal logic circuitry. For example, when addressing the third slave device on the second board, the board address is set to 010, the chip select address is set to 011, and the overall address field is 010011. Understandably, the length of the address field can be flexibly adjusted according to the system scale. If the number of slave devices is larger, the number of bits in the board address and chip select address can be expanded, for example, both can be expanded to 4 bits to support the addressing requirements of 16 boards, each with 16 slave devices.

[0033] Regarding the construction of the control field, for example, the control field includes at least a pin range identifier and a range quantity identifier, both of which are implemented through the register configuration of the master device. The pin range identifier is typically set to 4 bits in length, used to specify a pin control range within the slave device. Each pin control range corresponds to 32 consecutive input / output pins, meaning 32 bits of data correspond to one range.

[0034] For example, if the device has 288 pins, or 9 intervals, the pin interval identifier ranges from 0000 to 1000, corresponding to intervals 0-8. The master device writes the corresponding pin interval identifier in the control field according to the starting position of the pin to be controlled. For example, if the pin to be controlled starts from pins 32-63, i.e., the second interval, the pin interval identifier is set to 0001. The interval quantity identifier is also set to 4 bits, with a value range of 0000-1111, corresponding to intervals 1-16. The master device determines its value based on the number of consecutive intervals to be controlled at once. For example, if intervals 2-4, i.e., a total of 3 intervals, need to be controlled, the interval quantity identifier is set to 0010, i.e., the quantity is 2, corresponding to "the quantity indicated by the interval quantity identifier plus 1 = 3".

[0035] Regarding the construction of the data field, for example, the length of the data field is determined by the interval quantity identifier, specifically the product of 32 bits and (the quantity indicated by the interval quantity identifier plus 1). In implementation, the master control device first generates the logic level corresponding to each pin according to the level requirements of the pin to be controlled, where high level is 1 and low level is 0. Then, these levels are grouped according to pin intervals, with each group of 32 bits corresponding to the data of one pin control interval.

[0036] For example, when the interval number is 0010, which corresponds to 3 intervals, the data field length is 32 bits x 3 = 96 bits, and the master device fills the level states of the 32 x 3 = 96 pins of the 2nd-4th intervals into the data field in turn to form a continuous binary data stream.

[0037] The end code is constructed, for example, in the same structure as the synchronization code, that is, 4 bits of 1100, which corresponds to "two high levels and two low levels", and the master device appends the end code to the end of the communication frame after the data field is constructed to identify the end of the frame.

[0038] In one embodiment, after the data link layer frame structure is constructed, the master device modulates the entire communication frame by Manchester coding, as shown in Figure 2 The master device end provided in the embodiment provides an IP framework diagram of a data transmission protocol host (DTP Master), and the process is implemented by a dedicated coding module, such as a Figure 2 Manchester coding module in FIG. 2. As shown in Figure 3 A Manchester coding mode modulation signal timing diagram is adopted, and specifically, the coding module modulates each bit of the logic level of the communication frame according to the following rules: when the logic level is "1", the coding module outputs a signal of "high level jump to low level", that is, in a symbol period, the first half period is high level and the second half period is low level; when the logic level is "0", the coding module outputs a signal of "low level jump to high level", that is, in a symbol period, the first half period is low level and the second half period is high level.

[0039] For example, if the logic sequence of a certain 4-bit in the communication frame is 1011, after Manchester coding, the signal waveform is: the first symbol, that is, logic 1: high→low; the second symbol, that is, logic 0: low→high; the third symbol, that is, logic 1: high→low; and the fourth symbol, that is, logic 1: high→low.

[0040] Thus, by this coding mode, each bit of data contains a level jump, which can ensure that the slave device realizes clock synchronization through the jump edge in the receiving process, and avoids the error code caused by clock drift in traditional asynchronous communication.

[0041] In one embodiment, while sending the Manchester coded signal, the master device can generate and send a clock signal along the way for the slave device to synchronize and decode the signal.

[0042] Specifically, the frequency of the accompanying clock signal is consistent with the symbol rate of the Manchester encoding, for example, if the symbol rate of the encoded data is 20MHz, and each symbol period is 50ns, then the frequency of the accompanying clock signal is also set to 20MHz. In hardware implementation, the master device generates the clock signal through an internal clock generator, such as the PLL module of the FPGA, and transmits it to all slave devices through a dedicated clock signal line. It can be understood that the frequency of the accompanying clock signal can be adjusted according to system requirements, and its range is usually 10KHz-15MHz, in order to balance the communication rate and signal stability.

[0043] In some embodiments, for step S2, the slave device needs to complete the reception, decoding, field analysis and pin control operation of the accompanying clock signal and the Manchester encoding signal.

[0044] Specifically, please refer to Figure 4 The data transfer protocol slave (DTP Slave) IP framework diagram shown in the slave device end, the slave device receives the accompanying clock signal and the Manchester encoding signal sent by the master device through a dedicated signal receiving port, wherein the accompanying clock signal is connected to the clock input end of the slave device as the synchronous clock of the decoding process; the Manchester encoding signal is connected to the data input end, and is decoded by the Manchester decoding module in the slave device, such as Figure 4 .

[0045] Specifically, the decoding module takes the accompanying clock signal as the reference, samples the level jump of the Manchester encoding signal at the rising edge or the falling edge of each clock period, and restores the original logic level according to the jump direction: if a "high level jump to low level" is sampled, it is decoded as logic "1"; if a "low level jump to high level" is sampled, it is decoded as logic "0".

[0046] For example, the waveform of a certain segment of Manchester encoding signal received by the slave device is "high→low→low→high→high→low", that is, corresponding to 3 symbol periods, then the decoding module restores the logic 1, logic 0, and logic 1 in turn according to the jump direction, so as to obtain the original data sequence.

[0047] In one embodiment, the decoding module continuously monitors the synchronization code, i.e. the frame start flag sequence, while restoring the original data. When 4 bits of 1100, i.e. "two high levels and two low levels", are continuously detected, it is determined that it is a frame start, and then the address field, the control field, the data field and the end code are analyzed in turn according to the field order of the data link layer.

[0048] Specifically, for address field parsing, for example, the slave device internally stores its own board address and chip select address, which are set by hardware pin configuration or initialization register, the parsing module splits the received address field into board address and chip select address, and compares them with the stored addresses. If they completely match, it is determined that the slave device is addressed, and the subsequent field is parsed; if they do not match, the communication frame is ignored, and the subsequent parsing operation is stopped.

[0049] For control field parsing, the addressed slave device parses the pin interval identifier and interval number identifier in the control field to determine the pin range to be controlled. For example, if the pin interval identifier is 0001 corresponding to the 2nd interval and the interval number identifier is 0010 corresponding to 3 intervals, the pin range to be controlled is the 2nd-4th interval, 32x3=96 pins.

[0050] For data field parsing, for example, the parsing module determines the length of the data field according to the interval number identifier, splits the data field into multiple sub-data of 32 bits each, and each sub-data corresponds to the pin level configuration of one pin interval. For example, when the data field length is 96 bits, it is split into 3 32-bit sub-data, which correspond to the pin levels of the 2nd-4th interval.

[0051] For end code parsing, for example, when 1100 of 4 bits is parsed, it is determined that the frame is ended, and the parsing of the entire communication frame is completed.

[0052] After completing the field parsing, the slave device performs level setting operation on the target pins according to the pin range and data field content obtained by parsing, through the internal IO control module, such as the IO Ctrl module in Figure 4 Specifically, the IO control module associates each bit of each 32-bit sub-data with the corresponding pin, and if a bit is logic 1, the corresponding pin is set to high level; if it is logic 0, it is set to low level.

[0053] For example, the 32-bit sub-data of the 2nd interval is 0xFFFFFFFF, i.e. all 1s, and the IO control module sets all 32 pins of the 2nd interval to high level; if the sub-data is 0x00000000, i.e. all 0s, the pins are all set to low level. It can be understood that the IO control module needs to have fast response capability to ensure that the pin level configuration is completed in time after the communication frame is received, reducing control delay.

[0054] In one embodiment, optionally, to verify the validity of the communication link, the control field further includes a read-back enable bit. When communication verification is needed, the master device first sets the state of the read-back enable bit in the control field.

[0055] Specifically, the readback enable bit is usually 1 bit, and a high level, i.e., a logic 1, indicates validity, and a low level, i.e., a logic 0, indicates invalidity. The host device sets the readback enable bit to 1 by configuring a bit 1 of an internal register, such as a write_cmd register, while keeping other fields, such as an address field, a pin range identifier, and a range number identifier, normally configured, for example, the address field points to the slave device to be verified, and the pin range identifier and the range number identifier can be set to default values. Subsequently, the host device encodes the communication frame containing the readback enable bit into a Manchester code according to the procedure of step S1, and sends the Manchester code to the slave device together with a clock signal.

[0056] When parsing the communication frame, if the readback enable bit in the control field is detected to be valid, i.e., a logic 1, the addressed slave device stops waiting for the subsequent data field after receiving the address field and the control field, and immediately starts to generate a response frame. Specifically, a control module of the slave device, such as a CPLD Ctrl module in the CPLD, directly takes the received address field and control field as the core data link layer content of the response frame, and adjusts the readback enable bit and the read / write bit therein. Figure 4

[0057] Specifically, the slave device sets the readback enable bit in the response frame to a preset invalid value, such as a logic 0, to distinguish the response frame from the original instruction frame sent by the host device; the slave device sets the read / write bit in the response frame to a preset "slave device write" state, such as a logic 0, and if the read / write bit in the original instruction frame is a logic 1 of "host device read", to identify that the frame is the response data sent by the slave device to the host device; after the response frame is constructed, the slave device encodes the response frame through a Manchester encoding module of the slave device, according to the same encoding rule as the host device, for example, a logic 1 = high→low, and a logic 0 = low→high, to generate a Manchester encoded signal, and sends the Manchester encoded signal back to the host device through a dedicated response signal line, such as a CPLD sending signal line when the slave device is a CPLD. It should be noted that, since only one slave device is addressed at the same time, bus conflict caused by multiple slave devices sending response frames at the same time does not occur.

[0058] After sending the communication frame containing the readback enable bit, the host device immediately switches to a receiving state, receives the Manchester encoded response signal sent by the slave device through an internal decoding module, such as a manchester decoding module in the CPLD, and decodes the Manchester encoded response signal based on a clock signal. Figure 2

[0059] ​​Specifically, if the address field in the response frame is consistent with the address field of the original instruction frame, and the fields in the control field, except the read-back enable bit and the read-write bit, such as the pin interval identifier and the interval number identifier, are consistent with the original fields, it is determined that the communication is normal, and the link validity verification is passed. If the fields in the response frame are inconsistent with the original fields, or the response frame is not received within a preset timeout time, such as 50us, it is determined that the communication is abnormal, and the master device can trigger a retry mechanism, such as resending a read-back instruction or an alarm mechanism, to prompt the user to troubleshoot the link problem.

[0060] For example, in the original instruction frame sent by the master device, the address field is 010011, that is, the 3rd slave device of the 2nd board card, the control field is 1, that is, the read-back enable bit, 0, that is, the read-write bit, 0001, that is, the pin interval identifier, and 0010, that is, the interval number identifier. In the response frame generated by the slave device, the address field is still 010011, the control field is changed to 0, that is, the read-back enable bit, 0, that is, the read-write bit, 0001, that is, the pin interval identifier, and 0010, that is, the interval number identifier. After the master device decodes the response frame, the key parts of the address field and the control field, such as the pin interval identifier and the interval number identifier, are consistent, so it is determined that the communication is normal.

[0061] In one embodiment, preferably, to support the read operation of the master device on the pin level of the slave device, the control field further includes a read-write bit, which is implemented on the basis of the basic communication flow by adding the data acquisition and return link of the slave device.

[0062] Specifically, when the master device needs to read the current level state of a pin interval of the slave device, the state of the read-write bit in the control field is first set. Specifically, the read-write bit is 1 bit, and logic 1 usually represents "read operation" and logic 0 represents "write operation".

[0063] The master device sets the read-write bit to 1 by configuring the bit0 of the internal register, such as the write_cmd register, and specifies the slave device to be read in the address field, specifies the pin range to be read in the pin interval identifier and the interval number identifier, for example, the pin interval identifier 0010 and the interval number identifier 0001, corresponding to the 3rd-4th interval. Then, the master device encodes the communication frame containing the "read operation" read-write bit according to the flow of step S1, and sends it to the slave device together with the clock signal.

[0064] The addressed slave device, when parsing the communication frame, if the read-write bit in the control field is detected as "read operation" (i.e. logical 1), collects the current level state of the specified pin interval through the internal IO control module. Specifically, the IO control module determines the pin range to be collected according to the pin interval identifier and the interval quantity identifier, and samples the level of each pin in real time: if the pin is sampled as high level, it is recorded as logical 1; if the pin is sampled as low level, it is recorded as logical 0.

[0065] After sampling is completed, the IO control module will, for example, as shown in Figure 4 , arrange the sampling results of each pin interval of the IO Ctrl module into sub-data in groups of 32 bits, for example, the 3rd-4th interval to be read, i.e. a total of 2 intervals containing 64 pins, generates two 32-bit sub-data after sampling, corresponding to the pin level state of the 3rd interval and the 4th interval respectively.

[0066] After the slave device completes the pin level collection, a response frame containing the sampling data is generated. Specifically, the data link layer structure of the response frame is consistent with the communication frame sent by the master device, including synchronization code, address field, control field, data field and end code: synchronization code and end code: consistent with the basic flow of the foregoing embodiment, both are 4 bits of 1100; address field: consistent with the address field in the instruction frame of the master device, to identify the slave device corresponding to the response frame; control field: read-write bit is set to "slave device write" state, i.e. logical 0, pin interval identifier and interval quantity identifier are consistent with the instruction frame, read-back enable bit is set to invalid, i.e. logical 0; data field: length is 32 bits x (interval quantity identifier + 1), containing sub-data of each pin interval collected by the IO control module.

[0067] Subsequently, the slave device encodes the response frame through the Manchester encoding module, for example, as shown in Figure 4 , and sends it back to the master device through the response signal line. For example, the 3rd interval sub-data collected by the slave device is 0xAAAAAAAA, and the 4th interval sub-data is 0x55555555, and the data field of the response frame is 0xAAAAAAAA55555555, i.e. a total of 64 bits.

[0068] After the master device receives the response frame sent by the slave device, it encodes the response frame through the decoding module, for example, as shown in Figure 2The Manchester decoding module in the data field restores the sample data in the data field and stores it to internal registers, such as read_data0-read_data8 registers. The host computer can obtain the current level state of the device pin by reading these registers, and realize the monitoring of the pin state. For example, the host device decodes the third interval sub-data 0xAAAAAAAA, which corresponds to the pin level alternately high and low, and the fourth interval sub-data 0x55555555, which corresponds to the pin level alternately low and high. Therefore, the host computer can intuitively understand the real-time state of these pins after reading the registers. If it is found that the level of a pin does not match the expected value, further troubleshooting of hardware failure or communication problem can be performed.

[0069] In one embodiment, preferably, the address field is further divided into a board card address and a chip select address, wherein the board card address is used to select a target board card in a plurality of board cards, and the chip select address is used to select a target slave device in a plurality of slave devices on the target board card.

[0070] Specifically, in order to improve the flexibility and accuracy of the slave device addressing, the address field is further divided into a board card address and a chip select address, and the number of bits of the board card address and the chip select address can be flexibly adjusted according to the size of the chip interconnection system.

[0071] In the preferred embodiment of the present application, if the system includes 8 board cards numbered 0-7, and each board card includes 8 slave devices numbered 0-7, the board card address is set to 3 bits, i.e. the value range is 000-111, corresponding to 8 board cards, and the chip select address is set to 3 bits, i.e. the value range is 000-111, corresponding to 8 slave devices, and the total length of the address field is 6 bits. If the system size is larger, for example, it includes 16 board cards, and each board card includes 16 slave devices, the board card address and the chip select address can be both expanded to 4 bits, i.e. the value range is 0000-1111, and the total length of the address field is 8 bits, to meet the addressing requirement of 16x16=256 slave devices.

[0072] The board card address is configured through the hardware pins on the board card, for example, 3 address pins, such as A2, A1, and A0, are set on each board card, and are pulled down or up to low or high level through external resistors to determine the value of the board card address. For example, the A2, A1, and A0 of the board card 0 are all connected to a pull-down resistor, corresponding to low, low, and low levels, and the board card address is 000; the A2 of the board card 1 is connected to a pull-down resistor, the A1 is connected to a pull-down resistor, and the A0 is connected to a pull-up resistor, corresponding to low, low, and high levels, and the board card address is 001; and so on, the A2, A1, and A0 of the board card 7 are all connected to pull-up resistors, corresponding to high, high, and high levels, and the board card address is 111.

[0073] When the slave device is powered on and initialized, the address pin level of the board card is read by the internal level detection module, which is converted into the corresponding board card address and stored in the internal register. When receiving a communication frame, the slave device parses the board card address in the address field and compares it with the stored board card address. If they are inconsistent, the frame is directly ignored; if they are consistent, the chip select address is continued to be parsed.

[0074] The chip select address is configured by the hardware pin of the slave device itself, for example, 3 chip select pins such as S2, S1, S0 are set for each slave device, and the level is configured by external resistance pull-down or pull-up. For example, 8 slave devices on board card 0: S2, S1, S0 of slave device 0 are all pulled down, and the chip select address is 000; S2 of slave device 1 is pulled down, S1 is pulled down, and S0 is pulled up, and the chip select address is 001; …… S2, S1, S0 of slave device 7 are all pulled up, and the chip select address is 111.

[0075] When the slave device is powered on and initialized, the chip select pin level of the slave device is read by the level detection module, which is converted into the chip select address and stored. After the board card address is matched, the slave device parses the chip select address in the address field and compares it with the stored chip select address. If they are consistent, it is determined that the slave device is the addressed device, and the subsequent parsing is continued; if they are inconsistent, the frame is ignored.

[0076] Through the subdivision of the board card address and the chip select address, the precise addressing of each slave device in the system can be realized, and the addressing confusion problem of a single address field when the number of slave devices is large can be avoided. For example, in a system containing 8 board cards x 8 slave devices = 64 slave devices, each slave device can be uniquely identified by 3-bit board card address and 3-bit chip select address, ensuring that the master device can accurately communicate with the target slave device.

[0077] In some embodiments, preferably, in order to improve the anti-interference ability and transmission distance of signal transmission, conversion between single-ended signal and differential signal is adopted on the hardware link, which is implemented as follows: for the master device, the Manchester encoding signal and the clock signal output by the master device such as FPGA are single-ended signals, i.e. level signals relative to ground, which need to be converted into differential signals by a single-ended to differential chip before transmission.

[0078] Specifically, the single-ended signal output pin of the master device is connected to the single-ended input pin of the single-ended to differential chip, and the differential output pin of the chip is connected to the backplane or transmission cable through a twisted pair. For example, the Manchester encoding single-ended signal (TX) of the master device is connected to the DI pin of the chip, the clock single-ended signal (CLK) is connected to another DI pin of the chip, and the A and B pins of the chip output corresponding differential signals, i.e. TX+, TX- and CLK+, CLK-.

[0079] The working principle of the single-ended to differential chip is to convert a single-ended signal into a pair of differential signals with opposite phases and equal amplitudes. For example, when the input single-ended signal is high, the differential output TX+ is high and TX- is low; when the input single-ended signal is low, the differential output TX+ is low and TX- is high.

[0080] Therefore, this differential transmission method can effectively suppress common-mode interference, such as electromagnetic interference between cables, because the interference signal will act on both lines of the differential pair at the same time, and the receiving end only pays attention to the level difference between the two lines, thereby reducing the impact of interference on the signal.

[0081] For the slave device, the slave device such as CPLD receives the differential signal sent by the master device through the differential to single-ended chip and restores it to a single-ended signal.

[0082] Specifically, the differential signal (TX+, TX- and CLK+, CLK-) is transmitted to the differential to single-ended chip at the slave device end through the twisted pair cable, which matches the chip model at the master device end. The differential input pins (A, B) of the chip receive the differential signal, and the single-ended output pin (RO) outputs the restored single-ended signal, which is connected to the Manchester encoded signal receiving pin and the clock signal receiving pin of the slave device, respectively.

[0083] The working principle of the differential to single-ended chip is to detect the level difference between the two lines of the differential pair and restore the original single-ended signal. For example, when the input differential signal TX+ is high and TX- is low, the chip outputs a high single-ended signal; when the input differential signal TX+ is low and TX- is high, the chip outputs a low single-ended signal.

[0084] Through this conversion, the slave device can obtain a single-ended signal consistent with the transmission end of the master device, ensuring the correctness of the subsequent decoding and parsing process.

[0085] The use of differential signal transmission has the following advantages: strong anti-interference ability: the differential signal has much better common-mode interference suppression ability than the single-ended signal, and is suitable for long-distance transmission in complex electromagnetic environments such as transmission distance exceeding 1 meter; long transmission distance: the differential signal has less attenuation, and can achieve longer transmission distance than the single-ended signal; reduced electromagnetic radiation: the electromagnetic fields generated by the two lines of the differential signal cancel each other out, reducing the electromagnetic radiation to the surrounding circuit.

[0086] In addition, the following matters need to be paid attention to in hardware design: the differential pair cable needs to be twisted pair, and the lengths of the two lines need to be consistent to avoid signal skew caused by the time delay difference of the differential signal; the single-ended to differential chip and the differential to single-ended chip need to be close to the signal transmission end and the receiving end to reduce the transmission distance of the single-ended signal on the board and reduce the interference on the board; the power and ground pins of the chip need to be well filtered, such as adding decoupling capacitors, to avoid the influence of power supply noise on the signal conversion performance of the chip.

[0087] In some embodiments, to further reduce the number of signal lines, the transmission of the clock signal can be cancelled, and the clock signal can be embedded in the Manchester encoded data, and the slave device can recover the clock by a digital phase-locked loop (DPLL).

[0088] Specifically, the Manchester encoding itself has the characteristic that each bit of data contains a level jump, and this jump can be used as a carrier of the clock information. Therefore, in some preferred embodiments, the transmission of the clock signal can be cancelled.

[0089] Specifically, in the Manchester encoding process, there is a level jump in each symbol period, i.e., a logic 1 is high→low, and a logic 0 is low→high. The edges of these jumps are the potential triggering edges of the clock. For example, when the symbol rate is 20 MHz, there is a level jump in every 50 ns, and the interval between these jump edges is the clock period, thereby realizing the fusion of the clock signal and the data signal.

[0090] The slave device extracts the clock signal from the Manchester encoded data by an internal digital phase-locked loop (DPLL) module. The working process of the DPLL includes three links of phase detection, loop filtering, and voltage-controlled oscillator (VCO) adjustment, which are as follows: phase detection: the phase detector of the DPLL compares the phase of the input Manchester encoded data signal and the local clock signal output by the VCO, and detects the phase difference between them. Since there is a jump in each symbol period of the Manchester encoded data, the phase detector takes these jump edges as the reference to judge the phase relationship between the local clock and the data jump edges, including leading, lagging, or being consistent; loop filtering: the phase difference signal output by the phase detector usually contains high-frequency noise, and the loop filter such as a low-pass filter filters the signal to remove the noise and generate a smooth control voltage; VCO adjustment: the control voltage acts on the VCO to adjust the frequency and phase of the local clock output by the VCO. If the phase of the local clock lags behind the data jump edge, the VCO increases the clock frequency so that the phase of the local clock leads; if the phase of the local clock leads the data jump edge, the VCO reduces the clock frequency so that the phase of the local clock lags; until the phase of the local clock is consistent with the data jump edge, the clock is locked.

[0091] For example, when the slave device receives the Manchester encoded data, the DPLL first detects the first jump edge of the data to adjust the local clock based on the jump edge. If the current frequency of the local clock is 19 MHz, the period is about 52.6 ns, and it lags behind the data jump edge with a period of 50 ns, the phase detector outputs a lag signal, the loop filter generates a positive control voltage, and the VCO increases the clock frequency to 20 MHz, so that the period of the local clock is consistent with the symbol period of the data, the phase is aligned, and the clock recovery is completed.

[0092] The advantage of canceling the clock signal and using the DPLL to recover the clock is that the number of signal lines is reduced from the original 3 signal lines, including the clock line, the FPGA sending line and the CPLD sending line, to 2, that is, the FPGA sending line and the CPLD sending line, and the hardware wiring is further simplified; the wiring complexity is reduced; the clock line and the data line do not need to be strictly equal in length, and the hardware design difficulty is reduced.

[0093] This mode is suitable for scenarios where the number of signal lines is strictly required and the slave device has DPLL resources, such as high-end CPLD or FPGA. It should be noted that if there are consecutive same logic levels in the Manchester encoded data, it should be noted that although Manchester encoding has a transition for each bit, the transition may be lost due to noise in actual transmission, which may cause the DPLL clock to lose lock, so a synchronization code needs to be inserted in the communication frame, such as once every certain length of data transmission, to ensure that the DPLL clock is continuously locked.

[0094] According to the embodiment of the application, by setting the interval number identifier to a value greater than or equal to zero, the burst transmission function of continuously controlling multiple pin intervals in one communication frame transmission can be realized.

[0095] Specifically, the interval number identifier is a 4-bit field in the control field, and the value range is 0000-1111, corresponding to “the number indicated by the interval number identifier plus 1” consecutive intervals, that is, the value 0000 corresponds to 1 interval, the value 0001 corresponds to 2 intervals, …, and the value 1111 corresponds to 16 intervals. The master control device configures the value of the interval number identifier in the internal register according to the number of consecutive intervals to be controlled at a time. For example, if the first to fifth intervals, that is, a total of five consecutive intervals, need to be controlled at a time, the interval number identifier is set to 0100, that is, the number is 4, and 4+1=5 intervals.

[0096] The length of the data field dynamically changes with the value of the interval number identifier, specifically 32bit×(interval number identifier+1). After the master control device configures the interval number identifier, it determines the length of the data field according to the identifier, and fills the pin level data of multiple consecutive intervals into the data field in sequence. For example: when the interval number identifier is 0000, that is, 1 interval, the data field length is 32bit×1=32bit, and only contains the pin level data of 1 interval; when the interval number identifier is 0010, that is, 3 intervals, the data field length is 32bit×3=96bit, and contains the pin level data of 3 consecutive intervals such as the second to fourth intervals; when the interval number identifier is 1111, that is, 16 intervals, the data field length is 32bit×16=512bit, and contains the pin level data of 16 consecutive intervals.

[0097] In the data field construction process, the host device needs to ensure that the order of the interval data is consistent with the starting interval order specified by the pin interval identifier, for example, the pin interval identifier is 0010, that is, the third interval, and the interval number identifier is 0010, that is, 3 intervals, then the data field is filled with 32-bit data of the third, fourth, and fifth intervals in turn, to avoid pin control errors caused by disordered data.

[0098] When the slave device parses the communication frame, the interval number identifier is used to determine the number and length of the intervals contained in the data field, and the 32-bit data of each interval is parsed in order and is correspondingly set to the level of the corresponding pin interval.

[0099] For example, the slave device parses the pin interval identifier as 0010, that is, the third interval, and the interval number identifier as 0010, that is, 3 intervals, then the first 32 bits of the data field are parsed as the level data of the third interval, the middle 32 bits are parsed as the level data of the fourth interval, and the last 32 bits are parsed as the level data of the fifth interval, and then the IO control module simultaneously sets the levels of the 96 pins of the three intervals.

[0100] The advantage of the burst transmission function is to reduce the number of communication frame transmissions and improve control efficiency. For example, if 512 pins of 16 intervals need to be controlled, only one communication frame needs to be sent for burst transmission; if burst transmission is not supported, one frame needs to be sent for each interval, a total of 16 frames, and the communication efficiency is significantly reduced. Therefore, this function is particularly suitable for scenarios that need to control a large number of pins at the same time, such as multi-pin parallel configuration in chip testing.

[0101] According to the embodiment of the application, to ensure that the host device can accurately identify the data type in the response frame of the slave device, the slave device uses the structure of "header and data" when sending the response frame, and the implementation is as follows: for the construction of the response frame header, the header of the response frame contains a synchronization code, an address field, and a control field, and the construction rule is consistent with the communication frame sent by the host device: the synchronization code is 1100 of 4 bits, used to identify the start of the response frame; the address field is consistent with the address field in the instruction frame of the host device, to ensure that the host device identifies the slave device corresponding to the response frame; the control field: the key adjustment is in the read-write bit, which needs to be set to a state indicating "the slave device writes to the host device" such as logic 0, to clearly indicate that the frame is data sent by the slave device; other fields such as the pin interval identifier and the interval number identifier are consistent with the instruction frame, to indicate the pin range corresponding to the data; the read-back enable bit is set to be invalid, that is, logic 0, to avoid confusion with the read-back verification function.

[0102] For example, in the read instruction frame sent by the master device, the address field is 001010, i.e., the 1st card and the 5th chip slave device, the control field is 1 (read / write bit, read), 0 (read back enable bit), 0100 (pin interval identifier, 5th interval), and 0001 (interval number identifier, 2 intervals). In the header of the response frame, the address field is still 001010, the control field is changed to 0 (read / write bit, slave device write), 0 (read back enable bit), 0100 (pin interval identifier), 0001 (interval number identifier), and the synchronization code is 1100.

[0103] For the construction of the data part of the response frame, the data part, i.e., the data field, of the response frame contains the pin level data collected by the slave device, and the length is 32bit x (interval number identifier + 1), which corresponds to the interval number identifier in the header control field. For example, when the interval number identifier is 0001, i.e., 2 intervals, the data part has a length of 64 bits, containing the pin level sampling data of the 5th interval and the 6th interval.

[0104] In the construction of the data part, the slave device needs to ensure that the order of the data is consistent with the order of the pin intervals, i.e., 32bit data of the starting interval is filled first, and then the data of the subsequent intervals is filled in sequence, to avoid the problem of data and interval mismatch when the master device parses.

[0105] For example, the master device can parse the "header and data" structure of the response frame, which can include the following steps: after the master device receives the response frame, it first parses the synchronization code, the address field and the control field in the header: the start of the frame is determined by the synchronization code; the corresponding slave device of the response frame is confirmed by the address field, which is compared with the address of the instruction frame sent by the master device to ensure the correct source; the data corresponding to the pin range is determined by the read / write bit in the control field, i.e., logical 0, which identifies the frame as the slave device writing data.

[0106] After the header is parsed correctly, the master device determines the length of the data part according to the interval number identifier, parses the pin level data of each interval, and stores it in the corresponding register. For example, the master device parses the interval number identifier in the header of the response frame as 0001, i.e., 2 intervals, then extracts the first 32 bits from the data part as the data of the 5th interval, and the last 32 bits as the data of the 6th interval, and stores them in the read_data4 and read_data5 registers respectively. Here, it is assumed that the interval 0 corresponds to read_data0.

[0107] Therefore, through the structure of "header and data", the master device can quickly distinguish the type of response frame, such as read response, read back verification response, etc., and clearly determine the pin range corresponding to the data, avoiding data parsing errors, especially when communicating with multiple slave devices at the same time, which can effectively improve the accuracy and efficiency of response frame processing.

[0108] In some embodiments, preferably, to adapt to different channel quality and slave synchronization capability, the master device can dynamically adjust the clock rate of the Manchester coded signal, achieving adaptive matching.

[0109] Specifically, before initiating formal data transmission, the master device first sets an initial clock rate, such as 10 MHz, which is usually a medium rate supported by the system, taking into account transmission efficiency and stability. Subsequently, the master device constructs a read-back test frame, which has the same structure as the read-back verification frame, i.e., the read-back enable position in the control field is valid, i.e., logic 1, the address field points to the target slave device, and the other fields are set to default values. The master device generates a clock signal along with the read-back test frame according to the initial clock rate, Manchester encodes the read-back test frame, and sends it to the slave device.

[0110] After sending the read-back test frame, the master device starts an internal timeout timer, which can be preset to a timeout time, such as 50 us, and waits for a response frame from the slave device. Specifically, if a response frame sent by the slave device is received within the timeout time, and the address field and control field in the response frame, except for the read-back enable bit and the read-write bit, are consistent with the test frame, it is determined that the current clock rate is suitable for the current channel quality and slave synchronization capability, and the master device initiates formal data transmission at this clock rate. If no response frame is received within the timeout time, or the received response frame fields are inconsistent with the test frame, it is determined that the current clock rate is too high, causing the slave device to fail to synchronize decoding or the channel error rate to be too high. At this time, the master device reduces the clock rate by one step, such as from 10 MHz to 8 MHz, resets the timeout timer, reconstructs and sends a read-back test frame, and repeats the above detection process. If the clock rate is reduced to the lowest threshold supported by the system, such as 10 KHz, and no correct response is received, it is determined that there is a fault in the communication link, such as a hardware connection error or a slave device failure, and the master device stops adjusting the clock rate and triggers an alarm mechanism, such as sending a fault prompt to the upper computer.

[0111] For example, the initial clock rate of the master device is set to 15 MHz, and after sending the read-back test frame, no response is received within the timeout time. The rate is reduced to 12 MHz, the test frame is sent again, and no response is still received. The rate is further reduced to 10 MHz, and after sending the test frame, a correct response is received, so 10 MHz is used as the clock rate for formal transmission.

[0112] The adaptive clock rate adjustment has the advantages of improving system compatibility, adapting to the synchronization capability difference of different models of slave devices, for example, the synchronization capability of some low-end CPLDs is weak and only supports a lower clock rate, while high-end CPLDs can support a higher rate; improving communication stability, automatically reducing the clock rate when the channel quality is poor, such as long transmission distance and strong electromagnetic interference, to reduce the bit error rate; maintaining a higher clock rate when the channel quality is good to ensure transmission efficiency; and fault diagnosis capability, which can preliminarily judge the cause of communication failure through the clock rate adjustment process. If there is still no response after being reduced to the minimum rate, it is probably a hardware failure, which facilitates subsequent troubleshooting.

[0113] This function is suitable for systems with unstable channel quality or diverse models of slave devices, such as multi-board distributed test systems. The slave devices of different boards may come from different manufacturers and have different synchronization capabilities. Adaptive adjustment can ensure the communication stability of the entire system.

[0114] In some embodiments, preferably, to reduce unnecessary bus transactions and reduce bus load, the master device can dynamically decide whether to send a communication frame and adjust the frame content according to the pin state change.

[0115] Specifically, the master device maintains a "current pin state register" inside, which stores the level state of each pin after the last control. Before initiating a new control operation, the master device compares the level state of the pin to be controlled this time, i.e., the new state, with the state in the current pin state register, i.e., the old state, bit by bit, to determine whether the pin state has changed: no change: if the new state of all pins to be controlled is completely consistent with the old state, such as all bits are equal, it is determined that no level adjustment is needed, and the sending of this communication frame is cancelled; partial change: if only part of the new state of the pin interval is inconsistent with the old state, record the range of the pin interval that has changed, such as the 2nd and 4th intervals;

[0116] full change: if the new state of all pins to be controlled is inconsistent with the old state, control all pin intervals as planned.

[0117] For example, the state of the 2nd interval in the current pin state register is 0xFFFFFFFF, i.e., all high, the state of the 3rd interval is 0x00000000, i.e., all low, and the state of the 4th interval is 0xAAAAAAAA, i.e., alternating; the new state to be controlled this time is that the 2nd interval is still 0xFFFFFFFF, the 3rd interval is changed to 0xFFFFFFFF, and the 4th interval is changed to 0x55555555. After comparison, it is found that the 2nd interval has no change, and the 3rd and 4th intervals have changes, and the changed interval is recorded as the 3rd and 4th intervals.

[0118] According to the judgment result of the pin state change, the master device dynamically adjusts the communication frame, specifically including canceling sending: if all does not change, the master device directly terminates the communication frame construction process and does not occupy the bus resource; adjusting field and sending: if part changes, the master device adjusts the pin interval identifier and interval number identifier of the communication frame, and only the pin interval that changes is included in the control range; pin interval identifier: set to the starting interval that changes, such as the third interval, identified as 0011; interval number identifier: set to the number of intervals that change minus 1, such as the change interval is the third and fourth intervals, a total of 2 intervals, identified as 0001; data field: only fill in the new state data of the changed interval, such as 0xFFFFFFFF for the third interval and 0x55555555 for the fourth interval.

[0119] Subsequently, the master device generates a Manchester encoding signal and a clock signal according to the adjusted frame structure and sends it to the slave device. After the slave device parses, only the pin interval that changes is set to the level, and the interval that does not change remains the original state.

[0120] The advantages of this optimization method are: reducing bus load: reducing unnecessary communication frame sending, especially when the pin state changes frequently but the change range is small, the number of bus transactions can be significantly reduced; improving transmission efficiency: the data field length of the communication frame is shortened, the transmission time is reduced, and the overall control efficiency is improved; reducing slave device power consumption: the slave device only needs to operate the changed pin interval, and does not need to repeatedly process the unchanged pin, reducing power consumption.

[0121] In implementation, it needs to be noted that the "current pin state register" of the master device needs to be updated in time, and after sending the communication frame and confirming that the slave device executes successfully, the new pin state needs to be written into the register to ensure the accuracy of subsequent comparison. If no confirmation response is received from the slave device after sending the communication frame, such as burst transmission without readback, the register is not updated temporarily to avoid judgment errors caused by inconsistent states.

[0122] Figure 5 A chip interconnection communication system 500 based on Manchester encoding is shown. The system embodiment and Figure 1The method embodiment shown corresponds to, and specifically includes: a master device and a slave device, wherein the master device is configured to generate and send a communication frame, a physical layer signal of the communication frame being modulated using Manchester coding, wherein a frame start and a frame end are defined by a flag sequence of a high level lasting two valid data widths followed by two low levels; the communication frame comprises, in a data link layer, the following fields arranged in sequence: a synchronization code, an address field, a control field, a data field, and an end code; wherein the address field is configured to address a specific slave device, the control field includes at least pin interval identification and interval number identification, the pin interval identification is configured to specify one pin control interval inside the slave device, each pin control interval corresponds to a group of continuous input / output pins, the interval number identification is configured to specify the number of continuously controlled pin intervals in one transmission, and each bit of the data field corresponds to the level state of a specific pin in a specified pin control interval; the master device provides a clock signal used by Manchester coding data to the slave device at the same time of sending the communication frame, so that the slave device performs signal synchronization and decoding; wherein the slave device is configured to receive the clock signal and the Manchester coding signal, decode the Manchester coding signal using the clock signal, identify the frame start flag, and analyze the address field, the control field, and the data field; when the address field matches the own address, the range of a target pin is determined according to the pin interval identification and the interval number identification, and a corresponding level setting operation is performed on the target pin according to the content of the data field.

[0123] The above merely describes specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A Manchester coding based chip interconnection communication method, applied to a chip interconnection system comprising a master device and at least one slave device, characterized in that, The method comprises the following steps: S1, a master device generates and sends a communication frame, a physical layer signal of the communication frame is modulated by Manchester coding, wherein a frame start and a frame end are defined by a mark sequence of a high level lasting two valid data widths followed by two low levels; the communication frame comprises the following fields arranged in sequence at a data link layer: a synchronization code, an address field, a control field, a data field, and an end code; wherein the address field is used for addressing a specific slave device, the control field at least comprises pin interval identification and interval number identification, the pin interval identification is used for specifying one pin control interval inside the slave device, each pin control interval corresponds to a group of continuous input / output pins, the interval number identification is used for specifying the number of pin intervals controlled continuously in one transmission, each bit of the data field corresponds to the level state of a specific pin in a specified pin control interval; the master device provides a clock signal used by Manchester coding data to the slave device for signal synchronization and decoding while sending the communication frame; S2, the slave device receives the clock signal and Manchester coding signal, decodes the Manchester coding signal by using the clock signal, identifies the frame start mark, and analyzes the address field, the control field, and the data field; when the address field matches the own address, the range of target pins is determined according to the pin interval identification and the interval number identification, and corresponding level setting operations are performed on the target pins according to the content of the data field.

2. The method of claim 1, wherein the Manchester encoding-based chip interconnection communication method is characterized by, The control field further comprises a read-back enabling bit, when the read-back enabling bit is set to be valid, the addressed slave device assembles the address field and the control field into a response frame after receiving the address field and the control field of the communication frame, sets the read-back enabling bit and a read-write bit in the response frame to preset values, and sends the response frame back to the master device by Manchester coding.

3. The method of claim 1, wherein the Manchester encoding is based on a Manchester code. The control field further comprises a read-write bit, when the read-write bit is set to be in a read state, the addressed slave device reads the current level state of the corresponding pin interval according to the pin interval identification and the interval number identification after receiving the communication frame, and encapsulates the read level state data into a response frame and sends the response frame back to the master device.

4. The method of claim 1, wherein the Manchester encoding-based chip interconnection communication method is characterized by, The address field is further divided into a board card address and a chip select address, wherein the board card address is used for selecting a target board card in a plurality of board cards, and the chip select address is used for selecting a target slave device in a plurality of slave devices on the target board card.

5. The method of claim 1, wherein the Manchester encoding-based chip interconnection communication method is characterized by, On a hardware link, the single-ended Manchester coding signal and the clock signal sent by the master device are first converted into differential signals by a single-ended to differential chip for transmission, and are restored into single-ended signals by a differential to single-ended chip at the receiving end of the slave device.

6. The method of claim 1, wherein the Manchester encoding-based chip interconnection communication method is characterized by, The clock signal is embedded into the Manchester coding data, and the slave device recovers the clock signal from the received data stream by a digital phase-locked loop to realize synchronization.

7. The Manchester encoding based chip interconnection communication method according to claim 1, wherein, The master device sets the interval number identifier to a value greater than or equal to zero, thereby enabling continuous control of multiple pin intervals in one communication frame transmission, and the length of the data field is dynamically determined according to the interval number identifier.

8. The method of claim 3, wherein the Manchester encoding-based chip interconnection communication method is characterized by, The slave device first transmits a header containing the address field and the control field when transmitting a response frame, wherein the read-write bit is set to a state indicating that the slave device writes to the master device, and then transmits the read level state data.

9. The Manchester encoding based chip interconnection communication method according to claim 1, wherein, The master device dynamically adjusts the clock rate of the Manchester encoded signal, including the master device sending a read-back test frame to the target slave device at an initial clock rate before initiating formal data transmission. If a correct response from the slave device is not received within a preset timeout period, the master device automatically reduces the clock rate by one level and re-sends the read-back test frame until a correct response is received or the minimum rate threshold is reached.

10. A Manchester encoding based chip interconnect communication system, characterized by, The master device and the slave device, wherein the master device is configured to generate and transmit a communication frame, and the physical layer signal of the communication frame is modulated using Manchester encoding, wherein the frame start and the frame end are delimited by a flag sequence of two high levels followed by two low levels; the communication frame contains the following fields arranged in sequence at the data link layer: a synchronization code, an address field, a control field, a data field, and an end code; wherein the address field is used to address a specific slave device, the control field includes at least a pin interval identifier and an interval number identifier, the pin interval identifier is used to specify a pin control interval within the slave device, each pin control interval corresponds to a group of consecutive input / output pins, and the interval number identifier is used to specify the number of pin intervals that are continuously controlled in one transmission; each bit of the data field corresponds to the level state of a specific pin within a specified pin control interval; the master device provides a clock signal used for Manchester encoded data to the slave device while transmitting the communication frame, so that the slave device can perform signal synchronization and decoding; wherein the slave device is configured to receive the clock signal and the Manchester encoded signal, decode the Manchester encoded signal using the clock signal, identify the frame start flag, and parse the address field, the control field, and the data field; when the address field matches the own address, the target pin range is determined according to the pin interval identifier and the interval number identifier, and the target pin is subjected to a corresponding level setting operation according to the content of the data field. The master device dynamically adjusts the clock rate of the Manchester encoded signal, including the master device sending a read-back test frame to the target slave device at an initial clock rate before initiating formal data transmission. If a correct response from the slave device is not received within a preset timeout period, the master device automatically reduces the clock rate by one level and re-sends the read-back test frame until a correct response is received or the minimum rate threshold is reached.

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