SAT elastic logic locking module for improving output damage, module variant and application

Abstract

The invention discloses an SAT elastic logic locking module for improving output damage, a module variant and application, and relates to the technical field of hardware security, the SAT elastic logic locking module comprises an n-bit traveling wave carry adder, a controllable output damage unit and a first AND gate; the module variant of the SAT elastic logic locking module is that a comparator and a second AND gate are added on the basis of the SAT elastic logic locking module; an SAT elastic logic locking module or a module variant forms an integrated circuit with an SFLL or an SARLock, and the integrated circuit can be applied to resisting deletion attacks, sensitization attacks, function analysis attacks and AppSAT attacks. According to the method, the effective resistance to the SAT attack is realized, and a new technical enlightenment is provided for the development of an SAT attack resistance technology.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of hardware security, in particular, to a SAT resilient logic locking module with improved output corruption, a module variant and an application. BACKGROUND

[0002] Integrated circuits (ICs) are the backbone of modern computing systems. Logic locking is a technique that aims to protect outsourced IC designs in the field of hardware security from untrusted foundry piracy and counterfeiting. When and only when the correct key is provided, the locked IC can unlock the correct design functionality. In the past decade, the security of logic locking has been threatened by a kind of attack called Boolean satisfiability (SAT) attack. For a locked design with a considerable number of key bits, this attack can decrypt the correct key of most logic locking schemes within a few hours. AppSAT attack (a variant of SAT attack) simplifies a composite scheme to a simple low-output corruption locking scheme by unlocking a high-output corruption locking scheme in the composite scheme. Attackers believe that the scheme itself is a high approximation of the original circuit. Therefore, it is necessary to design a SAT resilient logic locking module with improved output corruption to ensure circuit security.

[0003] Logic locking modifies the design circuit to be protected by locking the original design using key input bits. The resulting protected design circuit is called a locked design. Only when the correct key is applied to the key input, the locked design is functionally equivalent to the original design. The correct key is stored in a secure tamper-resistant memory after manufacturing, and its content cannot be accessed or tampered with outside the chip. The locking process is carried out in a trusted design room. After the locked design goes through the manufacturing and testing stages of an untrusted foundry, it is returned to the designer or remotely controlled by a secure key exchange protocol to load the correct key, thereby obtaining an activated circuit. Without the correct key, attackers cannot obtain the original design, therefore, logic locking can effectively prevent attackers from reverse engineering or overproducing circuit designs, thereby protecting intellectual property (IP) security.

[0004] The SAT attack model is composed of a locked gate netlist and an activated chip. The former can be obtained by reverse engineering of a GDSII layout file by an untrusted foundry or reverse engineering of a manufactured chip by an untrusted end user. The latter can be obtained by purchase from the public market. The SAT attack reveals the correct key by iteratively eliminating all incorrect keys. A set of carefully selected primary inputs and their correct outputs observed from the activated chip are used to identify and eliminate incorrect keys. These special input / output pairs are called distinguished input / output (DIO) pairs. Each DIO can identify a subset of the set of all incorrect keys. The incorrect key elements in any two subsets can be repeated, but each subset must be different. When no more DIOs can be found, it means that all incorrect keys have been identified, and the SAT attack can solve the correct key. So far, the SAT attack is still a very powerful attack technology. It can not only break through RLL, LUT, SLL, FLL and other locking technologies, but also effectively crack SARLock, Anti-SAT, ATD, TTLock and other defense mechanisms. It is still difficult for the prior art to effectively resist the SAT attack. SUMMARY

[0005] To solve the above problems, the purpose of the present application is to provide a SAT resilient logic locking technique with improved output corruption, which aims to maintain SAT resilience in the case of improved output corruption.

[0006] To achieve the above technical purpose, the first aspect of the exemplary embodiments of the present disclosure provides a SAT resilient logic locking module with improved output corruption, comprising: an n-bit ripple carry adder configured to perform a subtraction operation on a key input K and a primary input X; a controllable output corruption unit configured to receive a subtraction output result, perform conditional constraints through controllable output corruption m, and generate a controllable output corruption signal; a first AND gate configured to form an overlapped logic output signal by combining the output corruption signal and a highest bit carry output of the n-bit ripple carry adder.

[0007] Preferably, the input end of the n-bit ripple carry adder includes a lowest bit carry input.

[0008] Preferably, the controllable output corruption unit is configured to adjust the output corruption by controlling the size of m to ensure the number of errors under each key, wherein m is selected as a power of 2.

[0009] Preferably, the SAT resilient logic locking module is configured to resist deletion attacks, sensitization attacks, functional analysis attacks, and AppSAT attacks.

[0010] Based on the same inventive concept, the second aspect of the exemplary embodiments of the present disclosure provides a module variant of the SAT resilient logic locking module mentioned in the first aspect, which further comprises: The comparator is connected to the first AND gate and the second AND gate, and is used to control the n-bit ripple-carry adder to the low g-bit key input under the condition that the high h-bit key input and the main input X are constrained in the Hamming distance of 0, so as to construct the overlapping output corruption signal.

[0011] Based on the same inventive concept, the third aspect of the exemplary embodiments of the present disclosure provides an integrated circuit, which is integrated by the SAT resilient logic locking module mentioned in the first aspect and the SFLL.

[0012] Based on the same inventive concept, the fourth aspect of the exemplary embodiments of the present disclosure provides an integrated circuit, which is integrated by the module variant mentioned in the second aspect and the SFLL.

[0013] Based on the same inventive concept, the fifth aspect of the exemplary embodiments of the present disclosure provides an integrated circuit, which is integrated by the SAT resilient logic locking module mentioned in the first aspect and the SARLock.

[0014] Based on the same inventive concept, the sixth aspect of the exemplary embodiments of the present disclosure provides an integrated circuit, which is integrated by the module variant mentioned in the second aspect and the SARLock.

[0015] Based on the same inventive concept, the seventh aspect of the exemplary embodiments of the present disclosure provides an application of the integrated circuit, which is applied in resisting deletion attacks, sensitization attacks, functional analysis attacks and AppSAT attacks by the integrated circuit provided in any one of the third aspect, the fourth aspect, the fifth aspect and the sixth aspect.

[0016] The present disclosure discloses the following technical effects: 1. The overlapping logic OL can flexibly set the output corruption, and maintain the SAT resilience. The implementation of the OL introduces the ripple-carry adder, which is structurally adjusted to meet the design function, and this is proved by mathematical form.

[0017] 2. The block overlapping logic COL, as a variant of the OL, replaces part of the adder structure with a comparator to construct the block overlapping output corruption, which can effectively reduce the hardware overhead caused by the implementation complexity of the OL.

[0018] 3. The OL and the COL are integrated into the SARLock and the SFLL, which exhibits good compatibility and SAT resilience, and the corruption characteristics of the OL / COL help the defender to resist deletion attacks, functional analysis attacks and other attacks from a new angle.

[0019] 4. Low hardware overhead. Compared with the existing Anti-SAT, SFLL-HD, SKG-Lock and SKG-Lock+ etc. new locking schemes, the proposed OL / COL integrated scheme produces less hardware overhead. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described in the following description are only some embodiments of the present application, and all other drawings obtained by those of ordinary skill in the art without creative effort based on these drawings belong to the protection scope of the present application.

[0021] Figure 1 is a structural schematic diagram of overlapping logic (OL).

[0022] Figure 2 is a structural schematic diagram of block overlapping logic (COL).

[0023] Figure 3 is a Karnaugh map of overlapping logic (OL), wherein (a) m=2, (b) m=4, (c) m=8.

[0024] Figure 4 is a Karnaugh map of block overlapping logic (COL), wherein (a) m=2, g=3, (b) m=2, g=2, (c) m=4, g=3.

[0025] Figure 5 is a structural schematic diagram of the proposed OL / COL integrated scheme, wherein (a) is integrated with SARLock, (b) is integrated with SFLL. DETAILED DESCRIPTION

[0026] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will combine the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the protection scope of the present application.

[0027] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below in combination with the drawings and examples. It should be understood that the specific examples described herein are only used to explain the present application and do not limit the present application.

[0028] As shown in Figures 1-5 , the present application provides a SAT elastic logic locking technique with improved output failure, mainly including two aspects of design of overlapping logic (OL) and block overlapping logic (COL), specifically including the following contents: As shown in Figure 1 , the overlapping logic (OL) of the present application first uses an n-bit traveling wave carry adder to perform a subtraction operation on the key input K and the main input X (the main input X refers to the functional input, English is primary input, in scan-based testability design, the input is divided into primary input and pseudo-primary input, pseudo-primary input corresponds to a flip-flop, and primary input is the original input of the circuit, that is, the "main input X" mentioned in the present application is the functional input), wherein Cin is the lowest bit carry input, Sub_result is the subtraction output result, Cout is the highest bit carry output, and m is the controllable output failure. In the combinational logic, subtraction can be realized by addition, that is, K-X=K+~X+1, and ~X is the inverse code obtained by inverting X bit by bit. Then, the Sub_result is conditionally constrained to realize the controllable output failure, that is, whether the Sub_result is less than m is judged. Finally, the output failure signal is coordinated with Cout through an AND gate to form an overlapping logic output signal. It is worth noting that an important prerequisite for the proposed logic to realize K-X is K≥X, and the existence of Cout can satisfy this prerequisite with minimal overhead, and the proof process is as follows: Proof: To prove that Cout can judge K≥X, it is only necessary to prove that when K≥X, Cout is always 1, and when K<X, Cout is 0. For ease of understanding, let K and X be 4-bit wide signals. When K≥X, ~X≥~K, K+~X≥K+~K=1111, then K-X=K+~X+1≥10000, and the highest bit Cout is 1. When K<X, ~X<~K, K+~X<K+~K=1111, then K-X=K+~X+1≤01111, and the highest bit Cout is 0, which proves the conclusion. OL simplifies the value comparator in the subtraction process to an AND gate, which maximally reduces the additional overhead.

[0029] The overlap logic (OL) of the present application adjusts the output damage by controlling the size of m to ensure the number of errors under each key. For ease of implementation, the present application always selects m as a power of 2. It is worth mentioning that when the value of m increases, the complexity of implementing Sub_result

[0030] The security of OL against SAT attack is analyzed, where the Karnaugh map of OL under different m (2, 4, 8) settings is shown in Figure 3 . Assuming that the SAT attack follows sequential iteration (from X0to ), each main input pattern can exclude m keys, where m-1 of the m keys identified by the DIP of the ith iteration and the (i+1)th iteration are overlapped, at which time the SAT attack needs 2n-(m-1) DIPs to obtain the ideal iteration number, i.e. , where Nop represents the number of DIPs for iteration search. Since the actual SAT attack does not follow the sequential iteration process, the present application assumes that the SAT attack excludes m non-overlapping keys for each iteration, thereby obtaining the minimum iteration number, i.e. . Based on the above two assumptions, it can be inferred that the security of OL is between and .

[0031] The structure diagram of the block overlap logic (COL) of the present application is shown in Figure 2 , and the Karnaugh map of COL under different m and g settings is shown in Figure 4 . Considering the two assumptions that the SAT attack follows sequential iteration and non-sequential iteration, respectively, the ideal iteration number is obtained, i.e. , and the minimum iteration number is obtained, i.e. . It is not difficult to see that OL can be regarded as an instance of COL when h=0, and the security of COL is also between and .

[0032] The block overlap logic (COL) of the present application is constructed by a comparator and an adder, wherein the comparator constrains the high h-bit key input and the main input under the condition of Hamming distance 0 (i.e. K[n-1:g]=X[n-1:g]), and the adder is included in the OL which constructs the overlap output damage for the low g-bit input, h+g=n. By analyzing the OL and the Karnaugh map of the COL, the present application summarizes two characteristics of the proposed logic, as follows.

[0033] (1) Continuous damage characteristic: the OL, COL generates output damage corresponding to m continuous main input patterns under any set of key inputs. For example, m=4. Figure 3 (b) For example, m=4. Let the key input be K7, and the output damage corresponding to the four main input patterns X4, X5, X6, X7.

[0034] (2) Block damage characteristic: when the COL satisfies the condition K[n-1:g]=X[n-1:g], the data distribution of the Karnaugh map sub-blocks which construct the overlap output damage for the low g-bit input is the same. For example, m=4, g=3. Figure 4 (c) For example, m=4, g=3. Let n=4, when K[3]=X[3]=0 / 1, the data distribution of the Karnaugh map sub-blocks which construct the overlap output damage for the low 3-bit input is the same, as shown by the two diagonal sub-blocks. The above characteristics help the defender to resist other attacks from a new perspective, such as deletion attack, functional analysis attack, etc.

[0035] The integrated scheme constructed by the OL, COL is described in detail as follows, as shown in Figure 5 .

[0036] (1) Integration with SARLock: this scheme replaces the equality comparator in SATLock with OL / COL, and then performs AND operation on the outputs of the proposed logic and the mask logic to obtain the flip signal. The mask logic in the traditional SARLock prevents output damage by judging the correctness of the key input, and the attacker can easily identify this "key-only logic", and then delete this logic structure and construct a new "key-only logic" to break the correct function of the lock circuit.

[0037] The present application records the above mask logic constructed only by the key input as vertical mask logic (i.e. V-Mask), and proposes a new mask logic constructed only by the main input, recorded as horizontal mask logic (i.e. H-Mask), which prevents output damage when the main input is in certain patterns. Since the OL, COL has the continuous damage characteristic, the number of input bits required to be controlled by the H-Mask decreases with the increase of m, and the number of input bits required to be controlled by the V-Mask is fixed as n, which will make the H-Mask perform better than the V-Mask in terms of hardware overhead.

[0038] For example, m=4, g=3.Figure 3 (b) For example, m = 4. Assume n = 4, and the correct key is K7. H-Mask prevents the output from being corrupted when the primary input pattern is X4, X5, X6, X7, which can be achieved by controlling the 2-bit primary input (x3, x2) = (0, 0); while V-Mask needs to control the 4-bit key input (k3, k2, k1, k0) = (0, 1, 1, 1) to prevent the output from being corrupted. H-Mask has good applicability to OL and COL, and the application of this logic will make the attacker identify it as part of the original design, thereby preventing deletion attacks.

[0039] (2) Integration with SFLL: This scheme constructs a functional stripping circuit by corrupting the outputs of a controllable number of input patterns, and then XORs the output of this circuit with the output of the proposed logic as the recovery unit to obtain the locked output signal. This integration scheme sets the output corruption by controlling the size of m, which is equivalent to h in SFLL-HD. However, unlike SFLL-HD, due to the continuous corruption characteristics of the proposed logic, the functional stripping unit in the integration scheme can achieve the stripping function by setting m consecutive primary input patterns as protected cubes, and the simplification in design will result in a reduction in hardware overhead. In addition, due to the block corruption characteristics of COL, when m is a fixed value, the number of protected cubes in COL-SFLL is still variable.

[0040] With Figure 4 (c) For example, m = 4, g = 3. In the Karnaugh sub-block constructed by overlapping output corruption from low g-bit input, there are always some key input patterns with corruption number increasing from 1 to m, and when K0, K1, K2, K3 are set as the correct key respectively, the number of protected cubes in COL-SFLL is 1, 2, 3, 4 respectively, and the number of such sub-blocks is 2n-g, which is exponential in size. Therefore, the defender can flexibly adjust the number of protected cubes under a fixed m value by setting this special key input pattern as the correct key, so that the attacker cannot launch a functional analysis attack on the integration scheme by determining the value of m.

[0041] Based on the detailed description of the above OL, COL and their integration scheme, the proposed logic utilizes the m-1 overlapping error keys existing in adjacent input patterns, making it possible for the proposed OL / COL integration scheme to achieve the ideal iteration number (i.e. ), which greatly weakens the trade-off between output corruption and SAT resilience. With the increase of the number of locked bits, the number of iterations required by the unlocking circuit exceeds the general minimum iteration number (i.e. ), showing the same growth law. When n = 14, m = 2, the average number of iterations and average iteration time of the proposed OL / COL integrated scheme are in the range of 6275 ~ 9877 and 4720.72s ~ 8857.25s, respectively; when n = 128, the required number of iterations and iteration time are almost unestimable. Therefore, the proposed scheme is secure against SAT attack (i.e., SAT resilience is achieved). Moreover, due to the controllable higher output impairment of the proposed logic, the proposed scheme is also secure against AppSAT attack.

[0042] The present application is described in the context of the methods, apparatus (systems), and computer program products according to an embodiment of the present application, flowcharts and / or block diagrams. It is to be understood that each block of the flowchart and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more of the blocks in the flowchart and / or block diagram. Figure 1 means for performing the function specified by the block(s) of the flowchart and / or block diagram.

[0043] In the description of the present application, it is to be understood that the terms "first", "second", "third" and the like, merely identify features being described but do not imply or imply relative importance or a number of the features being referred to. Thus, a feature identified as "first" or "second" can implicitly or explicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified.

[0044] Obviously, various modifications and changes are possible in the present application without departing from the spirit and scope of the present application. Thus, it is intended that the present application cover modifications and variations of this application provided they come within the scope of the appended claims and their equivalents.

Claims

1. A SAT elastic logic lockout module for improving output damage, applied in a lockout circuit, characterized in that, include: An n-bit ripple carry adder is used to subtract the key input K from the main input X, where the main input X represents the function input. A controllable output damage unit is used to receive the subtraction output result, and to perform conditional constraints through controllable output damage m in order to generate a controllable output damage signal; The first AND gate is used to combine the output damaged signal with the highest bit carry output of the n-bit ripple carry adder to form an overlapped logic output signal.

2. The SAT resilient logic locking module for improving output failure as described in claim 1, characterized in that: The input of the n-bit ripple carry adder includes the least significant carry input.

3. The SAT resilient logic locking module for improving output failure as described in claim 2, characterized in that: The controllable output corruption unit is used to adjust the output corruption by controlling the size of m to ensure the number of errors under each key, wherein m is selected as a power of 2.

4. The SAT resilient logic locking module for improving output failure as described in claim 3, characterized in that: This SAT elastic logic locking module is used to defend against deletion attacks, sensitization attacks, functional analysis attacks, and AppSAT attacks.

5. A module variant of the SAT resilient logic locking module for improving output failure as described in claim 4, characterized in that, Also includes: A comparator, connected to the first AND gate and then to the second AND gate, is used to control an n-bit ripple carry adder to input the low g-bit key, constraining the high h-bit key input and the main input X to a Hamming distance of 0, in order to construct an overlapping output corrupted signal.

6. An integrated circuit, characterized in that, It is constructed by integrating the SAT elastic logic locking module as described in claim 1 with SFLL.

7. An integrated circuit, characterized in that, It is constructed by integrating the module variant as described in claim 5 with SFLL.

8. An integrated circuit, characterized in that, It is constructed by integrating the SAT elastic logic locking module as described in claim 1 with SARLock.

9. An integrated circuit, characterized in that, It is constructed by integrating SARLock with the module variant as described in claim 5.

10. An application of an integrated circuit, characterized in that, The application of the integrated circuit as described in any one of claims 6-9 in resisting deletion attacks, sensitization attacks, functional analysis attacks, and AppSAT attacks.

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