A method, device and storage medium for graphical simulation of signal flow

Abstract

The application discloses a kind of graphical simulation method of signal flow, device and equipment and storage medium.The method is by detecting the coupling relationship between the component to be simulated, when the coupling relationship between the component to be simulated is cross-domain coupling, then based on the component to be simulated and the edge structure object connected to the component to be simulated, generate original signal flow;Sparse boolean matrix is used to compile and eliminate redundancy to original signal flow, obtain preprocessed signal flow;Loop detection is carried out on preprocessed signal flow, and when loop is detected, the detected loop is broken, to generate target signal flow;Based on target signal flow, graphical simulation is completed, realizes that in the premise of not depending on manual intervention, automatically analyze the multi-domain coupling relationship in simulation model, generate the execution order in line with physical constraint, effectively improve the efficiency and accuracy of simulation modeling.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of system simulation, and in particular to a graphical simulation method and device for signal flow, equipment and a storage medium. BACKGROUND

[0002] Current multi-domain system simulation software (such as MATLAB / Simulink, Dassault Dymola, Siemens Amesim) generally adopts a graphical modeling method, and a user constructs a multi-domain coupled system model of a control domain, a mechanical domain, an energy domain, etc. by dragging and dropping components and connection lines. When constructing a model, a traditional simulation modeling algorithm cannot distinguish the signal interface dependency types of components in different domains because the attributes of the components in different domains are different, and determines that the components in different domains are parallel and can be calculated, which leads to data competition and numerical oscillation when coupling components across domains, and cannot accurately simulate a model containing a feedback loop in the same domain, greatly affecting the efficiency and accuracy of simulation modeling. SUMMARY

[0003] Embodiments of the present application provide a graphical simulation method for signal flow, which solves the problem of low efficiency and low accuracy of simulation modeling in the prior art, and automatically analyzes the multi-domain coupling relationship in a simulation model without human intervention, generates an execution order that meets physical constraints, reduces the configuration time from hours to seconds, greatly reduces the simulation error rate, and effectively improves the efficiency and accuracy of simulation modeling.

[0004] In a first aspect, embodiments of the present application provide a graphical simulation method for signal flow, comprising:

[0005] detecting a coupling relationship between nodes of a component to be simulated, and when the coupling relationship between the nodes of the component to be simulated is cross-domain coupling, generating an original signal flow based on the nodes of the component to be simulated and edge structure objects connecting the nodes of the component to be simulated;

[0006] compiling and eliminating redundancies of the original signal flow using a sparse Boolean matrix to obtain a preprocessed signal flow;

[0007] performing loop detection on the preprocessed signal flow, and when a loop is detected, performing loop breaking processing on the detected loop to generate a target signal flow;

[0008] completing graphical simulation based on the target signal flow.

[0009] In combination with the first aspect, in a possible implementation manner, when the coupling relationship between the nodes of the component to be simulated is cross-domain coupling, the original signal flow is generated based on the nodes of the component to be simulated and the edge structure objects connecting the nodes of the component to be simulated, comprising:

[0010] When the coupling relationship between the to-be-simulated component nodes is cross-domain coupling, type marking is performed on an edge structure object connecting the to-be-simulated component nodes, to obtain a cross-domain mark of each edge structure object;

[0011] A default delay time is set, and an original signal stream is generated based on each edge structure object, the to-be-simulated component nodes corresponding to each edge structure object, the reference weights of the to-be-simulated component nodes, the cross-domain marks, and the default delay time.

[0012] In combination with the first aspect, in a possible implementation manner, the original signal stream is compiled and redundancy is removed by using the sparse Boolean matrix, to obtain a preprocessed signal stream, including:

[0013] The original signal stream is input into a graph encoder for compilation, and the compiled data is stored by using a sparse Boolean matrix structure to construct an adjacency relationship matrix.

[0014] Based on the adjacency relationship matrix, the edge structure objects in the original signal stream are merged and removed, and the edge structure object with the largest weight is retained, to output a preprocessed signal stream.

[0015] In combination with the first aspect, in a possible implementation manner, the loop detection is performed on the preprocessed signal stream, and when a loop is detected, the detected loop is broken to generate a target signal stream, including:

[0016] Step 1: initialization processing is performed on the preprocessed signal stream, the priority of each to-be-simulated component node in the preprocessed signal stream is determined, and a priority queue is generated based on the to-be-simulated component nodes and the corresponding priorities.

[0017] Step 2: a to-be-simulated component node corresponding to the highest priority in the priority queue is selected as a source node, and the source node is added to an execution queue.

[0018] Step 3: the length of the execution queue is determined, and if the length of the execution queue is less than the total number of to-be-simulated component nodes in the preprocessed signal stream, it indicates that there is a strongly connected component constituting a loop in the preprocessed signal stream.

[0019] Step 4: when a loop is detected, the detected loop is broken to generate a target signal stream.

[0020] Step 5: all adjacent nodes of the source node in the priority queue are traversed, the in-degree value of each adjacent node is reduced by one, and the adjacent node with the reduced in-degree value of 0 is taken as a target node.

[0021] Step 6: the source node in the priority queue is deleted, and the target node is added to the priority queue, to update the priority queue.

[0022] Step seven: iteratively performing steps two to six until the priority queue is empty or the number of repeated iterations reaches a maximum number of iterations, then stopping.

[0023] With reference to the first aspect, in a possible implementation manner, the initialization processing on the pre-processing signal flow is performed, and priority of each to-be-simulated component node in the pre-processing signal flow is determined, including:

[0024] An initialization connection adjustment weight of each to-be-simulated component node in the pre-processing signal flow is calculated, and an in-degree value of each to-be-simulated component node is counted through a reverse adjacency matrix;

[0025] The initialization connection adjustment weight of each to-be-simulated component node is multiplied by the in-degree value to obtain the priority of the to-be-simulated component node.

[0026] With reference to the first aspect, in a possible implementation manner, the initialization connection adjustment weight of each to-be-simulated component node in the pre-processing signal flow is calculated, including:

[0027] A global connection density index, a global structure hub index, and a system-level propagation delay index of each to-be-simulated component node in the pre-processing signal flow are calculated;

[0028] A weight adjustment coefficient corresponding to each of the global connection density index, the global structure hub index, and the system-level propagation delay index is respectively acquired, and a first weight calculation formula is called to calculate the initialization connection adjustment weight;

[0029] The first weight calculation formula is specifically:

[0030]

[0031] In the formula, i represents the i th to-be-simulated component node, i represents an initialization connection adjustment weight of the i th to-be-simulated component node, w represents a weight adjustment coefficient corresponding to the global connection density index, represents a global connection density index of the i th to-be-simulated component node, w represents a weight adjustment coefficient corresponding to the global structure hub index, represents a global structure hub index of the i th to-be-simulated component node, w represents a weight adjustment coefficient corresponding to the system-level propagation delay index, and represents a system-level propagation delay index of the i th to-be-simulated component node. ​​​​​​​​​​​​​

[0032] With reference to the first aspect, in a possible implementation manner, the loop breaking processing on the detected loop to generate the target signal flow comprises the following steps.

[0033] When the loop is detected, the Tarjan algorithm is used to identify the strongly connected components among the nodes of the to-be-simulated components with the in-degree value of 0 in the preprocessed signal flow, and the loop in the preprocessed signal flow is determined according to the strongly connected components.

[0034] The set of nodes of the to-be-simulated components with the node attribute of allowing to be disconnected on the loop is taken as a candidate node set, and a second weight calculation formula is called to calculate the loop breaking connection adjustment weight of each node of the to-be-simulated components in the candidate node set, and the node of the to-be-simulated components with the largest weight is selected as the loop breaking point.

[0035] A delay module is inserted before the loop breaking point to complete the loop breaking processing, the preprocessed signal flow is updated, and the updated preprocessed signal flow is taken as the target signal flow.

[0036] The second weight calculation formula is specifically as follows.

[0037]

[0038] In the formula, the first to-be-simulated component node is represented as , the second to-be-simulated component node is represented as , the loop breaking connection adjustment weight of the second to-be-simulated component node is represented as , the component internal connection density index of the second to-be-simulated component node is represented as , the weight adjustment coefficient corresponding to the component internal connection density index is represented as , the loop breaking rate index of the second to-be-simulated component node is represented as , and the weight adjustment coefficient corresponding to the loop breaking rate index is represented as , the residual graph perturbation degree index of the second to-be-simulated component node is represented as , and the weight adjustment coefficient corresponding to the residual graph perturbation degree index is represented as .

[0039] In a second aspect, an embodiment of the present application provides a graphical simulation device of a signal flow, comprising:

[0040] An original signal flow generation module is configured to detect a coupling relationship among to-be-simulated component nodes, and when the coupling relationship among the to-be-simulated component nodes is cross-domain coupling, generate an original signal flow based on the to-be-simulated component nodes and an edge structure object connecting the to-be-simulated component nodes.

[0041] ​​​​a pre-processing signal stream generation module configured to compile and eliminate redundancy of the original signal stream by using a sparse Boolean matrix to obtain a pre-processing signal stream;

[0042] a target signal stream generation module configured to detect loops in the pre-processing signal stream, and when a loop is detected, break the detected loop to generate a target signal stream;

[0043] a target signal stream simulation module configured to complete graphical simulation based on the target signal stream.

[0044] In a third aspect, an apparatus is provided, and the apparatus includes a processor, a memory for storing processor-executable instructions, and the processor implements the method according to the first aspect or any possible implementation manner of the first aspect when executing the processor-executable instructions.

[0045] In a fourth aspect, a non-volatile computer-readable storage medium is provided, and the non-volatile computer-readable storage medium includes a computer program or instructions for storing, and when the computer program or instructions are executed, the method according to the first aspect or any possible implementation manner of the first aspect is implemented.

[0046] The one or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

[0047] In the embodiments of the present application, by detecting the coupling relationship between the nodes of the to-be-simulated component, it is determined whether the coupling relationship between the nodes of the to-be-simulated component is cross-domain coupling. When the coupling relationship between the nodes of the to-be-simulated component is cross-domain coupling, an original signal stream is generated based on the nodes of the to-be-simulated component and the edge structure object connecting the nodes of the to-be-simulated component. Then, a sparse Boolean matrix is used to compile and eliminate redundancy of the original signal stream formed by the nodes of the to-be-simulated component and the edge structure object connecting the nodes of the to-be-simulated component, to obtain a pre-processing signal stream. Then, loop detection is performed on the pre-processing signal stream, and when a loop is detected, the detected loop is broken to achieve the effect that in the graphical simulation process of the signal stream, manual intervention is not needed, the multi-domain coupling relationship in the simulation model can be automatically parsed, the execution order conforming to the physical constraint is generated, the configuration time during graphical simulation is reduced from hours to seconds, and the simulation error rate is greatly reduced, thereby effectively improving the efficiency and accuracy of simulation modeling. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0049] Figure 1 A flow chart of a graphical simulation method of a signal flow provided by an embodiment of the present application;

[0050] Figure 2 A flow chart of generating a target signal flow provided by an embodiment of the present application;

[0051] Figure 3 A flow chart of initializing a pre-processed signal flow provided by an embodiment of the present application;

[0052] Figure 4 A flow chart of determining an initialized connection adjustment weight provided by an embodiment of the present application;

[0053] Figure 5 A flow chart of loop resolving subprogram performing loop breaking provided by an embodiment of the present application;

[0054] Figure 6 A signal flow chart before loop breaking provided by an embodiment of the present application;

[0055] Figure 7 A signal flow chart after loop breaking provided by an embodiment of the present application;

[0056] Figure 8 A structural schematic diagram of a graphical simulation device of a signal flow provided by an embodiment of the present application. DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work belong to the scope of protection of the present application.

[0058] The following describes some technologies related to the embodiments of the present application to help understanding, which should be considered only as exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present application. Also, for clarity and conciseness, the description of some well-known functions and structures is omitted in the following description.

[0059] Figure 1 A flow chart of a graphical simulation method of a signal flow provided by an embodiment of the present application, comprising steps S10 to S40. Among them, Figure 1 Only one execution order is shown for an embodiment of the present application, which does not represent the only execution order of the graphical simulation method of a signal flow of the present application. In the case of achieving the final result,Figure 1 The steps shown can be executed in parallel or in reverse.

[0060] Specifically, the embodiment of the present application provides a graphical simulation method of a signal flow, comprising the following steps:

[0061] S10: detecting a coupling relationship between to-be-simulated component nodes, and when the coupling relationship between the to-be-simulated component nodes is cross-domain coupling, generating an original signal flow based on the to-be-simulated component nodes and an edge structure object connecting the to-be-simulated component nodes.

[0062] The to-be-simulated component node refers to a component that needs to be simulated. The cross-domain coupling refers to a relationship in which to-be-simulated component nodes in different physical domains are connected. The physical domains in the embodiment include but are not limited to a control domain, a mechanical domain and an energy domain. The original signal flow refers to a signal flow composed of to-be-simulated component nodes and an edge structure object connecting the to-be-simulated component nodes.

[0063] Specifically, after detecting the to-be-simulated component nodes, the simulation software traverses the physical attributes of the to-be-simulated component nodes to determine whether the to-be-simulated component nodes have a cross-domain coupling relationship, such as data coupling between a discrete controller (sampling period 1 ms) in the control domain and a continuous dynamics component (integration step 0.01 ms) in the mechanical domain. When it is determined that there is a cross-domain coupling relationship, a type label of a “hybrid zero-order hold type” is inserted into the edge structure object connecting the to-be-simulated component nodes, so that a cross-domain label of each edge structure object is obtained, and then a default delay time is set in the edge structure object.

[0064] Each to-be-simulated component node in the embodiment carries a reference weight. After the default delay time is obtained, the simulation software generates the original signal flow based on the to-be-simulated component nodes corresponding to each edge structure object, the reference weight of the to-be-simulated component node, the cross-domain label and the default delay time.

[0065] The reference weight of the to-be-simulated component node is derived from the static attributes of the to-be-simulated component node, including a calculation complexity level of the to-be-simulated component node, a sampling period reciprocal and a physical domain type coefficient. The reference weight is determined when the model is loaded for the first time and remains unchanged in subsequent dynamic calculation.

[0066] By inserting the type label into the edge structure object and setting the default delay time, the multi-domain coupling relationship in the graphical model can be automatically parsed without manual intervention, thereby overcoming the problem that the to-be-simulated component nodes in the cross-domain coupling relationship are determined as parallel computable in the traditional simulation modeling algorithm, resulting in data competition and data oscillation, and realizing the coupling of cross-domain data.

[0067] S20: compiling and eliminating redundancy of the original signal flow by using a sparse Boolean matrix to obtain a preprocessed signal flow.

[0068] The pre-processed signal stream refers to a signal stream obtained after compiling and redundancy elimination of the original signal stream.

[0069] Specifically, after obtaining the original signal stream, the original signal stream is input into a graph encoder for compilation, and the compiled data is stored in a sparse Boolean matrix structure to construct an adjacency relationship matrix. Then, based on the elements in the adjacency relationship matrix, the edge structure objects in the original signal stream are merged and removed, and the redundant connections and self-loop connections are removed, and the reference weight of the largest simulation component node and the corresponding edge structure object are retained to form the pre-processed signal stream.

[0070] The pre-processed signal stream is represented by a double matrix in a compressed sparse row (CRS) storage format, wherein the forward adjacency matrix is used for forward traversal calculation, and the reverse adjacency matrix is used for reverse tracing query. The CRS double matrix representation of the pre-processed signal stream can strictly control the memory occupation within the range of the sum of the node number and the edge number.

[0071] S30: Loop detection is performed on the pre-processed signal stream, and when a loop is detected, the detected loop is broken to generate a target signal stream.

[0072] S40: Graphical simulation is completed based on the target signal stream.

[0073] The target signal stream refers to a signal stream obtained after breaking the loop in the pre-processed signal stream.

[0074] Specifically, after obtaining the pre-processed signal stream, loop detection is performed on the pre-processed signal stream to determine whether there is a loop in the pre-processed signal stream. When a loop is detected, the detected loop is broken. The way of breaking the detected loop in this embodiment includes but is not limited to calling a loop resolution subroutine. The specific execution process of the loop resolution subroutine includes: identifying the strongly connected components between the simulation component nodes with an in-degree value of 0 in the pre-processed signal stream using the Tarjan algorithm, and determining the loop in the pre-processed signal stream according to the strongly connected components; taking the set of simulation component nodes with the node attribute of allowing to be disconnected on the loop as the candidate node set, and calculating the loop breaking connection adjustment weight of each simulation component node in the candidate node set by calling a second weight calculation formula, and selecting the simulation component node with the largest weight as the loop breaking point; inserting a delay module before the loop breaking point to complete the loop breaking, updating the pre-processed signal stream, and taking the updated pre-processed signal stream as the target signal stream; by executing the above loop breaking process, the automatic solution of the loop-containing model can be realized, and manual loop solving is not required, solving the problem that the traditional simulation modeling algorithm cannot terminate under the loop-containing model.

[0075] The target signal stream without loops obtained through the loop breaking processing is more in line with the execution order of physical constraints, and the graphical simulation using the target signal stream effectively improves the simulation efficiency and accuracy.

[0076] Further, after obtaining the preprocessed signal stream, as shown in Figure 2 Step S30, loop detection is performed on the preprocessed signal stream, and when a loop is detected, the detected loop is broken to generate a target signal stream, specifically including the following steps:

[0077] Step one: initialization processing is performed on the preprocessed signal stream to determine the priority of each to-be-simulated component node in the preprocessed signal stream, and a priority queue is generated based on the to-be-simulated component nodes and the corresponding priorities; Step two: a to-be-simulated component node corresponding to the highest priority in the priority queue is selected as a source node, and the source node is added to an execution queue; Step three: the length of the execution queue is determined, and if the length of the execution queue is less than the total number of to-be-simulated component nodes in the preprocessed signal stream, it indicates that there is a strongly connected component constituting a loop in the preprocessed signal stream; Step four: when a loop is detected, the detected loop is broken to generate a target signal stream; Step five: all adjacent nodes of the source node in the priority queue are traversed, and the in-degree value of each adjacent node is reduced by one, and the adjacent node with an in-degree value of zero after reduction is taken as a target node; Step six: the source node in the priority queue is deleted and the target node is added to the priority queue, and the priority queue is updated; Step seven: the above steps two to six are repeatedly executed until the priority queue is empty or the number of repeated iterations reaches a maximum iteration number, and then the process is stopped.

[0078] The maximum iteration number in this embodiment is the number of edge structure objects in the preprocessed signal stream.

[0079] Further, as shown in Figure 3 Step one, initialization processing is performed on the preprocessed signal stream to determine the priority of each to-be-simulated component node in the preprocessed signal stream, specifically including the following steps:

[0080] S31: The initialization connection adjustment weight of each to-be-simulated component node in the preprocessed signal stream is calculated, and the in-degree value of each to-be-simulated component node is counted through a reverse adjacency matrix.

[0081] The in-degree value of the to-be-simulated component node refers to the number of edge structure objects input into the to-be-simulated component node.

[0082] S32: The initialization connection adjustment weight of each to-be-simulated component node is multiplied by the in-degree value to obtain the priority of the to-be-simulated component node.

[0083] Specifically, the smaller the initialization connection adjustment weight of the to-be-simulated component node, the higher the priority.

[0084] Furthermore, such as Figure 4 As shown, in step S31, the initial connection adjustment weight of each node of the component to be simulated in the preprocessed signal stream is calculated, which specifically includes the following steps:

[0085] S311: Calculate the global connectivity density, global structural hub degree, and system-level propagation delay of each component node to be simulated in the preprocessed signal flow.

[0086] The global connection density index refers to the number of edge structure objects directly connected to the node of the component to be simulated in the preprocessed signal flow. The larger the value, the heavier the load as an information hub and the lower the initial priority.

[0087] The global structural hub index refers to the cumulative depth score of the component node to be simulated participating in all loops in the preprocessed signal flow. The larger the value, the deeper its level in the multi-ring nested structure and the lower its initial priority.

[0088] The system-level propagation delay index refers to the sum of the shortest paths from the node of the component to be simulated to all other nodes of the component to be simulated in the preprocessed signal stream. The larger the value, the wider its global influence as an information source and the lower its initial priority.

[0089] S312: Obtain the weight adjustment coefficients corresponding to the global connection density index, the global structural hub index, and the system-level propagation delay index respectively, and call the first weight calculation formula to calculate the initial connection adjustment weight.

[0090] The initial connection adjustment weights are weighted and synthesized based on the three dimensions of indicators in step S311. The synthesis formula is the sum of the products of each indicator and its corresponding weight adjustment coefficient.

[0091] The specific formula for calculating the first weight is as follows:

[0092]

[0093] In the formula, Indicates the first One component node to be simulated. Indicates the first Adjust the initial connection weights of each component node to be simulated. This represents the weight adjustment coefficient corresponding to the global connectivity density metric. Indicates the first The global connection density index of each component node to be simulated. This represents the weight adjustment coefficient corresponding to the global structural hub index. Indicates the first The global structural hub degree index of each component node to be simulated. This represents the weight adjustment coefficient corresponding to the system-level propagation delay metric. Indicates the first The system-level propagation delay metric for each component node to be simulated.

[0094] It should be noted that, The smaller the value, the more significant the difference in the number of nodes of the component to be simulated. The higher the computational readiness, the higher the priority, and the more likely it should be placed in the priority queue.

[0095] The weighting adjustment coefficient in this embodiment , and These are static benchmark coefficients, and the sum of the three is 1.

[0096]

[0097] In the formula, Indicates the first One component node to be simulated. Indicates the first The global connection density index of each component node to be simulated. Indicates the first preprocessed signal stream The number of edge structure objects connected to the input side of each component node to be simulated. Indicates the first preprocessed signal stream The number of edge structure objects connected to the output side of each component node to be simulated.

[0098]

[0099] In the formula, Indicates the first One component node to be simulated. Indicates the first The global structural hub degree index of each component node to be simulated. This indicates the total number of loops in the preprocessed signal stream. Indicates the first Each loop corresponds to a strongly connected component; For indicator functions, when For the first The node of the component to be simulated in each loop, then ,when Not for the first The node of the component to be simulated in each loop, then .

[0100]

[0101] In the formula, Indicates the first a system-level propagation delay indicator of a to-be-simulated component node, a to-be-simulated component node, a to-be-simulated component node, a to-be-simulated component node, a to-be-simulated component node, all to-be-simulated component nodes in a pre-processed signal flow, a to-be-simulated component node, a to-be-simulated component node, a to-be-simulated component node.

[0102] Further, as shown in step four, when a loop is detected, the detected loop is broken to generate a target signal flow, and the step specifically includes the following steps: Figure 5

[0103] S41: When a loop is detected, Tarjan algorithm (an algorithm for determining strongly connected components of a directed graph) is used to identify strongly connected components among to-be-simulated component nodes with an in-degree value of 0 in the pre-processed signal flow, and the loop in the pre-processed signal flow is determined according to the strongly connected components.

[0104] S42: A set of to-be-simulated component nodes with a node attribute of being allowed to be broken on the loop is taken as a candidate node set, and a second weight calculation formula is called to calculate the loop-breaking connection adjustment weight of each to-be-simulated component node in the candidate node set, and a to-be-simulated component node with the largest weight is selected as a loop breaking point.

[0105] Specifically, to-be-simulated component nodes with a node attribute of being allowed to be broken on the loop are taken as candidate points, a set formed by the candidate points is taken as a candidate node set, and a candidate node set includes a plurality of candidate points.

[0106] Further, the node attribute of being allowed to be broken on the loop is an inherent attribute of a to-be-simulated component node, which is set by a designer according to engineering experience in a simulation component construction stage and stored in metadata description of the simulation component. The attribute includes a Boolean value flag and a breaking constraint condition (such as a maximum delay time allowed, a breaking position limit, etc.).

[0107] Further, after the candidate node set is obtained, a second weight calculation formula is called to calculate the loop-breaking connection adjustment weight of each to-be-simulated component node in the candidate node set, so as to ensure that the calculation result reflects the latest signal flow state.

[0108] ​The broken ring connection adjustment weight determination method ensures that the loop resolution process always adapts to the current topology form by collecting the structure state of the simulation graph in real time, avoiding the invalidation of the reference weight caused by the structural transition of the simulation graph due to the previous operation. At the same time, the physical disconnectable attribute of the to-be-simulated component node is decoupled as a prior constraint and dynamic calculation, which not only ensures the controllability of the engineering rule, but also realizes the intelligentization of the loop resolution selection, meeting the dual needs of rule determinacy and adaptivity of industrial-level simulation systems.

[0109] Further, the second weight calculation formula is specifically:

[0110]

[0111] In the formula, the first to-be-simulated component node is represented by , the second to-be-simulated component node is represented by , the broken ring connection adjustment weight of the second to-be-simulated component node is represented by , the component-in connection density index of the second to-be-simulated component node (i.e., the connection density index of the second to-be-simulated component node in the strong connected component where it is located) is represented by , the weight adjustment coefficient corresponding to the component-in connection density index is represented by , the loop destruction rate index of the second to-be-simulated component node (i.e., the loop destruction rate index of the second to-be-simulated component node in the strong connected component where it is located) is represented by , the weight adjustment coefficient corresponding to the loop destruction rate index is represented by , the residual graph disturbance degree index of the second to-be-simulated component node (i.e., the residual graph disturbance degree index of the second to-be-simulated component node in the strong connected component where it is located) is represented by , and the weight adjustment coefficient corresponding to the residual graph disturbance degree index is represented by . The number of edge structure objects directly connected in the strong connected component (i.e., the loop) where the second to-be-simulated component node is located is represented by , and the greater the value, the more significant the hub role of the corresponding to-be-simulated component node in the loop. The disappearance ratio of reachable paths in the strong connected component (i.e., the loop) where the second to-be-simulated component node is located after removing the second to-be-simulated component node is represented by , and the greater the value, the more complete the destruction of the corresponding to-be-simulated component node to the integrity of the loop, and the more suitable it is as a loop breaking point.

[0112]

[0113]

[0114] ​​​​​​​ Indicates the first The sum of the shortest paths from each simulated component node to other simulated component nodes within its strongly connected component (i.e., loop) is considered. The larger the value, the greater the disturbance to other simulated component nodes when disconnecting the node. Therefore, more caution should be exercised when selecting a node to disconnect from a strongly connected component (i.e., loop).

[0115] It should be noted that the weighting adjustment coefficient in this embodiment is a static baseline value and does not change throughout the entire image simulation of the signal flow. Therefore, , , .

[0116] In this embodiment, Used for comprehensive evaluation of the component nodes to be simulated As a measure of a candidate point's merits, a higher value indicates a greater loop-breaking effect (stronger destructive power and less disturbance), and it should be given priority as a loop-breaking point.

[0117]

[0118] In the formula, Indicates the first One component node to be simulated. Indicates the first The component interconnect density index of each component node to be simulated. Indicates the first digit within the corresponding strongly connected component. The number of edge structure objects connected to the input side of each component node to be simulated. Indicates the first digit within the corresponding strongly connected component. The number of edge structure objects connected to the output side of each component node to be simulated.

[0119]

[0120] In the formula, Indicates the first One component node to be simulated. Indicates the first The loop failure rate index of each component node to be simulated. This represents the total number of original reachable paths between all pairs of nodes in the simulated component within the corresponding strongly connected component. This indicates temporarily removing the node of the component to be simulated within the corresponding strongly connected component. After considering the edges associated with the nodes, the total number of reachable paths between the remaining nodes.

[0121]

[0122] In the formula, Indicates the first a to-be-simulated component node, a to-be-simulated component node, a to-be-simulated component node, a to-be-simulated component node, a to-be-simulated component node, a to-be-simulated component node, a to-be-simulated component node, a to-be-simulated component node, a to-be-simulated component node, a to-be-simulated component node.

[0123] The breakable connection adjustment weight of the to-be-simulated component node calculated in the embodiment is generated in real time based on the connection topology of the current directed graph, rather than being pre-assigned statically. Whenever the loop resolution subroutine is triggered, the simulation software re-executes the weight evaluation process for all the nodes in the identified strongly connected component, which are physically breakable, to ensure that the calculation result reflects the latest signal flow state.

[0124] S43: Insert a delay module before the loop breaking point to complete the loop breaking process, update the preprocessed signal flow, and take the updated preprocessed signal flow as the target signal flow.

[0125] Specifically, after determining the loop in the preprocessed signal flow through the strongly connected component, first, the physically breakable attribute of all the to-be-simulated component nodes in the strongly connected component is read, and the to-be-simulated component nodes with the true flag (i.e., breakable) are selected as the candidate node set. Subsequently, only the second weight calculation formula is called to calculate the weight of the to-be-simulated component nodes in the candidate node set, to avoid wasting resources due to the participation of the to-be-simulated component nodes that are not breakable in the calculation. Finally, the to-be-simulated component node with the maximum weight value in the candidate node set is selected as the loop breaking point, and a delay module is inserted before it to complete the loop breaking process. In the embodiment, the delay parameter of the delay module is the minimum value allowed by the physical constraint (i.e., the smaller one of zero point one millisecond and one percent of the sampling period).

[0126] Further, for ease of understanding, the loop breaking process is described by taking an example. As shown in FIGS. 1 and 2, Figure 6 , Figure 7 it is assumed that the candidate node set specifically includes three to-be-simulated component nodes, namely A (controller), B (actuator), and C (sensor); the respective breakable connection adjustment weights of the three to-be-simulated component nodes are 10, 5, and 8, respectively; the to-be-simulated component node A with the maximum weight value is selected as the loop breaking point, and a DelayBlock (delay module) Delay=0.01ms is inserted before the node to complete the loop breaking process. Among them, Figure 6 is a simulation diagram of the signal flow before the loop is resolved, i.e., before the loop breaking process, Figure 7The simulation diagram of the signal flow after the loop is broken. It should be noted that the cross-domain mark is the attribute of the component node to be simulated, and thus is not represented in Figure 6 、 Figure 7 .

[0127] In the embodiment of the present application, the coupling relationship between the component nodes to be simulated is detected. When the coupling relationship between the component nodes to be simulated is cross-domain coupling, the edge structure object connecting the component nodes to be simulated is marked by type and a default delay time is set, so as to realize the unified processing of data in different domains under a single algorithm framework and avoid cross-domain data competition. The original signal flow formed by the component nodes to be simulated and the edge structure object connecting the component nodes to be simulated is compiled and redundant eliminated by using a sparse Boolean matrix, so as to obtain a pretreated signal flow. Then, when a loop is detected, a loop resolution subroutine is called to break the loop, so as to effectively solve the problem that the existing simulation technology cannot normally simulate the feedback loop in the same domain component and realize the automatic solution of the loop model. By implementing the embodiment of the present application, the multi-domain coupling relationship in the simulation model can be automatically analyzed without relying on manual intervention in the graphical simulation process of the signal flow, the execution order meeting the physical constraints is generated, the configuration time is reduced from hours to seconds during the graphical simulation, the simulation error rate is greatly reduced, and the efficiency and accuracy of the simulation modeling are effectively improved.

[0128] Although the present application provides the method operation steps as described in the embodiments or flowcharts, more or fewer operation steps can be included based on conventional or non-inventive labor. The order of steps listed in the embodiments is only one of the many execution orders, and does not represent the only execution order. When the device or client product is executed in practice, the method order shown in the embodiments or the drawings can be executed in sequence or in parallel (for example, in a parallel processor or multi-thread processing environment).

[0129] As shown in Figure 8 , the embodiment of the present application further provides a graphical simulation device of a signal flow. The device comprises:

[0130] The original signal flow generation module 10 is configured to detect the coupling relationship between the component nodes to be simulated. When the coupling relationship between the component nodes to be simulated is cross-domain coupling, the original signal flow is generated based on the component nodes to be simulated and the edge structure object connecting the component nodes to be simulated.

[0131] The pretreated signal flow generation module 20 is configured to compile and eliminate the redundancy of the original signal flow by using a sparse Boolean matrix, so as to obtain a pretreated signal flow.

[0132] The target signal stream generation module 30 is configured to perform loop detection on the preprocessed signal stream, and perform loop breaking on the detected loop when the loop is detected, to generate a target signal stream.

[0133] The target signal stream simulation module 40 is configured to complete graphical simulation based on the target signal stream.

[0134] Some of the modules in the apparatus described in the present application can be described in the general context of computer-executable instructions, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, classes, and the like that perform particular tasks or implement particular abstract data types. The present application can also be practiced in distributed computing environments where tasks are performed by remote processing devices that are connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including memory storage devices.

[0135] The apparatus or modules described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. For the convenience of description, the above apparatus is described as various modules with functions. In the implementation of the embodiments of the present application, the functions of the modules can be implemented in one or more software and / or hardware. Of course, the modules implementing certain functions can also be implemented by a combination of multiple sub-modules or sub-units.

[0136] The methods, apparatuses or modules described in the present application can be implemented in a computer readable program code in any appropriate manner, for example, the controller can take the form of, for example, a microprocessor or processor and a computer readable medium storing computer readable program code (for example, software or firmware) executable by the (micro)processor, logic gates, switches, application specific integrated circuits (ASIC), programmable logic controllers and embedded microcontrollers, examples of the controller include but are not limited to the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20 and Silicone Labs C8051F320, the memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art also know that in addition to implementing the controller in pure computer readable program code, the same function can be achieved by logically programming the method steps in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers and embedded microcontrollers. Therefore, such a controller can be considered as a hardware component, and the means included therein for implementing various functions can also be considered as structures within the hardware component. Alternatively, the means for implementing various functions can be considered as both a software module for implementing the method and a structure within the hardware component.

[0137] The embodiments of the present application also provide a device, which comprises: a processor; a memory for storing processor executable instructions; and the processor implements the method as described in the embodiments of the present application when executing the executable instructions.

[0138] The embodiments of the present application also provide a non-volatile computer readable storage medium, which stores a computer program or instructions, and when the computer program or instructions are executed, the method as described in the embodiments of the present application is implemented.

[0139] In addition, the functional modules in each of the embodiments of the present application can be integrated in one processing module, or each module can exist independently, or two or more modules can be integrated in one module.

[0140] The storage medium described above includes but is not limited to random access memory (RAM), read-only memory (ROM), cache, hard disk drive (HDD) or memory card. The memory can be used to store computer program instructions.

[0141] From the description of the above embodiments, those skilled in the art can clearly understand that the present application can be implemented by means of software and the necessary hardware. Based on such an understanding, the technical solutions of the present application can be embodied in the form of a software product or can be embodied in the form of data migration. The computer software product can be stored in a storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a plurality of instructions for causing a computer device (which can be a personal computer, a mobile terminal, a server, or a network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments of the present application.

[0142] The various embodiments in the specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments. The whole or part of the present application can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld devices or portable devices, tablet devices, mobile communication terminals, multi-processor systems, microprocessor-based systems, programmable electronic devices, network PCs, small computers, large computers, distributed computing environments including any of the above systems or devices, etc.

[0143] The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the present application; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the present application.

Claims

1. A method of graphical simulation of signal flow, characterized in that, The method comprises the following steps: detecting the coupling relationship between the nodes of the components to be simulated, and when the coupling relationship between the nodes of the components to be simulated is cross-domain coupling, generating an original signal stream based on the nodes of the components to be simulated and the edge structure objects connecting the nodes of the components to be simulated; compiling and eliminating the redundancy of the original signal stream by using a sparse Boolean matrix to obtain a pretreated signal stream; detecting a loop in the pretreated signal stream, and when a loop is detected, performing loop breaking processing on the detected loop to generate a target signal stream; completing graphical simulation based on the target signal stream; wherein when the coupling relationship between the nodes of the components to be simulated is cross-domain coupling, the original signal stream is generated based on the nodes of the components to be simulated and the edge structure objects connecting the nodes of the components to be simulated, which comprises the following steps: when the coupling relationship between the nodes of the components to be simulated is cross-domain coupling, the edge structure objects connecting the nodes of the components to be simulated are type-labeled to obtain the cross-domain labels of each edge structure object; a default delay time is set, and the original signal stream is generated based on each edge structure object, the nodes of the components to be simulated corresponding to each edge structure object, the reference weights of the nodes of the components to be simulated, the cross-domain labels and the default delay time; the loop detection of the pretreated signal stream, and when a loop is detected, the loop breaking processing is performed on the detected loop to generate the target signal stream, which comprises the following steps: Step 1: performing initialization processing on the pretreated signal stream to determine the priority of each node of the components to be simulated in the pretreated signal stream, and generating a priority queue based on the nodes of the components to be simulated and the priorities corresponding to the nodes of the components to be simulated; Step 2: selecting the node of the components to be simulated corresponding to the highest priority in the priority queue as a source node, and adding the source node to an execution queue; Step 3: determining the length of the execution queue, and if the length of the execution queue is less than the total number of nodes of the components to be simulated in the pretreated signal stream, it indicates that there is a strongly connected component constituting a loop in the pretreated signal stream; Step 4: when a loop is detected, performing loop breaking processing on the detected loop to generate a target signal stream; Step 5: traversing all adjacent nodes of the source node in the priority queue, and reducing the in-degree value of each adjacent node by one, and taking the adjacent node with the reduced in-degree value of 0 as a target node; Step 6: deleting the source node in the priority queue and adding the target node to the priority queue, and updating the priority queue; Step 7: iteratively executing the above steps 2 to 6 until the priority queue is empty or the number of repeated iterations reaches a maximum iteration number, and then stopping.

2. The method of claim 1, wherein, the compiling and redundancy elimination of the original signal stream by using a sparse Boolean matrix to obtain a pretreated signal stream, which comprises the following steps: inputting the original signal stream into a graph encoder for compiling, and storing the compiled data by using a sparse Boolean matrix structure to construct an adjacency relationship matrix; based on the adjacency relationship matrix, performing merging and removing processing on the edge structure objects in the original signal stream, retaining the edge structure object with the largest weight, and outputting a pretreated signal stream.

3. The method of claim 1, wherein, the initialization processing of the pretreated signal stream to determine the priority of each node of the components to be simulated in the pretreated signal stream, which comprises the following steps: Calculate an initial connection adjustment weight of each to-be-simulated component node in a preprocessed signal stream, and count an in-degree value of each to-be-simulated component node through an inverse adjacency matrix; Multiply the initial connection adjustment weight of each to-be-simulated component node by the in-degree value to obtain a priority of the to-be-simulated component node.

4. The method of claim 3, wherein, The calculating of the initial connection adjustment weight of each to-be-simulated component node in the preprocessed signal stream comprises: Calculate a global connection density index, a global structure hub index and a system-level propagation delay index of each to-be-simulated component node in the preprocessed signal stream; Obtain a weight adjustment coefficient corresponding to each of the global connection density index, the global structure hub index and the system-level propagation delay index respectively, and calculate the initial connection adjustment weight by calling a first weight calculation formula; The first weight calculation formula is specifically: In the formula, Indicates the first One component node to be simulated. Indicates the first Adjust the initial connection weights of each component node to be simulated. This represents the weight adjustment coefficient corresponding to the global connection density metric. Indicates the first The global connection density index of each component node to be simulated. This represents the weight adjustment coefficient corresponding to the global structural hub index. Indicates the first The global structural hub degree index of each component node to be simulated. This represents the weight adjustment coefficient corresponding to the system-level propagation delay metric. Indicates the first The system-level propagation delay metric for each component node to be simulated.

5. The method of claim 1, wherein, When the loop is detected, the Tarjan algorithm is used to identify a strongly connected component between to-be-simulated component nodes with a non-zero in-degree value in the preprocessed signal stream, and the loop in the preprocessed signal stream is determined according to the strongly connected component; A set of to-be-simulated component nodes with a node attribute of allowing disconnection on the loop is taken as a candidate node set, a second weight calculation formula is called to calculate a disconnection connection adjustment weight of each to-be-simulated component node in the candidate node set, and a to-be-simulated component node with the largest weight is selected as a loop disconnection point; A delay module is inserted before the loop disconnection point to complete the loop disconnection processing, the preprocessed signal stream is updated, and the updated preprocessed signal stream is taken as the target signal stream; The second weight calculation formula is specifically: Comprise: In the formula, represents the first component node to be emulated, represents the first component node to be emulated, a broken ring connection adjustment weight, represents the first component node to be emulated, a component internal connection density index, represents a weight adjustment coefficient corresponding to the component internal connection density index, represents the first component node to be emulated, a loop breaking rate index, represents a weight adjustment coefficient corresponding to the loop breaking rate index, represents the first component node to be emulated, a residual graph perturbation degree index, represents a weight adjustment coefficient corresponding to the residual graph perturbation degree index.

6. A graphical simulation apparatus of a signal flow, characterized by, The original signal stream generation module is configured to detect a coupling relationship between to-be-simulated component nodes, and when the coupling relationship between the to-be-simulated component nodes is cross-domain coupling, generate an original signal stream based on the to-be-simulated component nodes and edge structure objects connecting the to-be-simulated component nodes; The preprocessed signal stream generation module is configured to compile and eliminate redundancies of the original signal stream by using a sparse Boolean matrix to obtain a preprocessed signal stream; The target signal stream generation module is configured to detect a loop in the preprocessed signal stream, and when the loop is detected, perform loop disconnection processing on the detected loop to generate a target signal stream. The target signal stream simulation module is configured to complete graphical simulation based on the target signal stream; wherein, When the coupling relationship between the to-be-simulated component nodes is cross-domain coupling, the edge structure objects connecting the to-be-simulated component nodes are type-labeled to obtain a cross-domain label of each edge structure object; A default delay time is set, and the original signal stream is generated based on each edge structure object, the to-be-simulated component nodes corresponding to each edge structure object, the reference weights of the to-be-simulated component nodes, the cross-domain labels and the default delay time; The target signal stream generation module is configured to detect a loop in the preprocessed signal stream, and when the loop is detected, perform loop disconnection processing on the detected loop to generate a target signal stream. ​ ​ Step one: initializing the pre-processed signal stream, determining the priority of each to-be-simulated component node in the pre-processed signal stream, and generating a priority queue based on the to-be-simulated component node and the corresponding priority; Step two: selecting the to-be-simulated component node corresponding to the highest priority in the priority queue as a source node, and adding the source node to an execution queue; Step three: determining the length of the execution queue, and if the length of the execution queue is less than the total number of to-be-simulated component nodes in the pre-processed signal stream, it indicates that there is a strong connected component forming a loop in the pre-processed signal stream; Step four: when a loop is detected, the detected loop is broken to generate a target signal stream; Step five: traversing all adjacent nodes of the source node in the priority queue, reducing the in-degree value of each adjacent node by one, and taking the adjacent node with a reduced in-degree value of 0 as a target node; Step six: deleting the source node in the priority queue and adding the target node to the priority queue, and updating the priority queue; Step seven: iteratively executing steps two to six until the priority queue is empty or the number of repeated iterations reaches a maximum iteration number, then stopping.

7. An apparatus for performing a method of graphical simulation of signal flow, characterized in that, comprise: a processor; a memory for storing processor-executable instructions; when the processor executes the executable instructions, the method of any one of claims 1 to 5 is implemented.

8. A non-transitory computer readable storage medium, comprising: comprise a computer program or instructions for storing a computer program or instructions, when the computer program or instructions are executed, the method of any one of claims 1 to 5 is implemented.

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