Reference current generation circuit for tracking bit line voltage and non-volatile memory

Abstract

This disclosure provides a reference current generation circuit for tracking bit line voltage and a non-volatile memory. The non-volatile memory includes a bit line clamping circuit to set the bit line voltage to a preset value before a read operation. The reference current generation circuit includes a tracking current generation circuit and a constant current generation circuit electrically connected. The constant current generation circuit generates and outputs a constant current based on the applied reference voltage. The tracking current generation circuit generates and outputs a tracking current to track changes in the current of the memory cell under the influence of the bit line voltage. The sum of the output constant current and the tracking current forms the reference current. The reference current generation circuit of this disclosure can track current changes caused by changes in bit line voltage and temperature of the memory cell, improving the accuracy and speed of read operations, avoiding the use of a reference array, and thus mitigating the risk of voltage stress.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more particularly to a reference current generation circuit for tracking bit line voltage and a non-volatile memory. Background Technology

[0002] Nor Flash chips, manufactured using ETOX (Electrically Tunneling Oxide, a process technology for non-volatile memory), are commonly used for code storage in electronic products. With technological advancements, applications demand increasingly higher chip capacity and speed, prompting the industry to continuously develop processes to produce Nor Flash devices with smaller unit sizes. However, while shrinking memory cell size increases chip storage density, it also leads to more significant stress and degradation effects during normal operation.

[0003] In traditional Nor Flash chips, a read operation reference array (LOR) is typically designed to meet high-speed and accurate read requirements. This LLR tracks the bit line voltage or temperature characteristics of the memory cells. However, during read operations, since both word lines and bit lines are under voltage, the memory cells experience a weak programming effect under prolonged voltage stress, leading to a higher threshold voltage and consequently a lower channel current. This causes read stress issues with the LLR. As process dimensions shrink, the voltage stress effect of the LLR becomes increasingly significant, greatly impacting the chip's read functionality and speed. For high-capacity products, the cumulative read stress time is longer, resulting in a greater impact. Summary of the Invention

[0004] The technical problem to be solved by this disclosure is to overcome the defect in the prior art where the voltage stress of the read operation reference array seriously affects the read function and speed of the chip as the size of Nor Flash process decreases, and to provide a reference current generation circuit for tracking bit line voltage and a non-volatile memory.

[0005] This disclosure solves the above-mentioned technical problems through the following technical solution:

[0006] According to a first aspect of this disclosure, a reference current generating circuit for tracking bit line voltage is provided, the reference current generating circuit being applied in a non-volatile memory, the non-volatile memory including a bit line clamping circuit, the bit line clamping circuit being used to set the bit line voltage to a preset voltage value before a read operation, the reference current generating circuit including a tracking current generating circuit and a constant current generating circuit electrically connected.

[0007] The constant current generating circuit is used to generate and output a constant current based on the input reference voltage;

[0008] The tracking current generating circuit is used to generate and output a tracking current for tracking changes in the current of the memory cell under the action of the bit line voltage.

[0009] The sum of the output constant current and the tracking current forms the reference current.

[0010] Optionally, the tracking current generating circuit includes a first resistor and a second resistor;

[0011] One end of the first resistor is electrically connected to the constant current generating circuit, the other end of the first resistor is connected to one end of the second resistor, and the other end of the second resistor is grounded.

[0012] The resistance values ​​of the first resistor and the second resistor are set to match the change in current of the storage unit.

[0013] Optionally, the constant current generating circuit includes a reference current generating circuit, a current replication circuit, and a current mirror circuit that are connected in sequence.

[0014] The current mirror circuit is connected to one end of the first resistor;

[0015] The reference current generating circuit is used to generate a reference current based on the accessed reference voltage, and output the reference current to the current replication circuit;

[0016] The current replication circuit is used to replicate the reference current, generate a replicated current, and output it to the current mirror circuit.

[0017] The current mirror circuit is used to mirror the replicated current to generate the constant current.

[0018] Optionally, the reference current generation circuit includes an error amplifier, a capacitor, a first NMOS (N-Metal-Oxide-Semiconductor) transistor, and a third resistor;

[0019] The positive terminal of the error amplifier is used to connect to the reference voltage, the negative terminal of the error amplifier is connected to the source of the first NMOS transistor and one end of the third resistor, and the output terminal of the error amplifier is connected to the first plate of the capacitor and the gate of the first NMOS transistor.

[0020] The drain of the first NMOS transistor is electrically connected to the current replication circuit, and the second plate of the capacitor and the other end of the third resistor are both grounded.

[0021] Optionally, the current replication circuit includes a first PMOS (P-Channel-Oxide-Semiconductor) transistor and a second PMOS transistor;

[0022] The source of both the first PMOS transistor and the source of the second PMOS transistor are connected to the power supply voltage.

[0023] The gate of the first PMOS transistor, the drain of the first PMOS transistor, the gate of the second PMOS transistor, and the drain of the first NMOS transistor are connected.

[0024] The drain of the second PMOS transistor is electrically connected to the current mirror circuit.

[0025] Optionally, the reference current generating circuit includes an error amplifier, a capacitor, a third PMOS transistor, and a third resistor;

[0026] The negative terminal of the error amplifier is used to connect to the reference voltage, the positive terminal of the error amplifier is connected to the second plate of the capacitor, the drain of the third PMOS transistor, and one end of the third resistor, and the output terminal of the error amplifier is electrically connected to the first plate of the capacitor, the gate of the third PMOS transistor, and the current replication circuit.

[0027] The source of the third PMOS transistor is connected to the power supply voltage, and the other end of the third resistor is grounded.

[0028] Optionally, the current replication circuit includes a fourth PMOS transistor;

[0029] The source of the fourth PMOS transistor is connected to the power supply voltage;

[0030] The gate of the fourth PMOS transistor is connected to the output terminal of the error amplifier, the first plate of the capacitor, and the gate of the third PMOS transistor.

[0031] The drain of the fourth PMOS transistor is electrically connected to the current mirror circuit.

[0032] Optionally, the reference current generating circuit further includes a fourth resistor;

[0033] The other end of the third resistor is connected to one end of the fourth resistor, and the other end of the fourth resistor is grounded.

[0034] The temperature coefficients of the third resistor and the fourth resistor are set to match the temperature state of the storage unit.

[0035] Optionally, the current mirror circuit includes a second NMOS transistor and a third NMOS transistor;

[0036] The drain of the second NMOS transistor, the gate of the second NMOS transistor, and the gate of the third NMOS transistor are electrically connected to the current replication circuit.

[0037] The drain of the third NMOS transistor is connected to one end of the first resistor;

[0038] The source of the second NMOS transistor and the source of the third NMOS transistor are both grounded;

[0039] And / or,

[0040] The temperature coefficient of the sum of the resistance values ​​of the first resistor and the second resistor is set to match the temperature state of the storage cell.

[0041] According to a second aspect of this disclosure, a non-volatile memory is provided, the non-volatile memory including the reference current generation circuit described in the first aspect of this disclosure.

[0042] Based on common knowledge in the field, the above optional conditions can be combined arbitrarily to obtain the optional examples of this disclosure.

[0043] The positive advancements of this disclosure are as follows: It proposes a novel reference current generation circuit for tracking bit line voltage. This circuit can track the current changes caused by changes in bit line voltage and temperature of the memory cell, ensuring sufficient current margin even with changes in bit line voltage and temperature. This improves the accuracy and speed of read operations, avoids the need for a reference array, and thus mitigates the risk of voltage stress. At the same time, the reference current generation circuit occupies a small space, making it suitable for the trend of chip process miniaturization. Attached Figure Description

[0044] Figure 1 A schematic diagram of an existing read operation framework using a reference array;

[0045] Figure 2 Channel current-word line voltage curves for different bit line voltages of memory cells in the erase state;

[0046] Figure 3 A comparison chart of test results for read voltage stress of reference array cells using different processes under high temperature conditions;

[0047] Figure 4 This is a schematic diagram of the first circuit structure of the reference current generating circuit of this disclosure;

[0048] Figure 5 The channel current-bit line voltage curves are typical for erase-state and program-state memory array cells;

[0049] Figure 6This is a schematic diagram of the second circuit structure of the reference current generating circuit of this disclosure;

[0050] Figure 7 This is a schematic diagram of the third circuit structure of the reference current generating circuit of this disclosure;

[0051] Figure 8 This is a schematic diagram of the fourth circuit structure of the reference current generating circuit of this disclosure;

[0052] Figure 9 This is a schematic diagram of the fifth circuit structure of the reference current generating circuit of this disclosure;

[0053] Figure 10 This is a schematic diagram of the sixth circuit structure of the reference current generating circuit of this disclosure;

[0054] Figure 11 This is a schematic diagram of the circuit structure for the read operation of the non-volatile memory disclosed herein. Detailed Implementation

[0055] The present disclosure is further illustrated below by way of embodiments, but the present disclosure is not limited to the scope of the embodiments described herein.

[0056] The prefixes such as "first" and "second" used in this disclosure are merely for distinguishing different descriptive objects and do not limit the position, order, priority, quantity, or content of the described objects. The use of ordinal numbers and other prefixes used to distinguish descriptive objects in this disclosure does not constitute a limitation on the described objects. The description of the described objects is given in the context of the embodiments, and the use of such prefixes should not constitute unnecessary restrictions. Furthermore, in the description of this embodiment, unless otherwise stated, "multiple" means two or more.

[0057] In traditional Nor Flash chips, the read operation reference array is composed of memory cells. To ensure manufacturing consistency, its size is often 16 word lines * 16 bit lines or 32 word lines * 32 bit lines, etc. Figure 1 As shown, the decoders in the X (horizontal) and Y (vertical) directions select the word lines and bit lines of the memory array to be read, and simultaneously select reference cells in the reference array. The currents of the two are compared to derive the data in the memory array. During the read operation, the word line voltage and bit line voltage of the reference array are consistent with those of the memory array. Because the characteristics of the reference array cells are consistent with those of the memory array cells, there is a natural tracking effect on the memory array cells. Whether it is the word line voltage, bit line voltage, or temperature characteristics, the memory cells can be tracked very well to ensure the accuracy of the read operation.

[0058] like Figure 2 As shown in the figure, the horizontal axis represents the word line voltage (unit: volts V), and the vertical axis represents the channel current (unit: microamps μA). The two different curves correspond to the channel current-word line voltage curves at a bit line voltage of 0.9V and 0.8V, respectively. Obviously, changes in word line voltage and bit line voltage will significantly affect the channel current. Therefore, voltage tracking is very important for ensuring the current margin of read operations.

[0059] For reference arrays, read stress is an unavoidable design consideration. Read stress refers to the voltage applied to word lines and bit lines during read operations. Prolonged voltage stress can lead to a weak programming effect in memory cells, causing a higher threshold voltage and consequently a lower channel current. In products with larger process dimensions, this stress effect is less noticeable and does not significantly impact chip operation over its lifespan. However, as process dimensions shrink further, this voltage stress effect becomes increasingly significant, greatly affecting the chip's read functionality and speed. For high-capacity products, the accumulated voltage stress on the reference array lasts longer, resulting in a greater impact.

[0060] like Figure 3 As shown in the figure, Ref0 and Ref1 represent reference array cells of different processes, and the horizontal axis represents time (unit: hours h). Under voltage stress of 0.9V or 0.7V at 125℃, Ref0 maintains a small current change for 4 hours. However, Ref1 of the more advanced process has a smaller and smaller current as time increases under the condition of 0.9V at 125℃. If the drain voltage is changed to 0.7V, there will be a significant improvement.

[0061] To address the voltage stress effect, existing solutions include: still using a reference array design, reducing the gate and drain voltages to decrease the cross voltage and thus reduce the voltage stress effect; or using multiple reference arrays, dividing the memory array into several smaller memory arrays, and mapping different reference arrays to different smaller memory arrays to reduce the voltage stress time; or using multiple reference arrays while reducing the gate and drain voltages to further reduce the impact of voltage stress.

[0062] However, while reducing the gate and drain voltages is simple to implement and can still track the word line voltage, bit line voltage, and temperature characteristics of the memory cell, the current will decrease, affecting the current margin of the read operation, and the voltage stress effect will still exist. As the process technology advances further, this solution will become ineffective. On the other hand, using multiple reference arrays will greatly increase the chip area, which is not suitable for the development requirements of process size reduction.

[0063] In view of this, this disclosure provides a reference current generation circuit for tracking bit line voltage and a non-volatile memory to solve the problem in the prior art where the voltage stress of the read operation reference array seriously affects the read function and speed of the chip as the size of Nor Flash process decreases.

[0064] Example 1

[0065] In one specific embodiment, a reference current generation circuit for tracking bit line voltage is provided. This reference current generation circuit is applied in a non-volatile memory, which includes a bit line clamping circuit. The bit line clamping circuit is used to set the bit line voltage to a preset voltage value before a read operation, such as... Figure 4 As shown, the reference current generating circuit includes a tracking current generating circuit 1 and a constant current generating circuit 2 that are electrically connected.

[0066] The constant current generating circuit 2 is used to generate and output a constant current based on the input reference voltage;

[0067] The tracking current generating circuit 1 is used to generate and output a tracking current for tracking changes in the current of the memory cell under the action of the bit line voltage.

[0068] The sum of the output constant current and the tracking current forms the reference current.

[0069] Specifically, such as Figure 5 As shown in the figure, the vertical axis represents the channel current, and the horizontal axis represents the bit line voltage. It can be seen that the actual channel current and bit line voltage have a non-linear relationship, regardless of whether the memory cell is in the erase state or the programmable state. In most cases, the bit line voltage operates between 0.4V and 1.2V. Therefore, for the reference current tracking the bit line, it is only necessary to ensure a sufficiently large current margin between the memory cell current and the reference current within the 0.4V to 1.2V voltage range. Thus, by fitting the channel current of the memory cell in the erase state and the channel current in the programmable state, the curve Iref-V, representing the magnitude of the reference current as the bit line voltage changes, can be obtained.

[0070] The reference current generating circuit consists of a tracking current generating circuit 1 and a constant current generating circuit 2. The constant current generating circuit 2 generates a constant current I1 under the drive of the reference voltage. The tracking current generating circuit 1 is an adjustable linear resistor string, and the sum of the resistance values ​​of the linear resistor string is the reciprocal of the slope of the Iref-V curve.

[0071] The reference current generation circuit is electrically connected to the bit line clamping circuit. During a memory cell read operation, the bit line clamping circuit precharges the bit line of the selected memory cell to be read to a stable preset voltage value. At the same time, the reference current generation circuit also receives an equal bit line voltage. The tracking current generation circuit 1 in the reference current generation circuit generates a tracking current I2 that varies with the bit line voltage under the drive of the bit line voltage. The generated constant current I1 and tracking current I2 are both transmitted to the Iref port to form a reference current corresponding to the bit line voltage, thereby realizing the tracking of the memory cell bit line voltage.

[0072] This specific implementation uses a reference current generation circuit to track the current changes caused by the bit line voltage changes of the memory cell, ensuring sufficient current margin when the bit line voltage changes, improving the accuracy and speed of read operations, avoiding the use of a reference array, and thus avoiding the risk of voltage stress; at the same time, the reference current generation circuit occupies little space, which is suitable for the development trend of chip process size reduction.

[0073] In one specific implementation, such as Figure 4 As shown, the tracking current generating circuit 1 includes a first resistor R1 and a second resistor R2; one end of the first resistor R1 is electrically connected to the constant current generating circuit 2, the other end of the first resistor R1 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is grounded to GND.

[0074] The resistance values ​​of the first resistor R1 and the second resistor R2 are set to match the change in current of the storage unit.

[0075] Specifically, the first resistor R1 and the second resistor R2 can be variable resistors. The first resistor R1 and the second resistor R2 are connected in series between the Iref port and ground. The sum of the resistance values ​​of the first resistor R1 and the second resistor R2 is adjusted to be the reciprocal of the slope of the Iref-V curve. When the bit line voltage (Iref port voltage) changes, the current through the resistor series will also change. The slope of the current change is the slope of the Iref-V curve, thereby realizing the tracking of the bit line voltage of the memory cell.

[0076] Furthermore, the first resistor R1 and the second resistor R2 can also be temperature-coefficient adjustable resistors, with the temperature coefficient of the sum of the resistance values ​​of the first resistor R1 and the second resistor R2 matched to the temperature state of the memory cell. For example, the temperature coefficients of the first resistor R1 and the second resistor R2 are opposite, one is a positive temperature coefficient and the other is a negative temperature coefficient. By adjusting the ratio of the resistance values ​​of the first resistor R1 and the second resistor R2, the temperature coefficient of the current flowing through the tracking current generation circuit 1 is made consistent with the temperature coefficient of the current of the memory cell, and the sum of the resistance values ​​of the first resistor R1 and the second resistor R2 is the reciprocal of the slope of the Iref-V curve, thereby achieving simultaneous tracking of the bit line voltage and temperature characteristics of the memory cell.

[0077] In one specific implementation, such as Figure 6 As shown, the constant current generating circuit 2 includes a reference current generating circuit 21, a current replication circuit 22, and a current mirror circuit 23 connected in sequence.

[0078] The current mirror circuit 23 is connected to one end of the first resistor R1;

[0079] The reference current generation circuit 21 is used to generate a reference current based on the input reference voltage and output the reference current to the current replication circuit 22;

[0080] The current replication circuit 22 is used to replicate the reference current, generate the replicated current, and output it to the current mirror circuit 23;

[0081] The current mirror circuit 23 is used to mirror the replicated current to generate a constant current.

[0082] The current mirror circuit 23 includes a second NMOS transistor MN2 and a third NMOS transistor MN3; the drain of the second NMOS transistor MN2, the gate of the second NMOS transistor MN2, and the gate of the third NMOS transistor MN3 are electrically connected to the current replication circuit 22; the drain of the third NMOS transistor MN3 is connected to one end of the first resistor R1; the source of the second NMOS transistor MN2 and the source of the third NMOS transistor MN3 are both grounded.

[0083] Specifically, the reference current generation circuit 21 generates a constant reference current with zero temperature drift based on the input reference voltage and transmits the reference current to the current replication circuit 22. The current replication circuit 22 replicates the reference current and provides it to the current mirror circuit 23. The third NMOS transistor MN3 in the current mirror circuit 23 mirrors the channel current of the second NMOS transistor MN2 and adds it to the tracking current of the tracking current generation circuit 1 to form a reference current. The magnitude of this reference current can reach the current magnitude of the Iref-V curve.

[0084] In one specific implementation, such as Figure 7As shown, the reference current generation circuit 21 includes an error amplifier EA, a capacitor C, a first NMOS transistor MN1, and a third resistor R3;

[0085] The positive terminal of the error amplifier EA is used to connect to the reference voltage Vref, the negative terminal of the error amplifier EA is connected to the source of the first NMOS transistor MN1 and one end of the third resistor R3, and the output terminal of the error amplifier EA is connected to the first plate of the capacitor C and the gate of the first NMOS transistor MN1.

[0086] The drain of the first NMOS transistor MN1 is electrically connected to the current replication circuit 22, and the second plate of capacitor C and the other end of the third resistor R3 are both grounded.

[0087] Specifically, the reference current generation circuit 21 includes an error amplifier EA, a first NMOS transistor MN1, a third resistor R3, and a capacitor C. The first NMOS transistor MN1 acts as a source follower. The gate of the first NMOS transistor MN1 is connected to the output terminal of the error amplifier EA, the source is connected to the third resistor R3, and the drain is connected to the current replication circuit 22. The third resistor R3 is connected between the source of the first NMOS transistor MN1 and ground. The positive terminal of the error amplifier EA is connected to a zero-temperature-drift reference voltage, and the negative terminal is connected to the third resistor R3 and the source of the first NMOS transistor MN1 to form negative feedback. The capacitor C is connected between the output terminal of the error amplifier EA and ground as a compensation capacitor.

[0088] In one specific implementation, such as Figure 7 As shown, the current replication circuit 22 includes a first PMOS transistor MP1 and a second PMOS transistor MP2;

[0089] The source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are both connected to the power supply voltage VDD.

[0090] The gate of the first PMOS transistor MP1, the drain of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2 are connected to the drain of the first NMOS transistor MN1.

[0091] The drain of the second PMOS transistor MP2 is electrically connected to the current mirror circuit 23.

[0092] Specifically, the first PMOS transistor MP1 and the second PMOS transistor MP2 in the current replication circuit 22 are connected to form a PMOS current mirror, which is used to replicate the reference current generated by the reference current generation circuit 21 and provide it to the current mirror circuit 23.

[0093] In one specific implementation, such as Figure 8 As shown, the reference current generating circuit 21 also includes a fourth resistor R4;

[0094] The other end of the third resistor R3 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is grounded.

[0095] The temperature coefficients of the third resistor R3 and the fourth resistor R4 are set to match the temperature state of the storage cell.

[0096] Specifically, due to Figure 4 The temperature coefficient of the medium current and the voltage tracking of the bit line are both adjusted by the resistor string in the current generation circuit 1. Therefore, the adjustment of the temperature coefficient and the resistance value of the resistor string will affect each other, resulting in low adjustment efficiency.

[0097] Therefore, a fourth resistor R4 is added to the reference current generation circuit 21. The third resistor R3 and the fourth resistor R4 are temperature coefficient adjustable resistors. By adjusting the ratio of the resistance values ​​of the third resistor R3 and the fourth resistor R4, the temperature characteristics consistent with the storage cell can be obtained. The tracking current generation circuit 1 only needs to adjust the bit line voltage tracking characteristics, thereby decoupling the temperature coefficient adjustment and the bit line voltage tracking adjustment, and effectively improving the adjustment efficiency of the bit line voltage characteristics and temperature characteristics.

[0098] It should be noted that the first resistor R1 and the second resistor R2 can be resistors with adjustable temperature coefficients or resistors with non-adjustable temperature coefficients. When the temperature coefficients of the first resistor R1 and the second resistor R2 are adjustable, it is only necessary to adjust the sum of the resistance values ​​of the first resistor R1 and the second resistor R2 to zero temperature drift.

[0099] In another specific implementation, such as Figure 9 As shown, the reference current generation circuit 21 includes an error amplifier EA, a capacitor C, a third PMOS transistor MP3, and a third resistor R3;

[0100] The negative terminal of the error amplifier EA is used to connect to the reference voltage Vref. The positive terminal of the error amplifier EA is connected to the second plate of the capacitor C, the drain of the third PMOS transistor MP3, and one end of the third resistor R3. The output terminal of the error amplifier EA is electrically connected to the first plate of the capacitor C, the gate of the third PMOS transistor MP3, and the current replication circuit 22.

[0101] The source of the third PMOS transistor MP3 is connected to the power supply voltage, and the other end of the third resistor R3 is grounded.

[0102] Specifically, the reference current generating circuit 21 can be composed of two stages of amplifiers. The first stage is an error amplifier EA, whose positive terminal is connected to the drain of the third PMOS transistor MP3, its negative terminal is connected to the zero-temperature drift reference voltage, and its output terminal is connected to the gate of the third PMOS transistor MP3. The second stage is a PMOS common-source amplifier (the third PMOS transistor MP3), whose source is connected to the power supply voltage, its drain is connected to the third resistor R3, and its gate is connected to the output terminal of the error amplifier EA. The third resistor R3 is connected between the drain of the third PMOS transistor MP3 and ground. The drain of the third PMOS transistor MP3 and one end of the third resistor R3 are connected to the positive terminal of the error amplifier EA to form negative feedback. The capacitor C is connected to the gate and drain of the third PMOS transistor MP3 as Miller compensation.

[0103] In one specific implementation, such as Figure 9 As shown, the current replication circuit 22 includes a fourth PMOS transistor MP4;

[0104] The source of the fourth PMOS transistor MP4 is connected to the power supply voltage;

[0105] The gate of the fourth PMOS transistor MP4 is connected to the output terminal of the error amplifier EA, the first plate of the capacitor C, and the gate of the third PMOS transistor MP3.

[0106] The drain of the fourth PMOS transistor MP4 is electrically connected to the current mirror circuit 23.

[0107] Specifically, the current replication circuit 22 can be a PMOS current source composed of the fourth PMOS transistor MP4, with its gate connected to the output terminal of the error amplifier EA, its source connected to the power supply voltage, and its drain connected to the current mirror circuit 23.

[0108] In one specific implementation, such as Figure 10 As shown, the reference current generating circuit 21 also includes a fourth resistor R4;

[0109] The other end of the third resistor R3 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is grounded.

[0110] The temperature coefficient of the sum of the resistances of the third resistor R3 and the fourth resistor R4 is set to match the temperature state of the storage cell.

[0111] The working principle can be found in the description of the foregoing embodiments, and will not be repeated here.

[0112] This embodiment uses a reference current generation circuit to track the current changes caused by changes in the bit line voltage and temperature of the memory cell, ensuring sufficient current margin even with changes in bit line voltage and temperature. This improves the accuracy and speed of read operations and avoids the risk of voltage stress by avoiding the use of a reference array.

[0113] Example 2

[0114] This embodiment provides a non-volatile memory, which includes the reference current generation circuit provided in Embodiment 1 above.

[0115] Specifically, such as Figure 11 As shown, the non-volatile memory includes a storage array, a reference current generation circuit, a Y-axis decoder, a bit line clamping circuit, and a sensitive amplifier. During a read operation, the bit line clamping circuit sets the bit line voltage to a preset voltage value. The storage array and the reference current generation circuit output the storage cell current and the reference current, respectively. The sensitive amplifier compares the storage cell current and the reference current to obtain the data in the storage array.

[0116] Non-volatile memory can be, but is not limited to, Nor Flash.

[0117] In this embodiment, the reference current generation circuit can track the current changes caused by the bit line voltage and temperature changes of the memory cell, ensuring that there is still sufficient current margin when the bit line voltage and temperature change, improving the accuracy and speed of the read operation, avoiding the use of a reference array, and thus avoiding the risk of voltage stress; at the same time, the reference current generation circuit occupies little space, which is suitable for the development trend of chip process size reduction.

[0118] While specific embodiments of this disclosure have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of this disclosure is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of this disclosure, but all such changes and modifications fall within the scope of protection of this disclosure.

Claims

1. A reference current generation circuit for tracking bit line voltage, characterized in that, The reference current generation circuit is applied in a non-volatile memory, which includes a bit line clamping circuit. The bit line clamping circuit is used to set the bit line voltage to a preset voltage value before a read operation. The reference current generation circuit includes a tracking current generation circuit and a constant current generation circuit that are electrically connected. The constant current generating circuit is used to generate and output a constant current based on the input reference voltage; The tracking current generating circuit is used to generate and output a tracking current for tracking changes in the current of the memory cell under the action of the bit line voltage. The sum of the output constant current and the tracking current forms the reference current; The tracking current generating circuit includes a first resistor and a second resistor; One end of the first resistor is electrically connected to the constant current generating circuit, the other end of the first resistor is connected to one end of the second resistor, and the other end of the second resistor is grounded. The resistance values ​​of the first resistor and the second resistor are set to match the change in current of the storage unit. The constant current generating circuit includes a reference current generating circuit, a current replication circuit, and a current mirror circuit that are connected in sequence. The current mirror circuit is connected to one end of the first resistor; The reference current generating circuit is used to generate a reference current based on the accessed reference voltage, and output the reference current to the current replication circuit; The current replication circuit is used to replicate the reference current, generate a replicated current, and output it to the current mirror circuit. The current mirror circuit is used to mirror the replicated current to generate the constant current.

2. The reference current generating circuit according to claim 1, characterized in that, The reference current generating circuit includes an error amplifier, a capacitor, a first NMOS transistor, and a third resistor; The positive terminal of the error amplifier is used to connect to the reference voltage, the negative terminal of the error amplifier is connected to the source of the first NMOS transistor and one end of the third resistor, and the output terminal of the error amplifier is connected to the first plate of the capacitor and the gate of the first NMOS transistor. The drain of the first NMOS transistor is electrically connected to the current replication circuit, and the second plate of the capacitor and the other end of the third resistor are both grounded.

3. The reference current generating circuit according to claim 2, characterized in that, The current replication circuit includes a first PMOS transistor and a second PMOS transistor. The source of both the first PMOS transistor and the source of the second PMOS transistor are connected to the power supply voltage. The gate of the first PMOS transistor, the drain of the first PMOS transistor, the gate of the second PMOS transistor, and the drain of the first NMOS transistor are connected. The drain of the second PMOS transistor is electrically connected to the current mirror circuit.

4. The reference current generating circuit according to claim 1, characterized in that, The reference current generating circuit includes an error amplifier, a capacitor, a third PMOS transistor, and a third resistor; The negative terminal of the error amplifier is used to connect to the reference voltage, the positive terminal of the error amplifier is connected to the second plate of the capacitor, the drain of the third PMOS transistor, and one end of the third resistor, and the output terminal of the error amplifier is electrically connected to the first plate of the capacitor, the gate of the third PMOS transistor, and the current replication circuit. The source of the third PMOS transistor is connected to the power supply voltage, and the other end of the third resistor is grounded.

5. The reference current generating circuit according to claim 4, characterized in that, The current replication circuit includes a fourth PMOS transistor; The source of the fourth PMOS transistor is connected to the power supply voltage; The gate of the fourth PMOS transistor is connected to the output terminal of the error amplifier, the first plate of the capacitor, and the gate of the third PMOS transistor. The drain of the fourth PMOS transistor is electrically connected to the current mirror circuit.

6. The reference current generating circuit according to any one of claims 2 to 5, characterized in that, The reference current generating circuit also includes a fourth resistor; The other end of the third resistor is connected to one end of the fourth resistor, and the other end of the fourth resistor is grounded. The temperature coefficients of the third resistor and the fourth resistor are set to match the temperature state of the storage unit.

7. The reference current generating circuit according to any one of claims 1 to 5, characterized in that, The current mirror circuit includes a second NMOS transistor and a third NMOS transistor; The drain of the second NMOS transistor, the gate of the second NMOS transistor, and the gate of the third NMOS transistor are electrically connected to the current replication circuit. The drain of the third NMOS transistor is connected to one end of the first resistor; The source of the second NMOS transistor and the source of the third NMOS transistor are both grounded; And / or, The temperature coefficient of the sum of the resistance values ​​of the first resistor and the second resistor is set to match the temperature state of the storage cell.

8. A non-volatile memory, characterized in that, The non-volatile memory includes a reference current generation circuit as described in any one of claims 1 to 7.

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