Multi-level master-slave architecture frequency converter based on clock source synchronization control method and system

Abstract

This invention relates to a multi-level master-slave architecture frequency converter based on a clock source synchronous control method and system, comprising multiple six-phase motors driving the same load and mechanically connected via a long shaft system. Each of the six-phase motors is driven by a master-slave frequency converter. The master frequency converter of one of the six-phase motors serves as the first-level control link, the master frequency converters of all six-phase motors serve as the second-level control link, and the current control loops and execution units of all frequency converters serve as the third-level control link. The master control systems of all frequency converters are connected to a system clock source serving as a unified time reference via a high-speed communication bus. The three-level master-slave architecture control achieves time-division calibration of control command calculation, distribution, and application. This method is suitable for applications where multiple frequency converters and multiple motors collaboratively drive ultra-high power long shaft loads, effectively compensating for control asynchrony problems caused by communication delays, and significantly improving the speed synchronization, torque balance capability, and operational reliability of the multi-motor drive system.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of frequency converter control for driving motor operation, and particularly discloses a clock source synchronization control method and system for a multi-level master-slave architecture frequency converter, which is particularly suitable for the case of driving a super large power long shaft load by multiple six-phase motors. BACKGROUND

[0002] In large industrial equipment, frequency converters are used as driving devices to provide stable driving output for motors and the loads driven by the motors. Due to the power of the frequency converter power devices and the power of a single frequency converter, a single frequency converter or even a single master-slave structure of multiple frequency converters cannot complete the driving of such loads. A super large load device with a power of hundreds of megawatts needs to be driven by multiple frequency converters and multiple motors. In order to increase the capacity of a single motor in a limited space, a double-winding six-phase motor is usually used as a driving motor. The two sets of windings of the motor are driven by two frequency converters, so that a higher equivalent power output of a motor is achieved. A load device needs to be driven by multiple motors, and each six-phase motor needs to be driven by two frequency converters. Therefore, there is a cooperative operation relationship between multiple motors, and a hierarchical architecture is used for the control part of the frequency converter to achieve coordinated output, thereby forming a multi-level master-slave architecture frequency converter driving system.

[0003] In such a system in which multiple frequency converters and multiple motors are used to drive the same large power load device, the mechanical characteristics of the load device are usually sensitive, which can easily cause a slight deviation and damage to the device. Therefore, the requirements for the start-stop synchronization of the frequency converter control motor and the control synchronization in the multi-level master-slave architecture frequency converter driving system are extremely high, and the requirements for control accuracy are also extremely high, such as zero-speed starting without reversing, synchronous starting of the motors at both ends of the load long shaft without mutual torsion, and control accuracy of the rotational speed being better than 0.02% under each driving rotational speed. These requirements pose extremely high requirements for the start-stop synchronization and control synchronization of the driving system.

[0004] In the multi-level master-slave architecture frequency converter driving system, due to the complexity of the communication level and the inherent delay of signal transmission, the start-stop actions of the frequency converters are not synchronized, which can further cause device vibration, efficiency reduction, control accuracy reduction, and even mechanical damage. Traditional solutions usually use hardware trigger synchronization, reduce the communication level, or use a simple master-slave cascade structure to reduce synchronization errors, but often have the following deficiencies:

[0005] 1. It is difficult to balance the flexibility and scalability under the multi-level architecture;

[0006] 2. It is not possible to finely time-constrain the calculation, transmission, and application of control data at each level;

[0007] 3. In the case of inevitable communication delay, the compensation ability of the existing scheme for the delay is limited.

[0008] Therefore, it is necessary to design a new multi-level master-slave architecture frequency converter synchronous control driving system, which can overcome the problem of control asynchronization caused by communication delay while maintaining the flexibility of the layered architecture of the driving system, improve the speed synchronization of the system, guarantee the torque balance ability, and improve the operation reliability of the driving system. SUMMARY

[0009] The purpose of the present application is to design a multi-level master-slave architecture frequency converter based on clock source synchronization control method and system to solve the problems of start-stop and control asynchronization, speed and torque imbalance in the existing multi-level master-slave architecture frequency converter driving system caused by communication delay. By introducing a unified time reference and a clear timing distribution mechanism, the unified clock source is used to calculate, transmit and apply control data based on time calibration and unified update, so as to realize the precise synchronization control of multiple frequency converters on six-phase motors (hereinafter referred to as motors) under complex hierarchical structure.

[0010] To achieve the above purpose, the present application provides a multi-level master-slave architecture frequency converter based on clock source synchronization control method and system. The multi-level master-slave architecture frequency converter based on clock source synchronization control system comprises a multi-level master-slave architecture frequency converter. The multi-level master-slave architecture frequency converter comprises multiple six-phase motors driving the same load and connected by a long shaft system. Two sets of windings of the six-phase motor are driven by the corresponding frequency converters respectively, and the two frequency converters driving the two sets of windings of the same six-phase motor are connected to each other through master-slave control communication signal lines. One of the frequency converters is a master frequency converter, and the other is a slave frequency converter. The master frequency converters corresponding to each six-phase motor are connected through master-slave control communication signal lines. The synchronization control system is provided with a system clock source, and is connected to the master control system of each frequency converter through a high-speed communication bus for providing a unified digital clock signal as a time reference.

[0011] The synchronization control system takes the master frequency converter of one of the six-phase motors as the first level control link, and includes a speed curve generation unit of the master frequency converter. The master frequency converters of all six-phase motors are taken as the second level control link, and include speed regulators and flux regulator units of all master frequency converters. The current control loop and execution unit of all frequency converters are taken as the third level control link, and include excitation current regulators and torque current regulators of all frequency converters.

[0012] The high-speed communication bus is used for transmitting each instruction and digital clock signal between the first level control link, the second level control link and the third level control link, and the first level control link, the second level control link and the third level control link are used for data calculation, transmission and application according to the unified digital clock signal provided by the system clock source, so as to realize the synchronous control of the multiple frequency converters.

[0013] The frequency of the digital clock signal provided by the system clock source is 10 f Hz, wherein f is the data update frequency of each master control system, and the typical value is 6.4 kHz, and the transmission rate of the digital clock signal of the system clock source is 64 kHz.

[0014] The multi-level master-slave architecture frequency converter based on the clock source synchronous control method comprises the following steps:

[0015] S1, according to a preset clock count calibration sequence, a synchronous digital clock signal count value is provided to the master control system of each frequency converter through a unified system clock source;

[0016] S2, the first level control link generates a reference speed instruction according to an external start-stop signal and a speed given instruction, and distributes the reference speed instruction to the second level control link when receiving the count value corresponding to the preset clock count calibration sequence;

[0017] S3, the second level control link generates a torque reference current instruction and a reference excitation current instruction according to the received reference speed instruction, and distributes the torque reference current instruction and the reference excitation current instruction to the third level control link when the preset count value is received;

[0018] S4, the third level control link generates a torque voltage instruction and an excitation voltage instruction according to the torque reference current instruction and the reference excitation current instruction, and drives the synchronous operation of the multiple six-phase motors;

[0019] S5, the multi-level master-slave architecture frequency converter completes the corresponding work of the clock calibration moment in the preset clock count calibration sequence according to the count value of the synchronous digital clock signal provided by the system clock source, and all the frequency converters synchronously apply the newly generated torque voltage instruction and excitation voltage instruction, so as to realize the synchronous control of the multiple frequency converters.

[0020] In the synchronous control method, according to the preset clock count calibration sequence, 0-9, a total of 10 different count values are generated by the system clock source, and the specific control timing corresponding to different count values is as follows:

[0021] (1) the first level control link calculates a new reference speed instruction according to an external start-stop signal and a speed given instruction when the count value is 1, and sends the reference speed instruction to the second level control link when the count value is 2;

[0022] (2) the second level control link operates the received reference speed instruction to obtain a torque reference current instruction and a reference excitation current instruction when the count value is 3, and sends the two current instructions to the third level control link when the count value is 4;

[0023] (3) the third level control link adjusts and operates the received reference torque current instruction and the reference excitation current instruction to obtain a torque voltage instruction and an excitation voltage instruction when the count value is 5;

[0024] (4) when the count value is converted from 9 to 0, the main control system of all frequency converters synchronously applies the torque voltage instruction and the excitation voltage instruction control data obtained by the above calculation to drive the corresponding six-phase motor winding to operate.

[0025] The beneficial effects of the application are:

[0026] 1. The application limits the influence of communication delay within the same control period by introducing a unified clock source and binding the calculation, transmission and application of control data of each level to the preset clock count value, and synchronously updating the control data at the unified count jump moment, thereby fundamentally improving the time synchronization during the start-stop action and operation process of multiple frequency converters;

[0027] 2. The three-level master-slave architecture simultaneously realizes the cooperative control between the motors and between the double windings of the same six-phase motor, which is beneficial to maintaining the uniformity of the rotational speed of the two motors and the balance of the torque in the long shaft structure, and reducing the mechanical vibration and torsional vibration risk;

[0028] 3. The control timing under the conditions of zero-speed starting and high-precision speed regulation is finely designed, so that the multi-motor drive system can obtain high speed synchronization accuracy and steady speed accuracy in the full speed range, and meet the strict index requirement that the speed control accuracy is better than 0.02%;

[0029] 4. The synchronization mechanism of the application is realized based on the clock source and the high-speed communication bus, and has less dependence on hardware trigger signals, can adapt to multi-motor drive systems of different structures and scales without significantly increasing the hardware complexity, and has good engineering realizability and expansibility. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a schematic diagram of the multi-level master-slave architecture frequency converter drive system structure of the application.

[0031] Figure 2 Figure 1 is a schematic diagram of the control flow of the multi-level master-slave architecture frequency converter driving system of the present application.

[0032] Figure 3 Figure 2 is a schematic diagram of the level control relationship of the multi-level master-slave architecture frequency converter driving system of the present application.

[0033] Figure 4 Figure 3 is a schematic diagram of the synchronization control process of the multi- frequency converter of the present application based on the system clock source.

[0034] Figure 5 Figure 4 is a schematic diagram of the start timing of the multi-frequency converter synchronization control method of the present application.

[0035] 1, first motor M1; 2, second motor M2; 3, system clock source; 5, long axis system connecting piece; 6, high-speed communication signal line;

[0036] 7, first master-slave control communication signal line; 71, second master-slave control communication signal line; 72, third master-slave control communication signal line;

[0037] 8, first level control link; 81, speed curve generation link;

[0038] 9, second level control link; 91, first motor M1 torque current and excitation current given generation link; 92, second motor M2 torque current and excitation current given generation link;

[0039] 10, third level control link; 101, first motor M1 two winding current regulator link; 102, second motor M2 two winding current regulator link;

[0040] 11, first frequency converter VFD11; 12, second frequency converter VFD12; 13, first winding of first motor M1; 14, second winding of first motor M1;

[0041] 21, third frequency converter VFD21; 22, fourth frequency converter VFD22; 23, first winding of second motor M2; 24, second winding of second motor M2;

[0042] Speedref is the reference speed command calculated by the first frequency converter VFD11 through the speed curve; Idsref is the reference excitation current command; Iqsref is the torque reference current command; Vdsref is the excitation voltage command; Vqsref is the torque voltage command. DETAILED DESCRIPTION

[0043] The present application will be further described below in conjunction with the drawings and specific embodiments.

[0044] The application is a multi-level master-slave architecture frequency converter based on clock source synchronization control method and system, as shown in the figure Figure 1 In the embodiment, the multi-level master-slave architecture frequency converter based on clock source synchronization control system adopts two six-phase motors, namely first motor M1 and second motor M2, which are mechanically connected through long shaft system connecting piece 5 and jointly drive the same load to operate. In the long shaft system structure, the torque driving of the two motors is not uniform or the speed is not synchronized, which is easy to cause mechanical torsional vibration, and in severe cases, it can cause fatigue fracture of the long shaft system, so the system has high requirements for the speed synchronization and torque balance of the motor. The two sets of windings of the first motor M1 are driven by the first frequency converter VFD11 and the second frequency converter VFD12, and the two sets of windings of the second motor M2 are driven by the third frequency converter VFD21 and the fourth frequency converter VFD22. The system clock source 3 is connected with the main control systems of the four frequency converters through high-speed communication signal lines 6, and provides a unified reference clock reference for each main control system. The first frequency converter VFD11 and the second frequency converter VFD12 are connected through the second master-slave control communication signal line 71 and correspondingly drive the two sets of windings of the first motor M1, wherein the first frequency converter VFD11 is the master frequency converter, and the second frequency converter VFD12 is the slave frequency converter. The third frequency converter VFD21 and the fourth frequency converter VFD22 are connected through the third master-slave control communication signal line 72 and correspondingly drive the two sets of windings of the second motor M2, wherein the third frequency converter VFD21 is the master frequency converter, and the fourth frequency converter VFD22 is the slave frequency converter. The first frequency converter VFD11 and the third frequency converter VFD21 are connected through the first master-slave control communication signal line 7, wherein the first frequency converter VFD11 is the master frequency converter, and the third frequency converter VFD21 is the slave frequency converter.

[0045] As shown in the figure Figure 2 and Figure 3As shown, at the control level, the first inverter VFD11, acting as the first-level control link 8, receives the user's start / stop signal and speed command. After speed curve acceleration adjustment, it generates a reference speed command and shares this reference speed command with the third inverter VFD21 via the high-speed communication signal line 6. The speed regulator and flux regulator links of the first inverter VFD11 and the third inverter VFD21, acting as the second-level control link 9, calculate the torque reference current command based on the received reference speed command through their respective speed regulators, and simultaneously generate a reference excitation current command through the flux regulator. The first inverter VFD11 shares the two current commands with the second inverter VFD12, and the third inverter VFD21 shares the two current commands with the fourth inverter VFD22. Throughout the entire drive process, the reference data source obtained by all four inverters is based on the data source obtained at the same time from the system clock source 3. The current control loop and execution unit of the four inverters, acting as the third-level control link 10, further enhance the control process. The excitation voltage command Vdsref and torque voltage command Vqsref in the rotating coordinate system generated by the third-level control loop 10 are transformed into a three-phase reference voltage U by VR / 2-3. aref U bref U cref The output is modulated by the SVPWM actuator. The specific implementation of the VR / 2-3 conversion is as follows: the excitation voltage command Vdsref and the torque voltage command Vqsref are combined with the rotating magnetic field orientation angle θ to perform a Park inverse transformation to obtain the voltage command U. alpha with U beta Then, the three-phase reference voltage command U is generated through Clarke inverse transformation. aref U bref U cref Ultimately, at the same moment, all four frequency converters output corresponding voltage waveforms through their respective current loop control loops, achieving coordinated drive of the two six-phase motors, thereby completing the joint drive of the long-shaft load. The formula for the Park inverse transform is:

[0046] ;

[0047] The formula for the Clarke inverse transform is:

[0048] .

[0049] like Figure 4 As shown, in the synchronous control process of multiple frequency converters based on system clock source 3 in this invention, system clock source 3 transmits digital clock signals to the main control system of each frequency converter through high-speed communication signal line 6 according to a preset clock counting calibration sequence, and the transmission frequency is fixed at 10. fHz, the update frequency of each main control system for calculating and transmitting control data is respectively f Hz. That is, within one data update cycle of the main control system, system clock source 3 will generate 10 different count values ​​from 0 to 9. Each main control system executes the corresponding control operation upon receiving a different count value. The specific control timing is as follows:

[0050] 1. The first-level control loop calculates a new reference speed command when the count value is 1, and sends the reference speed command to the second-level control loop when the count value is 2; the first-level control loop includes the speed curve generation part of the first frequency converter VFD11.

[0051] 2. When the count value is 3, the second-level control loop calculates the received reference speed command to obtain the torque reference current command and the reference excitation current command. When the count value is 4, the two current commands are sent to the third-level control loop. The second-level control loop includes the speed regulator part and the flux regulator part of the first frequency converter VFD11 and the third frequency converter VFD21.

[0052] 3. When the count value is 5, the third-level control loop adjusts and calculates the received reference torque current command and reference excitation current command to obtain the torque voltage command and excitation voltage command respectively. The third-level control loop includes the excitation current regulator part and the torque current regulator part of all four frequency converters.

[0053] 4. After the multi-level master-slave architecture frequency converter completes the corresponding work of one clock calibration moment in the preset clock counting calibration sequence according to the counting value of the synchronous digital clock signal provided by the system clock source, that is, when the counting value changes from 9 to 0, the master control system of all frequency converters synchronously applies the newly calculated torque voltage command and excitation voltage command control data to drive their respective motor windings to run.

[0054] Therefore, this invention divides a control cycle into multiple counting time slots, sequentially connecting the three stages of "calculation-transmission-application" at different levels, and synchronously applying the control data at a unified time, thereby ensuring strict time synchronization of the reference current and voltage commands used by the drive motor during operation. Generally, the control data update frequency... f The typical value is 6.4 kHz, corresponding to a transmission rate of 64 kHz for system clock source 3.

[0055] like Figure 5As shown, in the standby startup condition, to ensure that the operating speed and output torque of the first motor M1 and the second motor M2 remain consistent, the first-level control loop obtains the start command when the count value is 1, and sequentially transmits the start command to the second-level and third-level control loops according to the preset counting sequence. The main control systems of all frequency converters synchronously execute startup control when the count value changes from 9 to 0, thereby achieving synchronous startup of the four frequency converters and two six-phase motors, avoiding unbalanced torque between the motors at both ends of the long shaft.

[0056] In the synchronous control method described in this invention, when the multi-level master-slave architecture frequency converter performs corresponding work based on the clock source synchronous control system according to the received digital clock signal, the main control system of the frequency converter can execute the corresponding instructions by reading the non-transient storage medium storing executable instructions. These executable instructions can also be stored in the form of a chip connected to the main control system of the frequency converter.

[0057] Those skilled in the art will understand that, without departing from the spirit of the present invention, various equivalent or equivalent substitutions or combinations of the above embodiments fall within the protection scope of the present invention.

Claims

1. A method for clock source synchronization control of a multi-level master-slave architecture frequency converter, characterized in that, The multi-level master-slave architecture frequency converter comprises multiple six-phase motors driving the same load and connected by a long shaft system, two sets of windings of the six-phase motor are respectively driven by a corresponding frequency converter, and two frequency converters driving two sets of windings of the same six-phase motor are connected with each other through master-slave control communication signal lines, one of the frequency converters is a master frequency converter, and the other is a slave frequency converter, each master frequency converter corresponding to each six-phase motor is connected with each other through the master-slave control communication signal lines, and the master control systems of each frequency converter are connected with a system clock source through a high-speed communication bus, the master frequency converter of one six-phase motor is a first-level control link, the master frequency converters of all six-phase motors are second-level control links, and the current control loops and execution units of all frequency converters are third-level control links. S1, according to a preset clock counting calibration sequence, a counting value of a synchronous digital clock signal is provided to the master control systems of the frequency converters through a unified system clock source; S2, the first-level control link generates a reference speed instruction according to an external start-stop signal and a speed given instruction, and distributes the reference speed instruction to the second-level control link when a counting value corresponding to the preset clock counting calibration sequence is received; S3, the second-level control link generates a torque reference current instruction and a reference excitation current instruction according to the received reference speed instruction, and distributes the torque reference current instruction and the reference excitation current instruction to the third-level control link when a preset counting value is received; S4, the third-level control link generates a torque voltage instruction and an excitation voltage instruction according to the torque reference current instruction and the reference excitation current instruction, and drives multiple six-phase motors to synchronously operate; S5, after the frequency converters complete the corresponding work of a clock calibration moment in the preset clock counting calibration sequence according to the counting value of the synchronous digital clock signal provided by the system clock source, all the frequency converters synchronously apply the newly generated torque voltage instruction and excitation voltage instruction, and the synchronous control of the multiple frequency converters is realized.

2. The method according to claim 1, wherein the multi-level master-slave architecture frequency converter based on clock source synchronization control method is characterized in that: In the synchronous control method, according to the preset clock counting calibration sequence, the system clock source generates 10 different counting values of 0-9, and the specific control time sequence corresponding to different counting values is as follows: (1) the first-level control link calculates a new reference speed instruction according to an external start-stop signal and a speed given instruction when the counting value is 1, and sends the reference speed instruction to the second-level control link when the counting value is 2; (2) the second-level control link operates the received reference speed instruction to obtain a torque reference current instruction and a reference excitation current instruction when the counting value is 3, and sends the two current instructions to the third-level control link when the counting value is 4; (3) the third-level control link adjusts and operates the received reference torque current instruction and reference excitation current instruction to obtain a torque voltage instruction and an excitation voltage instruction respectively when the counting value is 5. (4) When the count value is converted from 9 to 0, the main control system of all the frequency converters synchronously applies the torque voltage command and the excitation voltage command control data calculated according to the control timing (3) to drive the corresponding six-phase motor windings to operate.

3. A clock source synchronization control system based on a multi-level master-slave architecture frequency converter, used for the clock source synchronization control method based on a multi-level master-slave architecture frequency converter in any one of claims 1 to 2, characterized in that The synchronous control system comprises a multi-level master-slave architecture frequency converter, the multi-level master-slave architecture frequency converter comprises multiple six-phase motors driving the same load and connected by a long shaft system, two sets of windings of the six-phase motors are respectively driven by the corresponding frequency converters, and the two frequency converters driving the two sets of windings of the same six-phase motor are connected with each other through master-slave control communication signal lines, one of the frequency converters is a master frequency converter, and the other is a slave frequency converter, the master frequency converters corresponding to the six-phase motors are connected with each other through the master-slave control communication signal lines, the synchronous control system is provided with a system clock source, and is connected with the main control systems of the frequency converters through a high-speed communication bus, and is used to provide a unified digital clock signal as a time reference.

4. The multi-level master-slave architecture frequency converter based clock source synchronization control system according to claim 3, wherein: The synchronous control system takes the master frequency converter of one of the six-phase motors as a first-level control link, and comprises a speed curve generation unit of the master frequency converter; takes the master frequency converters of all the six-phase motors as a second-level control link, and comprises a speed regulator and a flux regulator unit of all the master frequency converters; and takes a current control loop and an execution unit of all the frequency converters as a third-level control link, and comprises an excitation current regulator and a torque current regulator unit of all the frequency converters.

5. The multi-level master-slave architecture frequency converter based clock source synchronization control system according to claim 4, wherein: The high-speed communication bus is used to transmit each command and digital clock signal between the first-level control link, the second-level control link and the third-level control link, and the first-level control link, the second-level control link and the third-level control link are used for data calculation, transmission and application according to the unified digital clock signal provided by the system clock source, so as to realize the synchronous control of the multiple frequency converters.

6. The multi-level master-slave architecture frequency converter based clock source synchronization control system according to claim 3 or 5, characterized in that: The digital clock signal provided by the system clock source has a frequency of 10 f Hz, wherein f is the data update frequency of each master system, f The value of is 6.4 kHz, and the transmission rate of the digital clock signal of the system clock source is 64 kHz.

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