Low-duty-ratio distortion capacitor isolation OOK signal modulation and demodulation circuit

Abstract

The invention discloses a low duty ratio distortion capacitance isolation OOK signal modulation and demodulation circuit. The circuit comprises a differential OOK modulation circuit, a high-voltage isolation capacitor Ctp, a high-voltage isolation capacitor Crp, a high-voltage isolation capacitor Ctn, a high-voltage isolation capacitor Crn, an input buffer circuit, a differential filtering amplification circuit, an envelope detection circuit, a PVT fluctuation detection circuit, an error compensation calculation circuit and a reference voltage adjustment circuit. On the basis of the prior art, the error amount brought by PVT fluctuation to the duty ratio characteristic of the isolator is detected in real time, then the corresponding error compensation amount is calculated through the error compensation calculation circuit, and finally the reference voltage of an existing envelope detection circuit is adjusted and compensated through the reference voltage adjusting circuit. Adjustment of the duty ratio of the OOK demodulation output signal is realized, and low duty ratio distortion is realized. The signal transmission circuit can be applied to various signal transmission circuits adopting the OOK technology for signal transmission.

Description

TECHNICAL FIELD

[0001] The application relates to a low-duty-cycle distortion capacitive isolation OOK signal modulation and demodulation circuit and belongs to the technical field of integrated circuits. BACKGROUND

[0002] Isolation transmission is an application scheme for transmitting signal energy or signals between two independent systems while blocking voltage and current between the two systems. A circuit for realizing the isolation transmission function is called an isolator chip. The isolator chip for isolation transmission is widely used in current electronic communication systems due to its excellent electrical isolation characteristics. In the current industrial electronic development process, the market has increasingly strict requirements for small-area, low-power and high-speed isolation chips. The capacitive isolation technology based on on-off keying (OOK) modulation has a very wide application prospect due to its high reliability and small-area characteristics.

[0003] A kind of OOK isolator modulation and demodulation circuit and its working circuit waveform schematic diagram are given in patent application CN202310590055.1, see Figure 1 and Figure 2 OOK isolator modulation and demodulation circuit includes a transmitter on the left side of the high-voltage capacitor and a receiver on the right side. The transmitter samples the level of the input signal. If the input is high, the carrier is transmitted across the isolation barrier. If the input is low, no energy is transmitted to the receiver. The receiver demodulates the signal using envelope detection. The latest generation of high-speed OOK isolation technology has the following difficulties: achieving a transient withstand voltage of several thousand volts with standard CMOS technology; ensuring correct modulation (encoding) and demodulation (decoding) of the signal under high-speed signal input; and achieving extremely low transmission delay of nanoseconds. When the modulator signal frequency exceeds 100MHz, the minimum time of the high and low levels of the data signal is less than 5ns. At this time, the duty cycle variation of the output data will be very important, and the duty cycle distortion needs to be controlled to be less than 3ns to meet the data transmission requirements of high-speed isolators.

[0004] To analyze the duty cycle distortion principle of the OOK isolator modulation and demodulation circuit, we again observe Figure 2OOK modulation and demodulation circuit waveform diagram is shown. In the OOK transmitter, the carrier OSC signal is modulated with the Din signal to generate the DXP signal. Obviously, the rising or falling edge of the Din signal occurs at the time, the OSC signal is high or low level for random phenomenon, DXP will introduce the signal duty cycle distortion time is not higher than the OSC one cycle. In order to reduce the random duty cycle distortion, only to try to improve the OSC carrier frequency. After the DXP signal is input into the OOK receiving circuit in the right dashed box, the input high frequency signal INP / INN will be gradually amplified to obtain the Inp2 / Inn2 signal with relatively high amplitude, and enter the envelope detection circuit to demodulate the Dout digital signal. Usually, the envelope detection circuit will further cause a certain duty cycle distortion.

[0005] Figure 3 The envelope detection circuit schematic diagram of the prior art OOK signal demodulation circuit. When the differential output signal Inp2 and Inn2 have high frequency modulation signal input, the detection NMOS tube M705 and M706 will have current passing through, and the current at node A of M705 and M706 is summed; if the current at node A increases, the voltage at node A increases, and once the voltage exceeds the reference threshold voltage Vdet, the Vo1 voltage rises, and after the full wave detector second stage circuit integration amplification, the Vo2 signal with higher level is obtained, and the standard high level digital signal Dout is obtained after the digital shaping circuit; on the contrary, when Inp2 and Inn2 have no high frequency modulation signal input, if A point is lower than the reference threshold voltage Vdet, the voltage of node Vo1 is pulled down, and the Vo2 output low level signal is obtained, and the standard low level digital signal Dout is obtained after the digital shaping circuit. Figure 4 For Figure 3 The envelope detection circuit data demodulation process simulation waveform diagram is given. The voltages of nodes Vo1 and Vo2 are analog signals with relatively large amplitude, and the reference threshold voltage Vdet and the common mode voltage of Inp2 and Inn2 are easily affected by PVT fluctuation, so that the Dout has obvious duty cycle distortion. Therefore, the present application provides a low duty cycle distortion capacitor isolation OOK signal modulation and demodulation circuit with low duty cycle distortion characteristic. SUMMARY

[0006] The present application provides a low duty cycle distortion capacitor isolation OOK signal modulation and demodulation circuit.

[0007] The low-duty-cycle distortion capacitor-isolated OOK signal modulation and demodulation circuit comprises a differential OOK modulation circuit, a high-voltage capacitor-isolated circuit, an input buffer circuit, a differential filter amplification circuit and an envelope detection circuit, and is characterized in that it further comprises a PVT fluctuation detection circuit, an error compensation calculation circuit and a reference voltage adjustment circuit; wherein the four high-voltage isolation capacitors constituting the high-voltage capacitor-isolated circuit are capacitors with the same voltage resistance and the same capacitance value. The input end of the differential OOK modulation circuit is connected to a carrier clock OSC and an input data Din, respectively; the first output end DXP and the second output end DXN of the differential OOK modulation circuit output complementary and opposite high-frequency pulse signals, which are connected to two input ends of the high-voltage capacitor-isolated circuit, respectively, and output differential signals INP and INN through the high-voltage capacitor-isolated circuit; the signals INP and INN are connected to the input end of the input buffer circuit, and output first-stage differential output signals Inp1 and Inn1 through the input buffer circuit, respectively; the signals Inp1 and Inn1 are connected to the differential filter amplification circuit, respectively, and output second-stage differential output signals Inp2 and Inn2 through the differential filter amplification circuit, which are connected to the envelope detection circuit. The PVT fluctuation detection circuit detects the process deviation, the power voltage and the temperature on chip in real time, and obtains process deviation error amount deP, power voltage error amount deV and temperature error amount deT, which are output to the error compensation calculation circuit; the error compensation calculation circuit calculates error compensation code Dadj according to the three error amounts output by the PVT fluctuation detection circuit, and outputs the error compensation code Dadj to the reference voltage adjustment circuit; the reference voltage adjustment circuit generates modulation compensation signal Vdet1 according to the error compensation code Dadj, and outputs the modulation compensation signal Vdet1 to the envelope detection circuit, so as to adjust and compensate the reference voltage of the envelope detection circuit through the reference voltage adjustment circuit. The envelope detection circuit takes the modulation compensation signal Vdet1 as the reference voltage, processes the signals Inp2 and Inn2, and obtains OOK output signal Dout.

[0008] Specifically, the PVT fluctuation detection circuit comprises a process fluctuation detection circuit, a power voltage detection circuit, a temperature detection circuit, J process error comparators P1-PJ, K power error comparators V1-VK, and L temperature error comparators T1- TL; a process fluctuation error voltage Vdp output by the process fluctuation detection circuit is connected to the process error comparators P1-PJ respectively and compared with J reference voltages Vrp1-VrpJ respectively to obtain J-bit process deviation error amounts deP; a power voltage error voltage Vdv output by the power voltage detection circuit is connected to the power error comparators V1-VK respectively and compared with K reference voltages Vrv1-VrvK respectively to obtain K-bit power voltage error amounts deV; a temperature error voltage Vdt output by the temperature detection circuit is connected to the temperature error comparators T1-TL respectively and compared with L reference voltages Vrp1-VrpL respectively to obtain L-bit temperature error amounts deT; J, K, and L are integers greater than 2. The size and threshold boundary of the J reference voltages Vrp1-VrpJ are set according to the process fluctuation error voltage Vdp fluctuation range obtained by actual test, the maximum and minimum values of the reference voltages Vrp1-VrpJ must be greater than the fluctuation range of the process fluctuation error voltage Vdp, and the voltage interval between adjacent two reference voltages in the reference voltages Vrp1-VrpJ is set to be equal interval to obtain the J-bit process deviation error amounts deP as a temperature code; similarly, the voltage interval between adjacent two reference voltages in the K reference voltages Vrv1-VrvK is set to be equal interval to obtain the K-bit power voltage error amounts deV as a temperature code; and the voltage interval between adjacent two reference voltages in the L reference voltages Vrp1-VrpL is set to be equal interval to obtain the L-bit temperature error amounts deT as a temperature code.

[0009] Specifically, the error compensation calculation circuit comprises a process fluctuation register circuit, a power voltage register circuit, a temperature detection register circuit, a process error weight calculation unit, a power error weight calculation unit, a temperature error weight calculation unit, and a compensation amount calculation circuit. The J-bit process deviation error amount deP enters the process fluctuation register circuit under the control of the control clock CK0, and obtains a process deviation error code dp, while the process deviation error code dp enters the process error weight calculation unit under the control of the control clock CK1, and obtains a process fluctuation error compensation code dpc after calculation; the K-bit power voltage error amount deV enters the power voltage register circuit under the control of the control clock CK0, and obtains a power voltage error code dv, while the power voltage error code dv enters the power error weight calculation unit under the control of the control clock CK1, and obtains a power error compensation code dvc after calculation; the L-bit temperature error amount deT enters the temperature detection register circuit under the control of the control clock CK0, and obtains a temperature error code dt, while the temperature error code dt enters the temperature error weight calculation unit under the control of the control clock CK1, and obtains a temperature error compensation code dtc after calculation; the process fluctuation error compensation code dpc, the power error compensation code dvc and the temperature error compensation code dtc enter the compensation amount calculation circuit under the control of the control clock CK1, and obtain an n-bit error compensation code Dadj after calculation; wherein n is an integer greater than any one of J, K and L.

[0010] Specifically, the reference voltage adjustment circuit comprises: a conversion decoder, 2 n inversors, 2 n +1 switch selection PMOS tubes MP0~MP2 n +1, 7 bias NMOS tubes MN31~MN37, 2 n +1 switch selection NMOS tubes MN1~MN2 n +1, 2 n capacitors, 2 n +1 resistor; the conversion decoder is used for converting the data format of the input error compensation code Dadj, if the error compensation code Dadj is a binary code, it is converted into a thermometer code, if the error compensation code Dadj has already been in the thermometer code format, no conversion is needed. 2 n output ends Y1~Y2 of the conversion decoder n output YN1~YN2 through 2 n inversors respectively n , the conversion decoder and 2 n inversors constitute a reference voltage enable signal generation module; 7 bias NMOS tubes MN31~MN37, PMOS tube MP31, PMOS tube MP0 and 2 n +1 resistors R1~R2 n +1 constitute a reference voltage signal generation module, 2 n capacitors C1~C2 n , 2 n+1 switch selection PMOS MP1~MP2 n +1 and 2 n +1 switch selection NMOS MN1~MN2 n +1 reference voltage output module; PMOS MP0 and resistors R1~R2 n +1 in series, PMOS MP0 source connected to high level VCC, PMOS MP0 gate and drain connected to the upper end of resistor R1, from resistor R1 to resistor R2 n Each resistor upper end through capacitor C1~C2 n Ground, and connect a drain of a transmission gate circuit structure; the transmission gate circuit structure includes a pair of switch selection PMOS and switch selection NMOS with connected drain and connected source, wherein switch selection PMOS MP1~MP2 n Gate connected to inverted signal YN1~YN2 n , switch selection NMOS MN1~MN2 n Gate connected to signal Y1~Y2 n ; resistor R2 n Lower end connected to NMOS MN37 drain and resistor R2 n +1 upper end, resistor R2 n +1 lower end connected to NMOS MN31 drain, NMOS MN33 drain and NMOS MN37 source, NMOS MN31 source connected to NMOS MN32 drain, NMOS MN31 gate connected to NMOS MN32 gate, NMOS MN33 gate, NMOS MN34 gate, NMOS MN35 gate, NMOS MN35 drain, PMOS MP31 drain, NMOS MN36 gate, NMOS MN33 source connected to NMOS MN34 drain, NMOS MN35 source connected to NMOS MN36 drain, NMOS MN32 source, NMOS MN34 source, NMOS MN36 source connected to ground GND; the source of each pair of switch selection PMOS and switch selection NMOS is commonly connected to PMOS MP2 n +1 drain and NMOS MN2 n +1 drain, PMOS MP2 n +1 gate connected to ground GND, NMOS MN2 n +1 gate connected to high level VCC, PMOS MP2 n +1 source and NMOS MN2 n +1 source connected, output modulation compensation signal Vdet1; NMOS MN37 gate connected to signal V adj_en, PMOS MP31 gate connected signal V ctrl , PMOS MP31 source connected signal I bias ; PMOS MP31 as an enabling device, when V ctrl The reference voltage adjustment circuit works normally, and the output voltage is determined by the error compensation calculation circuit output signal when the reference voltage adjustment circuit output is high level VCC when V ctrl The reference voltage adjustment circuit output is low level; NMOS MN31~MN36 mirror current source for reference voltage signal generation module provides power supply, its size is determined by the signal I bias ; I bias The greater, the greater the current mirror current; NMOS MN37 and resistor R2 n +1 for calibration and adjustment of reference voltage adjustment circuit output signal; when the reference voltage adjustment circuit is found to be large throughout the output range, by setting V adj_en The output range can be reduced by being high.

[0011] The reference voltage adjustment circuit works, resistor string R1~R2 n Different reference voltage signal values are generated by voltage division; the n-bit error compensation code Dadj signal output by the error compensation calculation circuit is converted by the decoder to generate two n NMOS reference voltage enable signals Y1~Y2 n These signals pass through the inverter to generate corresponding PMOS reference voltage enable signals YN1~YN2 n Each time only one reference voltage enable signal is valid; finally, the reference voltage output module transmits the corresponding reference voltage signal to the envelope detection circuit based on different enable signals through the corresponding transmission gate circuit structure.

[0012] The advantages of the low duty cycle distortion capacitor isolation OOK signal modulation and demodulation circuit are: based on the prior art, the error amount caused by the PVT fluctuation to the duty cycle characteristic of the isolator is detected in real time, then the corresponding error compensation amount is calculated by the error compensation calculation circuit, and finally the reference voltage of the existing envelope detection circuit is adjusted and compensated by the reference voltage adjustment circuit, the adjustment of the duty cycle of the OOK demodulation output signal is realized, and low duty cycle distortion is realized. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1The structure block diagram of the existing OOK signal modulation and demodulation circuit.

[0014] Figure 2 The signal modulation and demodulation process diagram of the existing OOK signal modulation and demodulation circuit.

[0015] Figure 3 The principle diagram of the envelope detection circuit in the existing OOK signal demodulation circuit.

[0016] Figure 4 The data demodulation process simulation waveform diagram of the existing envelope detection circuit.

[0017] Figure 5 The structure block diagram of the low duty cycle distortion capacitor isolation OOK signal modulation and demodulation circuit.

[0018] Figure 6 The embodiment of the PVT fluctuation detection circuit.

[0019] Figure 7 The embodiment of the error compensation calculation circuit.

[0020] Figure 8 The embodiment of the reference voltage adjustment circuit. DETAILED DESCRIPTION

[0021] The application will be further described in detail below in combination with the drawings and examples.

[0022] As shown in Figure 5 The low duty cycle distortion capacitor isolation OOK signal modulation and demodulation circuit includes: a differential OOK modulation circuit 101, a high-voltage capacitor isolation circuit (including a high-voltage isolation capacitor Ctp, a high-voltage isolation capacitor Crp, a high-voltage isolation capacitor Ctn, and a high-voltage isolation capacitor Crn), an input buffer circuit 102, a differential filter amplification circuit 103, an envelope detection circuit 104, a PVT fluctuation detection circuit 105, an error compensation calculation circuit 106, and a reference voltage adjustment circuit 107. The high-voltage isolation capacitor Ctp, the high-voltage isolation capacitor Crp, the high-voltage isolation capacitor Ctn, and the high-voltage isolation capacitor Crn are capacitors with the same voltage resistance and capacitance value.

[0023] The connection relationship of the above circuit is: the first input end of the differential OOK modulation circuit 101 is connected with the carrier clock OSC, and the second input end of the differential OOK modulation circuit 101 is connected with the input data Din; the first output end DXP of the differential OOK modulation circuit 101 is connected with the left end of the high-voltage isolation capacitor Ctp, the second output end DXN of the differential OOK modulation circuit 101 is connected with the left end of the high-voltage isolation capacitor Ctn, the right end of the high-voltage isolation capacitor Ctp is connected with the left end of the high-voltage isolation capacitor Crp, the right end of the high-voltage isolation capacitor Crp is connected with the left end of the high-voltage isolation capacitor Crn, the right end of the high-voltage isolation capacitor Crp is connected with the first input end INP of the input buffer circuit 102, and the right end of the high-voltage isolation capacitor Crn is connected with the second input end INN of the input buffer circuit 102. The first output end Inp1 of the input buffer circuit 102 is connected to the first input end of the differential filter amplification circuit 103, the second output end Inn1 of the input buffer circuit 102 is connected to the second input end of the differential filter amplification circuit 103, the first output end Inp2 of the differential filter amplification circuit 103 is connected to the first input end of the envelope detection circuit 104, and the second output end Inn2 of the differential filter amplification circuit 103 is connected to the second input end of the envelope detection circuit 104.

[0024] The PVT fluctuation detection circuit 105 detects the process deviation, power voltage and on-chip temperature of the whole chip in real time, obtains the process deviation error amount deP, power voltage error amount deV and temperature error amount deT, and simultaneously provides them to the error compensation calculation circuit 106.

[0025] The error compensation calculation circuit 106 calculates the error compensation code Dadj according to the three error amounts output by the PVT fluctuation detection circuit 105.

[0026] The reference voltage adjustment circuit 107 generates a modulation compensation signal Vdet1 according to the error compensation code Dadj. The envelope detection circuit 104 processes the Inp2 and Inn2 signals and the modulation compensation signal Vdet1 to obtain the OOK output signal Dout.

[0027] Figure 5In the shown circuit, the function of the differential OOK modulation circuit 101 is to use the on-off keying technology to modulate the input data Din with the OSC carrier oscillator signal. The first output terminal DXP and the second output terminal DXN of the differential OOK modulation circuit 101 output complementary opposite high-frequency pulse signals. If the input data Din is high, the output differential high-frequency pulse signals DXP and DXN of the differential OOK modulation circuit 101 will be transmitted through the high-voltage capacitor isolation circuit composed of high-voltage isolation capacitors Ctp, Crp, Ctn and Crn; if the input data Din is low, the output differential high-frequency pulse signals DXP and DXN of the differential OOK modulation circuit 101 are both low level signals, at this time no energy is transmitted to the high-voltage capacitor isolation circuit. The right side OOK RX receiving circuit obtains differential signals INP and INN through high-voltage capacitor coupling, and demodulates the signals by frequency detection to obtain the received digital signal Dout which is the same as the input data Din but slightly delayed. The first stage of the OOK RX receiving circuit is the input buffer circuit 102, which is used to pre-amplify the differential signals INP and INN and provide a certain common mode bias Vcm1 to obtain the first stage differential output signals Inp1 and Inn1; the second stage of the OOK RX receiving circuit is the differential filter amplification circuit 103, which is used to further amplify the first stage differential output signals Inp1 and Inn1 and filter high-frequency spike interference signals to obtain the second stage differential output signals Inp2 and Inn2 with a common mode bias Vcm2; the envelope detection circuit 104 compares and processes Inp2 and Inn2 signals with the modulation compensation signal Vdet1 to obtain the OOK output signal Dout.

[0028] OOK output signal Dout should theoretically be the same digital signal as input data Din but slightly delayed. However, in the actual circuit, due to the influence of PVT fluctuation, the common mode bias Vcm1 and the common mode bias Vcm2 will have a certain offset, and the modulation compensation signal Vdet1 is a fixed value, so the output data high-low duty cycle of Dout will be offset, forming duty cycle distortion. Conversely, assuming that the common mode bias Vcm2 has an offset of ΔVcm, if the modulation compensation signal Vdet1 compensates for the offset amount of ΔVcm, the duty cycle distortion of the OOK output signal Dout will be offset and reduced.

[0029] Figure 5In the embodiment of the application shown, the PVT fluctuation detection circuit 105, the error compensation calculation circuit 106 and the reference voltage adjustment circuit 107 compensate for the duty cycle distortion of the OOK output signal Dout according to the above idea. The PVT fluctuation detection circuit 105 detects the process deviation, the power voltage and the temperature on chip in real time, and obtains three error amounts, i.e. the process deviation error amount deP, the power voltage error amount deV and the temperature error amount deT. The three error amounts will all cause the shift of the common-mode bias Vcm2, so the error compensation calculation circuit 106 calculates the error compensation code Dadj according to the three error amounts output by the PVT fluctuation detection circuit 105, and the error compensation code Dadj needs to accurately reflect the shift amount ΔVcm of the common-mode bias Vcm2. The reference voltage adjustment circuit 107 generates the modulation compensation signal Vdet1 according to the error compensation code Dadj, and the adjustment amplitude of the modulation compensation signal Vdet1 is usually equal to the shift amount ΔVcm of the common-mode bias Vcm2.

[0030] Figure 6 An embodiment of the PVT fluctuation detection circuit 105 of the application is provided. The PVT fluctuation detection circuit 105 comprises a process fluctuation detection circuit 501, a power voltage detection circuit 502, a temperature detection circuit 503, J process error comparators P1-PJ, K power error comparators V1-VK and L temperature error comparators T1- TL. J, K and L are integers greater than 2. The process fluctuation error voltage Vdp output by the process fluctuation detection circuit 501 is compared with J reference voltages Vrp1-VrpJ respectively, to obtain J-bit process deviation error amounts deP; the power voltage error voltage Vdv output by the power voltage detection circuit 502 is compared with K reference voltages Vrv1-VrvK respectively, to obtain K-bit power voltage error amounts deV; and the temperature error voltage Vdt output by the temperature detection circuit 503 is compared with L reference voltages Vrp1-VrpL respectively, to obtain L-bit temperature error amounts deT.

[0031] The specific implementation of the process fluctuation detection circuit 501, the power supply voltage detection circuit 502, and the temperature detection circuit 503 can be achieved by using the prior art. Since the process fluctuation error is relatively fixed after the chip manufacturing is completed, the J process error comparators P1-PJ can be implemented by using a low-speed high-precision low-offset comparator to reduce power consumption as much as possible under the condition of meeting the accuracy. The change of the power supply voltage is disturbed by external interference, which may exist MHz-level high-frequency jitter or sharp pulse fluctuation. Therefore, the K power supply error comparators V1-VK need to use a high-speed comparator with a speed greater than 1 MHz to detect the power supply voltage error amount deV caused by the change of the power supply voltage in real time. The temperature change is a slowly changing error amount, so the L temperature error comparators T1-TL can use a medium-speed high-precision comparator with a speed greater than 1 KHz. For the size of the J reference voltages Vrp1-VrpJ and the threshold boundary setting, the J reference voltages Vrp1-VrpJ must be greater than the process fluctuation error voltage Vdp fluctuation range obtained by actual test, and the voltage interval between adjacent two reference voltages in the J reference voltages Vrp1-VrpJ is set to be equal interval, so that the process deviation error amount deP is J-bit thermometer code. Similarly, the voltage interval between adjacent two reference voltages in the K reference voltages Vrv1-VrvK is set to be equal interval, so that the power supply voltage error amount deV is K-bit thermometer code; the voltage interval between adjacent two reference voltages in the L reference voltages Vrp1-VrpL is set to be equal interval, so that the temperature error amount deT is L-bit thermometer code.

[0032] Figure 7 An embodiment of the error compensation calculation circuit 106 of the application. The error compensation calculation circuit 106 includes a process fluctuation register circuit 601, a power supply voltage register circuit 602, a temperature detection register circuit 603, a process error weight (P) calculation unit 604, a power supply error weight (V) calculation unit 605, a temperature error weight (T) calculation unit 606, and a compensation amount calculation circuit 607.

[0033] The J-bit process deviation error amount deP enters the process fluctuation register circuit 601 under the control of the control clock CK0, and obtains the process deviation error code dp, and at the same time enters the process error weight (P) calculation unit 604 under the control of the control clock CK1, and calculates to obtain the process fluctuation error compensation code dpc.

[0034] The K-bit power supply voltage error amount deV enters the power supply voltage register circuit 602 under the control of the control clock CK0, and obtains the power supply voltage error code dv, and at the same time enters the power supply error weight (V) calculation unit 605 under the control of the control clock CK1, and calculates to obtain the power supply error compensation code dvc.

[0035] The L-bit temperature error amount deT enters the temperature detection register circuit 603 under the control of the control clock CK0, and obtains a temperature error code dt, and enters the temperature error weight (T) calculation unit 606 under the control of the control clock CK1, and obtains a temperature error compensation code dtc after calculation.

[0036] The process fluctuation error compensation code dpc, the power error compensation code dvc and the temperature error compensation code dtc enter the compensation amount calculation circuit 607 under the control of the control clock CK1, and obtain an n-bit error compensation code Dadj after calculation. n is an integer greater than any one of J, K and L.

[0037] Figure 7 In the embodiment of the circuit, the register bit number of the process fluctuation register circuit 601 is J bits, the register bit number of the power voltage register circuit 602 is K bits, and the register bit number of the temperature detection register circuit 603 is L bits. The specific setting of the error compensation code Dadj needs to be selected by compromise according to the overall circuit speed and accuracy. The accuracy depends on the weight coefficient and data accuracy of the process error weight (P) calculation unit 604, the power error weight (V) calculation unit 605 and the temperature error weight (T) calculation unit 606, and the speed depends on the refresh frequency of the control clock CK1. Under the condition of a typical 1.8V voltage, assuming that the overall digital isolator rate is 200Mbps, the designed duty cycle distortion is less than 3ns. The process fluctuation error compensation code dpc can be set to 7-bit thermometer code, the power error compensation code dvc can be set to 7-bit thermometer code, and the temperature error compensation code dtc can be set to 7-bit thermometer code. The refresh frequency of the control clock CK0 is 1MHz, which is used for accurate data collection of analog error amount; the refresh frequency of the control clock CK1 can be a low-speed clock of 10KHz to reduce power consumption. Considering that the process fluctuation error compensation code dpc, the power error compensation code dvc and the temperature error compensation code dtc have different sensitivities to the influence of the duty cycle distortion, the weight coefficient distribution of the process error weight (P) calculation unit 604, the power error weight (V) calculation unit 605 and the temperature error weight (T) calculation unit 606 needs to be allocated according to the actual error test data, and the objective conditions of different application backgrounds also need to be considered.

[0038] For example, if the isolator circuit is used as a sub-module of a high-voltage analog system chip, the noise, power supply interference, and temperature variations of the overall isolator will be quite severe. Therefore, it is necessary to focus on the weighting coefficients of the power supply error weighting (V) calculation unit 605 and the temperature error weighting (T) calculation unit 606. The weighting coefficients of the process fluctuation error compensation code DPC, power supply error compensation code DVC, and temperature error compensation code DTC can be set to 2:4:4. However, in situations where the power supply voltage is relatively stable, the weighting coefficients of the process fluctuation error compensation code DPC, power supply error compensation code DVC, and temperature error compensation code DTC can be set to 2:2:6.

[0039] The compensation calculation circuit 607 calculates the error compensation code Dadj based on the process fluctuation error compensation code dpc, power supply error compensation code dvc, and temperature error compensation code dtc under the control of the control clock CK1. The calculation method can employ existing methods such as lookup table method, PID control method, or neural network calculation. It is important to note that the center value of the error compensation code Dadj calculated by the algorithm used by the compensation calculation circuit 607 needs to be set based on actual test data. Furthermore, the output data format of the error compensation code Dadj can be selected according to application requirements. If the error compensation code Dadj needs to be transmitted over a long distance, a binary encoding format can be selected to reduce the number of transmission signal lines; alternatively, a thermometer code or other encoding methods can be used.

[0040] Figure 8 This is an embodiment of the reference voltage adjustment circuit 107 of the present invention. The reference voltage adjustment circuit 107 includes: a transcoder / decoder, and 2... n Inverters INV1~INV2 n 2 n +1 switch selects PMOS transistors MP0 ~ MP2 n +1, PMOS transistor MP31, 2 n +1 switch to select NMOS transistors MN1~MN2 n +1, 7 bias NMOS transistors MN31~MN37, 2 n Capacitors C1~C2 n 2 n +1 resistor R1 ~ R2 n +1.

[0041] Among them, the transcoder and decoder and 2 n Inverters INV1~INV2 n This constitutes the reference voltage output enable signal generation module; 7 bias NMOS transistors MN31~MN37, PMOS transistor MP31, PMOS transistor MP0 and 2 n +1 resistor R1~R2n +1 constitutes a reference voltage signal generation module; 2 n capacitors C1~C2 n , 2 n +1 switch selection PMOS tube MP1~MP2 n +1 and 2 n +1 switch selection NMOS tube MN1~MN2 n +1 constitutes a reference voltage output module.

[0042] The transcoder circuit is used for converting the data format of the input error compensation code Dadj, if the error compensation code Dadj is binary code, it needs to be converted into thermometer code, if the error compensation code Dadj is already in thermometer code format, no conversion is needed.

[0043] Figure 8 The reference voltage adjustment circuit 107 embodiment is given, the working principle of the circuit is: (1) the error compensation code Dadj signal (A1~A N ) output by the error compensation calculation circuit 106, after the transcoder, 2 n NMOS tube reference voltage enable signal Y1~Y2 n , these signals pass through the inverter to generate the corresponding PMOS tube reference voltage enable signal YN1~YN2 n , each time only one reference voltage enable signal is valid. (2) for the reference voltage signal generation module, resistors R1~R2 n generate different reference voltage signal values by voltage division. The PMOS tube MP31 gate connects the signal V ctrl , the PMOS tube MP31 as an enabler, when V ctrl is high, the reference voltage adjustment circuit 107 works normally, the output voltage is determined by the compensation calculation circuit output signal, when V ctrl is low, the reference voltage adjustment circuit 107 outputs high voltage VCC. The PMOS tube MP31 source connects the signal I bias , NMOS tube MN31~MN36 constitute a mirror current source to provide power for the reference voltage signal generation module, its size is determined by I bias signal. I bias The greater, the corresponding current mirror produces the greater the current. NMOS tube MN37 and resistor R2 n +1 can be used for calibration and adjustment of the reference voltage output signal. NMOS tube MN37 gate connects the signal Vadj_en When it is found that the reference voltage is too large in the whole output range, the reference voltage output range can be reduced by setting V adj_en high, thereby reducing the reference voltage output range. (3) Finally, the reference voltage output module transmits the corresponding reference voltage signal to the envelope detection circuit 104 based on different enable signals through the corresponding transmission gate circuit structure.

[0044] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A low duty cycle distortion capacitor-isolated OOK signal modulation and demodulation circuit, comprising a differential OOK modulation circuit, a high-voltage capacitor isolation circuit, an input buffer circuit, a differential filter amplifier circuit, and an envelope detector circuit, characterized in that it also... The PVT fluctuation detection circuit, the error compensation calculation circuit and the reference voltage adjustment circuit are included. The input end of the differential OOK modulation circuit is connected with a carrier clock OSC and an input data Din respectively, the first output end DXP and the second output end DXN of the differential OOK modulation circuit output complementary high-frequency pulse signals, which are connected to two input ends of the high-voltage capacitor isolation circuit respectively, and then output differential signals INP and INN through the high-voltage capacitor isolation circuit; the signals INP and INN are connected to the input end of the input buffer circuit, and then output first-stage differential output signals Inp1 and Inn1 through the input buffer circuit, and the signals Inp1 and Inn1 are connected to the differential filter amplification circuit, and then output second-stage differential output signals Inp2 and Inn2 through the differential filter amplification circuit, and are connected to the envelope detection circuit; The PVT fluctuation detection circuit detects the process deviation, the power voltage and the temperature on chip in real time, and obtains a process deviation error amount deP, a power voltage error amount deV and a temperature error amount deT, which are output to the error compensation calculation circuit; the error compensation calculation circuit calculates an error compensation code Dadj according to the three error amounts output by the PVT fluctuation detection circuit, and outputs the error compensation code Dadj to the reference voltage adjustment circuit; the reference voltage adjustment circuit generates a modulation compensation signal Vdet1 according to the error compensation code Dadj, and outputs the modulation compensation signal Vdet1 to the envelope detection circuit, so as to adjust and compensate the reference voltage of the envelope detection circuit through the reference voltage adjustment circuit; The envelope detection circuit takes the modulation compensation signal Vdet1 as the reference voltage, processes the signals Inp2 and Inn2, and obtains an OOK output signal Dout. The PVT fluctuation detection circuit includes a process fluctuation detection circuit, a power voltage detection circuit, a temperature detection circuit, J process error comparators P1-PJ, K power error comparators V1-VK and L temperature error comparators T1- TL; the process fluctuation error voltage Vdp output by the process fluctuation detection circuit is connected to the process error comparators P1-PJ respectively, compared with J reference voltages Vrp1-VrpJ respectively, and J-bit process deviation error amounts deP are obtained; the power voltage error voltage Vdv output by the power voltage detection circuit is connected to the power error comparators V1-VK respectively, compared with K reference voltages Vrv1-VrvK respectively, and K-bit power voltage error amounts deV are obtained; the temperature error voltage Vdt output by the temperature detection circuit is connected to the temperature error comparators T1- TL respectively, compared with L reference voltages Vrp1-VrpL respectively, and L-bit temperature error amounts deT are obtained; J, K and L are integers greater than 2.

2. The low duty cycle distorted capacitive isolated OOK signal modem circuit of claim 1, wherein, ​ The process deviation error amount deP of J bits is obtained by setting the voltage interval between two adjacent reference voltages in the J reference voltages Vrp1-VrpJ as an equal interval, and the process deviation error amount deP is a J-bit thermometer code; similarly, the power voltage error amount deV of K bits is obtained by setting the voltage interval between two adjacent reference voltages in the K reference voltages Vrv1-VrvK as an equal interval, and the power voltage error amount deV is a K-bit thermometer code; and the temperature error amount deT of L bits is obtained by setting the voltage interval between two adjacent reference voltages in the L reference voltages Vrp1-VrpL as an equal interval, and the temperature error amount deT is an L-bit thermometer code.

3. The low duty cycle distorted capacitive isolated OOK signal modem circuit of claim 1, wherein, The error compensation calculation circuit comprises a process fluctuation register circuit, a power voltage register circuit, a temperature detection register circuit, a process error weight calculation unit, a power error weight calculation unit, a temperature error weight calculation unit, and a compensation amount calculation circuit. The J-bit process deviation error amount deP enters the process fluctuation register circuit under the control of a control clock CK0, and a process deviation error code dp is obtained; meanwhile, the process deviation error code dp enters the process error weight calculation unit under the control of a control clock CK1, and a process fluctuation error compensation code dpc is obtained through calculation; the K-bit power voltage error amount deV enters the power voltage register circuit under the control of the control clock CK0, and a power voltage error code dv is obtained; meanwhile, the power voltage error code dv enters the power error weight calculation unit under the control of the control clock CK1, and a power error compensation code dvc is obtained through calculation; the L-bit temperature error amount deT enters the temperature detection register circuit under the control of the control clock CK0, and a temperature error code dt is obtained; meanwhile, the temperature error code dt enters the temperature error weight calculation unit under the control of the control clock CK1, and a temperature error compensation code dtc is obtained through calculation; the process fluctuation error compensation code dpc, the power error compensation code dvc, and the temperature error compensation code dtc enter the compensation amount calculation circuit under the control of the control clock CK1, and an n-bit error compensation code Dadj is obtained through calculation; wherein n is an integer greater than any one of J, K, and L.

4. The low duty cycle distorted capacitive isolated OOK signal modem circuit of claim 3, wherein, The reference voltage adjustment circuit includes: a transcode decoder, and 2 n One inverter, 2 n +1 switch to select PMOS transistors MP0~MP2 n +1, PMOS transistor MP31, 7 bias NMOS transistors MN31~MN37, 2 n +1 switch to select NMOS transistors MN1~MN2 n +1, 2 n One capacitor, 2 n +1 resistor; The transcode decoder is used to convert the data format of the input error compensation code Dadj. If the error compensation code Dadj is binary code, it is converted to thermometer code. If the error compensation code Dadj is already in thermometer code format, no conversion is required. 2 transcoder / decoder n Each output terminal Y1~Y2 n After 2 respectively n Each inverter outputs YN1~YN2 n transcoder and 2 n An inverter constitutes a reference voltage enable signal generation module; 7 bias NMOS MN31~MN37, PMOS MP31, PMOS MP0 and 2 n +1 resistance R1~R2 n +1 reference voltage signal generation module, 2 n capacitor C1~C2 n , 2 n +1 switch selection PMOS MP1~MP2 n +1 and 2 n +1 switch selection NMOS MN1~MN2 n +1 reference voltage output module; PMOS MP0 and resistance R1~R2 n +1 in turn, PMOS MP0 source connected to high level VCC, PMOS MP0 gate and drain connected to the upper end of resistance R1, from resistance R1 to resistance R2 n Each resistance upper end through capacitor C1~C2 n Ground, and connect a drain of a transmission gate circuit structure; the transmission gate circuit structure includes a pair of drain connected source also connected switch selection PMOS and switch selection NMOS, wherein switch selection PMOS MP1~MP2 n Gate connected to the inverting signal YN1~YN2 n , switch selection NMOS MN1~MN2 n Gate connected to the signal Y1~Y2 n ; resistance R2 n Lower end connected to the drain of NMOS MN37 and resistance R2 n +1 upper end, resistance R2 n +1 lower end connected to the drain of NMOS MN31, NMOS MN33 and NMOS MN37 source, NMOS MN31 source connected to the drain of NMOS MN32, NMOS MN31 gate connected to the gate of NMOS MN32, NMOS MN33, NMOS MN34, NMOS MN35, NMOS MN35 drain, PMOS MP31 drain, NMOS MN36 gate, NMOS MN33 source connected to the drain of NMOS MN34, NMOS MN35 source connected to the drain of NMOS MN36, NMOS MN32 source, NMOS MN34 source, NMOS MN36 source connected to ground GND; each pair of switch selection PMOS and switch selection NMOS source is commonly connected to PMOS MP2 n +1 drain and NMOS MN2 n +1 drain, PMOS MP2 n +1 gate connected to ground GND, NMOS MN2 n +1 gate connected to high level VCC, PMOS transistor MP2 n +1 source connected to and NMOS transistor MN2 n +1 source connected, output modulation compensation signal Vdet1; NMOS transistor MN37 gate connected to a signal V adj_en PMOS transistor MP31 gate connected to a signal V ctrl PMOS transistor MP31 source connected to a signal I bias ; PMOS transistor MP31 is an enabling device, when V ctrl When the reference voltage adjustment circuit is normal, the output voltage is determined by the error compensation calculation circuit output signal, when V ctrl When the reference voltage adjustment circuit is normal, the output voltage is determined by the error compensation calculation circuit output signal, when NMOS MN31~MN36 constitute mirror current source to provide power supply for reference voltage signal generation module, whose size is determined by signal I bias determination; I bias The greater, the greater the current generated by the current mirror; NMOS MN37 and resistor R2 n +1 for calibration and adjustment of the reference voltage adjustment circuit output signal; when the reference voltage adjustment circuit is found to be large throughout the output range, the output range can be reduced by setting V adj_en high level.

5. The low duty cycle distorted capacitive isolated OOK signal modem circuit of claim 4, wherein, The reference voltage adjusting circuit works, and the resistance series R1~R2 n Different reference voltage signal values are generated by voltage division; the n-bit error compensation code Dadj signal output by the error compensation calculation circuit generates 2 n NMOS tube reference voltage enable signals Y1~Y2 n These signals generate corresponding PMOS tube reference voltage enable signals YN1~YN2 through inverters n Only one reference voltage enable signal is valid each time; finally, the reference voltage output module transmits corresponding reference voltage signals to the envelope detection circuit based on different enable signals through the corresponding transmission gate circuit structure.

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