SIMD register-based sm3 and sm4 fusion optimization method and system

Abstract

The application provides an SM3 and SM4 fusion optimization method and system based on a SIMD register, belongs to the technical field of data encryption and hash optimization, and comprises: a required stack area; performing SM3 message expansion, writing an expansion result into the stack area according to a determined mapping relationship, then a compression function reads expansion data from the stack area according to the mapping relationship and performs a preset round operation of an SM3 compression function; reading an SM4 parameter pointer address from the stack area, loading a data block to be encrypted into a SIMD register, and performing format conversion of big-endian sequence to little-endian sequence on the data; inserting a round function of SM4 realized by using a SIMD instruction into a post-set round compression function of SM3, so that the compression function instruction of SM3 and the round function instruction of SM4 are alternately executed to complete post-set round calculation after merging; after all round function calculation of SM3 and SM4 is completed, the encryption result of SM4 is stored back into a memory, then an SM3 parameter pointer is read from the stack area, and the hash result of SM3 is written back into the memory.

Description

Technical Field

[0001] This invention belongs to the field of data encryption and hash optimization technology, and particularly relates to a method and system for SM3 and SM4 fusion optimization based on SIMD registers. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] In modern network communication, the IPSec (Internet Protocol Security) protocol is widely used to ensure the secure transmission of data in insecure networks. The IPSec protocol uses an ESP (Encapsulating Security Payload) to encapsulate the security payload and achieve data encryption and integrity authentication. It typically employs symmetric encryption algorithms to encrypt the data and uses hash algorithms to generate Message Authentication Codes (MACs) to ensure data confidentiality and integrity.

[0004] In commercial cryptography systems, SM4 is a national standard symmetric encryption algorithm, and SM3 is a national standard hash algorithm. Both are widely used in security systems such as IPSec, SSL, VPN, and digital signatures.

[0005] In IPsec's ESP mode, each data packet requires SM4 encryption and SM3 hashing. For example, the sender first performs SM4 encryption, then uses SM3 to calculate the authentication hash. The receiver first verifies the hash using SM3, and then decrypts it using SM4 after successful verification.

[0006] However, current implementations generally employ serial execution or independent calls, with SM4 and SM3 each occupying independent registers and cache spaces. In the serial mode, SM4 encryption and SM3 hashing are two separate function calls. Each function requires its own set of CPU registers to store its internal state, round keys, intermediate data, etc. In the current architecture, the number of general-purpose registers is limited. When the SM4 function executes, it needs to occupy a portion of these registers. After execution, if the intermediate results in these registers need to be passed to the SM3 function, they are usually written back to memory (stack) to free up registers for the SM3 function. Subsequently, the SM3 function begins execution, requiring it to reload its state and data from memory into another set of registers. This process leads to frequent "register overflows," where data that should be stored in high-speed registers is forced to move to the much slower L1 / L2 cache or memory.

[0007] Furthermore, in serial mode, SM4 must write the entire plaintext of the data block back into memory. The SM3 function then rereads this same plaintext data from memory to calculate the hash. This incurs significant data movement overhead, making memory access several orders of magnitude slower than register access. Simultaneously, it pollutes the CPU cache, crowding out other potentially more useful data.

[0008] This results in low utilization of CPU register resources, and its performance is limited by the efficiency of register resource allocation, making it difficult to fully utilize the computing power of modern multi-port CPUs. Summary of the Invention

[0009] To overcome the shortcomings of the prior art, this invention provides a method and system for the fusion optimization of SM3 and SM4 based on SIMD registers. By fusing the execution of the round function of SM4 and the compression function of SM3 at the CPU instruction level, and utilizing the parallel computing capabilities of SIMD registers and general-purpose registers on different CPU ports, parallel encryption of SM4 and hash calculation of SM3 are realized simultaneously, thereby achieving efficient data processing.

[0010] To achieve the above objectives, one or more embodiments of the present invention provide the following technical solutions:

[0011] Firstly, a method for optimizing the fusion of SM3 and SM4 based on SIMD registers is disclosed, including:

[0012] Allocate the required stack space to store the message extension array of SM3, the registers that need to be saved during function calls, and the parameter pointer addresses of SM3 and SM4, and store the parameter pointer addresses of SM3 and SM4 into the stack area;

[0013] The SM3 message extension is executed, and the extension result is written to the stack area according to the determined mapping relationship. Then the compression function reads the extended data from the stack area according to the mapping relationship and executes the pre-set round operation of the SM3 compression function.

[0014] The system reads the parameter pointer address of SM4 from the stack, loads the data block to be encrypted into the SIMD register, and performs a big-endian to little-endian format conversion on the data. The round function of SM4, implemented using SIMD instructions, is inserted into the post-round compression function of SM3, so that the compression function instructions of SM3 and the round function instructions of SM4 are executed alternately to complete the post-round calculation after merging. After completing the calculation of all round functions of SM3 and SM4, the encryption result of SM4 is stored back into memory. Then, the parameter pointer of SM3 is read from the stack, and the hash result of SM3 is written back into memory.

[0015] As a further technical solution, after applying for the required stack space, the stack area is divided into storage spaces according to a fixed layout, including:

[0016] The message extension area is used to store message words;

[0017] The parameter pointer area is used to store the parameter pointer addresses of SM3 and SM4, and the parameter pointers of SM3 and SM4 are written into this area after the stack area is allocated;

[0018] The register storage area is used to save the state of critical general-purpose registers before a function call, so that the register contents can be restored after the function execution is complete.

[0019] As a further technical solution, the message expansion stage writes the expansion result to the stack area according to the mapping relationship. The specific mapping formula is as follows:

[0020] (STACK_W + ((((round) / 3) - 1)) * 32 + (offs) + ((widx) * 4))(%rsp)

[0021] Where `round` represents the round index of the current message expansion or compression function; `offs` represents the fixed offset within the group; `widx` represents the index of the currently stored message word. `STACK_W` is the identifier for the message expansion region, and `rsp` is the stack pointer register.

[0022] As a further technical solution, the parameter pointer address of SM4 is read from the stack area, the data block to be encrypted is loaded into the SIMD register, and the data is converted from big-endian to little-endian format, specifically including:

[0023] The output buffer pointer, input data pointer, and round key pointer of SM4 are read sequentially from the parameter pointer area of ​​the stack and loaded into a general-purpose register. Then, the data block to be encrypted is loaded into the SIMD register, and the data in the SIMD register is rearranged using a byte mask to convert the data from big-endian format to little-endian format.

[0024] As a further technical solution, the SM4 round function implemented using SIMD instructions is inserted into the SM3 post-setting round compression function, so that the SM3 compression function instructions and the SM4 round function instructions are executed alternately to complete the calculation of the merged post-setting round, specifically including:

[0025] SM3 operation is executed, using general-purpose registers to store the working variables a~h of SM3. A circular left shift is performed on a to obtain the intermediate variable t0. t0 is added to the constant e to obtain the intermediate variable t1. Then, a circular left shift is performed on t1, and the message word W of the corresponding round is read from the stack and placed into h. Subsequently, SIMD operation is performed on SM4, broadcasting the current round key to the xmm0 register, and XORing it with the data block stored in the previous round's status register in sequence, storing the result in the xmm0 register.

[0026] In the SM3 phase, t1 is added to h and stored back to h. Then, h is XORed with t0. The message word W′ of the current round is read from the stack and loaded into register d. Then, the SM4 operation is executed, and the result in register xmm0 is used to perform the pre-affine transformation.

[0027] In the SM3 stage, the Boolean function FF is executed on the working variables a, b, and c, the result is stored in t1, and t1 is added to d; then the SM4 operation is executed, and the result in the register xmm0 is used to perform the inverse calculation and inverse affine transformation.

[0028] In the SM3 stage, the Boolean function GG is executed on the working variables e, f, and g, the result is stored in t2, and t2 is added to h; then the SM4 operation is executed, the result in register xmm0 is circularly shifted to the left, and the result is stored in registers xmm10, xmm9, xmm8, and xmm0 respectively;

[0029] In the SM3 stage, a 19-bit circular left shift is performed on the working variable f, and the intermediate variable t0 is added to d; then the SM4 operation is performed, the aforementioned intermediate registers xmm10, xmm9, xmm8, and xmm0 are XORed, and the result is stored in xmm1;

[0030] In the SM3 stage, the working variable b is circularly shifted left by 9 bits. Then, h is circularly shifted left by 9 bits and stored in the intermediate variable t2. Next, h is circularly shifted left by 17 bits and stored in the intermediate variable t1. Finally, an XOR operation is performed on h, t1, and t2.

[0031] As a further technical solution, after completing all round function calculations for SM3 and SM4, the encryption result of SM4 is stored back into memory. Subsequently, the parameter pointer of SM3 is read from the stack, and the hash result of SM3 is written back into memory. Specifically, this includes:

[0032] Read the output buffer pointer of SM4 from the stack, convert the encryption result to little endian, and write the processed result back to the memory location pointed to by the parameter pointer; then read the output buffer pointer of SM3 from the stack, perform XOR operations on the working variables a~h stored in general-purpose registers r8d to r15d with the original variables A~H in sequence, and write the calculated hash result back to memory.

[0033] Secondly, a fusion optimization system for SM3 and SM4 based on SIMD registers is disclosed, including:

[0034] The stack space management module is configured to: request the required stack space to store the message extension array of SM3, the registers that need to be saved during function calls, and the parameter pointer addresses of SM3 and SM4, and store the parameter pointer addresses of SM3 and SM4 into the stack area;

[0035] The message expansion and front-round compression module is configured to: perform SM3 message expansion, write the expansion result to the stack area according to the determined mapping relationship, and then the compression function reads the expanded data from the stack area according to the mapping relationship and performs the front-round operation of the SM3 compression function;

[0036] The SM4 data loading and preprocessing module is configured to: read the parameter pointer address of SM4 from the stack area, load the data block to be encrypted into the SIMD register, and perform big-endian to little-endian format conversion on the data;

[0037] The fusion round function calculation module is configured to insert the SM4 round function implemented using SIMD instructions into the SM3 post-setting round compression function, so that the SM3 compression function instructions and the SM4 round function instructions are executed alternately to complete the fusion post-setting round calculation; the result write-back module is configured to: after completing all round function calculations of SM3 and SM4, store the encryption result of SM4 back to memory, then read the parameter pointer of SM3 from the stack area and write the hash result of SM3 back to memory.

[0038] The above one or more technical solutions have the following beneficial effects:

[0039] This scheme, based on the fusion of SM4 and SM3 using SIMD registers, fully leverages the collaborative computing capabilities of SIMD registers and general-purpose registers by alternately executing SM4 parallel encryption instructions and SM3 compression function instructions within the same round of computation, achieving high-efficiency computation. Compared to traditional schemes that execute SM3 hashing and SM4 encryption separately, this invention significantly improves data processing efficiency in scenarios requiring simultaneous encryption and hashing operations, such as IPSec ESP mode, while ensuring system stability, achieving fast and secure data encryption and hashing processing.

[0040] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0041] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0042] Figure 1 A flowchart of the SM3 and SM4 fusion optimization method based on SIMD registers provided in this embodiment of the invention. Detailed Implementation

[0043] It should be noted that the following detailed descriptions are exemplary and intended to provide further illustration of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0044] It should be noted that the terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the exemplary implementations of the present invention.

[0045] Where there is no conflict, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0046] Example 1

[0047] like Figure 1 As shown, this embodiment discloses a method for SM3 and SM4 fusion optimization based on SIMD registers, including:

[0048] S101: Allocate a fixed-size stack area to store message extension data, register storage, and parameter pointer addresses of SM3 and SM4, and store the parameter pointer addresses of SM3 and SM4 into the stack area;

[0049] Register storage area: Used to store the initial state of general-purpose registers and SIMD registers. It is stored immediately after the stack area is allocated in step S101. It does not belong to SM3 or SM4. It belongs to the general runtime environment of the entire fusion function. It ensures that when SM3 and SM4 are executed together, they will not destroy each other's register state. It belongs to the beginning of storage.

[0050] SM3 and SM4 parameter pointer addresses: After storing the register state in the storage area, the parameter pointer addresses of SM4 and SM3 are stored in the stack area; after the first 32 rounds of the SM3 compression function are executed, the input pointer address of SM4 is read and the data is read; after the last 32 rounds of the fusion function are executed, the output pointer address of SM4 is read and the SM4 result is stored, and then the parameter pointer address of SM3 is read and the SM3 result is stored, which is the beginning of storage.

[0051] Message extension data: This data is stored in the stack area during subsequent SM3 message extension execution and is considered subsequent storage.

[0052] S102: Execute SM3 message expansion, write the expansion result to the stack area according to the determined mapping relationship, and then the compression function reads the expansion result from the stack area according to the mapping relationship and executes the first 32 rounds of operations;

[0053] SM3 requires 64 rounds of compression functions to be executed; this step involves executing the first 32 rounds of compression functions.

[0054] S103: Read the parameter pointer address of SM4 from the stack area, load the data block to be encrypted into the SIMD register, and perform big-endian to little-endian conversion on the data;

[0055] S104: Insert the round function of SM4 implemented using SIMD instructions into the last 32 rounds of SM3 compression function, so that SM3 and SM4 instructions are executed alternately, and then the merged last 32 rounds of compression function are executed.

[0056] S105: After completing all round function calculations for SM3 and SM4, the encryption result of SM4 is stored back to the corresponding memory location. Then, the parameter pointer of SM3 is read from the stack, and the hash result of SM3 is written back to the corresponding memory location. The parameter pointer address of SM4 includes the output pointer address, input pointer address, and round key address. The encryption result of SM4 is stored back to the corresponding memory location, which here refers to the output parameter pointer address of SM4. The encryption result is stored in the memory location pointed to by the output parameter pointer.

[0057] In a specific embodiment, S101: Allocate a fixed-size stack space for storing message extension data, register storage, and parameter pointer addresses of SM3 and SM4, and store the parameter pointer addresses of SM3 and SM4 onto the stack, including:

[0058] The stack area is allocated storage space according to a fixed layout, totaling 704 + 64 + 64 = 832 bytes of stack space, of which:

[0059] The message extension area, identified by the symbol STACK_W, occupies 704 bytes, with 32-byte storage units. Each unit stores three 4-byte message words W and three 4-byte message words W′, for a total of 64 W and 64 W′ message words.

[0060] The parameter pointer area, identified by the symbol STACK_PTR, occupies 64 bytes and is used to store the parameter pointer addresses of SM3 and SM4. The parameter pointers of SM3 and SM4 are written into this area after the stack area is allocated.

[0061] The register storage area, identified by the symbol STACK_REG_SAVE, occupies 64 bytes and is used to store the state of critical general-purpose registers before a function call, so that the register contents can be restored after the function execution is complete.

[0062] To allocate a fixed-size stack area, specifically, during a function call, a fixed-size local space is allocated in the current thread's stack frame by adjusting the stack pointer. For example, the space of size STACK_SIZE can be allocated in the current thread's stack area by using subq $STACK_SIZE, %rsp; or an equivalent operation.

[0063] In this step, a large number of registers are used in the SM3 and SM4 processes. By using a unified, contiguous, and aligned stack layout, SM3 message extension data, SM3 and SM4 parameter pointers, and the status of key general-purpose registers can be stored efficiently, enabling secure management and fast access to register and stack data, thereby supporting the alternating parallel execution of SM3 and SM4 instructions.

[0064] S102: Execute SM3 message expansion. Based on the determined mapping relationship, write the expansion result to the stack area. The compression function then reads the expanded data from the stack area according to the mapping relationship and executes the first 32 rounds of operations, specifically:

[0065] During the message expansion phase, the expansion result is written to the stack area according to the mapping relationship. The specific mapping formula is as follows:

[0066] (STACK_W + ((((round) / 3) - 1)) * 32 + (offs) + ((widx) * 4))(%rsp)

[0067] Here, `round` represents the round index of the current message expansion or compression function; `offs` represents a fixed offset within the group, with the first 16 bytes used to store message word W and the last 16 bytes used to store message word W′; `widx` represents the index of the currently stored message word, ranging from 0 to 3, indicating the 0th to 3rd message word within a 32-byte storage unit; `STACK_W`: a symbolic identifier indicating the starting address in the stack area used to store the SM3 message expansion data W and message words W′; and `rsp`: the CPU's stack pointer register, where all data access in the stack area is performed relative to the offset of `rsp`.

[0068] Subsequently, the compression function phase reads the corresponding extended word from the stack area according to the same mapping relationship and executes the first 32 rounds of the SM3 compression function.

[0069] Regarding the compression function, based on the SM3 standard definition, the compression function performs 64 rounds of iterative calculations on the expanded results W[0..67] and W′[0..63]. Specifically, the SM3 compression function performs 64 rounds of iterative calculations on: 8 registers a, b, c, d, e, f, g, h; W′, W; and the constant Tj to obtain the new chain value.

[0070] Regarding the execution of SM3 message expansion, based on the SM3 standard definition, the input 64-byte message group is divided into 16 initial words W[0] to W

[15] in 4-byte increments; then, based on these 16 initial words, W

[16] to W

[67] are iteratively generated according to the message expansion formula defined in the standard; then, W′[0] to W′

[63] are generated according to the prescribed calculation rules, forming 64 auxiliary words for the compression function; finally, the result of message expansion is composed of the expansion word array W[0..67] and the auxiliary word array W′[0..63], and is used for the subsequent 64 rounds of compression.

[0071] The above processing method can clearly define the position of each message word in the stack area through a fixed mapping relationship, making the data access order between message expansion and compression functions predictable, continuous and aligned, while avoiding data reading errors and ensuring that the data read from the stack area in each round of SM3 compression function is correct.

[0072] S103: Read the parameter pointer address of SM4 from the stack area, load the data block to be encrypted into the SIMD register, and perform big-endian to little-endian conversion on the data, specifically:

[0073] The SM4 output buffer pointer, input data pointer, and round key pointer are read sequentially from the STACK_PTR parameter pointer area of ​​the stack and loaded into a general-purpose register. Then, the data block to be encrypted is loaded into the SIMD register, and the data in the SIMD register is rearranged using a byte mask to convert the data from big-endian format to little-endian format.

[0074] Regarding the data block to be encrypted, it refers to the basic operation unit of the SM4 algorithm. Each data block in serial SM4 is 16 bytes.

[0075] In a parallel SIMD implementation, multiple data blocks (e.g., 4 / 8 / 16, 4 data blocks in this example) can be loaded into the SIMD register at once for parallel encryption. After loading, each data block needs to be converted from big-endian to little-endian to ensure that the data is in the same order as the round function operations in the SIMD register.

[0076] It should be noted that after allocating the stack area at the function entry point and storing the important registers in the register storage area, the parameter pointer addresses of SM4 (output buffer pointer, input data pointer, and round key pointer) and the parameter pointer addresses of SM3 (SM3 message context pointer, input data pointer, and data block count pointer) are then stored in the stack area.

[0077] The data in the SIMD register is rearranged using a byte mask. The specific process is as follows: load the data into the SIMD register; prepare a little-endian byte mask; use SIMD instructions to convert the data in the register to little-endian. Big-endian is commonly used to store data in memory, while the CPU and SIMD instructions internally process integer / vector data in little-endian. Performing this rearrangement operation ensures the correctness of the data calculated by the round function.

[0078] In the steps described above, the first 32 rounds of compression for SM3 have been completed. The subsequent 32 rounds of fusion functions need to read the SM4 data into the SIMD register. The SM4 parameter pointers stored in the stack allow for quick access to the required inputs and round keys for SM4. Loading the data into the SIMD register and performing big-endian to little-endian conversion enables subsequent SM4 round functions to be executed efficiently and in parallel within vectorized instructions.

[0079] As a specific embodiment, S104: The round function of SM4 implemented using SIMD instructions is inserted into the last 32 rounds of compression function of SM3, so that SM3 and SM4 instructions are executed alternately, and then the merged last 32 rounds of compression function are executed, including:

[0080] S104-a1: First, the SM3 operation is executed. The working variables a~h of SM3 are stored in general-purpose registers r8 to r15. A 12-bit circular left shift is performed on a to obtain the intermediate variable t0. t0 is added to the constant e to obtain the intermediate variable t1. Then, a 7-bit circular left shift is performed on t1, and the message word W of the corresponding round is read from the stack area into h. Subsequently, the SIMD operation is performed on SM4. The current round key is broadcast to the xmm0 register, and XORed with the three data blocks stored in the previous round status register in sequence. The result is stored in the xmm0 register.

[0081] The previous round status register refers to the SIMD register that stores the encryption result of the previous round of SM4. SM4 is an iterative encryption algorithm, and the calculation of each round depends on the output of the previous round.

[0082] In the round function of SM4, four data blocks need to be processed. Specifically: initially, the last three data blocks are XORed with the round key; the result is then subjected to a non-linear transformation; the result after the non-linear transformation is then subjected to a linear transformation; and the result after the linear transformation is XORed with the first data block.

[0083] S104-a2: In the SM3 stage, t1 is added to h and stored back to h. Then, h is XORed with t0. The message word W′ of the current round is read from the stack and loaded into register d. Then, the SM4 operation is executed, and the result in register xmm0 is processed by the vgf2p8affineqb instruction to perform the pre-affine transformation.

[0084] S104-a3: In the SM3 stage, the Boolean function FF is executed on the working variables a, b, and c, the result is stored in t1, and t1 is added to d; then the SM4 operation is executed, and the inverse inverse affine transformation is performed on the result in the register xmm0 using the vgf2p8affineinvqb instruction.

[0085] S104-a4: In the SM3 stage, the Boolean function GG is executed on the working variables e, f, and g, the result is stored in t2, and t2 is added to h; then the SM4 operation is executed, the result in register xmm0 is circularly shifted left by 2 bits, 8 bits, 10 bits, and 14 bits respectively, and the result is stored in registers xmm10, xmm9, xmm8, and xmm0 respectively;

[0086] S104-a5: In the SM3 stage, a 19-bit circular left shift is performed on the working variable f, and the intermediate variable t0 is added to d; then the SM4 operation is performed, the aforementioned intermediate registers xmm10, xmm9, xmm8, and xmm0 are XORed, and the result is stored in xmm1;

[0087] S104-a6: In the SM3 stage, the working variable b is circularly shifted left by 9 bits. Then, h is circularly shifted left by 9 bits and stored in the intermediate variable t2. Next, h is circularly shifted left by 17 bits and stored in the intermediate variable t1. Finally, an XOR operation is performed on h, t1, and t2. The result of the XOR operation is stored back in the h register, which provides input for the next round of compression function or serves as the output result after the compression function ends. The output of SM3 is the result stored in a~h.

[0088] In this embodiment, the SM4 round function includes 32 rounds of computation. The data to be encrypted is processed by the 32 rounds of round function to obtain encrypted data. In this example, the round function is implemented using SIMD instructions. The specific details of the 32 rounds of round function after processing 64 bytes of data each time are as follows:

[0089] Execute one SM3 instruction, then one SM4 instruction, then another SM3 instruction, with SM3 and SM4 instructions being executed alternately.

[0090] In this embodiment, steps S104-a1 to S104-a5 all employ the same processing flow: first, the SM3 stage calculations are executed, followed by the SM4 stage calculations. Here, "SM3 stage" refers to the SM3 compression function operation in the corresponding round; "subsequently executing the SM4 operation" refers to the SM4 round function processing performed immediately after the completion of the SM3 round calculations. In step S104-a6, only the SM3 stage calculations are executed; the SM4 operation is not performed. At this point, all rounds of the SM3 compression function and all steps of the SM4 round function have been completed.

[0091] S104-a1 to S104-a6: These six steps constitute the function flow after the fusion of SM3 and SM4. Subsequent steps depend on the data in the registers from the previous steps.

[0092] In this embodiment, the CPU uses different execution ports for integer and vector calculations. The compression function of SM3 mainly involves integer operations and primarily occupies the general-purpose arithmetic logic unit (PLU) port; while the round function of SM4 mainly relies on SIMD instructions to perform vector operations, corresponding to a dedicated SIMD execution port. By alternating the execution of the general-purpose register operations of SM3 and the SIMD round function of SM4, they run in parallel on different CPU execution ports, thereby fully utilizing the register and SIMD computing capabilities, reducing memory access and register scheduling overhead, improving data throughput and computational efficiency, while ensuring the correctness and sequential consistency of the calculation results.

[0093] S105: Store the encryption result of SM4 back to the corresponding memory location, then read the parameter pointer of SM3 from the stack area, and write the hash result of SM3 back to the corresponding memory location. Specifically:

[0094] The output buffer pointer of SM4 is read from the STACK_PTR position in the stack area. The encryption result is converted from big-endian to little-endian and the result is written back to the memory location pointed to by the output buffer pointer of SM4. Then, the output buffer pointer of SM3 is read from the stack area. The working variables a~h stored in general-purpose registers r8d to r15d are XORed with the original variables A~H in sequence, and the calculated result of SM3 is written back to memory.

[0095] Furthermore, by alternately executing SM4 parallel encryption instructions and SM3 compression function instructions within the same round of computation, modern CPUs allocate different types of instructions to execution ports with different functions. The SM3 compression function mainly consists of integer operations and data loading operations, thus primarily occupying the integer execution port and the load port; while the SM4 parallel encryption process relies on vector instructions such as SIMD, GFNI, or AES-NI, and its computation is mainly completed by the CPU's SIMD execution port. This allows both to be executed in parallel on different ports of the CPU.

[0096] Example 2

[0097] The purpose of this embodiment is to provide a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the above-described method.

[0098] Example 3

[0099] The purpose of this embodiment is to provide a computer-readable storage medium.

[0100] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the steps of the above method.

[0101] Example 4

[0102] The purpose of this embodiment is to provide a SM3 and SM4 fusion optimization system based on SIMD registers, including:

[0103] The stack space management module is configured to: request the required stack area to store the message extension array of SM3, the registers that need to be saved during function calls, and the parameter pointer addresses of SM3 and SM4, and store the parameter pointer addresses of SM3 and SM4 into the stack area;

[0104] The message expansion and front-round compression module is configured to: perform SM3 message expansion, write the expansion result to the stack area according to the determined mapping relationship, and then the compression function reads the expanded data from the stack area according to the mapping relationship and performs the front-round operation of the SM3 compression function;

[0105] The SM4 data loading and preprocessing module is configured to: read the parameter pointer address of SM4 from the stack area, load the data block to be encrypted into the SIMD register, and perform big-endian to little-endian format conversion on the data;

[0106] The fusion round function calculation module is configured to insert the SM4 round function implemented using SIMD instructions into the SM3 post-setting round compression function, so that the SM3 compression function instructions and the SM4 round function instructions are executed alternately to complete the fusion post-setting round calculation; the result write-back module is configured to: after completing all round function calculations of SM3 and SM4, store the encryption result of SM4 back to memory, then read the parameter pointer of SM3 from the stack area and write the hash result of SM3 back to memory.

[0107] Example 5

[0108] The purpose of this embodiment is to provide a computer program product containing instructions that, when run on a computer, causes the computer to perform the methods and functions involved in any of the embodiments described above.

[0109] The steps and methods involved in the apparatus of the above embodiments correspond to those in Embodiment 1. For specific implementation details, please refer to the relevant description section of Embodiment 1. The term "computer-readable storage medium" should be understood as a single medium or multiple media including one or more instruction sets; it should also be understood as including any medium capable of storing, encoding, or carrying an instruction set for execution by a processor and enabling the processor to perform any of the methods in this invention.

[0110] Those skilled in the art will understand that the modules or steps of the present invention described above can be implemented using general-purpose computer devices. Optionally, they can be implemented using computer-executable program code, thereby allowing them to be stored in a storage device for execution by a computer device, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. The present invention is not limited to any particular combination of hardware and software.

[0111] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. A SM3 and SM4 fusion optimization method based on SIMD registers, characterized in that, include: Allocate the required stack area to store the message extension array of SM3, the registers that need to be saved during function calls, and the parameter pointer addresses of SM3 and SM4, and store the parameter pointer addresses of SM3 and SM4 into the stack area; The SM3 message extension is executed, and the extension result is written to the stack area according to the determined mapping relationship. Then the compression function reads the extended data from the stack area according to the mapping relationship and executes the pre-set round operation of the SM3 compression function. Read the parameter pointer address of SM4 from the stack area, load the data block to be encrypted into the SIMD register, and convert the data from big endian to little endian format. The SM4 round function, implemented using SIMD instructions, is inserted into the SM3 post-setting round compression function, so that the SM3 compression function instructions and the SM4 round function instructions are executed alternately to complete the calculation of the merged post-setting round. After completing all round function calculations for SM3 and SM4, the encryption result of SM4 is stored back into memory. Then, the parameter pointer of SM3 is read from the stack area, and the hash result of SM3 is written back into memory.

2. The SM3 and SM4 fusion optimization method based on SIMD registers as described in claim 1, characterized in that, After requesting the required stack area, the stack area is divided into storage spaces according to a fixed layout, including: The message extension area is used to store message words; The parameter pointer area is used to store the parameter pointer addresses of SM3 and SM4, and the parameter pointers of SM3 and SM4 are written into this area after the stack area is allocated; The register storage area is used to save the state of critical general-purpose registers before a function call, so that the register contents can be restored after the function execution is complete.

3. The SM3 and SM4 fusion optimization method based on SIMD registers as described in claim 1, characterized in that, The parameter pointer address of SM4 is read from the stack, the data block to be encrypted is loaded into the SIMD register, and the data is converted from big-endian to little-endian format, specifically including: The output buffer pointer, input data pointer, and round key pointer of SM4 are read sequentially from the parameter pointer area of ​​the stack and loaded into a general-purpose register. Then, the data block to be encrypted is loaded into the SIMD register, and the data in the SIMD register is rearranged using a byte mask to convert the data from big-endian format to little-endian format.

4. The SM3 and SM4 fusion optimization method based on SIMD registers as described in claim 1, characterized in that, The SM4 round function, implemented using SIMD instructions, is inserted into the SM3 post-setting round compression function, causing the SM3 compression function instructions and the SM4 round function instructions to be executed alternately, completing the calculation of the merged post-setting round. Specifically, this includes: SM3 operation is executed, using general-purpose registers to store the working variables a~h of SM3. A circular left shift is performed on a to obtain the intermediate variable t0. t0 is added to the constant e to obtain the intermediate variable t1. Then, a circular left shift is performed on t1, and the message word W of the corresponding round is read from the stack and placed into h. Subsequently, SIMD operation is performed on SM4, broadcasting the current round key to the xmm0 register, and XORing it with the data block stored in the previous round's status register in sequence, storing the result in the xmm0 register. In the SM3 phase, t1 is added to h and stored back to h. Then, h is XORed with t0. The message word W′ of the current round is read from the stack and loaded into register d. Then, the SM4 operation is executed, and the result in register xmm0 is used to perform the pre-affine transformation. In the SM3 stage, the Boolean function FF is executed on the working variables a, b, and c, the result is stored in t1, and t1 is added to d; then the SM4 operation is executed, and the result in the register xmm0 is used to perform the inverse calculation and inverse affine transformation. In the SM3 stage, the Boolean function GG is executed on the working variables e, f, and g, the result is stored in t2, and t2 is added to h; then the SM4 operation is executed, the result in register xmm0 is circularly shifted to the left, and the result is stored in registers xmm10, xmm9, xmm8, and xmm0 respectively; In the SM3 stage, a 19-bit circular left shift is performed on the working variable f, and the intermediate variable t0 is added to d; then the SM4 operation is performed, the aforementioned registers xmm10, xmm9, xmm8, and xmm0 are XORed, and the result is stored in xmm1; In the SM3 stage, the working variable b is circularly shifted left by 9 bits. Then, h is circularly shifted left by 9 bits and stored in the intermediate variable t2. Next, h is circularly shifted left by 17 bits and stored in the intermediate variable t1. Finally, an XOR operation is performed on h, t1, and t2.

5. The SM3 and SM4 fusion optimization method based on SIMD registers as described in claim 1, characterized in that, After completing all round function calculations for SM3 and SM4, the encryption result of SM4 is stored back into memory. Then, the parameter pointer of SM3 is read from the stack, and the hash result of SM3 is written back into memory. Specifically, this includes: Read the output buffer pointer of SM4 from the stack, convert the encryption result to little endian, and write the processed result back to the memory location pointed to by the parameter pointer; then read the output buffer pointer of SM3 from the stack, perform XOR operations on the working variables a~h stored in general-purpose registers r8d to r15d with the original variables A~H in sequence, and write the calculated hash result back to memory.

6. A SM3 and SM4 fusion optimization system based on SIMD registers, characterized by including: The stack space management module is configured to: request the required stack area to store the message extension array of SM3, the registers that need to be saved during function calls, and the parameter pointer addresses of SM3 and SM4, and store the parameter pointer addresses of SM3 and SM4 into the stack area; The message expansion and front-round compression module is configured to: perform SM3 message expansion, write the expansion result to the stack area according to the determined mapping relationship, and then the compression function reads the expanded data from the stack area according to the mapping relationship and performs the front-round operation of the SM3 compression function; The SM4 data loading and preprocessing module is configured to: read the parameter pointer address of SM4 from the stack area, load the data block to be encrypted into the SIMD register, and perform big-endian to little-endian format conversion on the data; The fusion round function calculation module is configured to insert the SM4 round function implemented using SIMD instructions into the SM3 post-setting round compression function, so that the SM3 compression function instructions and the SM4 round function instructions are executed alternately to complete the fusion post-setting round calculation; The result write-back module is configured to: after completing all round function calculations for SM3 and SM4, store the encryption result of SM4 back into memory, then read the parameter pointer of SM3 from the stack area and write the hash result of SM3 back into memory.

7. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 5.

8. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method described in any one of claims 1-5.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it performs the steps of the method described in any one of claims 1-5.

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