Semiconductor device

Abstract

The invention provides a semiconductor device which is applied to the technical field of semiconductors. According to the invention, by changing the width of the interval between the adjacent bit line structures, the widths of the connecting pad structures formed between the different adjacent bit line structures are different in the horizontal direction, so that the positions of part of the second isolation structures are shifted, and the purpose of communicating part of the adjacent connecting pad structures is achieved.

Description

[0001] This application is a divisional application of the application with the application number "202411515207.2", the application date "2024-10-28", and the application name "A semiconductor device and a manufacturing method thereof". TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor technology, and in particular to a semiconductor device. BACKGROUND

[0003] Dynamic random access memory (DRAM) is a kind of volatile memory, including an array area composed of a plurality of memory cells and a peripheral area composed of a control circuit. Each memory cell is composed of a transistor and a capacitor electrically connected to the transistor. The transistor controls the storage or release of the charge in the capacitor to achieve the purpose of storing data. The control circuit can address each memory cell through the word line (WL) and the bit line (BL) that cross the array area and are electrically connected to each memory cell, to control the access of the data of each memory cell. However, due to the limitations of process technology, the existing dynamic random access memory still has many defects, and further improvement and effective improvement of the performance and reliability of the related memory components are needed. SUMMARY

[0004] The purpose of the present application is to provide a semiconductor device to improve the reliability and performance of the semiconductor device.

[0005] To solve the above technical problems, an embodiment of the present application provides a semiconductor device, comprising:

[0006] a substrate;

[0007] a plurality of bit line structures arranged on the substrate in a mutually separated manner;

[0008] a plurality of first connection pad structures arranged between adjacent bit line structures and directly contacting the substrate;

[0009] a plurality of first isolation structures arranged between adjacent first connection pad structures to isolate the adjacent first connection pad structures from each other;

[0010] a second connection pad structure arranged between adjacent bit line structures and directly contacting the substrate;

[0011] A second isolation structure is located in the second connection pad structure, and the second isolation structure is isolated from the bit line structure.

[0012] To solve the above technical problems, one embodiment of the present application provides a semiconductor device, comprising:

[0013] A substrate;

[0014] A plurality of bit line structures are arranged on the substrate in a spaced manner;

[0015] A plurality of first connection pad structures are arranged between adjacent bit line structures and directly contact the substrate;

[0016] A plurality of first isolation structures are arranged between adjacent first connection pad structures to isolate the adjacent first connection pad structures from each other;

[0017] A second connection pad structure is arranged between adjacent bit line structures and directly contacts the substrate;

[0018] A second isolation structure is located in the second connection pad structure, and a top surface of the second isolation structure is located at the same horizontal plane as a top surface of the first isolation structure.

[0019] To solve the above technical problems, one embodiment of the present application provides a semiconductor device, comprising:

[0020] A substrate;

[0021] A plurality of bit line structures are arranged on the substrate in a spaced manner;

[0022] A plurality of first connection pad structures are arranged between adjacent bit line structures and directly contact the substrate;

[0023] A plurality of first isolation structures are arranged between adjacent first connection pad structures to isolate the adjacent first connection pad structures from each other;

[0024] A second connection pad structure is arranged between adjacent bit line structures and directly contacts the substrate;

[0025] A second isolation structure comprises a bottom and two opposite side surfaces, the bottom and the side surfaces are located in the second connection pad structure, and a top surface of the second isolation structure is located at the same horizontal plane as a top surface of the first isolation structure.

[0026] To solve the above technical problems, one embodiment of the present application provides a semiconductor device, comprising:

[0027] A substrate;

[0028] a plurality of bit line structures disposed on the substrate in a spaced-apart manner;

[0029] a plurality of first connection pad structures disposed between adjacent bit line structures and directly contacting the substrate;

[0030] a plurality of first isolation structures disposed between adjacent first connection pad structures to isolate the adjacent first connection pad structures from each other;

[0031] a second connection pad structure disposed between adjacent bit line structures and directly contacting the substrate;

[0032] a second isolation structure located in the second connection pad structure, and a bottom of the second isolation structure being completely covered by the second connection pad structure.

[0033] To solve the above technical problems, an embodiment of the present application provides a semiconductor device, comprising:

[0034] a substrate;

[0035] a plurality of bit line structures disposed on the substrate in a spaced-apart manner;

[0036] a plurality of first connection pad structures disposed between adjacent bit line structures and directly contacting the substrate;

[0037] a plurality of first isolation structures disposed between adjacent first connection pad structures to isolate the adjacent first connection pad structures from each other;

[0038] a second connection pad structure disposed between adjacent bit line structures and directly contacting the substrate;

[0039] a second isolation structure comprising a bottom and two opposite side surfaces, the bottom and the side surfaces being located in the second connection pad structure, and the bottom of the second isolation structure being completely covered by the second connection pad structure.

[0040] To solve the above technical problems, an embodiment of the present application provides a semiconductor device, comprising:

[0041] a substrate;

[0042] a plurality of bit line structures disposed on the substrate in a spaced-apart manner;

[0043] a plurality of first connection pad structures disposed between adjacent bit line structures and directly contacting the substrate;

[0044] a plurality of first isolation structures disposed between adjacent first connection pad structures to isolate the adjacent first connection pad structures from each other;

[0045] a second connection pad structure disposed between adjacent bit line structures and directly contacting the substrate;

[0046] a second isolation structure located in the second connection pad structure, and a top surface of the second isolation structure being at a same horizontal level as a top surface of the second connection pad structure.

[0047] To solve the above technical problems, one embodiment of the present application provides a semiconductor device, comprising:

[0048] a substrate;

[0049] a plurality of bit line structures disposed on the substrate in a spaced-apart manner;

[0050] a plurality of first connection pad structures disposed between adjacent bit line structures and directly contacting the substrate;

[0051] a plurality of first isolation structures disposed between adjacent first connection pad structures to isolate the adjacent first connection pad structures from each other;

[0052] a second connection pad structure disposed between adjacent bit line structures and directly contacting the substrate;

[0053] a second isolation structure comprising a bottom and two opposite side surfaces, the bottom and the side surfaces being located in the second connection pad structure, and a top surface of the second isolation structure being at a same horizontal level as a top surface of the second connection pad structure.

[0054] To solve the above technical problems, one embodiment of the present application provides a semiconductor device, comprising:

[0055] a substrate;

[0056] a plurality of bit line structures disposed on the substrate in a spaced-apart manner;

[0057] a plurality of first connection pad structures disposed between adjacent bit line structures and directly contacting the substrate;

[0058] a plurality of first isolation structures disposed between adjacent first connection pad structures to isolate the adjacent first connection pad structures from each other;

[0059] a second connection pad structure disposed between adjacent bit line structures and directly contacting the substrate;

[0060] a second isolation structure located in the second connection pad structure, and a topmost point of the second isolation structure in a vertical direction being not lower than a topmost point of the second connection pad structure in the vertical direction.

[0061] To solve the above technical problems, one embodiment of the present application provides a semiconductor device, comprising:

[0062] a substrate;

[0063] a plurality of bit line structures arranged on the substrate in a spaced manner;

[0064] a plurality of first connection pad structures arranged between adjacent bit line structures and directly contacting the substrate;

[0065] a plurality of first isolation structures arranged between adjacent first connection pad structures to isolate the adjacent first connection pad structures from each other;

[0066] a second connection pad structure arranged between adjacent bit line structures and directly contacting the substrate;

[0067] a second isolation structure comprising a bottom and two opposite side surfaces, the bottom and the side surfaces are located in the second connection pad structure, and the topmost point of the second isolation structure in the vertical direction is not lower than the topmost point of the second connection pad structure in the vertical direction.

[0068] To solve the above technical problems, one embodiment of the present application provides a semiconductor device, comprising:

[0069] a substrate;

[0070] a plurality of bit line structures arranged on the substrate in a spaced manner;

[0071] a plurality of first connection pad structures arranged between adjacent bit line structures and directly contacting the substrate;

[0072] a plurality of first isolation structures arranged between adjacent first connection pad structures to isolate the adjacent first connection pad structures from each other;

[0073] a second connection pad structure arranged between adjacent bit line structures and comprising a second upper half and a second lower half connected to each other, the second lower half directly contacts the substrate, and the second upper half is partially located above the bit line structure;

[0074] a second isolation structure comprising a bottom and two opposite side surfaces, the bottom and the side surfaces are located in the second upper half, and the bottommost point of the second isolation structure in the vertical direction is higher than the topmost point of the second lower half in the vertical direction.

[0075] To solve the above technical problems, one embodiment of the present application provides a semiconductor device, comprising:

[0076] a substrate;

[0077] a plurality of bit line structures disposed on the substrate in a spaced-apart manner, each of the bit line structures comprising a metal layer and a cap layer stacked in sequence from bottom to top;

[0078] a plurality of first connection pad structures disposed between adjacent bit line structures and in direct contact with the substrate;

[0079] a plurality of first isolation structures disposed between adjacent first connection pad structures to isolate the adjacent first connection pad structures from each other;

[0080] a second connection pad structure disposed between adjacent bit line structures and comprising a second upper half and a second lower half connected to each other, the second lower half being in direct contact with the substrate, and the second upper half being partially located above the bit line structures;

[0081] a second isolation structure comprising a bottom and two opposite side surfaces, the bottom and the side surfaces being located within the second upper half, and a lowest point of the second isolation structure in a vertical direction being higher than a lowest point of the cap layer in the vertical direction.

[0082] Further, the bit line structures comprise a metal layer and a cap layer stacked in sequence from bottom to top, and the first isolation structures are in direct contact with the cap layer.

[0083] Further, the second connection pad structure comprises a second upper half and a second lower half connected to each other, the second lower half being in direct contact with the substrate, and the second upper half being partially located above the bit line structures, wherein a lowest point of the second isolation structure is higher than a highest point of the second lower half.

[0084] Further, a first spacing is provided between adjacent first isolation structures, and a second spacing is provided between adjacent first isolation structures and the second isolation structure, the first spacing being smaller than the second spacing.

[0085] Further, a width of the first connection pad structure in a horizontal direction is smaller than a width of the second connection pad structure in the horizontal direction.

[0086] In the present application, by setting the interval between the adjacent first bit line structure and the second bit line structure to be larger than the interval between the adjacent first bit line structures, the width of the connection pad structure formed between the two adjacent first bit line structures in the horizontal direction is smaller than the width of the connection pad structure formed between the adjacent first bit line structure and the second bit line structure in the horizontal direction, and further, the second isolation structure within the connection pad structure formed between the adjacent first bit line structure and the second bit line structure is offset in the direction close to the second bit line structure, so as to achieve the purpose of allowing the connection pad structure between the adjacent first bit line structure and the second bit line structure to communicate with the connection pad structure adjacent to it and located between the adjacent first bit line structures. BRIEF DESCRIPTION OF DRAWINGS

[0087] The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and are

[0088] Figures 1-7 For the semiconductor device provided in the first embodiment of the present application, the second isolation structure within the connection pad structure formed between the adjacent first bit line structure and the second bit line structure is offset in the direction close to the second bit line structure during the preparation process along the portion of the structure shown in the sectional view taken along the line AA' of the top view. Figure 6

[0089] Figure 6 For the semiconductor device provided in the first embodiment of the present application, the second isolation structure within the connection pad structure formed between the adjacent first bit line structure and the second bit line structure is offset in the direction close to the second bit line structure during the preparation process along the portion of the structure shown in the sectional view taken along the line AA' of the top view. Figure 5

[0090] Figures 8-14 For the semiconductor device provided in the second embodiment of the present application, the second isolation structure within the connection pad structure formed between the adjacent first bit line structure and the second bit line structure is offset in the direction close to the second bit line structure during the preparation process along the portion of the structure shown in the sectional view taken along the line AA' of the top view. Figure 13

[0091] Figure 13 For the semiconductor device provided in the second embodiment of the present application, the second isolation structure within the connection pad structure formed between the adjacent first bit line structure and the second bit line structure is offset in the direction close to the second bit line structure during the preparation process along the portion of the structure shown in the sectional view taken along the line AA' of the top view. Figure 12

[0092] In the drawings, the reference signs are as follows:

[0093] ​​​​100 - Substrate, 110 - Trench isolation, 120 - Insulating layer, 130 - Bit line material layer, 131 - Semiconductor layer, 132 - Barrier layer, 133 - Metal layer, 134 - Cap layer, BL - Bit line structure, BL1 - First bit line structure, BL2 - Second bit line structure, BL3 - Third bit line structure, SP1 - First spacer, SP2 - Second spacer, SP3 - Third spacer, SP4 - Fourth spacer, 140 - Sidewall structure, 141 - First sidewall, 142 - Second sidewall, 150 - Contact structure, 160 - Silicate layer, 170 - Connector pad structure, 170.1 - First connector pad layer, 170.2 - Second connector pad layer, 171 - First connector pad structure, 172 - Second connector pad structure, 180 - Isolation structure, 181 - First isolation structure, 182 - Second isolation structure, d1 - First pitch, d2 - Second pitch.

[0094] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation

[0095] The semiconductor device and its manufacturing method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention may be practiced in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.

[0096] Please refer to Figure 5 and Figure 6 , Figure 6 The drawing shows a partial top view of the semiconductor device according to the first embodiment of the present invention. Figure 5 The illustration shows a semiconductor device according to a first embodiment of the present invention. Figure 6 The diagram shows a cross-sectional view of a portion of the tangent line AA'. The semiconductor device of this invention can be used to manufacture dynamic random access memory (DRAM), and without departing from the spirit of this invention, it can also be applied to other types of memory.

[0097] like Figure 5As shown, the semiconductor device includes a substrate 100, a plurality of bit line structures BL, a plurality of connection pad structures 170, and a plurality of isolation structures 180. The substrate 100 can be any suitable substrate material known in the art, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe), a silicon-on-insulator substrate, or other suitable material, without limitation. In one embodiment, a plurality of trench isolations 110 (e.g., including silicon oxide) can be further provided in the substrate 100 to define a plurality of active regions (not shown) extending in the same direction (not shown) in the substrate 100. In one embodiment, the trench isolations 110 can be elongated. In addition, an insulating layer 120 can be provided on the substrate 100. In one embodiment, the insulating layer 120 can be a single layer, such as a silicon oxide layer or a silicon nitride layer, or a composite layer, such as an ONO composite layer including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, without limitation. In one embodiment, the insulating layer 120 can be a single layer (e.g., including a silicon nitride layer).

[0098] In the present embodiment, the bit line structure BL is disposed on the substrate 100, and the details include a plurality of first bit line structures BL1 and a second bit line structure BL2 which are separated from each other and have different widths and different intervals. Specifically, the plurality of first bit line structures BL1 are arranged in sequence along a direction parallel to the surface of the substrate 100 (hereinafter referred to as the horizontal direction), and the second bit line structure BL2 is located outside one side of the plurality of first bit line structures BL1. Specifically, if the width of the first bit line structure BL1 in the horizontal direction is a first width, and the width of the second bit line structure BL2 in the horizontal direction is a second width, the first width is smaller than the second width. If the interval between adjacent first bit line structures BL1 is a first interval SP1, and the interval between adjacent first bit line structures BL1 and the second bit line structure BL2 is a second interval SP2, the first interval SP1 is smaller than the second interval SP2. In an embodiment, the first bit line structure BL1 and the second bit line structure BL2 have the same multi-layer bit line material layer, for example, a bit line material layer 130 composed of a semiconductor layer 131, a barrier layer 132, a metal layer 133, and a cap layer 134 stacked in sequence from bottom to top. The material of the semiconductor layer 131 can include crystalline silicon, poly silicon, amorphous silicon, doped silicon, silicon germanium (SiGe), or other suitable semiconductor materials, but is not limited thereto. The material of the barrier layer 132 can include metal, metal silicide, or metal nitride, for example, titanium (Ti), titanium nitride (TiN), tungsten silicide (WSi), cobalt silicide (CoSi), tungsten nitride (WN), but is not limited thereto. The material of the metal layer 133 can include tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a compound, alloy, and / or composite layer of the aforementioned metal materials, but is not limited thereto. The cap layer 134 can include a dielectric material, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), or a combination of the aforementioned materials, but is not limited thereto. For example, the material of the semiconductor layer 131 is poly silicon, the material of the barrier layer 132 is cobalt silicide (CoSi), the material of the metal layer 133 is tungsten (W), and the material of the cap layer 134 is silicon nitride (SiN).

[0099] In addition, the sidewall of the first bit line structure BL1 and the second bit line structure BL2 in the present embodiment can also be provided with a sidewall structure 140. The sidewall structure 140 can also have a multi-layer structure, for example Figure 5The first and second sidewalls 141 and 142 are shown to be stacked in a horizontal direction in sequence, and the first sidewall 141 is in direct contact with the sidewall of the first or second bit line structure BL1 or BL2. Specifically, the first and second sidewalls 141 and 142 can each include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or a combination thereof, but are not limited thereto. For example, the first sidewall 141 can be made of silicon oxide (SiO2), and the second sidewall 142 can be made of silicon nitride (SiN).

[0100] With continued reference to Figure 5 As shown, the semiconductor device in the present embodiment can further include a plurality of contact structures 150 and a silicide layer 160. In particular, a contact structure 150 and a silicide layer 160 on the contact structure 150 are formed in a first space SP1 between adjacent first bit line structures BL1 and a second space SP2 between the first and second bit line structures BL1 and BL2, respectively. The contact structure 150 is vertically extended in a direction perpendicular to the surface of the substrate 100 (hereinafter referred to as a vertical direction) in the substrate 100 between the adjacent bit line structures BL, and is electrically connected to the substrate 100. In one embodiment, the contact structure 150 can include crystalline silicon, poly silicon, amorphous silicon, doped silicon, silicon germanium (SiGe), or other suitable silicon-containing semiconductor materials, but is not limited thereto. For example, the contact structure 150 can be made of phosphorus-doped silicon (SiP).

[0101] Further, the connection pad structure 170 in the embodiment is specifically arranged between adjacent bit line structures BL and covers the top surface of the silicide layer 160, the top surface of the sidewall structure 140 and the top surface of the bit line structure BL in a co-typed manner, and the isolation structure 180 is specifically arranged between adjacent connection pad structures 170. In an embodiment, the connection pad structure 170 can include a first connection pad layer 170.1 and a second connection pad layer 170.2 stacked in sequence from bottom to top; the material of the first connection pad layer 170.1 can include conductive barrier materials such as titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN), but is not limited to this; the material of the second connection pad layer 170.2 can include metals such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), nitrides, silicides, alloys and / or composite layers of the foregoing materials, and preferably tungsten (W), but is not limited to this.

[0102] In the embodiment, since the first spacing SP1 between adjacent first bit line structures BL1 and the second spacing SP2 between adjacent first bit line structures BL1 and second bit line structures BL2 are different, i.e., the first spacing SP1 < the second spacing SP2, the widths of the connection pad structures 170 located between adjacent first bit line structures BL1 and the connection pad structures 170 and the silicide layers 160 and contact structures 150 thereunder located between adjacent first bit line structures BL1 and second bit line structures BL2 in the horizontal direction are also different. For the sake of distinction, the connection pad structure located between adjacent first bit line structures BL1 is named as a first connection pad structure 171, and the connection pad structure located between adjacent first bit line structures BL1 and second bit line structures BL2 is named as a second connection pad structure 172 (as shown in Figure 4 Therefore, the width of the second connection pad structure 172 in the horizontal direction in the embodiment is greater than the width of the first connection pad structure 171 in the horizontal direction, and the width of the contact structure 150 located under the first connection pad structure 171 in the horizontal direction is also less than the width of the contact structure 150 located under the second connection pad structure 172 in the horizontal direction.

[0103] Under this arrangement, the isolation structure 180 in the embodiment can also be divided into a first isolation structure 181 and a second isolation structure 182 due to the difference between the first spacing SP1 between adjacent first bit line structures BL1 and the second spacing SP2 between adjacent first bit line structures BL1 and second bit line structures BL2, as shown in Figure 5In detail, the first isolation structure 181 directly contacts the first connection pad structure 171 and the first bit line structure BL1 in a vertical direction, and the second isolation structure 182 passes through the second connection pad structure 172 in a vertical direction and is completely covered by the second connection pad structure 172 at a bottom surface thereof, so that the second isolation structure 182 is isolated from the first bit line structure BL1 and the second bit line structure BL2 on both sides of the second connection pad structure 172. In other words, if a distance between adjacent first isolation structures 181 is a first distance d1, and a distance between adjacent first isolation structures 181 and second isolation structures 182 is a second distance d2, the first distance d1 is less than the second distance d2. In an embodiment, the isolation structure 180 (including the first isolation structure 181 and the second isolation structure 182) can be made of the same material, and can specifically include nitride, such as silicon nitride, or oxide, such as silicon oxide, and is preferably silicon nitride, but is not limited thereto.

[0104] In the prior art, the first connection pad structure 171 and the second connection pad structure 172 need to be isolated by the second isolation structure 182 to avoid shorting of the two contact structures 150 located below the first connection pad structure 171 and the second connection pad structure 172. However, in actual applications, the first bit line structure BL1 located at the edge and the second bit line structure BL2 adjacent thereto are often used as dummy structures for adjusting the pattern density of the semiconductor device. Therefore, in the embodiment of the present application, the second isolation structure 182 located in the second space SP2 between the first bit line structure BL1 and the second bit line structure BL2 is offset in a horizontal direction close to the second bit line structure BL2, so that the first connection pad structure 171 and the second connection pad structure 172 located above the first bit line structure BL1 and the second bit line structure BL2 are connected, thereby avoiding the technical problem that some contact structures are stripped during the process such as photolithography due to the difference in pattern density, and improving the reliability and performance of the semiconductor device.

[0105] In addition, referring to Figure 7 The semiconductor device in the embodiment can further include a capacitor structure CAP disposed on the first connection pad structure 171 between adjacent first bit line structures BL1. The capacitor structure CAP includes a lower electrode BE, a dielectric layer DL, and an upper electrode TE. The lower electrode BE is disposed on the first connection pad structure 171, the upper electrode TE is disposed on the lower electrode BE, and the dielectric layer DL is disposed between the upper electrode TE and the lower electrode BE.

[0106] It should be understood that "common" in the embodiments of the present invention refers to the construction of a continuous structural shape by utilizing the morphological similarity and correlation between two or more shapes.

[0107] Those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device of this invention may have other forms and is not limited to those described above. Further descriptions will follow regarding other embodiments or variations of the semiconductor device of this invention. For simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. Furthermore, identical components in the embodiments of this invention are designated with the same reference numerals to facilitate comparison between embodiments.

[0108] Please refer to Figure 12 and Figure 13 , Figure 13 The drawing shows a partial top view of a semiconductor device according to a second embodiment of the present invention. Figure 12 The illustration shows a semiconductor device according to a second embodiment of the present invention. Figure 13 The diagram shows a cross-sectional view of a portion of the AA' tangent. The structure of the semiconductor device in this embodiment is largely the same as that in the first embodiment described above. For example, the semiconductor device also includes multiple first bit line structures BL1 arranged horizontally and mutually separated on the substrate 100, and second bit line structures BL2 located on the outer side of one side of the multiple first bit line structures BL1, multiple contact structures 150, etc. The similarities will not be repeated here. The main difference between the semiconductor device in this embodiment and the first embodiment described above is that at least one third bit line structure BL3 is also provided in the multiple bit line structures BL of the semiconductor device, and the top surface of the third bit line structure BL3 is located at a different horizontal height from the top surfaces of the first bit line structure BL1 and the second bit line structure BL2, so that the second isolation structure 182 located on the top surface of the third bit line structure BL3 is also different.

[0109] Specifically, such as Figure 12As shown, the semiconductor device in this embodiment is provided with a third bit line structure BL3 between the adjacent first bit line structure BL1 and the second bit line structure BL2, so that the first bit line structure BL1, the third bit line structure BL3 and the second bit line structure BL2 are arranged in a horizontal direction and spaced apart from each other, and the top surface of the third bit line structure BL3 is lower than the top surfaces of the first bit line structure BL1 and the second bit line structure BL2. In an embodiment, the third bit line structure BL3 has the same multi-layer bit line material layers, such as the semiconductor layer 131 (e.g., polysilicon), the barrier layer 132 (e.g., cobalt silicide) and the metal layer 133 (e.g., tungsten) stacked from bottom to top; the third spacing SP3 between the third bit line structure BL3 and the first bit line structure BL1 adjacent thereto can be the same as the first spacing SP1 between the adjacent first bit line structures BL1, and the fourth spacing SP4 between the third bit line structure BL3 and the second bit line structure BL2 adjacent thereto can be smaller than the third spacing SP3.

[0110] It should be particularly noted that the connection pad structure 170 in this embodiment is still divided into the first connection pad structure 171 and the second connection pad structure, and the isolation structure 180 is still divided into the first isolation structure 181 and the second isolation structure 182; since the multi-layer bit line material layers of the third bit line structure BL3 do not include the cap layer 134, the connection pad structure 170 in this embodiment located between the adjacent first bit line structure BL1 and the second bit line structure BL2 changes from one in the first embodiment to two in this embodiment, i.e., a second connection pad structure 172 located in the third spacing SP3 between the top surface of the third bit line structure BL3 and the first bit line structure BL1 adjacent thereto (at this time, the first connection pad layer 170.1 in the second connection pad structure 172 is in direct contact with the metal layer 134 of the third bit line structure BL3), and a second connection pad structure 172 located in the fourth spacing SP4 between the third bit line structure BL3 and the second bit line structure BL2 adjacent thereto and on the top surface of the second bit line structure BL2.

[0111] Under this arrangement, the isolation structure 180 in this embodiment located between the first bit line structure BL1 and the second bit line structure BL2 also changes from the second isolation structure 182 in the first embodiment which is completely covered by the second connection pad structure 172 at the bottom to a second isolation structure 182 located above the third bit line structure BL3 and isolated from the third bit line structure BL3 and the bit line structures BL on both sides of the third bit line structure BL3, and a second isolation structure 182 located above the second bit line structure BL2 and in direct contact with the second bit line structure BL2.

[0112] Apparently, the second isolation structure 182 above the third bit line structure BL3 in this embodiment has process deviation, so that the two adjacent second connection pad structures 172 above the third bit line structure BL3 are communicated, to avoid the technical problem that part of the contact structure is stripped in the process such as photolithography due to large pattern density difference, and to further improve the reliability and performance of the semiconductor device.

[0113] Further, based on the same inventive concept, the present embodiment also provides a manufacturing method for manufacturing the semiconductor device, which can specifically include the following steps:

[0114] Step S100, providing a substrate 100;

[0115] Step S200, forming a plurality of bit line structures BL, the bit line structure BL including a first bit line structure BL1 and a second bit line structure BL2 arranged on the substrate 100 in a separated manner;

[0116] Step S300, forming a plurality of connection pad structures 170 arranged between adjacent bit line structures BL;

[0117] Step S400, forming a plurality of isolation structures 180 arranged between adjacent connection pad structures 170, the isolation structure 180 including a first isolation structure 181 directly contacting the first bit line structure BL1 and the connection pad structure 170, and a second isolation structure 182 located between the first bit line structure BL1 and the second bit line structure BL2, and the bottom surface of the second isolation structure 182 is completely covered by the connection pad structure 170.

[0118] In order to enable those skilled in the art to easily understand the manufacturing method of the semiconductor device in the present embodiment, the manufacturing method of the semiconductor device proposed in the present application will be further described below in conjunction with the structure schematic diagram of the manufacturing method in the preparation process.

[0119] Please refer to Figures 1-7 , Figures 1-7 is the structure schematic diagram of the manufacturing method of the semiconductor device provided in the first embodiment of the present application in the preparation process.

[0120] Please refer to Figure 1, performing the above step S100 and the above step S200: providing a substrate 100, and forming a plurality of trenches in the substrate 100 by using an etching process, and filling insulating material (such as silicon oxide, silicon nitride, etc.) in the plurality of trenches by using a deposition process (such as at least one of physical vapor deposition process, chemical vapor deposition process, or atomic layer deposition process) to form a plurality of trench isolations 110, which define a plurality of active regions in the substrate 100. Then, forming an insulating layer 120 (such as a silicon oxide layer or a silicon nitride layer) on the substrate 100, and forming a multilayer bit line material layer on the insulating layer 120. Specifically, forming the multilayer bit line material layer can include sequentially forming a semiconductor layer 131, a barrier layer 132, a metal layer 133, and a cap layer 134 on the substrate 100 from bottom to top, and exemplarily, the material of the semiconductor layer 131 is polysilicon, the material of the barrier layer 132 is cobalt silicide (CoSi), the material of the metal layer 133 is tungsten (W), and the material of the cap layer 134 is silicon nitride (SiN). Then, sequentially etching the multilayer structure of the bit line material layer in a vertical direction by using an etching process, so as to form a plurality of mutually separated bit line structures BL in the bit line material layer; specifically, the bit line structure BL in detail includes a plurality of first bit line structures BL1 and a second bit line structure BL2, the plurality of first bit line structures BL1 are sequentially arranged apart in a horizontal direction, the second bit line structure BL2 is located on one side of the plurality of first bit line structures BL1, and the width of the first bit line structure BL1 in the horizontal direction is less than the width of the second bit line structure BL2 in the horizontal direction, and the first interval SP1 between adjacent first bit line structures BL1 is less than the second interval SP2 between adjacent first bit line structures BL1 and the second bit line structure BL2.

[0121] Please refer to Figure 2 , continuing the above step S200, forming a sidewall structure 140 self-aligned to the sidewalls of the first bit line structures BL1 and the second bit line structure BL2 on both sides of the plurality of first bit line structures BL1 and the second bit line structure BL2; in an embodiment, the sidewall structure 140 has a multilayer structure, for example, a first sidewall 141 (such as silicon oxide) and a second sidewall 142 (such as silicon nitride) sequentially stacked in a horizontal direction.

[0122] Please refer to Figure 3, the step S200 is performed: etching downward along the vertical direction to form a storage node contact trench (not shown) outside the sidewall structure 140 after removing the insulating layer 120 and part of the substrate 100, then forming a contact material layer (not shown) to cover the substrate 100 and fill the storage node contact trench, and then removing the contact material layer outside the storage node contact trench by etching or planarization process until the bit line structure BL and the top surface of the sidewall structure 140 are exposed, thereby obtaining the contact structure 150 in the storage node contact trench. The contact material layer can be a silicon-containing semiconductor material, such as phosphorus-doped silicon. Then, a metal material layer (not shown) is deposited on the substrate 100, and a silicidation process is performed on the metal material layer and the substrate 100, so that the top of the contact structure 150 with the silicon-containing semiconductor material, such as phosphorus-doped silicon, reacts with the metal material layer to form a silicide layer 160, thereby obtaining the structure shown in FIG. 1C. At this time, since the first interval SP1 between adjacent first bit line structures BL1 and the second interval SP2 between adjacent first bit line structures BL1 and second bit line structures BL2 are different, i.e. the first interval SP1 < the second interval SP2, the width of the contact structure 150 and the silicide layer 160 thereon between adjacent first bit line structures BL1 in the horizontal direction is different from the width of the contact structure 150 and the silicide layer 160 thereon between adjacent first bit line structures BL1 and second bit line structures BL2 in the horizontal direction, i.e. the width of the contact structure 150 and the silicide layer 160 thereon between adjacent first bit line structures BL1 in the horizontal direction is less than the width of the contact structure 150 and the silicide layer 160 thereon between adjacent first bit line structures BL1 and second bit line structures BL2 in the horizontal direction. Figure 3

[0123] Please refer to Figure 4 ​, the step S300 is performed: a first connection pad material layer (e.g. titanium nitride) and a second connection pad material layer (e.g. tungsten) of the connection pad structure 170 are deposited on the substrate 100 by a deposition process, and etched to form a first connection pad layer 170.1 wrapping the surfaces of the silicide layer 160, the first bit line structure BL1 and the second bit line structure BL2, and a second connection pad layer 170.2 filling the gap between the adjacent first bit line structure BL1 and the second bit line structure BL2 and having a top surface higher than the top surface of the first bit line structure BL1, thereby forming the connection pad structure 170 including the first connection pad layer 170.1 and the second connection pad layer 170.2 arranged in sequence from bottom to top. Similarly, due to the difference between the first spacing SP1 between the adjacent first bit line structures BL1 and the second spacing SP2 between the adjacent first bit line structure BL1 and the second bit line structure BL2, the plurality of connection pad structures 170 in the embodiment can be specifically divided into the first connection pad structure 171 and the second connection pad structure 172 according to the difference in width in the horizontal direction, wherein the first connection pad structure 171 is located between the adjacent first bit line structures BL1, the second connection pad structure 172 is located between the adjacent first bit line structure BL1 and the second bit line structure BL2, and the width of the first connection pad structure 171 in the horizontal direction is less than the width of the second connection pad structure 172 in the horizontal direction.

[0124] Please refer to Figure 5 , the step S400 is performed: a mask layer (not shown) having isolation structure patterns is formed on the connection pad structure 180, and a plurality of isolation structures 180 are formed on the connection pad structure 170 and part of the bit line structure BL on one side of the bit line structure BL by an etching process with the mask layer as a mask. Specifically, the isolation structure 180 includes the first isolation structure 181 and the second isolation structure 182 arranged in sequence and separated from each other in the horizontal direction, wherein the first isolation structure 181 passes through the first connection pad structure 171, and the bottom surface thereof extends to the first bit line structure BL1 to directly contact the corresponding first bit line structure BL1, and the second isolation structure 182 passes through the second connection pad structure 172 and the bottom surface thereof is completely covered by the second connection pad structure 172, so that the second isolation structure 182 is isolated from the first bit line structure BL1 and the second bit line structure BL2 located on both sides of the second connection pad structure 172. In an embodiment, the material of the isolation structure 180 (including the first isolation structure 181 and the second isolation structure 182) can be the same and specifically can include nitride such as silicon nitride, or oxide such as silicon oxide, and is preferably silicon nitride, but is not limited thereto.

[0125] Please refer to Figure 7After the step S400, a capacitor structure CAP is formed on the first connection pad structure 171 between the adjacent first bit line structures BL1, wherein the capacitor structure CAP comprises a lower electrode BE, a dielectric layer DL and an upper electrode TE. The lower electrode BE is disposed on the first connection pad structure 171, the upper electrode TE is disposed on the lower electrode BE, and the dielectric layer DL is disposed between the upper electrode TE and the lower electrode BE.

[0126] It should be noted that, since the first bit line structure BL1 located at the edge of the cell region and the second bit line structure BL2 located on the peripheral region are often used as dummy structures for adjusting the pattern density of the cell region in actual applications, the second isolation structure 182 located in the second space SP2 between the adjacent first bit line structure BL1 and the second bit line structure BL2 is offset in the horizontal direction close to the second bit line structure BL2 to make the first connection pad structure 171 and the second connection pad structure 172 located above the adjacent first bit line structure BL1 and the second bit line structure BL2 communicate. Therefore, when the isolation structure 180 is formed by the step S400, the isolation trench (not shown, located at the same position as the isolation structure) in the first connection pad structure 171 and the second connection pad structure 172 is offset in the horizontal direction close to the second bit line structure BL2, and the entire bottom surface of the second isolation structure 182 formed by filling the isolation trench with insulating material (such as silicon nitride) by the deposition process is covered by the second connection pad structure 172, that is, the communication between the first connection pad structure 171 and the second connection pad structure 172 located above the adjacent first bit line structure BL1 and the second bit line structure BL2 is realized.

[0127] It should be noted that, since the first bit line structure BL1 located at the edge of the cell region and the second bit line structure BL2 located on the peripheral region are often used as dummy structures for adjusting the pattern density of the cell region in actual applications, the second isolation structure 182 located in the second space SP2 between the adjacent first bit line structure BL1 and the second bit line structure BL2 is offset in the horizontal direction close to the second bit line structure BL2 to make the first connection pad structure 171 and the second connection pad structure 172 located above the adjacent first bit line structure BL1 and the second bit line structure BL2 communicate. Therefore, when the isolation structure 180 is formed by the step S400, the isolation trench (not shown, located at the same position as the isolation structure) in the first connection pad structure 171 and the second connection pad structure 172 is offset in the horizontal direction close to the second bit line structure BL2, and the entire bottom surface of the second isolation structure 182 formed by filling the isolation trench with insulating material (such as silicon nitride) by the deposition process is covered by the second connection pad structure 172, that is, the communication between the first connection pad structure 171 and the second connection pad structure 172 located above the adjacent first bit line structure BL1 and the second bit line structure BL2 is realized. Figures 8-14 Figures 8-14 The manufacturing method of the semiconductor device provided in the second embodiment of the present application is a schematic diagram of the structure during the preparation process.

[0128] The structure of the semiconductor device of the present embodiment is basically the same as that of the semiconductor device manufactured by the manufacturing method of the first embodiment, and the same parts will not be described here. The main difference between the manufacturing method of the semiconductor device of the present embodiment and the manufacturing method of the first embodiment is that, after the step S200 is performed to form the plurality of first bit line structures BL1 and the second bit line structure BL2 arranged in the horizontal direction in sequence, the cover layer 134 of one of the first bit line structures BL1 adjacent to the second bit line structure BL2 is removed by an etching process, such as a dry etching process, to form a third bit line structure BL3 between the adjacent first bit line structure BL1 and the second bit line structure BL2, as shown in​Figure 8 It should be understood that in other embodiments, the sidewall structure 140 can be formed on the sidewalls of the first bit line structure BL1 and the second bit line structure BL2 after the sidewall structure 140 is formed, and then an etching process is performed to form the structure as shown in FIG. 1C. Figure 9 The structure is described, but is not limited thereto.

[0129] In summary, in the present application, by setting the interval between the adjacent first bit line structure and the second bit line structure to be larger than the interval between the adjacent first bit line structures, the width of the connection pad structure formed between the adjacent two first bit line structures in the horizontal direction is smaller than the width of the connection pad structure formed between the adjacent first bit line structure and the second bit line structure in the horizontal direction, and further, the second isolation structure in the connection pad structure formed between the adjacent first bit line structure and the second bit line structure is offset in the direction close to the second bit line structure, and the purpose of allowing the connection pad structure between the adjacent first bit line structure and the second bit line structure to communicate with the connection pad structure adjacent thereto and located between the adjacent first bit line structures is achieved.

[0130] It should be noted that the relational terms herein such as first and second and the like are used solely to distinguish one from another entity or action, without necessarily requiring or implying any actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0131] Each of the embodiments in the present specification is described in a relevant manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments. In particular, for the device, electronic device, and computer readable storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiment.

[0132] The above only describes the preferred embodiments of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor device, characterized by, The method comprises: providing a substrate; providing a plurality of bit line structures on the substrate; providing a plurality of first connection pad structures between adjacent bit line structures and directly contacting the substrate; providing a plurality of first isolation structures between adjacent first connection pad structures to isolate the adjacent first connection pad structures from each other; providing a second connection pad structure between adjacent bit line structures and directly contacting the substrate; providing a second isolation structure within the second connection pad structure and isolating the second isolation structure from the bit line structures.

2. A semiconductor device, characterized by, The method comprises: providing a substrate; providing a plurality of bit line structures on the substrate; providing a plurality of first connection pad structures between adjacent bit line structures and directly contacting the substrate; providing a plurality of first isolation structures between adjacent first connection pad structures to isolate the adjacent first connection pad structures from each other; providing a second connection pad structure between adjacent bit line structures and directly contacting the substrate; providing a second isolation structure within the second connection pad structure and isolating the second isolation structure from the bit line structures.

3. A semiconductor device, characterized by, The method comprises: providing a substrate; providing a plurality of bit line structures on the substrate; providing a plurality of first connection pad structures between adjacent bit line structures and directly contacting the substrate; providing a plurality of first isolation structures between adjacent first connection pad structures to isolate the adjacent first connection pad structures from each other; providing a second connection pad structure between adjacent bit line structures and directly contacting the substrate; providing a second isolation structure within the second connection pad structure and isolating the second isolation structure from the bit line structures.

4. A semiconductor device, characterized by, The method comprises: providing a substrate; providing a plurality of bit line structures on the substrate; providing a plurality of first connection pad structures between adjacent bit line structures and directly contacting the substrate; providing a plurality of first isolation structures between adjacent first connection pad structures to isolate the adjacent first connection pad structures from each other; providing a second connection pad structure between adjacent bit line structures and directly contacting the substrate; providing a second isolation structure within the second connection pad structure and isolating the second isolation structure from the bit line structures.

5. A semiconductor device, characterized by, The method comprises: providing a substrate; providing a plurality of bit line structures on the substrate; providing a plurality of first connection pad structures between adjacent bit line structures and directly contacting the substrate; providing a plurality of first isolation structures between adjacent first connection pad structures to isolate the adjacent first connection pad structures from each other; providing a second connection pad structure between adjacent bit line structures and directly contacting the substrate; providing a second isolation structure within the second connection pad structure and isolating the second isolation structure from the bit line structures.

6. A semiconductor device, characterized by The method comprises: providing a substrate; providing a plurality of bit line structures on the substrate; providing a plurality of first connection pad structures between adjacent bit line structures and directly contacting the substrate; providing a plurality of first isolation structures between adjacent first connection pad structures to isolate the adjacent first connection pad structures from each other; providing a second connection pad structure between adjacent bit line structures and directly contacting the substrate; providing a second isolation structure within the second connection pad structure and isolating the second isolation structure from the bit line structures. The method comprises: providing a substrate; providing a plurality of bit line structures on the substrate; providing a plurality of first connection pad structures between adjacent bit line structures and directly contacting the substrate; providing a plurality of first isolation structures between adjacent first connection pad structures to isolate the adjacent first connection pad structures from each other; providing a second connection pad structure between adjacent bit line structures and directly contacting the substrate; providing a second isolation structure within the second connection pad structure and isolating the second isolation structure from the bit line structures. The method comprises: providing a substrate; a plurality of bit line structures disposed on the substrate in a spaced-apart manner; a plurality of first connection pad structures disposed between adjacent bit line structures and directly contacting the substrate; a plurality of first isolation structures disposed between adjacent first connection pad structures to isolate the adjacent first connection pad structures from each other; a second connection pad structure disposed between adjacent bit line structures and directly contacting the substrate; a second isolation structure located within the second connection pad structure, and a top surface of the second isolation structure is at a same level as a top surface of the second connection pad structure.

7. A semiconductor device, characterized by comprising: comprising: a substrate; a plurality of bit line structures disposed on the substrate in a spaced-apart manner; a plurality of first connection pad structures disposed between adjacent bit line structures and directly contacting the substrate; a plurality of first isolation structures disposed between adjacent first connection pad structures to isolate the adjacent first connection pad structures from each other; a second connection pad structure disposed between adjacent bit line structures and directly contacting the substrate; a second isolation structure comprising a bottom portion and two opposite side surfaces, the bottom portion and the side surfaces are located within the second connection pad structure, and a top surface of the second isolation structure is at a same level as a top surface of the second connection pad structure.

8. A semiconductor device, characterized by comprising: comprising: a substrate; a plurality of bit line structures disposed on the substrate in a spaced-apart manner; a plurality of first connection pad structures disposed between adjacent bit line structures and directly contacting the substrate; a plurality of first isolation structures disposed between adjacent first connection pad structures to isolate the adjacent first connection pad structures from each other; a second connection pad structure disposed between adjacent bit line structures and directly contacting the substrate; a second isolation structure located within the second connection pad structure, and a topmost point of the second isolation structure in a vertical direction is not lower than a topmost point of the second connection pad structure in the vertical direction.

9. A semiconductor device, characterized by comprising: comprising: a substrate; a plurality of bit line structures disposed on the substrate in a spaced-apart manner; a plurality of first connection pad structures disposed between adjacent bit line structures and directly contacting the substrate; a plurality of first isolation structures disposed between adjacent first connection pad structures to isolate the adjacent first connection pad structures from each other; a second connection pad structure disposed between adjacent bit line structures and directly contacting the substrate; a second isolation structure comprising a bottom portion and two opposite side surfaces, the bottom portion and the side surfaces are located within the second connection pad structure, and a topmost point of the second isolation structure in a vertical direction is not lower than a topmost point of the second connection pad structure in the vertical direction.

10. A semiconductor device, characterized by comprising: comprising: a substrate; a plurality of bit line structures disposed on the substrate in a spaced-apart manner; a plurality of first connection pad structures disposed between adjacent bit line structures and directly contacting the substrate; a plurality of first isolation structures disposed between adjacent first connection pad structures to isolate the adjacent first connection pad structures from each other; A second connection pad structure is disposed between adjacent bit line structures and includes a second upper half and a second lower half connected to each other, the second lower half is in direct contact with the substrate, and the second upper half is partially above the bit line structure. A second isolation structure includes a bottom and two opposite side surfaces, the bottom and the side surfaces are both located in the second upper half, and the lowest point of the second isolation structure in the vertical direction is higher than the highest point of the second lower half in the vertical direction.

11. A semiconductor device, characterized by comprising: Comprise: a substrate; a plurality of bit line structures are disposed on the substrate in a spaced manner, including a metal layer and a cap layer stacked in turn from bottom to top; a plurality of first connection pad structures are disposed between adjacent bit line structures and in direct contact with the substrate; a plurality of first isolation structures are disposed between adjacent first connection pad structures to isolate adjacent first connection pad structures from each other; a second connection pad structure is disposed between adjacent bit line structures and includes a second upper half and a second lower half connected to each other, the second lower half is in direct contact with the substrate, and the second upper half is partially above the bit line structure; a second isolation structure includes a bottom and two opposite side surfaces, the bottom and the side surfaces are both located in the second upper half, and the lowest point of the second isolation structure in the vertical direction is higher than the highest point of the second lower half in the vertical direction.

12. The semiconductor device according to any one of claims 1 to 11, wherein The bit line structure includes a metal layer and a cap layer stacked in turn from bottom to top, and the first isolation structure is in direct contact with the cap layer.

13. The semiconductor device according to any one of claims 1 to 9, wherein The second connection pad structure includes a second upper half and a second lower half connected to each other, the second lower half is in direct contact with the substrate, and the second upper half is partially above the bit line structure, wherein the lowest point of the second isolation structure is higher than the highest point of the second lower half.

14. The semiconductor device according to any one of claims 1 to 11, wherein The first interval between adjacent first isolation structures is smaller than the second interval between adjacent first isolation structures and second isolation structures.

15. The semiconductor device according to any one of claims 1 to 11, wherein The width of the first connection pad structure in the horizontal direction is smaller than the width of the second connection pad structure in the horizontal direction.

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