Artificial synapse transistor based on thermal field regulation and manufacturing method thereof

Abstract

The application relates to the research and application field of semiconductor devices, in particular to an artificial synapse transistor based on thermal field regulation and a manufacturing method thereof. The artificial synapse transistor comprises a substrate, a carbon nanotube channel, a gate dielectric layer, a gate electrode and source-drain electrodes in contact with the carbon nanotube channel; the substrate is a silicon dioxide / heavily doped P-type silicon wafer / silicon dioxide laminated structure from bottom to top; the transistor channel is an irregular single-walled carbon nanotube layer obtained by water bath heating deposition; the gate dielectric layer is a hafnium oxide layer obtained by atomic layer deposition; and the gate electrode and the source-drain electrodes are a titanium / gold laminated composite structure from bottom to top. The application utilizes temperature regulation to regulate the charge trap state at the carbon nanotube channel and the top dielectric interface, realizes the gradual control of the device conductance polymorphism, and further realizes the effective regulation of the synapse weight.

Description

Technical Field

[0001] This invention relates to the field of research and development and application of semiconductor devices, specifically to an artificial synaptic transistor based on thermal field modulation and its fabrication method, which is applicable to neuromorphic chips, biosensors, programmable logic devices, etc. Background Technology

[0002] The explosive growth of data in the information age poses a severe challenge to traditional von Neumann computing architectures, especially when processing massive amounts of unstructured data, where energy efficiency and speed bottlenecks are becoming increasingly prominent. Inspired by the efficient information processing mechanisms of the biological brain, neuromorphic computing, by constructing artificial networks that simulate biological neurons and synapses, exhibits powerful parallel processing, adaptive learning capabilities, and high fault tolerance, providing a promising approach to overcoming computational bottlenecks. In this system, the plasticity of artificial synapses—that is, the ability to adjust connection strength, such as long-term enhancement (LTP) and long-term inhibition (LTD)—is the cornerstone of learning and memory functions. Therefore, developing high-performance artificial synaptic devices is crucial.

[0003] Artificial synapses based on reconfigurable transistors possess the ability to dynamically control electrical properties such as polarity and threshold, providing an effective way to achieve synaptic plasticity and potentially improving system energy efficiency and integration through multifunctional single-device design. To achieve this goal, researchers have explored various physical mechanisms to dynamically control device conductance. Electric field manipulation is one of the most commonly used strategies. Floating-gate transistors simulate weights by changing the floating gate charge through tunneling or hot electron injection, but they typically face challenges such as high programming voltage, slow speed, and reliability. Ferroelectric field-effect transistors utilize the residual polarization of ferroelectric materials to control the channel, but their durability is limited by the ferroelectric domain flipping speed and fatigue effects. Electrolyte-gate transistors utilize the double-layer effect to achieve strong electrostatic doping at low voltages, but their response speed is limited by slow ion migration, and long-term stability and electrolyte compatibility remain potential issues. Besides electric fields, other mechanisms have been extensively explored. Chemical doping schemes introduce / remove dopants through electrochemical reactions to modulate conductivity, achieving non-volatility, but are slow and difficult to precisely control doping distribution. Devices based on phase change materials utilize the significant resistance difference between crystalline and amorphous states to store weights; however, phase change processes typically require high energy triggering, leading to high power consumption and potential material fatigue and phase separation issues, affecting cycle stability. Although these diverse schemes have made significant progress in simulating synaptic functions, they generally have inherent limitations in power consumption, speed, accuracy, stability, or combinations of these factors. More importantly, these studies often pay less attention to the compatibility of devices with biological systems, such as high operating voltages, potential chemical toxicity, or the biosafety risks of the materials themselves, which greatly limits their practical potential in neuromorphic applications that require direct interaction with the biological environment.

[0004] Patent CN113659078A discloses a synaptic transistor device based on a novel polyimide gate insulating layer and its fabrication method. However, this device relies on an electric field to control the interface between the gate insulating layer and the semiconductor layer, lacking thermal field control mechanisms. Therefore, it cannot simulate the temperature-dependent synaptic plasticity of biological nervous systems, and its temperature adaptability is limited to room temperature environments. Furthermore, the semiconductor layer uses organic polymers such as poly(3-hexylthiophene), whose carrier mobility is much lower than that of carbon nanotubes, resulting in limited device response speed and on / off ratio. Additionally, organic polymer materials lack biocompatibility, failing to meet the requirements for applications involving interaction with the biological environment, such as neural interfaces. The patent with publication number CN119584756A proposes a thermoelectrically driven fiber-based organic electrochemical synaptic transistor, its preparation method and application. Since it does not utilize the thermal field to regulate the conductivity or synaptic function of the device, it still relies on a single electric field for regulation. The material system uses composite fibers and ion gel electrolyte. The ion gel has poor stability and is prone to failure after long-term use. In addition, it lacks a temperature-sensitive charge trapping layer formed by HfO2, etc., and cannot achieve temperature-driven charge trapping / detrapping regulation and reversible polarity conversion of the device.

[0005] To overcome the aforementioned limitations, exploring novel materials and regulatory mechanisms is imperative. Single-walled carbon nanotubes (CNTs), with their unique one-dimensional structure, high carrier mobility, excellent electrostatic control capabilities, high environmental sensitivity, and potential biocompatibility, have become an ideal choice for constructing artificial synapses. Meanwhile, temperature regulation, as an emerging and bio-inspired approach, is attracting attention. Temperature not only profoundly affects semiconductor performance but also regulates key processes such as neurotransmitter release and receptor binding in biological nervous systems. Therefore, utilizing temperature-regulated artificial synapses holds promise for achieving more bio-adaptive neuromorphic hardware that more closely approximates biological thermodynamic response mechanisms and may enable multi-physics synergistic regulation with electricity and light, expanding device functionality. Summary of the Invention

[0006] The purpose of this invention is to propose an artificial synaptic transistor based on thermal field control and its fabrication method. By using temperature to control the charge trap state at the interface between the channel and the top dielectric of the carbon nanotube, the device's conductance can be controlled in a progressive manner, thereby achieving effective adjustment of synaptic weights.

[0007] The technical solution of the present invention: An artificial synaptic transistor based on thermal field modulation is disclosed. The transistor comprises a substrate, a carbon nanotube channel, a gate dielectric layer, a gate electrode, and source / drain electrodes in contact with the carbon nanotube channel. The overall structure is a bottom-up stacked composite structure of silicon dioxide / heavily doped P-type silicon wafer / silicon dioxide / titanium / gold / semiconductor carbon nanotube / hafnium oxide / titanium / gold. Specifically, the substrate is a bottom-up stacked structure of silicon dioxide / heavily doped P-type silicon wafer / silicon dioxide; the transistor channel is a random single-walled carbon nanotube layer deposited using water bath heating; the gate dielectric layer is a hafnium oxide layer deposited atomically; and the gate electrode and source / drain electrodes are bottom-up titanium / gold stacked composite structures. A layer of non-stoichiometric oxide (HfO) is sandwiched between the top of the carbon nanotube channel and the middle of the hafnium oxide layer. x x = 2~10.

[0008] The aforementioned thermally modulated artificial synaptic transistor uses a hafnium oxide layer, obtained by atomic layer deposition, to dope the carbon nanotube channel, thereby achieving a charge trapping state at the interface between the thermally modulated channel and the top dielectric layer. A thermoelectric device is mounted under the substrate using a phase-change thermally conductive material, connecting the thermoelectric device to the carbon nanotube field-effect transistor. The thermoelectric device is connected to an external DC power supply. The temperature of the carbon nanotube field-effect transistor is controlled based on the Peltier effect. Temperature changes significantly affect the rate and equilibrium state of charge trapping and release at the interface. Combined with the electric field activation effect of the gate voltage, the number of trapped charges can be non-volatilely changed, effectively controlling the carrier concentration and conductivity of the carbon nanotube channel. This achieves multi-state, progressive control of the device's conductance and simulates an artificial synapse.

[0009] A method for fabricating an artificial synaptic transistor based on thermal field modulation includes the following steps: (1) The substrate is ultrasonically cleaned with acetone and isopropanol in sequence to remove surface impurities, and then further removed by oxygen plasma cleaning machine to remove surface residues; (2) Photolithography is used to precisely form a photoresist mask layer on the substrate. The maximum effective range of the mask layer is a 2×2cm exposure area. The required source and drain electrode areas are exposed on the substrate. The titanium / gold stacked metal electrode is prepared in the designated area by vacuum electron beam evaporation technology to construct the source and drain electrodes of the transistor. (3) Use oxygen plasma cleaning technology to remove residues on the surface of the silicon wafer and the source / drain electrode surfaces; (4) After uniformly spin-coating Primer onto the substrate, immerse it in a carbon nanotube solution that has been ultrasonically dispersed, and deposit carbon nanotubes on the substrate to form a transistor channel layer by water bath heating. (5) First, a photoresist mask layer is precisely constructed on the substrate on which carbon nanotube channels have been deposited by photolithography to pattern the carbon nanotube channel area; then, the carbon nanotubes outside the channel are etched by oxygen plasma cleaning technology to effectively remove excess carbon nanotube film. (6) Using atomic layer deposition technology, a hafnium oxide dielectric layer is uniformly deposited on the carbon nanotube channel. Hafnium oxide is used to dope the carbon nanotube channel, forming an interface doped layer that can be controlled by the thermal field. (7) Using photolithography, the required gate electrode deposition area is exposed on the hafnium oxide dielectric layer. The titanium / gold gate electrode that is in close contact with the hafnium oxide dielectric layer is prepared by vacuum electron beam evaporation technology. (8) Photolithography is used to fabricate a photoresist mask layer, expose the required hafnium oxide etching area, and expose the titanium / gold source and drain metal electrodes that are in contact with the carbon nanotube channel and the substrate. Previously, reactive ion etching technology was used with carbon tetrafluoride as the reactive gas to precisely etch hafnium oxide, and finally a carbon nanotube field effect transistor array with a complete structure was obtained. (9) Construct a thermoelectric device compatible with carbon nanotube field effect transistors. Spray acetone and isopropanol onto the surface of the thermoelectric device to remove surface impurities. Then, attach a phase change thermal conductive material to the upper surface of the thermoelectric device and attach the transistor substrate tightly to the surface of the phase change thermal conductive material. By applying an external DC power supply, the surface temperature of the thermoelectric device can be precisely controlled, thereby flexibly adjusting the operating temperature of the transistor.

[0010] In the method for fabricating the artificial synaptic transistor based on thermal field control, in steps (2) and (7), the source and drain electrodes at both ends and the top gate electrode are deposited using an electron beam evaporator. The thickness of the titanium layer ranges from 5 to 6 nm, and the thickness of the gold layer ranges from 50 to 51 nm.

[0011] In the method for fabricating artificial synaptic transistors based on thermal field control, step (3) involves oxygen plasma cleaning for 20 min, oxygen flow rate of 180 sccm, and power of 200 W.

[0012] In the method for fabricating artificial synaptic transistors based on thermal field regulation, in step (4), carbon nanotubes and toluene are mixed in a mass ratio of 1:8, and carbon nanotube bundles and insoluble substances are removed by ultrasonic dispersion and centrifugation to obtain a semiconductor carbon nanotube solution. The supernatant is collected as a channel material, and the carbon nanotube solution is subjected to ultrasonic treatment at a frequency of 40 Hz, a power of 100 W, and a time of 5 min. The carbon nanotube solution after ultrasonic vibration dispersion is transferred to a petri dish. In the process of carbon nanotube film deposition, the cleaned substrate was first heated to 180 ℃ on a hot plate for 30 min to remove moisture. To better adsorb the carbon nanotubes onto the substrate and disperse them evenly, a primer was spin-coated onto the surface of the substrate using a spin coater, and then the substrate was placed on a hot plate at 105 ℃ for 2 min. The baked substrate was then immersed in a culture dish containing a carbon nanotube solution dispersed by ultrasonic vibration, and the culture dish was placed in a 60 ℃ water bath, where the level of deionized water was just above the level of the carbon nanotube solution in the culture dish. The carbon nanotube film deposition was completed after 2-3 hours.

[0013] In the method for fabricating artificial synaptic transistors based on thermal field control, in step (5), LOR3A and S-1813 double-layer photoresist are spin-coated sequentially on the surface of the carbon nanotube film using a spin coater, and the exposed pattern is a square area with a side length of 180~182 μm; the exposed sample is placed in an oxygen plasma cleaner with an oxygen flow rate of 180 sccm and a power of 200 W for 2 min to remove excess carbon nanotube film outside the channel.

[0014] In the method for fabricating an artificial synaptic transistor based on thermal field control, step (6) involves using an atomic layer deposition (ALD) device at a temperature of 200 °C to prepare a 40 nm hafnium oxide dielectric layer on top of a carbon nanotube film. For the precursor selection, tetrakis(dimethylamino)hafnium is chosen as the hafnium precursor, and water is chosen as the oxygen source precursor. The deposition process parameters include temperature setting, gas flow rate, and pulse time setting. Regarding temperature, the temperatures of the hafnium precursor and the substrate are key parameters, and the deposition temperature is 200 °C. The gas flow rate needs to be precisely controlled, and the pulse time refers to the residence time of the precursor gas in the reaction chamber. The deposition cycle begins with the introduction of hafnium precursor gas, followed by carrier gas purging after adsorption. Then, oxygen source precursor gas is introduced, and after the reaction, carrier gas purging is performed again. Repeating these steps constitutes one ALD cycle, with each cycle depositing a 0.05~0.2 nm hafnium oxide film. The film thickness is precisely controlled by controlling the number of cycles. The reaction temperature is set to 200 °C. At ℃, the flow rate of hafnium precursor was 30 sccm, the flow rate of water vapor was 150 sccm, and the flow rate of nitrogen as carrier gas was 100 sccm. In each cycle, the pulse time of hafnium precursor was 0.5 seconds, the pulse time of water vapor was 1 second, and the purging time of carrier gas was 5 seconds. After 200~500 atomic layer deposition cycles, hafnium oxide dielectric layers with a thickness of 10~50 nm were prepared.

[0015] In the method for fabricating the artificial synaptic transistor based on thermal field control, step (8) involves etching using a reactive ion etching machine. The etching conditions are as follows: carbon tetrafluoride with a flow rate of 50 sccm is used as the etching gas, the pressure is 5.0~5.5 Pa, the power is 100 W, and the etching time is 5~10 min.

[0016] In the method for fabricating the artificial synaptic transistor based on thermal field control, in step (9), the surface of the thermoelectric device is sequentially sprayed with acetone and isopropanol for cleaning, left to stand for 1 minute, and then wiped dry with a lint-free cloth to remove surface impurities. The phase change thermal conductive material is attached to the surface of the thermoelectric device and attached to the bottom of the carbon nanotube field effect transistor substrate. The surface temperature of the thermoelectric device is controlled by an external DC power supply, with a temperature range of -25 ℃ to 120 ℃, a temperature change step accurate to 0.1 ℃, and a temperature change rate of 3.84 ℃ / s.

[0017] The design concept of this invention is: The rapid growth of data in the information age has exposed the severe limitations of traditional von Neumann computing architectures, which are inefficient in terms of speed and energy consumption when processing unstructured data such as videos or biological signals. In contrast, the human brain exhibits remarkable parallel processing, adaptive learning, and fault tolerance. Inspired by this biological efficiency, neuromorphic computing aims to mimic neurons and synapses, with plastic artificial synapses such as long-term enhancement (LTP) and long-term inhibition (LTD) enabling learning and memory functions, making its development crucial for next-generation computing.

[0018] Reconfigurable transistors (RTTs) have become an ideal platform for artificial synapses due to their ability to dynamically adjust electrical properties such as polarity and threshold voltage. Unlike traditional fixed-function devices, these transistors offer versatility within a single unit, improving energy efficiency and integration density. This adaptability supports in-memory computing and allows conductance adjustment to simulate changes in synaptic weights, directly replicating biological excitatory and inhibitory behaviors. This versatility makes RTTs a cornerstone for building efficient, brain-like systems. Despite their potential, existing RTT approaches face significant obstacles. For example, floating-gate transistors require high programming voltages, are slow, and have poor reliability. Ferroelectric field-effect transistors (FETs) reduce voltage requirements but are limited by slow domain switching speeds and material fatigue. Electrolyte-gate transistors (ECTs) utilize ion migration for low-voltage operation but suffer from insufficient response time and stability. Other methods, such as chemical doping or phase-change materials, also suffer from slow speed, high power consumption, or accuracy issues. Furthermore, these designs often neglect biocompatibility, and high voltages and toxic materials hinder their application in biosensors or neural interfaces.

[0019] Therefore, exploring novel materials and regulatory mechanisms is imperative. Temperature control offers a bio-inspired solution to these challenges, influencing semiconductor properties such as carrier mobility and conductivity, while also being linked to biological processes such as neurotransmitter regulation. Unlike electric or chemical methods, thermal regulation enables rapid, precise, and non-volatile adjustments over a wide range, avoiding high voltages or toxic substances. This approach aligns with biothermodynamics, enhancing compatibility with neuromorphic systems interacting with organisms. Single-walled carbon nanotubes (CNTs) are ideal for artificial synapses due to their one-dimensional structure, superior carrier mobility, and low interfacial defect density. Their flexibility (bendable to a radius of 3 mm) is suitable for wearable electronic devices, while their carbon-based nature ensures biocompatibility. The temperature sensitivity of CNTs further enhances their applicability in thermal regulation, enabling precise control over electrical properties.

[0020] This invention fabricates single-walled carbon nanotube channels using a solution deposition method with water bath heating, and then combines photolithography, gold evaporation, and atomic layer deposition (ALD) techniques to create hafnium oxide-doped carbon nanotube field-effect transistors (CNTFETs). To enhance the temperature sensitivity of the CNTFET, hafnium oxide (HfO2) is deposited above the CNT channel using ALD to dope the CNTs, and a temperature-sensitive charge trapping layer is constructed above the channel. This invention employs a temperature control (TEC) system to apply precise and dynamic temperature control to the device, covering a wide range from -25 °C to 120 °C. Temperature changes significantly affect the rate and equilibrium state of charge trapping and release at the interface. Combined with the electroactivation effect of the gate voltage, temperature can non-volatilely change the amount of trapped charge, thereby effectively controlling the carrier concentration and conductivity of the CNT channel. At 25 °C, the channel polarity is bipolar; while when the temperature rises to 120 °C, the channel polarity changes to N-type. Under temperature control, T-RFETs can achieve reversible switching between bipolar and N-type modes, demonstrating the advantages of multi-physical coupling control. During testing, we comprehensively characterized key artificial synapse performance parameters, including excitatory postsynaptic current, pairing pulse facilitation, peak duration-dependent plasticity, and weighting of artificial synapses under different voltage stimuli. This provides theoretical support and technical pathways for breaking through traditional computing boundaries and constructing truly brain-like intelligent systems.

[0021] This invention achieves the dynamic characteristics of a reconfigurable transistor (T-RFET) through a thermoelectric device (TEC), successfully simulating the excitation / inhibition transition of biological synapses. We designed a temperature-driven trapping / detrapping T-RFET, constructing a charge storage interface above the CNT channel, utilizing an HfO2 layer as the top gate dielectric layer, and using the defect states at the interface with the CNT as temperature-sensitive charge trapping / detrapping centers. By integrating the TEC, we achieved precise (temperature control accuracy 0.1℃) and dynamic (temperature change rate 3.84℃ / s) temperature control, covering a wide range from -25℃ to 120℃. Temperature changes significantly affect the charge trapping and release rate and equilibrium state of the interface traps. Combined with the electric field activation effect of the gate voltage, the number of trap charges is non-volatilely controlled, thereby effectively changing the carrier concentration and conductivity of the CNT channel. Experiments show that temperature regulation can reversibly switch the polarity of a Trans-RFET (between N-type and bipolar types), and through precise, stepwise temperature adjustment, achieve multi-state, gradual control of the device's conductance, successfully simulating long-term enhancement and long-term inhibition behaviors of synapses. This study, using temperature as the core control parameter, demonstrates the advantages of thermal field modulation in terms of control precision and wide temperature range. Utilizing temperature as a unique and potentially biocompatible physical field, a thermo-electric coupling modulation mechanism was constructed, providing a new paradigm for simulating synaptic plasticity and opening new avenues for developing biologically plausible multi-physics-controlled neuromorphic devices and constructing flexible, environmentally adaptable neuromorphic computing systems.

[0022] The advantages and beneficial effects of this invention are: 1. This invention relates to a thermally modulated artificial synaptic transistor, using a carbon nanotube field-effect transistor (CNTFET) as the core device carrier. By integrating thermoelectric devices and constructing a temperature-sensitive charge trap layer, the CNTFET is endowed with the ability to simulate the plasticity of biological synapses, ultimately forming a thermally modulated artificial synaptic transistor. Utilizing the high carrier mobility, significant on / off ratio, and obvious polarity transition characteristics of thermally reconfigurable CNTFETs, temperature-controlled artificial synaptic performance is achieved. Temperature regulation of the transistor via thermoelectric devices efficiently, conveniently, quickly, and controllably realizes the reversible polarity transition of the CNTFET. This enables temperature-controlled adjustment of the artificial synaptic EPSC (excitatory postsynaptic current), PPF (pairing pulse facilitation), SDDP (spiking duration-dependent plasticity), SADP (spiking peak value-dependent plasticity), and synaptic weight adjustment at different temperatures, ensuring the stability of the device testing process. This provides theoretical support and a technical path for breaking the boundaries of traditional computing and constructing truly brain-like intelligent systems.

[0023] 2. The artificial synaptic transistor based on thermal field control involved in this invention uses a water bath heating method to deposit carbon nanotube solutions to obtain carbon nanotube channels. The preparation process is simple, effective, clean and non-destructive, ensuring the uniformity of device performance.

[0024] 3. The artificial synaptic transistor based on thermal field control involved in this invention utilizes atomic layer deposition technology to grow a 40nm hafnium oxide dielectric layer to achieve oxygen vacancy thermal doping of the carbon nanotube channel, thereby constructing a temperature-sensitive charge trap layer. This enables the polarity switching of the carbon nanotube field-effect transistor under temperature control. The process is simple and effective, ensuring that the device has high carrier mobility and polarity switching performance.

[0025] 4. This invention proposes an artificial synaptic transistor based on thermal field modulation, innovatively employing miniaturized thermoelectric devices to achieve dynamic temperature control. The evolution of the electrical characteristics of CNTFETs over a wide temperature range (-20℃ to 120℃) was systematically studied. For the first time, the experiment captured the bipolar / N-type polarity switchability phenomenon exhibited by the device within a temperature variation range of 20℃ to 70℃, and a temperature-electrical parameter mapping model was constructed. Through the synergistic effect of in-situ thermoelectric cooling / heating dual modes, efficient, convenient, rapid, and controllable control of temperature on the artificial synapse EPSC, PPF, SDDP, SADP, and synaptic weight adjustment at different temperatures was achieved, providing a physical basis for the time-varying characteristic modulation of CNTFETs. This breakthrough not only promotes the progress of neuromorphic devices in terms of dynamic environmental adaptability but also opens up new paths for developing intelligent transistors with temperature self-sensing capabilities, demonstrating significant application value in the fields of thermal management of neuromorphic chips, programmable logic devices, and biosensing. Attached Figure Description

[0026] Figure 1 Image a is a three-dimensional structural schematic diagram of the artificial synaptic transistor device based on thermal field modulation according to the present invention; image b is a schematic diagram of the thermal field modulation mechanism. The artificial synaptic device is composed of a carbon nanotube transistor with a top-gate structure, and the dielectric layer is a 30 nm thick hafnium oxide layer.

[0027] Figure 2 This is a schematic diagram of the front structure of the thermally modulated artificial synaptic transistor involved in this invention. In the figure, the bottom layer is a silicon dioxide (SiO2) layer, above which is a heavily doped silicon (P2O3) layer. + A Si substrate is used. On top of this substrate, carbon nanotubes connect the source (S) and drain (D), serving as the channel material for the transistor. The source and drain are made of metallic materials to inject and collect charge carriers into the carbon nanotube channel. The carbon nanotubes are covered with a non-stoichiometric oxide (NDO, i.e., a hafnium oxide layer, HfO). x(x=2~10)), which plays a role in interface regulation. Above the NDO layer is the gate (G), and the conductivity of the carbon nanotube channel is adjusted by controlling the gate voltage. The entire structure shows the temperature-sensitive charge trap layer built above the carbon nanotube channel, as well as the layout of the gate, source, and drain electrodes.

[0028] Figure 3 This is a schematic diagram of an optical microscope of the thermally modulated artificial synaptic transistor device involved in this invention. In the figure, the transistor source and drain are Ti / Au, the gate is Ti / Au, the channel is carbon nanotubes (CNTs), the gate oxide is HfO2, and a layer of non-stoichiometric oxide HfO is sandwiched between the top of the channel CNT and the gate oxide HfO2. x (x=2~10).

[0029] Figure 4 This invention relates to a theoretical band structure diagram of hafnium oxide-doped carbon nanotubes (HfO) for thermally modulated artificial synaptic transistors. The diagram shows the band structure schematics of the N-type doped carbon nanotube field-effect transistor (CNTFET) at room temperature and high temperature. The diagram contains two main parts: the left side is HfO... x The interface between HfO and carbon nanotubes (CNTs) is shown, with the band structure on the right. The left side shows HfO. x Oxygen vacancies in the layer, and the electrons released by these vacancies. HfO x The layer is connected to the carbon nanotubes. The band structure diagram to the right of the Au electrode below shows the band structure of the carbon nanotubes (CNTs) and the Au electrode. The conduction band (E) is marked in the diagram. c ), price band (E) v ), Fermi level (E F The valence band position of carbon nanotubes changes at high temperatures compared to room temperature. The dashed lines represent defect energy levels after doping. The overall structure is used to illustrate the band structure changes of an N-type doped CNTFET at different temperatures. Electrons released from oxygen vacancies affect the Fermi level and barrier height of the carbon nanotubes, thus influencing transistor performance.

[0030] Figure 5 This is a Raman spectrum of the hafnium oxide-coated carbon nanotube channel region in the transistor of the present invention. In the figure, the curves represent the Raman spectral changes of the carbon nanotube field-effect transistor during temperature control from -25 °C to 120 °C. The horizontal axis, Raman Shift, represents the Raman frequency shift (cm). -1 The vertical axis Intensity represents the relative intensity (au) of the scattered light, and the D peak, G peak and 2D peak correspond to the characteristic peaks of carbon nanotubes.

[0031] Figure 6 This is a current-time diagram of the EPSC (excitatory postsynaptic current) of the thermally modulated artificial synaptic transistor device involved in this invention. In the figure, the vertical axis represents the source-drain current of the transistor, with Current on the vertical axis. I DS (A), where the horizontal axis Time (s) represents the pulse duration.

[0032] Figure 7 This is a PPF (Pulse-Promoted Pulse) current-time diagram of the thermally modulated artificial synaptic transistor device involved in this invention. In the figure, the vertical axis represents the source-drain current of the transistor, Current. I DS (A), where the horizontal axis Time (s) represents the pulse duration.

[0033] Figure 8 This invention relates to the PPF (Paired Pulse Facilitation) / Electrical Pulse Amplitude-Temperature curves of the thermally modulated artificial synaptic transistor device. In the figure, the vertical axis represents the PPF index (%), which is the paired pulse facilitation index, and the horizontal axis represents the temperature state (°C).

[0034] Figure 9 This invention relates to the SDDP (spiking duration-dependent plasticity) / electrical pulse period-temperature curves of the thermally modulated artificial synaptic transistor device. In the figure, the vertical axis SDDP index (%) represents the spike duration-dependent plasticity index, and the horizontal axis Temperature (°C) represents the temperature state.

[0035] Figure 10 This invention relates to the PPF (pairing pulse facilitator) / electrical pulse amplitude-temperature curves of the thermally modulated artificial synaptic transistor device. In the figure, the vertical axis represents the PPF index (%), which is the pairing pulse facilitator index, and the horizontal axis represents the temperature state (°C).

[0036] Figure 11 This invention relates to the SADP (Peak-to-Peak Depth Dependence Plasticity) / Electrical Pulse Amplitude-Temperature curves of the thermally modulated artificial synaptic transistor device. In the figure, the vertical axis represents the SADP index (%), which is the peak-to-peak dependence plasticity index, and the horizontal axis represents the temperature state (°C).

[0037] Figure 12The invention relates to an artificial synapse based on a thermally reconfigurable transistor, and demonstrates the strong dependence of the synaptic weight change on the polarity of the stimulation pulse under electrical pulse stimulation at different operating temperatures and with different pulse amplitudes, proving the feasibility of backpropagation in artificial synaptic devices. In the figure, the vertical axis represents the source-drain current. I DS (A), where the horizontal axis represents Time (s), indicating the pulse period applied to the transistor. Detailed Implementation

[0038] In its specific implementation, this invention proposes for the first time an artificial synaptic transistor device based on thermal field modulation. A carbon nanotube field-effect transistor was fabricated at room temperature. A 40 nm hafnium oxide dielectric layer was deposited using atomic layer deposition (ALD) technology, and the carbon nanotube channel material was doped to construct a temperature-sensitive CNT / HfO transistor. x A charge-trapping layer was constructed, enabling high-performance and efficient field-effect gate voltage regulation and temperature control of the oxygen-vacancy-doped carbon nanotube channel. Reversible polarity transitions were observed within different temperature ranges. Weight adjustment of the oxygen-vacancy-doped CNTFET-based artificial synaptic device was systematically studied, and performance parameters such as EPSC, PPF, SDDP, and SADP of the artificial synaptic device under different temperature conditions were obtained. The performance regulation method of the artificial synaptic device based on thermally reconfigurable carbon nanotube field-effect transistors can effectively characterize the impact of environmental temperature changes on the performance of the artificial synaptic device, simulating the biological response to environmental temperature changes, thereby improving the stability and reliability of specific device performance. The realization of the thermally reconfigurable carbon nanotube field-effect transistor-based artificial synaptic device not only promotes the progress of neuromorphic devices in dynamic environmental adaptability but also opens up new paths for developing intelligent transistors with temperature self-sensing capabilities, demonstrating significant application value in the fields of thermal management of neuromorphic chips, programmable logic devices, and biosensing.

[0039] The present invention will now be further described in detail with reference to embodiments and accompanying drawings. Example

[0040] In this embodiment, the artificial synaptic transistor device based on thermal field modulation and its fabrication method are as follows: like Figure 1 , Figure 2 As shown, this CNTFET adopts a vertically stacked heterostructure, specifically from bottom to top as follows: 300 nm silicon dioxide layer / 300 μm heavily doped boron (P + Type, doping concentration 10 19 ~10 21The design employs a sandwich structure consisting of a silicon substrate (atoms / cm³) and a 300 nm silicon dioxide layer. This design leverages the double-layer passivation properties of silicon dioxide to effectively isolate charge interference between the silicon substrate and the functional layers, while the heavily doped silicon can serve as the back gate electrode. The source and drain electrodes are composite metal electrodes consisting of a 5 nm titanium (Ti) adhesion layer and a 50 nm gold (Au) conductive layer. The titanium layer reduces contact resistance by enhancing the metal-semiconductor interface bonding, while the gold layer provides high conductivity. The channel layer is a solution-deposited single-walled carbon nanotube (SWCNT) network film (3–6 nm thick). High-quality arc-discharge carbon nanotubes (1.55 ± 0.1 nm in diameter) from Carbon Solution Inc. have a bandgap of approximately 1 eV. The gate dielectric layer is a 40 nm hafnium oxide (HfO₂) thin film grown by atomic layer deposition, and the top gate electrode is a 5 nm Ti / 50 nm Au stacked electrode.

[0041] The manufacturing process is as follows: The first step is a substrate pretreatment and cleaning process, which involves a three-step process: acetone (40 kHz ultrasound, 100 W, 5 min), isopropanol (40 kHz ultrasound, 100 W, 5 min), and oxygen plasma (O2 flow rate 180 sccm, 200 W, 10 min) to remove organic residues and surface oxide layers.

[0042] The second step involves fabricating source / drain metal electrodes onto the target substrate. Photolithography patterning is performed using S1813 positive resist (spin-coated to a thickness of 1.5 μm) combined with UV lithography to form a 2×2 cm substrate. 2 Effective exposure area. Titanium / gold electrodes at the source and drain are deposited by electron beam evaporation of Ti / Au (substrate temperature 50°C).

[0043] The third step involves carbon nanotube channel deposition. High-quality arc-discharge carbon nanotubes from Carbon Solution Inc. were selected for their concentrated diameter distribution, with a peak diameter of 1.55 ± 0.1 nm and a bundle length of 1–5 μm. First, bulk carbon nanotubes were mixed with toluene at a mass ratio of 1:8. The mixture was then ultrasonically dispersed (30 min) and centrifuged (45000 g, 1 h) to remove carbon nanotube bundles and insoluble substances, yielding a semiconductor single-walled carbon nanotube solution with a purity higher than 99.9 wt%. The supernatant was collected as the channel material. Next, the carbon nanotube solution was ultrasonically treated at a frequency of 40 Hz and a power of 100 W. The ultrasonically dispersed carbon nanotube solution was then transferred to a petri dish.

[0044] In the deposition of carbon nanotube films, the cleaned silicon substrate was first heated to 180°C on a hot plate for 30 minutes to remove moisture. To ensure better adsorption and uniform dispersion of single-walled carbon nanotubes on the substrate, a precursor primer (MCC-Primer, Micro Chem Corporation Primer, as a base coat) was spin-coated onto the substrate surface using a spin coater. The substrate was then baked at 105°C for 2 minutes on a hot plate. The baked substrate was then immersed in a culture dish containing an ultrasonically dispersed carbon nanotube solution. The culture dish was placed in a 60°C water bath, with the level of deionized water in the water bath just exceeding the level of the carbon nanotube solution in the culture dish. After two and a half hours, the deposition of single-walled carbon nanotubes was completed, forming a carbon nanotube film.

[0045] The fourth step is patterning etching. LOR3A and S-1813 double-layer photoresist are spin-coated sequentially on the surface of the carbon nanotube film using a spin coater. The exposed pattern is a square area with a side length of 180~182 μm. The exposed sample is then placed in an oxygen plasma cleaner with an oxygen flow rate of 180 sccm and a power of 200 W for 2 min to remove excess carbon nanotube film exposed outside the source and drain metal electrodes.

[0046] The fifth step involves integrating the gate dielectric layer with the top gate, using ALD to grow HfO2 with C8H 24 Using HfN4 precursor and H2O as the reaction source, a dense 40 nm thin film was obtained by cycling at 200 °C for 500 cycles (0.08 nm thickness per cycle). The top gate electrode was then fabricated using a source-drain process.

[0047] The sixth step involves fabricating a photoresist mask layer using reactive ion etching and photolithography. The maximum effective area of ​​the mask is 2 × 2 cm. 2 The exposure area exposes the required hafnium oxide etching region, revealing the titanium / gold source / drain metal electrodes in contact with the carbon nanotube channels and the substrate. The patterned hafnium oxide is etched using carbon tetrafluoride, exposing the source / drain electrodes to air to obtain a carbon nanotube field-effect transistor array. The etching conditions are as follows: reactive ion etching (RIE) is used, with carbon tetrafluoride at a flow rate of 50 sccm as the etching gas, a pressure of 5.0–5.5 Pa, a power of 100 W, and an etching time of 5 min 30 s.

[0048] In the carbon nanotube field-effect transistor, the substrate is composed of silicon dioxide / heavily doped silicon wafer / silicon dioxide from bottom to top. The source / drain electrodes and gate electrodes are composed of titanium / gold stacked composite structures from bottom to top. The channel is composed of solution-deposited single-walled carbon nanotubes. The dielectric layer between the gate electrode and the channel is hafnium oxide. The overall structure is a stacked composite structure of silicon dioxide / silicon / silicon dioxide / titanium / gold / semiconductor carbon nanotubes / hafnium oxide / titanium / gold from bottom to top. The thicknesses are, in descending order: 300 nm / 300 μm / 300 nm / 5 nm / 50 nm / 3~6 nm / 30 nm / 5 nm / 50 nm. The growth temperature of the hafnium oxide dielectric layer is 200 ℃.

[0049] The above describes the fabrication process of carbon nanotube field-effect transistors, which in turn constitutes... Figure 1 The device structure shown has a bottom substrate composed of silicon dioxide (SiO2) / P-type doped silicon (Si) / silicon dioxide (SiO2) from bottom to top. First, titanium (Ti) / gold (Au) electrodes, serving as the source and drain, are deposited on top of the silicon substrate using electron beam evaporation. Carbon nanotubes (CNTs) in contact with the electrodes and the silicon substrate serve as the device channel. Hafnium oxide (HfO2) is grown above the carbon nanotube channel as a dielectric layer, and titanium (Ti) / gold (Au) electrodes are deposited on top of the dielectric layer as the device's gate electrodes.

[0050] like Figure 2 The image shows a schematic diagram of the two-dimensional structure of a carbon nanotube field-effect transistor (CFET) fabricated by atomic layer deposition of a hafnium oxide dielectric layer doped with carbon nanotube channels. This CFET primarily employs a vertically stacked structure and mainly comprises the following functional layers: Carbon nanotube channel: Single-walled carbon nanotubes serve as conductive channels, with a diameter of approximately 1–2 nm. HfO x Hafnium oxide dielectric layer: A high-dielectric-constant oxide with a thickness of approximately 5-10 nm, uniformly coated onto the CNT surface via atomic layer deposition (ALD) to form the gate dielectric layer. Au electrode system: Symmetrical gold electrodes are used for the source (S) and drain (D), forming ohmic contacts with the CNTs through van der Waals forces to ensure efficient carrier injection. Oxygen vacancy distribution: In HfO x Oxygen vacancies are enriched at the / CNT interface, serving as active sites for charge transfer.

[0051] In specific experiments, HfO x The / CNT layer primarily performs the following functions: Hafnium oxide dielectric modulation: High dielectric properties enable HfO... x Achieving a stronger gate electric field with the same physical thickness effectively shields interface scattering and improves transconductance (g). m CNT bandgap engineering: Undoped CNTs are typical P-type semiconductors (hole-dominated), but oxygen vacancy doping can raise the Fermi level (E).F Guide belt (E) c ) Move to achieve N-type conversion. Defect-carrier coupling: Oxygen vacancies act as localized state traps, releasing electrons to the CNT conduction band through thermal excitation or electric field action, forming a non-equilibrium carrier concentration gradient. In this embodiment, the artificial synaptic transistor device based on thermal field control and its fabrication method include the following steps: (1)~(8) are the specific fabrication process flow of hafnium oxide-doped carbon nanotube field-effect transistors. (9) is the detail of the specific temperature control scheme of carbon nanotube field-effect transistors through thermoelectric devices.

[0052] (1) In this embodiment, acetone and isopropanol are used to clean the device in the entire ultrasonic cleaning process. The ultrasonic frequency is set to 40 Hz and the power is 100W for each cleaning, and the cleaning time for each solvent is 10 min. In the oxygen plasma cleaning step, the cleaning time is set to 10 min, the oxygen flow rate is controlled at 180 sccm, and the power is maintained at 200 W. (2) In this embodiment, photolithography is used to prepare the source and drain electrodes. A photoresist mask layer is precisely formed on the substrate. The maximum effective area of ​​the mask layer is a 2×2cm exposure area. The required source and drain electrode deposition area is exposed on the substrate. A titanium / gold multilayer metal electrode is prepared in the designated area by vacuum electron beam evaporation technology to construct the source and drain electrodes of the transistor. The deposition thickness of the Ti layer is set in the range of 5~6 nm, and the deposition thickness of the Au layer is controlled between 50~51 nm. (3) In this embodiment, oxygen plasma etching technology is used. The oxygen plasma cleaning time is 20 min, the oxygen flow rate is 180 sccm, and the power is 200 W to remove the residues on the surface of the Si wafer and the source and drain electrodes. (4) In this embodiment, carbon nanotubes and toluene were mixed in a mass ratio of 1:8, and then purified by ultrasonic dispersion and centrifugation to remove carbon nanotube bundles and insoluble impurities, resulting in a semiconducting carbon nanotube solution. The supernatant was used as the channel material. Next, the carbon nanotube solution was ultrasonically treated at a frequency of 40 Hz and a power of 100 W for 5 min. The ultrasonically dispersed solution was then transferred to a petri dish for later use.

[0053] In the carbon nanotube thin film deposition process, the cleaned silicon substrate was first placed on a hot plate and baked at 180 °C for 30 min to remove moisture. To enhance the adsorption and dispersion uniformity of carbon nanotubes on the substrate, a primer was spin-coated onto the substrate surface using a spin coater, and then baked on a hot plate at 105 °C for 2 min. Afterward, the baked silicon substrate was immersed in a petri dish containing an ultrasonically dispersed carbon nanotube solution, and the petri dish was placed in a 60 °C water bath, with the level of deionized water slightly higher than the solution level in the petri dish. After two and a half hours, the carbon nanotubes were deposited, forming a thin film. (5) In this embodiment, oxygen plasma cleaning technology and photolithography are used. A spin coater is used to spin coat LOR3A and S-1813 double-layer photoresist onto the surface of the carbon nanotube film. After exposure, the pattern forms a square area with a side length of 180~182 μm. This step is to pattern the carbon nanotube channel areas that need to be protected. Subsequently, using oxygen plasma cleaning technology, the exposed sample is placed in an oxygen plasma cleaner with an oxygen flow rate of 180 sccm and a power of 200 W for 2 min. The part outside the source and drain metal electrodes is finely etched to effectively remove excess carbon nanotube film that may cause interference. (6) In this embodiment, an atomic layer deposition technique was used to prepare a 40 nm hafnium oxide dielectric layer covering the carbon nanotube film at a temperature of 200 °C. For the precursor selection, the hafnium precursor was tetrakis(dimethylamino)hafnium (C8H4O3). 24 (HfN4), the oxygen source precursor can be water (H2O), and the deposition process parameters include temperature setting, gas flow rate, and pulse time setting. Regarding temperature, the temperatures of the hafnium precursor and the substrate are key parameters, and the deposition temperature range is generally around 200 °C. Gas flow rate needs precise control, and pulse time refers to the residence time of the precursor gas in the reaction chamber. The deposition cycle begins with the introduction of hafnium precursor gas, followed by adsorption and carrier gas purging. Then, oxygen source precursor gas is introduced, and after the reaction, carrier gas purging is performed again. Repeating these steps constitutes an ALD cycle, each cycle depositing approximately 0.1–0.2 nm of hafnium oxide film. The film thickness is precisely controlled by controlling the number of cycles. Tetra(dimethylamino)hafnium (C8H4) was used in the experiment. 24 HfN4 was used as the hafnium precursor, and water vapor was used as the oxygen source precursor. The reaction temperature was set at 200 °C, and tetrakis(dimethylamino)hafnium (C8H4) was reacted. 24 The flow rate of HfN4 was 30 sccm, the water vapor flow rate was 150 sccm, and the carrier gas (nitrogen) flow rate was 100 sccm. In each cycle, tetrakis(dimethylamino)hafnium (C8H) 24The pulse duration of HfN4 was 0.5 s, the pulse duration of water vapor was 1 s, and the carrier gas purging time was 5 s. After 200 ALD cycles, a 40 nm thick hafnium oxide dielectric layer was successfully prepared.

[0054] A hafnium oxide dielectric layer is uniformly coated on the carbon nanotube channel. By doping the carbon nanotube channel with hafnium oxide, an interface doping layer that can be thermally controlled is formed, which provides the basis for the subsequent thermal field-octane and also forms an insulating basis for the subsequent gate electrode fabrication. (7) In this embodiment, photolithography is used to expose the required gate electrode deposition area on the hafnium oxide dielectric layer. Vacuum electron beam evaporation technology is used, wherein the deposition thickness of the Ti layer is set in the range of 5~6 nm and the deposition thickness of the Au layer is controlled between 50~51 nm; a titanium / gold gate electrode that is in close contact with the hafnium oxide dielectric layer is prepared. (8) In this embodiment, photolithography is used to fabricate a photoresist mask layer, exposing the required hafnium oxide etching area and exposing the titanium / gold source / drain metal electrodes in contact with the carbon nanotube channel and the substrate. Reactive ion etching is used for etching under the following conditions: carbon tetrafluoride at a flow rate of 50 sccm is used as the etching gas, pressure is 5.0 ~ 5.5 Pa, power is 100 W, and etching time is 7 min 30 s. This allows for precise etching of the hafnium oxide, ultimately resulting in a structurally complete carbon nanotube field-effect transistor array. Figure 3 The image shows a light micrograph of a single hafnium oxide-doped carbon nanotube field-effect transistor (CNT), including the source, drain, gate, channel, and gate oxide. A layer of non-stoichiometric oxide HfO is sandwiched between the top of the channel CNT and the gate oxide HfO2. x .

[0055] (9) In this embodiment, a thermoelectric device compatible with a carbon nanotube field-effect transistor is constructed. Acetone is sprayed onto the surface of the thermoelectric device, followed by isopropanol. After each spraying, the device is left to stand for 1 minute and then wiped dry with a lint-free cloth to remove surface impurities. Subsequently, a phase change thermal conductive material is attached to the surface of the thermoelectric device and then attached to the substrate of the carbon nanotube field-effect transistor. The surface temperature of the thermoelectric device is adjusted by an external DC power supply, with a temperature range of -25 ℃ to 120 ℃, a temperature control accuracy of up to 0.1 ℃, and a heating or cooling rate of up to 3.84 ℃ / s.

[0056] To reveal the underlying mechanism of the aforementioned temperature-induced polarity reversal from a physical perspective, we constructed a CNT / HfO... x The energy band diagram of the interface, such as Figure 4 As shown. (i) Under initial low temperature or no heat treatment conditions, the Au electrode (work function 5.1 eV) and the intrinsic CNT (E V ~ -4.8 eV, EC ~ -3.0 eV) contact to form a Schottky barrier (Φ SB At this point, due to the physical adsorption of oxygen molecules from the air and their removal of electrons from the CNT surface, the hole concentration in the channel increases, endowing the device with certain P-type conductivity characteristics or bipolar behavior. Simultaneously, HfO in the device... x The dielectric layer (grown via atomic layer deposition) is rich in oxygen vacancy defects, which are present in CNT / HfO x (ii) Temperature-sensitive localized defect states are formed at the interface. When the temperature rises, multiple physical processes work together: First, oxygen molecules adsorbed on the CNT surface undergo thermal desorption, releasing the captured electrons back into the channel; more importantly, the high temperature activates HfO x Oxygen vacancy defects in the dielectric layer enable the trapping of oxygen molecules desorbed from the CNT surface, simultaneously injecting electrons into the CNT channel. This defect-induced electron injection process causes the CNT's conduction band to shift towards the Fermi level (E). F The electrons are significantly brought closer together, thus greatly improving electron injection efficiency and effectively suppressing hole conduction, ultimately causing the device to switch from bipolar to N-type dominance. As the temperature decreases, HfO... x Oxygen molecules trapped by defect states are re-released and physically adsorbed again onto the CNT surface, allowing the device's polarity to be reversibly restored. Furthermore, the dynamic changes in oxygen content within the dielectric layer also affect the interface state density. These interface states, by trapping charge carriers, modulate the device's threshold voltage, manifesting as a positive shift. The entire process is theoretically similar to that of a charge-trapping floating-gate transistor, but its core driving force originates from the unique modulation of interfacial chemical-physical processes (oxygen adsorption / desorption) and defect state activity by temperature.

[0057] Temperature-controlled Raman spectroscopy can effectively explain the oxygen desorption process. When oxygen molecules adsorb onto the surface of carbon nanotubes, they extract electrons from the π-electron system of the carbon nanotubes, exhibiting a p-type doping effect. Under thermal field control, the heating conditions provide the energy required for desorption of the adsorbed oxygen molecules, and the electrons return to the π-electron system of the carbon nanotubes, thereby weakening or even eliminating this p-type doping effect. This charge transfer significantly alters the position of the Fermi level, thus affecting the states of electrons and phonons participating in Raman scattering, ultimately leading to spectral changes. Figure 5 As shown, during the temperature control process from -25 ℃ to 120 ℃, as electrons flow back into the carbon nanotubes in the channel region, the Fermi level rises, causing the G peak to redshift and return to a lower position. Similarly, due to the restoration of resonance conditions and changes in phonon energy, the 2D peak redshifts and returns to its intrinsic position. As for the D peak, the heating process removes a small number of oxygen-containing functional groups, repairing the sp... 2The carbon network reduced defects, thus weakening the D peak intensity. However, during the cooling process from 120 °C to room temperature (25 °C), we observed a reversible peak position change: the G and 2D peaks underwent a blue shift, and the D peak intensity increased again. This indicates that the temperature-induced polarity reversal is reversible.

[0058] like Figure 6 The figure shows the current-time plot of EPSC (excitatory postsynaptic current) of an artificial synaptic transistor based on thermal field modulation. The EPSC of an artificial synapse simulates the current response generated by a postsynaptic neuron in a biological nervous system when it receives an excitatory signal. Its core mechanism is similar to that of the EPSC in a biological synapse, but it is implemented in an artificial device in an electrical form. The existence and dynamic characteristics of the EPSC reveal the functional performance of the artificial synapse and its potential in neuromorphic computing.

[0059] The thermally modulated artificial synaptic transistor involved in this invention, when stimulated by the same positive gate voltage pulse, causes oxygen vacancies in the hafnium oxide dielectric layer-doped carbon nanotube field-effect transistor to migrate into the semiconducting carbon nanotube channel, thereby enhancing the channel conductivity and manifesting as an instantaneous increase in postsynaptic current. Because the device operates at different ambient temperatures of 20°C and 120°C, the different device polarities lead to different amplitudes of the instantaneous EPSC current. At 20°C, the current rapidly reaches its peak after the pulse is applied, then decays exponentially, eventually stabilizing near the baseline. This dynamic process closely matches the typical waveform of biological synaptic EPSC (rapid depolarization followed by slow repolarization). The 5V, 2s input pulse corresponds to the duration of biological action potentials (milliseconds to seconds), indicating that the device can effectively simulate the time-domain response characteristics of biological synapses.

[0060] The rapid decay (Q reduction) of EPSC at high temperatures inhibits the conversion from STM to LTM, making it suitable for temporary information storage scenarios requiring dynamic erasure and rewriting (such as buffers); while the high Q value at low temperatures (20℃) is beneficial for long-term weight solidification. The EPSC maintains stable output (no current oscillation or baseline drift) at 120℃, indicating that the device has high-temperature reliability, making it suitable for high-temperature resistant neuromorphic chips in automotive electronics or industrial automation.

[0061] like Figure 7The figure shows the PPF (paired pulse facilitation) current-time plot of an artificial synaptic transistor based on thermal field modulation. Paired pulse facilitation in artificial synapses is one of the core characteristics simulating short-term plasticity (STP) in biological synapses. Essentially, it reveals the dynamic response mechanism and temporary memory capacity of synapses through the dynamic changes in postsynaptic current under two consecutive pulse stimuli. In biological nervous systems, when a presynaptic neuron receives two consecutive pulse stimuli with a very short interval, the postsynaptic current triggered by the second stimulus is significantly stronger than that of the first; this phenomenon is called double-pulse facilitation. Its core mechanism is related to the dynamic changes in the concentration of calcium ions released from presynaptic neurotransmitters, manifesting as a "temporary memory" effect of the synapse on the previous stimulus. In artificial synaptic devices (such as double-layer transistors and ferroelectric synapses), PPF is achieved by modulating the relaxation time of carrier or ion migration within the material. The PPF value is defined as the ratio of the peak value of the second pulse response (A2) to the peak value of the first pulse response (A1) (A2 / A1×100%).

[0062] The electrical pulse stimulation parameters received by the device involved in this invention are: double pulse voltage 5 V, pulse width 4 s, and interval ΔT = 2 s. The pulse interval time (4 s) is within the typical PPF response sensitive region (1~10 s), which can effectively trigger the non-equilibrium superposition of charge carriers / ions. Response amplitude: The absolute value of the first peak (A1) at 20 ℃ is 3.24 × 10⁻⁶. -8 A, the second peak (A2) is 4.43 × 10 -8 A, the PPF index (A2 / A1) reaches 127%; at 120 ℃, A1 = 1.09 × 10 -6 A, A2 = 1.15 × 10 -6 A. The PPF index dropped to 110%. High temperature caused a 17.3% decrease in PPF efficiency. The main reason is that oxygen vacancies release more electrons at high temperatures, enhancing the initial conductivity (A1 increases), but high temperature also accelerates electron-hole recombination, thus limiting the increase in A2.

[0063] like Figure 8 As shown, the non-monotonic temperature-dependent characteristic of the PPF index is evident. When the device operates in the low-temperature region (20~80℃), the PPF index decreases linearly with increasing temperature for all voltage cycles (1s, 2s, 3s). For example, at V=1s: PPF≈28% at 0℃, and drops to its lowest point ≈8% at 80℃, a decrease of 71.4%. At V=3s: PPF≈25% at 0℃, and ≈5% at 80℃, a decrease of 80%. The dominant mechanism in this stage is the thermal enhancement effect of carrier mobility: the increase in temperature leads to enhanced lattice vibration (phonon scattering), which reduces carrier mobility, shortens the residence time of carriers in the channel, and reduces the double-pulse superposition effect.

[0064] When the device operates in the high-temperature region (80~120 ℃), the PPF index increases significantly with increasing temperature. For example: V=1 s: ​​PPF ≈ 18% at 120 ℃, an increase of 125% compared to 80 ℃. V=3 s: PPF ≈ 10% at 120 ℃, more than double that at 80 ℃. The dominant mechanism shifts to trap-assisted charge release: high temperature activates deep-level defect states (oxygen vacancies), releasing trapped charges, enhancing the carrier concentration gradient, and restoring pulse superposition efficiency.

[0065] also, Figure 8 It also reflects the regulatory law of voltage cycle on PPF index: Short cycle advantage (V=1 s): At all temperatures, the PPF index of 1 s period is higher than that of 2 s and 3 s. For example, at 120 ℃, the PPF of V=1 s (18%) is 80% higher than that of V=3 s (10%). The main mechanism is that the short cycle pulse maintains the non-equilibrium concentration through high-frequency carrier injection, reduces recombination loss, and enhances the synergistic effect of the two pulses. Long cycle sensitivity (V=3 s): The long cycle (3 s) is more sensitive to temperature changes, and the decrease from 0 ℃ to 80 ℃ (80%) is significantly greater than that of the 1 s period (71.4%). The main mechanism is that the long cycle allows carriers to diffuse fully to the trap state, recombination dominates at low temperatures, and the trap release effect is delayed at high temperatures, resulting in a hysteresis response.

[0066] like Figure 9 As shown, this invention relates to the SDDP (Spike Duration-Dependent Plasticity) / electrical pulse period-temperature curve of an artificial synaptic transistor based on thermal field modulation. SDDP (Spike Duration-Dependent Plasticity) is a key mechanism in artificial synapses that simulates the plasticity of biological synapses, describing the dynamic adjustment of synaptic weights (such as conductance and current response) as the duration of the input pulse changes. SDDP mimics the time dependence of signal transmission in biological synapses: when the duration of the pulse signal released by the presynaptic neuron is different, the response intensity of the postsynaptic neuron will show differences. When the device operates in the low-temperature region (20~60 ℃), the SDDP exponent of the device increases sharply from 2000% to a peak value of 8000%. The temperature rise promotes carrier mobility and ion migration rate, and the electric double layer capacitance (EDLC) is formed rapidly, enhancing the pulse superposition effect. When the device operates in the high-temperature region (60~120℃), the SDDP index of the device drops sharply from 8000% to 4000% due to the enhanced phonon scattering and the intensified recombination of trapped states, resulting in a decline in carrier storage capacity.

[0067] also, Figure 9It also shows the three-stage competition of carriers in the device: Stage I (T < 60 °C): Thermal excitation dominates, the carrier concentration and mobility increase synchronously, and the SDDP index is positively correlated with the product. Stage II (60 °C < T < 100 °C): Trap-assisted recombination becomes the main cause, offsetting the mobility gain. Stage III (T > 100 °C): Lattice vibration (phonon) scattering and ion disorder intensify, the carrier mean free path approaches the quantum confinement scale, and the transport efficiency collapses.

[0068] As Figure 10 shown, the present invention relates to the PPF / electrical pulse amplitude-temperature curve characterization of an artificial synaptic transistor based on thermal field regulation. It mainly reflects the temperature-voltage synergy effect of the device. For carrier scattering dominated by temperature at low temperatures (0 - 80 °C): the PPF index at all voltages (3 V / 4 V / 5 V) continuously decreases in the range of 0 - 80 °C. For example: 5V pulse: PPF ≈ 28% at 0 °C, drops to the lowest point of about 8% at 80 °C, with a decrease of 71.4%; 3 V pulse: PP is about 25% at 0 °C, about 5% at 80 °C, with a decrease of 80%. The main mechanism is that the increase in temperature leads to enhanced lattice vibration (phonon scattering), a decrease in carrier mobility, a shortening of the carrier residence time, and a weakening of the double-pulse superposition effect. And the PPF of the device at high voltage (5V) decreases more slowly in the low-temperature region (0 - 40 °C) because the strong electric field accelerates carrier injection, partially offsetting the decrease in mobility.

[0069] When the artificial synaptic device operates at a temperature greater than 80 °C, deep-level defects (such as oxygen vacancies in HfO2) are thermally activated (Ea ≈ 0.35 eV), releasing trapped charges and restoring the carrier concentration gradient. For example: 5V pulse: PPF rises back to ≈ 12% at 120 °C, with an increase of 50%; 3 V pulse: rises back to ≈ 8% at 120 °C, with an increase of 60%. The main mechanism is that the trap-assisted charge release rate exceeds the recombination loss. The PPF increase amplitude of the 5V pulse (4%) is significantly higher than that of the 3V pulse (3%) because the high voltage enhances the carrier delocalization driven by the electric field, suppressing high-temperature recombination.

[0070] As Figure 11As shown, this invention relates to an artificial synaptic transistor based on thermal field modulation, and its SADP (Spike Amplitude-Dependent Plasticity) / electrical pulse amplitude-temperature curve. SADP is a key mechanism for simulating biological synaptic plasticity, its core feature being the dynamic adjustment of synaptic weights (such as conductance and current response) with changes in the amplitude (intensity) of the input pulse signal. SADP mimics the intensity-dependent mechanism of signal transmission in biological synapses: when the intensity (amplitude) of the pulse signal released by the presynaptic neuron differs, the response intensity of the postsynaptic neuron will show differences. Figure 11 In the low-temperature region (0~60 ℃): the SADP exponent increases sharply from 0% to a peak of 9000%, with the temperature rise promoting carrier injection efficiency under high electric fields and a simultaneous increase in ion migration rate. In the high-temperature region (60~120 ℃): the exponent drops sharply from 9000% to 2000%, due to the dominance of phonon scattering and trap state recombination, leading to a collapse in carrier storage capacity. In the mid-temperature optimal region (40~100 ℃): the SADP reaches a peak of 8000% at 80 ℃, as the moderate electric field balances the decrease in mobility and trap activation. In the high-temperature degradation region (>100 ℃): the exponent drops rapidly to 4000%, as lattice disorder exacerbates carrier localization.

[0071] like Figure 12 As shown, the change in synaptic weight of the thermally modulated artificial synaptic transistor under electrical pulse stimulation of different operating temperatures and pulse amplitudes of different polarities is strongly dependent on the polarity of the stimulation pulse. The device's response characteristics at 20 °C are as follows: +5 V pulse: output current is positive (red line), amplitude approximately 10... -7 A. -5 V pulse: The output current remains positive (green line), with an amplitude similar to +5 V. A key characteristic is that both positive and negative pulses drive unidirectional carrier (e.g., holes) injection, exhibiting no polarity dependence, allowing for artificial synaptic weight adjustment through positive and negative voltage pulse modulation. The device's response characteristics at 120 °C are as follows: +5 V pulse: Positive current maintained, amplitude increases to 10. -6 A (increases by one order of magnitude). -5 V pulse: Output current reverses (green line negative), amplitude approximately -10. -9 A. The key features are a strong correlation between polarity dependence and temperature sensitivity. Negative pulses trigger the injection of reverse charge carriers (such as electrons), which can achieve unidirectional voltage pulse modulation of artificial synaptic weight adjustment.

[0072] Since the device operates primarily through hole injection at low temperatures, HfO2 dielectric-doped carbon nanotube devices exhibit bipolar semiconductor behavior, with oxygen vacancies acting as acceptor defects. These vacancies trap electrons, leading to hole-dominated conductivity. At high temperatures (120 °C), oxygen vacancies are thermally activated, releasing electrons to become additional charge carriers, causing the material to transition from bipolar to N-type. Oxygen vacancies introduce shallow donor levels in the band gap, allowing electrons to thermally transition to the conduction band (E0). c ).

[0073] Using the above method, the artificial synaptic transistor based on thermal field modulation proposed in this invention has been successfully realized.

[0074] The results of the embodiments show that this invention, based on thermally modulated artificial synaptic transistors, achieves reversible polarity switching of carbon nanotube field-effect transistors under varying temperatures through a method of doping carbon nanotubes with a hafnium oxide dielectric layer grown by atomic layer deposition. The reconfigurability of artificial synapses under temperature control was systematically studied, and the performance modulation of artificial synapses within different temperature ranges was observed. The results of artificial synapses under different temperature conditions show that electrical performance parameters such as EPSC, PPF, SDDP, and SADP change to varying degrees with temperature. Furthermore, key artificial synaptic performance parameters, including excitatory postsynaptic current, pairing pulse facilitation, peak duration-dependent plasticity, and weight adjustment of artificial synapses under different voltage stimuli, were comprehensively characterized. This provides theoretical support and technical pathways for breaking through the boundaries of traditional computing and constructing truly brain-like intelligent systems.

Claims

1. An artificial synaptic transistor based on thermal field modulation, characterized in that, This artificial synaptic transistor comprises a substrate, a carbon nanotube channel, a gate dielectric layer, a gate electrode, and source / drain electrodes in contact with the carbon nanotube channel. The overall structure is a bottom-up stacked composite structure of silicon dioxide / heavily doped P-type silicon wafer / silicon dioxide / titanium / gold / semiconductor carbon nanotubes / hafnium oxide / titanium / gold. Specifically, the substrate is a bottom-up stacked structure of silicon dioxide / heavily doped P-type silicon wafer / silicon dioxide; the transistor channel is a layer of irregular single-walled carbon nanotubes deposited using a water bath heating method; the gate dielectric layer is a hafnium oxide layer deposited atomically; and the gate electrode and source / drain electrodes are bottom-up titanium / gold stacked composite structures. A layer of non-stoichiometric oxide (HfO) is sandwiched between the top of the carbon nanotube channel and the middle of the hafnium oxide layer. x x = 2~10; A hafnium oxide layer obtained by atomic layer deposition is used to dope the carbon nanotube channel, forming a thermally modulated interface doped layer. This results in a charge trapping state at the interface between the thermally tunable channel and the top dielectric layer. A thermoelectric device is mounted under the substrate using a phase-change thermally conductive material, connecting the thermoelectric device to the carbon nanotube field-effect transistor (FET). Using the FET as the core device carrier, by integrating the thermoelectric device and constructing a temperature-sensitive charge trapping layer, the FET possesses the ability to simulate the plasticity of biological synapses, ultimately forming a thermally modulated artificial synaptic transistor. The thermoelectric device is connected to an external DC power supply, and the temperature of the FET is controlled from -20 °C to 120 °C based on the Peltier effect. Temperature changes significantly affect the rate and equilibrium state of charge trapping and release at the interface. Combined with the electric field activation effect of the gate voltage, the number of trapped charges can be changed non-volatilely, thereby effectively controlling the carrier concentration and conductivity of the carbon nanotube channel. The dynamic characteristics of the reconfigurable transistor are realized through thermoelectric devices, simulating the excitation / inhibition switching of biological synapses. Temperature regulation reversibly switches the polarity of the reconfigurable transistor between N-type and bipolar types. Through step temperature regulation, multi-state and progressive control of the device conductivity is achieved, and artificial synapses are simulated based on this. As the temperature rises, multiple physical processes work synergistically: First, oxygen molecules adsorbed on the CNT surface undergo thermal desorption, releasing the captured electrons back into the channel; high temperature activates HfO x Oxygen vacancy defects in the dielectric layer enable the capture of oxygen molecules desorbed from the CNT surface and simultaneous injection of electrons into the CNT channel; this defect-induced electron injection process causes the conduction band of the CNT to shift towards the Fermi level (E). F The proximity of HfO improves electron injection efficiency and effectively suppresses hole conduction, ultimately causing the device to switch from bipolar to N-type dominance; as the temperature decreases, HfO... x Oxygen molecules trapped by defect states are re-released and physically adsorbed again onto the CNT surface, allowing the device's polarity to be reversibly restored. In addition, the dynamic changes in the oxygen content in the dielectric layer also affect the interface state density. These interface states modulate the device's threshold voltage by trapping charge carriers, resulting in a positive shift.

2. A method for fabricating an artificial synaptic transistor based on thermal field modulation as described in claim 1, characterized in that, Includes the following steps: (1) The substrate is ultrasonically cleaned with acetone and isopropanol in sequence to remove surface impurities, and then further removed by oxygen plasma cleaning machine to remove surface residues; (2) Photolithography is used to precisely form a photoresist mask layer on the substrate. The maximum effective range of the mask layer is 2×2 cm exposure area. The required source and drain electrode areas are exposed on the substrate. The titanium / gold stacked metal electrode is prepared in the designated area by vacuum electron beam evaporation technology to construct the source and drain electrodes of the transistor. (3) Use oxygen plasma cleaning technology to remove residues on the surface of the silicon wafer and the source / drain electrode surfaces; (4) After uniformly spin-coating Primer onto the substrate, immerse it in a carbon nanotube solution that has been ultrasonically dispersed, and deposit carbon nanotubes on the substrate to form a transistor channel layer by water bath heating. (5) First, a photoresist mask layer is precisely constructed on the substrate on which carbon nanotube channels have been deposited by photolithography to pattern the carbon nanotube channel area; then, the carbon nanotubes outside the channel are etched by oxygen plasma cleaning technology to effectively remove excess carbon nanotube film. (6) Using atomic layer deposition technology, a hafnium oxide dielectric layer is uniformly deposited on the carbon nanotube channel. Hafnium oxide is used to dope the carbon nanotube channel, forming an interface doped layer that can be controlled by the thermal field. (7) Using photolithography, the required gate electrode deposition area is exposed on the hafnium oxide dielectric layer. The titanium / gold gate electrode that is in close contact with the hafnium oxide dielectric layer is prepared by vacuum electron beam evaporation technology. (8) Photolithography is used to fabricate a photoresist mask layer, expose the required hafnium oxide etching area, and expose the titanium / gold source and drain metal electrodes that are in contact with the carbon nanotube channel and the substrate. Previously, reactive ion etching technology was used with carbon tetrafluoride as the reactive gas to precisely etch hafnium oxide, and finally a carbon nanotube field effect transistor array with a complete structure was obtained. (9) Construct a thermoelectric device compatible with carbon nanotube field-effect transistors, and spray acetone and isopropanol onto the surface of the thermoelectric device to remove surface impurities; Subsequently, a phase change thermal conductive material is bonded to the upper surface of the thermoelectric device, and the transistor substrate is tightly bonded to the surface of the phase change thermal conductive material. By applying an external DC power supply, the surface temperature of the thermoelectric device can be precisely controlled, thereby flexibly adjusting the operating temperature of the transistor.

3. The method for fabricating an artificial synaptic transistor based on thermal field modulation according to claim 2, characterized in that, In steps (2) and (7), the source and drain electrodes at both ends and the top gate electrode are deposited using an electron beam evaporator. The titanium layer thickness ranges from 5 to 6 nm, and the gold layer thickness ranges from 50 to 51 nm.

4. The method for fabricating an artificial synaptic transistor based on thermal field modulation according to claim 2, characterized in that, In step (3), the oxygen plasma cleaning time is 20 min, the oxygen flow rate is 180 sccm, and the power is 200 W.

5. The method for fabricating an artificial synaptic transistor based on thermal field modulation according to claim 2, characterized in that, In step (4), carbon nanotubes and toluene are mixed at a mass ratio of 1:

8. The carbon nanotube bundles and insoluble substances are removed by ultrasonic dispersion and centrifugation to obtain a semiconductor carbon nanotube solution. The supernatant is collected as a channel material. The carbon nanotube solution is subjected to ultrasonic treatment at a frequency of 40 Hz, a power of 100 W, and a time of 5 min. The carbon nanotube solution after ultrasonic dispersion is transferred to a petri dish. In the process of carbon nanotube film deposition, the cleaned substrate was first heated to 180 ℃ on a hot plate for 30 min to remove moisture. To better adsorb the carbon nanotubes onto the substrate and disperse them evenly, a primer was spin-coated onto the surface of the substrate using a spin coater, and then the substrate was placed on a hot plate at 105 ℃ for 2 min. The baked substrate was then immersed in a culture dish containing a carbon nanotube solution dispersed by ultrasonic vibration, and the culture dish was placed in a 60 ℃ water bath, where the level of deionized water was just above the level of the carbon nanotube solution in the culture dish. The carbon nanotube film deposition was completed after 2-3 hours.

6. The method for fabricating an artificial synaptic transistor based on thermal field modulation according to claim 2, characterized in that, In step (5), LOR3A and S-1813 double-layer photoresist are spin-coated sequentially on the surface of the carbon nanotube film using a spin coater, and the exposed pattern is a square area with a side length of 180~182 μm; The exposed sample was placed in an oxygen plasma cleaner with an oxygen flow rate of 180 sccm and a power of 200 W for 2 minutes to remove excess carbon nanotube film outside the channels.

7. The method for fabricating an artificial synaptic transistor based on thermal field modulation according to claim 2, characterized in that, In step (6), an atomic layer deposition device is used to prepare a 40 nm hafnium oxide dielectric layer on top of a carbon nanotube film at a temperature of 200 °C. For the precursor selection, tetra(dimethylamino)hafnium is selected as the hafnium precursor, and water is selected as the oxygen source precursor. The deposition process parameters include temperature setting, gas flow rate setting, and pulse time setting. In terms of temperature, the temperature of the hafnium precursor and the substrate are key parameters, and the deposition temperature is 200 °C. The gas flow rate needs to be precisely controlled, and the pulse time refers to the residence time of the precursor gas in the reaction chamber. The deposition cycle begins with the introduction of hafnium precursor gas, followed by adsorption and purging with carrier gas. Then, oxygen precursor gas is introduced, and after the reaction, purging with carrier gas is performed again. This process is repeated to form an atomic layer deposition cycle, with each cycle depositing a 0.05–0.2 nm hafnium oxide film. The film thickness is precisely controlled by adjusting the number of cycles. The reaction temperature is set at 200 °C, the hafnium precursor flow rate is 30 sccm, the water vapor flow rate is 150 sccm, and the nitrogen flow rate as the carrier gas is 100 sccm. In each cycle, the pulse time for the hafnium precursor is 0.5 seconds, the pulse time for the water vapor is 1 second, and the carrier gas purging time is 5 seconds. After 200 to 500 atomic layer deposition cycles, a hafnium oxide dielectric layer with a thickness of 10 to 50 nm was prepared.

8. The method for fabricating an artificial synaptic transistor based on thermal field modulation according to claim 2, characterized in that, In step (8), a reactive ion etching machine is used for etching. The etching conditions are as follows: carbon tetrafluoride with a flow rate of 50 sccm is used as the etching gas, the pressure is 5.0~5.5 Pa, the power is 100 W, and the etching time is 5~10 min.

9. The method for fabricating an artificial synaptic transistor based on thermal field modulation according to claim 2, characterized in that, In step (9), the surface of the thermoelectric device is sprayed with acetone and isopropanol in sequence for cleaning. After standing for 1 minute, it is wiped dry with a lint-free cloth to remove surface impurities. The phase change thermal conductive material is attached to the surface of the thermoelectric device and attached to the bottom of the carbon nanotube field effect transistor substrate. The surface temperature of the thermoelectric device is controlled by an external DC power supply. The temperature range is -25 ℃ to 120 ℃, the temperature change step is accurate to 0.1 ℃, and the temperature change rate reaches 3.84 ℃ / s.

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