TVS protection device based on trench isolation structure and preparation method thereof

Abstract

The application relates to the field of semiconductor device manufacturing and process technology, in particular to a TVS protection device based on a Trench groove isolation structure and a preparation method thereof. The application comprises the following steps: S1, a mask is prepared on the surface of a silicon substrate through photolithography to expose an etching area; S2, a high-depth-width-ratio Trench structure with high verticality and smooth sidewalls is prepared through a millisecond-level pulse switching cycle etching and passivation process by using an ICP device; S3, the groove is cleaned and decontaminated in multiple stages, and a gradient temperature annealing is performed to repair lattice damage; and S4, epitaxial growth or non-cavity dense filling of insulating medium is carried out to form a TVS device isolation structure. The application reduces the dangling bonds and defect energy levels caused by interface roughness and prevents local electric field concentration.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor device manufacturing and process, in particular to a TVS protection device based on Trench trench isolation structure and a preparation method thereof. BACKGROUND

[0002] In the development of high power density and miniaturization of existing transient voltage suppression (TVS) protection devices, a deep trench (Trench) isolation structure is often used to achieve electrical isolation between cells. However, there are many process challenges in preparing deep trenches with high aspect ratio. The traditional deep silicon etching process often has constant gas flow and lacks pulse modulation, making it difficult to balance the etching rate of the top and bottom of the trench, resulting in serious scallop effect on the sidewall of the trench and grass-like defects on the bottom. The roughness of this micro-morphology not only introduces a large number of interface states and dangling bonds, causing abnormal increase of reverse leakage current, but also reduces the breakdown voltage and isolation voltage of the device due to local electric field concentration caused by uneven sidewall. In addition, as the depth of the trench increases, the mass transfer limitation in the deep hole makes it difficult to remove the etching by-products and the polymer residues are difficult to clean. The conventional chemical vapor deposition filling process is prone to form premature closure on the top of the trench, resulting in voids and stacking faults inside the isolation structure. In addition, the conventional constant temperature annealing process cannot completely repair the deep lattice damage induced by etching, ultimately leading to a decrease in the insulation performance of the device, which is prone to internal burst or sidewall thermal breakdown under surge impact, and is difficult to meet the circuit protection requirements in harsh industrial environments with high reliability. SUMMARY

[0003] The purpose of the present application is to provide a TVS protection device based on Trench trench isolation structure and a preparation method thereof. By using a process combining pulse-modulated etching and dynamic gas flow adjustment, the present application overcomes the defects of severe scallop effect on the sidewall, grass-like defects on the bottom, and voids formed during deep hole filling in the existing deep trench preparation process. In addition, the present application also takes into account the excellent interface lattice repair and electrical isolation performance, thereby effectively reducing the reverse leakage current and improving the surge resistance while meeting the requirements of device miniaturization and high power density. Specifically, the technical solution of the present application is as follows:

[0004] A preparation method of a TVS protection device based on Trench trench isolation structure, comprising the following steps:

[0005] Step S1: Mask preparation is performed on the surface of a semiconductor silicon substrate defined by photolithography, exposing the area to be etched;

[0006] Step S2: Place the silicon substrate with the mask in the reaction chamber, introduce etching gas for deep silicon etching reaction, and prepare a Trench structure with high aspect ratio on the silicon substrate through cyclic alternating etching and passivation process;

[0007] Step S3: Perform multi-stage cleaning on the Trench structure, use ultrasonic vibration to disperse and remove polymer residues and microscopic impurities generated during the etching process, and then perform gradient temperature annealing to repair lattice damage and reduce interface state density.

[0008] Step S4: Perform epitaxial growth or insulating dielectric filling within the Trench structure. By controlling the kinetic parameters of chemical vapor deposition, achieve void-free dense filling to form the isolation structure of the TVS protection device.

[0009] Specifically, the preparation of the Trench structure in step S2 includes:

[0010] In inductively coupled plasma (ICP) equipment, the radio frequency bias power and chamber pressure are controlled to dissociate the etching gas and form a high-density plasma. Anisotropic etching is used to cut the silicon substrate downwards, and the sidewall passivation gas is deposited. The bias power is periodically changed by switching gas pulses at the millisecond level and using a power supply synchronous pulse modulation mode. At the same time, the flow ratio of etching gas and sidewall passivation gas is dynamically adjusted according to the trench depth to balance the downward etching rate and the sidewall protection effect, ultimately obtaining a deep trench with high verticality and smooth sidewalls.

[0011] Preferably, in step S2, the etching gas includes a fluorine-based gas and a fluorocarbon passivation gas; the fluorine-based gas is SF6, and the fluorocarbon passivation gas is C4F8; the dynamic adjustment specifically involves increasing the flow rate ratio of the fluorocarbon passivation gas as the trench depth increases, based on a preset etching schedule or real-time depth monitoring data, to suppress sidewall roughness and scalloped effect.

[0012] Preferably, the depth range of the Trench structure prepared in step S2 is 10-20 μm; the bottom morphology of the Trench structure is formed by controlling the etching parameters to form a flat bottom or rounded corner structure, so as to avoid grass-like defects caused by micromasking.

[0013] Preferably, the multi-stage cleaning process in step S3 uses a chemical cleaning solution with high permeability and low surface tension. The solution utilizes its high permeability to enter the bottom of the Trench structure and utilizes its chemical dissolution properties to dissolve and remove polymer residues. The polymer residues are mainly a mixture of etching byproducts, silicon halides and fluorocarbon polymers.

[0014] Preferably, the annealing process in step S3 includes static heat preservation under an inert atmosphere, with the temperature control range set to 950℃-1050℃, to ensure that the leakage current index of the TVS device meets the qualified standard of the engineering batch parameter test.

[0015] Preferably, the epitaxial growth or insulating medium filling in step S4 adopts a chemical vapor deposition process. By adjusting the precursor flow rate and growth temperature or deposition / etching time ratio, the orderly arrangement of the deposited material on the inner wall of the trench structure is controlled. During the epitaxial growth or insulating medium filling process, a step-by-step deposition or deposition-etching method is adopted to prevent stacking faults, polycrystalline nucleation, or top closed voids from forming in the deep trench.

[0016] Preferably, the isolation structure is used to achieve electrical isolation between TVS device units; the TVS device unit blocks the current path from adjacent units through the isolation structure, and the interface chemical integrity of the isolation structure supports the device's resistance to high voltage surges.

[0017] The present invention also provides a TVS protection device based on a Trench isolation structure, which is fabricated by a method for preparing a TVS protection device based on a Trench isolation structure; the Trench structure has vertical and smooth sidewalls with a scalloped texture roughness of less than 20 nm, and the epitaxial layer or dielectric layer has no voids or stacking faults; the interface state density is low, and it has low reverse leakage current characteristics.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] 1. This invention effectively solves the challenge of controlling the microstructure of high aspect ratio trenches through a deep silicon etching process that combines power-synchronous pulse modulation mode with dynamic adjustment of the gas flow ratio. By switching gas pulses at the millisecond level and dynamically adjusting the flow ratio of fluorine-based gas and fluorocarbon passivation gas according to the trench depth, the downward etching rate and sidewall protection effect can be balanced, overcoming the mass transfer limitations within deep holes. This not only significantly suppresses the scalloped sidewall effect commonly seen in traditional processes and controls the sidewall roughness to a low level, but also avoids bottom grass-like defects caused by micro-masking of volatile byproducts. The resulting trench structure has extremely high verticality and smooth sidewalls, reducing dangling bonds and defect levels introduced by interface roughness and preventing local electric field concentration.

[0020] 2. This invention introduces a post-processing technique that combines multi-stage cleaning with gradient temperature annealing, significantly improving the interface quality and electrical performance of the device. Utilizing a highly permeable chemical cleaning solution with low surface tension, combined with ultrasonic / megasonic oscillation, it can penetrate deep into the bottom of high aspect ratio trenches, thoroughly removing insoluble etching byproducts. Combined with gradient temperature annealing under an inert atmosphere, sufficient relaxation time is provided to the lattice, effectively eliminating etching-induced deep lattice damage and significantly reducing the interface state density. Test results show that this process maintains the reverse leakage current of the device at the nanoampere level and exhibits excellent breakdown voltage consistency, superior to conventional isothermal annealing processes.

[0021] 3. In the isolation structure filling step, this invention employs a step-by-step deposition or multi-cycle deposition-etch-back process mode, solving the void problem in deep trench filling. By precisely controlling the kinetic parameters of chemical vapor deposition, the orderly conformal growth of silicon atoms on the inner wall of the trench is controlled, effectively preventing voids formed by premature closure of the precursor at the top of the deep trench and eliminating internal stacking faults. This void-free dense filling ensures the mechanical strength and chemical integrity of the isolation structure, eliminates thermal resistance and stress concentration points under surge impact, and avoids internal cracking or sidewall thermal breakdown of the device under harsh environments.

[0022] 4. The TVS protection device prepared by this invention has excellent surge protection capability and process robustness. Thanks to the optimized trench morphology and dense isolation structure, the device can withstand extremely high peak pulse power, and has low clamping voltage and safe failure mode. This preparation method can adapt to manufacturing requirements from small size to enhanced high power size and different depths, meeting the application requirements of miniaturization, high reliability and high power density of TVS devices in consumer electronics and automotive electronics. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a flowchart of the preparation process of the present invention;

[0025] Figure 2 The image shows a comparison of the SEM cross-sections of the trench filling integrity at the extreme depth between Example 5 and Comparative Example 2. Detailed Implementation

[0026] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0027] Example 1:

[0028] Please see Figure 1This embodiment provides a method for fabricating a TVS protection device based on a trench isolation structure. The method specifically includes: fabricating a photolithographically defined mask on the surface of a semiconductor silicon substrate to expose the area to be etched; subsequently, placing the masked silicon substrate in a reaction chamber; and, in an inductively coupled plasma (ICP) apparatus, controlling the radio frequency bias power and chamber pressure, introducing a fluorine-based gas selected from SF6 and a fluorocarbon passivation gas selected from C4F8 as etching gases. The gas flow rate ratio is dynamically adjusted according to the trench depth based on a preset etching schedule or real-time depth monitoring data. The C4F8 flow rate increases linearly from 60 sccm to 100 sccm with increasing depth, while the SF6 gas flow rate is maintained at 120 sccm. The current trench depth is determined by an endpoint detection system or a pre-tested etching rate schedule, and the C4F8 gas flow rate is controlled accordingly to increase linearly from 60 sccm to 90 sccm with increasing depth. That is, throughout the etching process, a power-synchronous pulse modulation mode is used to periodically change the bias power, with a response time of less than 10 ms. The fast-response mass flow controller is used in conjunction with a high-speed gas switching valve. Specifically, the RF power supply pulse frequency is set to 12.5Hz, the duty cycle is 40%, and the gas switching cycle is set to: SF6 gas is introduced for 50ms, followed by C4F8 gas for 30ms. Through the cyclic alternating etching and passivation process synchronized with the gas component switching, the silicon substrate is cut downward using anisotropic etching. Finally, a Trench structure with a depth of 10μm is fabricated on the silicon substrate and applied to a TVS device cell with a standard size of 0.50mm. The bottom morphology of the Trench structure is adjusted to a flat bottom structure by etching parameters.

[0029] Next, the Trench structure was cleaned in multiple stages. The bottom of the Trench structure was wetted by the capillary action of the low surface tension cleaning solution, and the polymer residue and microscopic impurities, mainly the etching byproducts silicon halide and fluoropolymer mixture, were removed by megasonic oscillation. Then, a gradient temperature annealing treatment was performed. The specific procedure was as follows: the temperature was increased from room temperature to 600℃ at a rate of 5℃ / min and held for 30 minutes. Then, the temperature was increased to the target annealing temperature at a rate of 10℃ / min. The temperature was then held in an inert atmosphere. The temperature control range was set to 950℃-1050℃. Finally, chemical vapor deposition is used to perform epitaxial growth or insulating dielectric filling within the Trench structure. In this embodiment, TEOS is selected as the precursor for depositing a silicon oxide dielectric layer. By adjusting the precursor flow rate and growth temperature and adopting a step-by-step deposition method, for example, after every 200nm of thickness, the process is paused and C4F8 etching gas with a flow rate of 80sccm is introduced for 5 seconds to etch back, and this cycle is repeated until the structure is filled, achieving a dense filling without voids and forming an isolation structure for electrical isolation between TVS device units, thereby obtaining a TVS protection device.

[0030] The TVS protection device prepared in this embodiment has a trench structure with high verticality and smooth sidewalls, resulting in reduced interface state density. This effectively suppresses sidewall roughness and scalloped effect. The TVS device unit blocks the current path from adjacent units through an isolation structure. The device leakage current index meets the qualified standard of engineering batch parameter testing and is suitable for consumer electronics circuit protection scenarios with certain requirements for low power consumption.

[0031] Example 2:

[0032] This embodiment provides a method for fabricating a TVS protection device based on a trench isolation structure. This method adjusts the process parameter range based on Embodiment 1, specifically including: after mask fabrication on the surface of a semiconductor silicon substrate, deep silicon etching is performed using an inductively coupled plasma (ICP) device. The etching gas dissociates to form a high-density plasma under power-synchronous pulse modulation mode. Millisecond-level gas pulse switching balances the downward etching rate and sidewall protection effect, fabricating a trench structure with a depth of 12 μm on the silicon substrate, applicable to a standard 0.50 mm TVS device unit. This trench structure undergoes a multi-stage cleaning process using a highly permeable and low-surface-tension chemical cleaning solution to effectively remove polymer residues within the deep holes. Gradient-temperature annealing repairs lattice damage. Finally, epitaxial growth is performed within the trench structure. By controlling the kinetic parameters of chemical vapor deposition, the reaction is confined to the surface reaction region, controlling the orderly conformal growth of silicon atoms on the inner wall of the trench structure, forming a dense isolation structure.

[0033] This embodiment overcomes the mass transfer limitations within deep holes by optimizing the fabrication process of the Trench structure. This allows the fabricated TVS protection device to maintain a small size while ensuring the interfacial chemical integrity of its isolation structure supports the device's ability to withstand high voltage surges. It also avoids grass-like defects caused by micromasking and improves the yield.

[0034] Example 3:

[0035] This embodiment provides a method for fabricating a TVS protection device based on a trench isolation structure. This method, with parameter settings tailored to medium-depth isolation requirements, specifically includes: exposing regions on a semiconductor silicon substrate via photolithography; introducing SF6 and C4F8 into a reaction chamber; utilizing gas pulse gaps to remove volatile byproducts and enhance ion bombardment energy at the trench bottom; fabricating a trench structure on the silicon substrate with a high aspect ratio, a depth of 15 μm, and applicable to a standard 0.50 mm TVS device unit; the bottom morphology of this trench structure is adjusted to a rounded corner structure; subsequently, the trench structure undergoes multi-stage cleaning and gradient temperature annealing to dissolve and remove etching byproducts and reduce interface state density; finally, epitaxial growth and filling are completed within the trench structure using a stepwise deposition method to prevent stacking faults or polycrystalline nucleation within the deep trench, thus forming an isolation structure.

[0036] The TVS protection device prepared in this embodiment has smooth Trench structure sidewalls, a tight bond between the isolation structure and the silicon substrate, and the device leakage current is within a preset low power consumption range, which can meet the stability requirements of the electrical isolation performance of TVS device units in fields such as automotive electronics.

[0037] Example 4:

[0038] This embodiment provides a method for fabricating a TVS protection device based on a trench isolation structure. This method focuses on the challenges of deeper trenches and high-power devices. Specifically, it includes: mask fabrication on the surface of a semiconductor silicon substrate; precise control of RF bias power and chamber pressure during the etching step; dynamic adjustment of the flow ratio of fluorine-based gas and fluorocarbon passivation gas; and coordination with a power synchronization pulse modulation mode to fabricate a trench structure with a depth of 18 μm on the silicon substrate, which is applied to a TVS device cell with an enhancement size of 0.80 mm (note: the size is increased to accommodate high-power heat dissipation requirements); the trench structure is then cleaned with a chemical cleaning solution under vacuum immersion and subjected to static annealing at 1050°C; finally, an insulating medium is filled into the trench structure or epitaxial growth is performed to form the isolation structure of the TVS protection device.

[0039] The TVS protection device fabricated in this embodiment maintains good verticality of the trench structure even at a depth of nearly 20 micrometers, effectively suppressing the morphological distortion that often occurs in deep hole etching. The isolation structure ensures current blocking between adjacent units, making it suitable for high-density circuit protection applications.

[0040] Example 5:

[0041] This embodiment provides a method for fabricating a TVS protection device based on a trench isolation structure. This method challenges the boundary values ​​of process parameters and specifically includes: fabricating a photolithographically defined mask on the surface of a semiconductor silicon substrate; in step S2, in order to overcome the mass transfer limitation in the deep hole, an optimized power synchronization pulse modulation mode and gas flow ratio are used to fabricate a trench structure with a depth of 20 μm on the silicon substrate, which is applied to a TVS device cell with an enhancement size of 0.80 mm. The bottom morphology of the trench structure is a flat-bottom structure; after the trench structure is cleaned by megasonic cavitation cleaning with a high-permeability cleaning solution and subjected to gradient temperature annealing, the lattice damage is repaired; in step S4, by finely adjusting the precursor flow rate and adopting a multi-cycle deposition-etch-back process mode, void-free epitaxial growth and filling are achieved in the trench structure to form an isolation structure.

[0042] The TVS protection device fabricated in this embodiment successfully achieved the fabrication of a Trench structure with a high aspect ratio. It has a low interface state density and strong ability to withstand high voltage surges, demonstrating the robustness of the fabrication method at extreme depths and meeting the requirements of high-performance industrial-grade protection devices.

[0043] Comparative Example 1:

[0044] This comparative example provides a method for fabricating a TVS protection device. The only difference between this method and Example 3 is that, in the step of fabricating the trench structure, the power synchronization pulse modulation mode was not used, and the flow ratio of the etching gas to the passivation gas was kept constant and not dynamically adjusted according to the trench depth. The remaining steps, such as photolithography, cleaning, annealing, and epitaxial filling processes, are consistent with Example 3, and a trench structure with a depth of 15 μm is finally fabricated. Due to the lack of dynamic adjustment and pulse modulation, the trench structure fabricated in this comparative example shows obvious scalloped texture on the sidewalls, and there are a small number of grass-like defects at the bottom of the trench, resulting in tiny gaps at the interface of the subsequently filled isolation structure. The final test showed that the leakage current of the device was higher than that of Example 3, indicating that simple constant parameter etching is difficult to meet the microstructure requirements of high aspect ratio trenches.

[0045] Comparative Example 2:

[0046] Please see Figure 2This comparative example provides a method for fabricating a TVS protection device, which differs from Example 5 only in that: in step S3, which is the post-processing of the trench structure, gradient heating annealing is not used, but conventional isothermal annealing is used instead; in step S4, during epitaxial growth, step-by-step deposition or deposition-etch-back method is not used, but continuous deposition is used instead; other parameters, such as trench depth of 20 μm and device size of 0.80 mm, are consistent with Example 5. Due to the difference in annealing process and deposition method, the lattice damage on the inner wall of the trench structure prepared in this comparative example is not completely repaired, and local stacking faults and top breakage-induced voids appear in the epitaxial layer inside the deep trench, resulting in a decrease in the insulation performance of the isolation structure. The device performs worse than Example 5 in the high voltage impact test and cannot fully meet the qualification standards for engineering batch parameter testing.

[0047] In Examples 1-5 and Comparative Examples 1-2, the semiconductor silicon substrate (N-type single-crystal silicon wafer) was sourced from Tianjin Zhonghuan Semiconductor Co., Ltd., with crystal orientation... <111> The resistivity is 0.001–0.005 Ω·cm, and the thickness is 200 μm. The etching gas, sulfur hexafluoride (SF6), is from Guangdong Huatai Gas Co., Ltd., electronic grade, purity ≥99.999%, CAS No.: 2551-62-4. The passivation gas, octafluorocyclobutane (C4F8), is from Guangdong Huatai Gas Co., Ltd., electronic grade, purity ≥99.999%, CAS No.: 115-25-3. The low surface tension cleaning solution (electronic grade isopropanol) is from Sinopharm Chemical Reagent Co., Ltd., MOS grade, purity ≥99.9%, CAS No.: 67-63-0. The photoresist is from Suzhou Ruihong Electronic Chemicals Co., Ltd., model RZJ-304, viscosity 18-22 cP. The chemical vapor deposition precursor, tetraethyl orthosilicate (TEOS), is from Shanghai Aladdin Biochemical Technology Co., Ltd., ACS grade, CAS No.: 78-10-4. All other products are commercially available.

[0048] The TVS protection devices prepared in Examples 1-5 and Comparative Examples 1-2 were tested accordingly, and the test results are shown below:

[0049] (1) Microscopic morphology and structural integrity test

[0050] Test method description:

[0051] The cross-sectional morphology of the trench structures prepared in Examples 1-5 and Comparative Examples 1-2 was observed using a field emission scanning electron microscope (FESEM, model: Hitachi SU8010, Hitachi, Ltd., Japan). The prepared wafer samples were cut and prepared, and the sidewall smoothness, bottom morphology, and internal structure after filling of the trench were observed in a vacuum environment. The sidewall roughness and the presence of voids in the internal filling were evaluated in particular. Five points were selected from the center and edge of each sample for observation, and the average value was recorded.

[0052] Table 1

[0053]

[0054] Results analysis:

[0055] As shown in Table 1, the trench structures of the TVS protection devices prepared by this invention all exhibit excellent morphological characteristics, with smooth sidewalls and high perpendicularity; with the increase of design depth (from 10 in Example 1), Up to Example 5 of 20 Although the sidewall roughness increased slightly due to the mass transfer limitations within the deep hole, it was all controlled within 20 nm and no obvious morphological distortion was observed.

[0056] A comparative analysis of Example 3 and Comparative Example 1 shows that: Although Comparative Example 1 reached 15 The depth of the deep silicon etching was high, but due to the lack of power synchronization pulse modulation mode and constant gas flow ratio, the sidewall roughness reached 125.60 nm, resulting in a noticeable scalloped effect. This is because in deep silicon etching, a constant gas flow rate cannot balance the etching / passivation rates at the top and bottom of the trench, leading to excessive erosion of the sidewalls. In contrast, Example 3 effectively suppressed the lateral etching of the sidewalls and achieved high verticality by dynamically adjusting the flow ratio of SF6 and C4F8 and combining it with pulse modulation. Furthermore, the grass-like defects at the bottom of Comparative Example 1 were caused by the micro-masking effect resulting from the failure to remove volatile byproducts in time.

[0057] A comparative analysis of Example 5 and Comparative Example 2 shows that at a maximum depth of 20... In Comparative Example 2, due to the use of continuous deposition in step S4 during epitaxial growth, the reaction precursor was deposited too quickly at the top of the trench and closed the opening, preventing the internal gas from escaping and thus forming a closed void at the top. In contrast, Example 5 adopted a multi-cycle deposition-etching process, which effectively prevented premature closure of the trench neck, achieved void-free dense filling in the deep trench, and ensured the mechanical and chemical integrity of the isolation structure.

[0058] (2) Electrical performance testing

[0059] Test method description:

[0060] The electrical performance of the packaged TVS protection device was tested using a semiconductor parameter analyzer (Keithley 4200-SCS, Tektronix, USA). The reverse leakage current and breakdown voltage of the device were tested at room temperature (25°C). The test voltage was progressively scanned, and the leakage current value was recorded when the device reached the specified reverse operating voltage. Twenty device units were randomly selected from each example and comparative example for testing. After removing defective units, the average value was taken. The test results are shown in Table 2.

[0061] Table 2

[0062]

[0063] Results analysis:

[0064] As shown in Table 2, the devices prepared in Examples 1-5 exhibit extremely low reverse leakage current and excellent breakdown voltage consistency. With the increase of trench depth, the leakage current increases slightly, which is due to the increase in the total number of surface states caused by the increase in the interface area of ​​the deep trench. However, the overall leakage current is still at the nanoampere (nA) level, which meets the standard for high-performance and low-power applications.

[0065] Compared to Example 3, Comparative Example 1 showed an abnormally high leakage current of 158.42 nA. Mechanistically, the severe scalloped effect in Comparative Example 1 led to a sharp increase in the surface area of ​​the trench sidewalls, and the rough interface introduced a large number of lattice defects and dangling bonds. These defect energy levels became recombination and generation centers for charge carriers, thus significantly increasing the surface leakage current. In addition, the unevenness of the sidewalls led to local electric field concentration, which reduced the overall breakdown voltage performance of the device.

[0066] Compared to Example 5, Comparative Example 2, although having the same trench depth, also experienced a leakage current of 89.75 nA and a decrease in isolation withstand voltage performance. This is because Comparative Example 2 did not employ gradient heating annealing in the post-processing steps, but instead used conventional isothermal annealing. Gradient heating annealing provides sufficient relaxation time for the lattice, effectively eliminating etching-induced deep lattice damage. In contrast, conventional annealing does not thoroughly repair the damage, resulting in a still high interface state density. Furthermore, the presence of micro-voids within Comparative Example 2 (see results in Table 1) leads to a decrease in the dielectric strength of the isolation structure, making it prone to local breakdown under high voltage and failing to meet the requirements for high-voltage isolation.

[0067] (3) Reliability and surge withstand capability test

[0068] Test method description:

[0069] Referring to standard IEC 61000-4-5 "Electromagnetic compatibility testing and measurement techniques - Surge (impulse) immunity test", a lightning surge generator (ESS-2000, NoiseKen, Japan) was used to test the surge immunity capability of the device; the applied waveform was 8 / 20. The pulse current is gradually increased, and the peak pulse current is gradually increased. Until the device fails (a sudden change in leakage current or a short circuit is detected at both ends); record the maximum peak pulse power that the device can withstand. ) and clamping voltage ( Repeat the test 3 times and take the average value.

[0070] Table 3

[0071]

[0072] Results analysis:

[0073] As shown in Table 3, the TVS protection devices of Examples 1-5 have excellent surge protection capabilities, and their power tolerance is significantly improved with the optimization of device size and trench depth. Example 5 achieved a peak pulse power of 650W, proving that the deep trench isolation structure not only achieves electrical isolation, but also assists in heat dissipation through good interface contact.

[0074] Compared with Example 3, Comparative Example 1 shows a decrease in peak pulse power and an increase in clamping voltage. This is because the grass-like defects and micro-roughness of the sidewalls of Comparative Example 1 cause local hot spots on the current path. Under high current impact, the electric field at these tip positions is extremely concentrated, leading to local overheating and premature thermal breakdown, which limits the current carrying capacity of the device.

[0075] Compared with Example 5, Comparative Example 2 exhibits an internal burst failure mode. The root cause lies in the stacking faults and voids within the isolation structure of Comparative Example 2. During the surge impact, the gas inside the void expands due to heat, generating enormous mechanical stress. In addition, the abnormal resistivity at the stacking faults leads to uneven heating, ultimately resulting in the destruction of the device's physical structure. Example 5, on the other hand, benefits from the dense filling achieved by the deposition-etch-back process, eliminating internal thermal resistance and stress concentration points, thus exhibiting stronger robustness and meeting the circuit protection requirements of harsh industrial environments.

[0076] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments that can be applied to other fields. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A method for fabricating a TVS protection device based on a Trench-groove isolation structure, characterized in that, The method comprises the following steps: Step S1: performing mask preparation on the surface of a semiconductor silicon substrate to expose the area to be etched; Step S2: placing the silicon substrate with the mask in a reaction chamber, introducing etching gas to perform deep silicon etching reaction, and preparing a Trench structure with high aspect ratio on the silicon substrate through cyclic and alternating etching and passivation processes; Step S3: performing multi-stage cleaning on the Trench structure, dispersing and removing polymer residues and micro impurities generated in the etching process through ultrasonic oscillation, and then performing gradient annealing treatment to repair lattice damage and reduce interface state density; Step S4: performing epitaxial growth or insulating medium filling in the Trench structure, realizing dense filling without cavity through control of the kinetic parameters of chemical vapor deposition, and forming an isolation structure of a TVS protection device; In the step S2, the preparation of the Trench structure specifically comprises: In an inductively coupled plasma device, the radio frequency bias power and the chamber pressure are controlled to make the etching gas dissociate to form a high-density plasma; the silicon substrate is cut down by anisotropic etching, and the deposition of the sidewall passivation gas is cooperated to periodically change the bias power by using a power synchronous pulse modulation mode through millisecond-level gas pulse switching, and the flow ratio of the etching gas and the sidewall passivation gas is dynamically adjusted according to the trench depth to balance the downward etching rate and the sidewall protection effect, so that a deep trench with high verticality and smooth sidewall is finally obtained.

2. The method for fabricating a TVS protection device based on a Trench-groove isolation structure according to claim 1, characterized in that, In the step S2, the etching gas comprises fluorine-based gas and fluorocarbon-based passivation gas; the fluorine-based gas is SF6, and the fluorocarbon-based passivation gas is C4F8; the dynamic adjustment specifically comprises: increasing the flow ratio of the fluorocarbon-based passivation gas with the increase of the trench depth according to a preset etching time table or real-time depth monitoring data to inhibit the sidewall roughness and scallop effect.

3. The method for fabricating a TVS protection device based on a Trench-groove isolation structure according to claim 1, characterized in that, The depth of the Trench structure prepared in the step S2 ranges from 10 to 20 μm; the bottom morphology of the Trench structure is formed into a flat bottom or a rounded corner structure by controlling the etching parameters to avoid grass-like defects caused by micro-shielding.

4. The method for fabricating a TVS protection device based on a Trench-groove isolation structure according to claim 1, characterized in that, The multi-stage cleaning process in the step S3 uses a chemical cleaning solution with high permeability and low surface tension to enter the bottom of the Trench structure by using its high permeability and to dissolve and carry away the polymer residues by using its chemical dissolution properties; the polymer residues are mainly a mixture of etching by-products, silicon halides and fluorocarbon polymers.

5. The method for fabricating a TVS protection device based on a Trench-groove isolation structure according to claim 1, characterized in that, The annealing process in the step S3 comprises standing and heat preservation in an inert atmosphere, and the temperature control interval is set to 950-1050℃ to ensure that the leakage current index of the TVS device meets the qualified standard of the engineering batch parameter test.

6. The method for fabricating a TVS protection device based on a Trench-groove isolation structure according to claim 1, characterized in that, The epitaxial growth or insulating medium filling in the step S4 adopts a chemical vapor deposition process to control the ordered arrangement of the deposited material on the inner wall of the Trench structure by adjusting the precursor flow rate, growth temperature or deposition / etching time ratio; in the epitaxial growth or insulating medium filling process, a step-by-step deposition or deposition-etching mode is adopted to prevent the generation of stacking faults, polycrystalline nucleation or top closed cavity in the deep trench.

7. The method for fabricating a TVS protection device based on a Trench-groove isolation structure according to claim 1, characterized in that, The isolation structure is used for realizing electrical isolation between TVS device units; the TVS device units block current paths with adjacent units through the isolation structure, and interface chemical integrity of the isolation structure supports that the device can withstand high voltage impact.

8. A TVS protection device based on a Trench-groove isolation structure, characterized in that, The application relates to a silicon substrate, a Trench structure formed in the silicon substrate, and an epitaxial layer or a dielectric layer filled in the Trench structure; the Trench structure is prepared by the preparation method in any one of claims 1 to 7; the Trench structure has a vertical smooth sidewall, the sidewall fan-shaped shell roughness is in a nanometer level, and the epitaxial layer or the dielectric layer is free of internal cavities and stacking faults; interface state density is low, and the device has a low reverse leakage current characteristic.

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