Display panel and display device

Abstract

A display panel comprises: a first substrate; the first electrode layer is located on the first substrate; a first weir layer and a second weir layer on the first electrode layer; the second electrode layer is positioned on one side, far away from the first substrate, of the first weir layer and the second weir layer; the second substrate is located on the side, away from the first substrate, of the second electrode layer. The first weir layer includes a plurality of first weir structures. The second weir layer includes a plurality of second weir structures. Each first weir structure surrounds a plurality of plasma particles in a respective one of the plurality of sub-pixels. Each first weir structure surrounds a respective second weir structure. Each second weir structure surrounds at least a portion of the plurality of plasma particles in the respective sub-pixel.

Description

TECHNICAL FIELD

[0001] The present application relates to display technology, in particular to a display panel and a display device. BACKGROUND

[0002] Display technology has undergone significant development, transitioning from cathode ray tubes to flat panels, with electronic paper displays being recognized for their low power consumption and superior reading experience in direct sunlight. Electrophoretic display technology, including microcapsule and microcup methods, has paved the way for current advances in electronic paper displays. SUMMARY

[0003] In one aspect, the present disclosure provides a display panel, comprising: a first substrate; a first electrode layer on the first substrate; a first weir layer and a second weir layer on the first electrode layer; a second electrode layer on a side of the first weir layer and the second weir layer distal to the first substrate; and a second substrate on a side of the second electrode layer distal to the first substrate; wherein the first weir layer comprises a plurality of first weir structures; the second weir layer comprises a plurality of second weir structures; each first weir structure of the plurality of first weir structures surrounds a plurality of plasmonic particles in a corresponding sub-pixel of a plurality of sub-pixels; the each first weir structure surrounds a corresponding second weir structure of the plurality of second weir structures; and the corresponding second weir structure surrounds at least a portion of the plurality of plasmonic particles in the corresponding sub-pixel.

[0004] Optionally, a first portion of the plurality of plasmonic particles in the corresponding sub-pixel is surrounded by the corresponding second weir structure, and a second portion of the plurality of plasmonic particles in the corresponding sub-pixel is located between the corresponding second weir structure and the corresponding first weir structure.

[0005] Optionally, the plurality of first weir structures are part of a unitary structure.

[0006] Optionally, the first weir layer is in direct contact with the first electrode layer and in direct contact with the second electrode layer; the first electrode layer, the second electrode layer, and the each first weir structure encapsulate the plurality of plasmonic particles in the corresponding sub-pixel; the second weir layer is in direct contact with the first electrode layer and in direct contact with the second electrode layer; and the first electrode layer, the second electrode layer, and the each second weir structure encapsulate at least a portion of the plurality of plasmonic particles in the corresponding sub-pixel.

[0007] Optionally, the plurality of second weir structures are spaced apart from each other; and two adjacent second weir structures of the plurality of second weir structures are spaced apart by a portion of a single first weir structure of the plurality of first weir structures.

[0008] Optionally, the first electrode layer includes a plurality of first electrode blocks; and each of the plurality of first electrode blocks is located in a corresponding sub-pixel.

[0009] Optionally, the orthographic projection of the first weir layer on the substrate does not overlap at least partially with the orthographic projection of the first electrode layer on the substrate; and the orthographic projection of each of the first weir structures on the substrate does not overlap at least partially with the orthographic projection of the corresponding first electrode block among the plurality of first electrode blocks on the substrate.

[0010] Optionally, the orthographic projections of two adjacent first electrode blocks on the substrate are separated by the orthographic projection of a portion of the first dam layer on the substrate; and the orthographic projections of each first electrode block on the substrate are substantially surrounded by the orthographic projection of the corresponding first dam structure on the substrate.

[0011] Optionally, the orthographic projection of each of the plurality of first electrode blocks on the substrate substantially covers the orthographic projection of the corresponding second weir structure on the substrate.

[0012] Optionally, each of the first weir structures surrounds a first opening; each of the second weir structures surrounds a second opening; the plurality of sub-pixels are arranged in an array having multiple rows and columns; each row of sub-pixels is arranged along a first direction; each column of sub-pixels is arranged along a second direction; the first opening has a first average width along the first direction; the second opening has a second average width along the first direction; and the ratio of the first average width to the second average width is in the range of 1.2:1 to 5:1.

[0013] Optionally, the display panel includes: a first conductive layer located on the first substrate; a gate insulating layer located on the side of the first conductive layer away from the first substrate; a second conductive layer located on the side of the gate insulating layer away from the first substrate; a first passivation layer located on the side of the second conductive layer away from the first substrate; a third conductive layer located on the side of the first passivation layer away from the first substrate; and a second passivation layer located on the side of the third conductive layer away from the first substrate; wherein the first electrode layer is located on the side of the second passivation layer away from the first substrate; and the third conductive layer is configured to be supplied with a constant voltage.

[0014] Optionally, the display panel includes: a first conductive layer located on the first substrate; a gate insulating layer located on the side of the first conductive layer away from the first substrate; a second conductive layer located on the side of the gate insulating layer away from the first substrate; and a second passivation layer located on the side of the second conductive layer away from the first substrate; wherein the first electrode layer is located on the side of the second passivation layer away from the first substrate; and the second conductive layer includes one or more electrode connection lines; wherein the display panel further includes one or more vias extending through at least the second passivation layer; and the first electrode layer is connected to the one or more electrode connection lines in the second conductive layer through the one or more vias.

[0015] Optionally, the orthographic projection of the first weir layer on the substrate does not overlap with the orthographic projection of the second weir layer on the substrate; and the orthographic projections of the plurality of first weir structures on the substrate do not overlap with the orthographic projections of the plurality of second weir structures on the substrate.

[0016] Optionally, the display panel further includes a plurality of recesses; wherein the orthographic projection of each of the plurality of second weir structures on the first substrate surrounds the orthographic projection of the corresponding recess among the plurality of recesses on the first substrate.

[0017] Optionally, a first portion of the plurality of plasma particles in the corresponding sub-pixel is surrounded by the corresponding second weir structure; a second portion of the plurality of plasma particles in the corresponding sub-pixel is located between the corresponding second weir structure and the corresponding first weir structure; and the first portion of the plurality of plasma particles has a higher response speed than the second portion of the plurality of plasma particles.

[0018] Optionally, each of the recesses is at least partially recessed into one or more passivation layers.

[0019] Optionally, the ratio of the total number of multiple first weir structures to the total number of multiple sub-pixels is in the range of 0.9:1 to 1.1:1.

[0020] Optionally, the ratio of the total number of multiple second weir structures to the total number of multiple sub-pixels is in the range of 0.9:1 to 1.1:1.

[0021] Optionally, the aperture ratio of the display panel is in the range of 85% to 95%.

[0022] On the other hand, this disclosure provides a display device including a display panel described herein or manufactured by the methods described herein, and one or more integrated circuits connected to the display panel. Attached Figure Description

[0023] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0024] Figure 1 This is a schematic diagram showing the structure of the relevant display panel.

[0025] Figure 2 This is a schematic diagram showing the structure of the relevant display panel.

[0026] Figure 3 This is a perspective view of a display panel according to some embodiments of the present disclosure.

[0027] Figure 4 This is a schematic diagram illustrating various layers in a portion of a display panel according to some embodiments of the present disclosure.

[0028] Figure 5 This is a plan view of a display panel according to some embodiments of the present disclosure.

[0029] Figure 6 It is along Figure 5 A cross-sectional view of line A-A' in the diagram.

[0030] Figure 7 This is a plan view of a display panel according to some embodiments of the present disclosure.

[0031] Figure 8 It is along Figure 7 A cross-sectional view of line B-B' in the diagram.

[0032] Figure 9 The optical effects of display panels with different aperture ratios are shown.

[0033] Figure 10 This shows the correlation between the white value of the display panel and the aperture ratio of the display panel.

[0034] Figure 11 This is a schematic diagram illustrating a weir structure in a display panel according to some embodiments of the present disclosure.

[0035] Figure 12 This is a schematic diagram illustrating a weir structure in a display panel according to some embodiments of the present disclosure.

[0036] Figure 13 This is a plan view of a display panel according to some embodiments of the present disclosure.

[0037] Figure 14 It is along Figure 13 A cross-sectional view of line C-C' in the diagram.

[0038] Figure 15This is a schematic diagram illustrating the structure of the first electrode layer, the first weir layer, and the second weir layer according to some embodiments of the present disclosure.

[0039] Figure 16 This is a schematic diagram illustrating the structure of a first electrode layer, a first weir layer, a second weir layer, and a third weir layer according to some embodiments of the present disclosure.

[0040] Figure 17 This is a schematic diagram illustrating the structure of a display panel according to some embodiments of the present disclosure.

[0041] Figure 18 This is a schematic diagram illustrating various layers in a portion of a display panel according to some embodiments of the present disclosure.

[0042] Figure 19 This is a plan view of a display panel according to some embodiments of the present disclosure.

[0043] Figure 20 It is along Figure 19 A cross-sectional view of the D-D' line in the diagram.

[0044] Figure 21 This is a schematic diagram illustrating the structure of a first electrode layer, a first weir layer, a second weir layer, and a plurality of recesses according to some embodiments of the present disclosure.

[0045] Figure 22 This is a plan view of a display panel according to some embodiments of the present disclosure.

[0046] Figure 23 It is along Figure 22 A cross-sectional view of the E-E' line in the diagram.

[0047] Figure 24 The electric field and particle polarization are shown in a relevant display panel without a weir structure.

[0048] Figure 25 The electric field and particle polarization are shown in the relevant display panel, which only has the first weir structure.

[0049] Figure 26 The electric field and particle polarization in a display panel according to some embodiments of the present disclosure are shown.

[0050] Figure 27 This is a schematic diagram illustrating the structure of a display device according to some embodiments of the present disclosure. Detailed Implementation

[0051] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0052] Plasma display technology, also known as novel display plasma (DES) technology, represents an innovative approach to electronic paper display technology. Unlike existing electrophoretic display microcapsule and microcup technologies, plasma display technology employs an isolation dam structure around each pixel. This patterned isolation dam structure ensures that the electrode unit of each pixel is encapsulated by the plasma isolation dam, achieving high-resolution display effects.

[0053] Traditional plasma display architectures typically rely on a single-layer isolation dam support structure or a double-dam cell structure. When the screen bends due to external forces, plasma particles distributed within the isolation dam tend to overflow. This disrupts the one-to-one correspondence between the isolation dam and the pixels, resulting in the loss of display plasma in some pixels, which affects the stability and optical display quality of the display.

[0054] Figure 1 This is a schematic diagram showing the structure of the relevant display panel. (Refer to...) Figure 1 The related display panel includes: a first substrate BS1; a driving board DP located on the first substrate BS1; a first electrode layer E1 located on the side of the driving board DP away from the first substrate BS1; a weir layer DL located on the side of the first electrode layer E1 away from the first substrate BS1; a second electrode layer E2 located on the side of the weir layer DL away from the first substrate BS1; and a second substrate BS2 located on the side of the second electrode layer E2 away from the first substrate BS1. The display panel includes multiple weir structures DS. Each weir structure in the multiple weir structures DS surrounds multiple plasma particles PP in a corresponding sub-pixel of multiple sub-pixels Sp of the display panel. Optionally, the weir layer DL is in direct contact with the first electrode layer E1 and in direct contact with the second electrode layer E2. Optionally, the first electrode layer E1, the second electrode layer E2, and the respective weir structures encapsulate the multiple plasma particles PP in the corresponding sub-pixel.

[0055] Figure 2 This is a schematic diagram showing the structure of the relevant display panel. (Refer to...) Figure 2The related display panel includes: a first substrate BS1; a driving plate DP located on the first substrate BS1; a first electrode layer E1 located on the side of the driving plate DP away from the first substrate BS1; a weir layer DL located on the side of the first electrode layer E1 away from the first substrate BS1; a second electrode layer E2 located on the side of the weir layer DL away from the first substrate BS1; and a second substrate BS2 located on the side of the second electrode layer E2 away from the first substrate BS1. The display panel includes a plurality of weir structures DS. Each weir structure in the plurality of weir structures DS surrounds a plurality of plasma particles PP in a corresponding sub-pixel of a plurality of sub-pixels Sp of the display panel. The weir layer DL includes: a first sub-weir layer sDL1 located on the side of the first electrode layer E1 away from the first substrate BS1; and a second sub-weir layer sDL2 located on the side of the first sub-weir layer sDL1 away from the first substrate BS1. Each weir structure includes a portion of the first sub-weir layer sDL1 and a portion of the second sub-weir layer sDL2. The orthographic projection of the first sub-dam layer sDL1 onto the first substrate BS1 at least partially overlaps with the orthographic projection of the second sub-dam layer sDL2 onto the first substrate BS1. Optionally, the first sub-dam layer sDL1 and the second sub-dam layer sDL2 are in direct contact. A portion of the first sub-dam layer sDL1 and a portion of the second sub-dam layer sDL2 are assembled together to form a corresponding dam structure. Optionally, a portion of the first sub-dam layer sDL1 is in direct contact with the first electrode layer E1. Optionally, a portion of the second sub-dam layer sDL2 is in direct contact with the second electrode layer E2. Optionally, the first electrode layer E1, the second electrode layer E2, and each dam structure encapsulate multiple plasma particles PP in the corresponding sub-pixel.

[0056] In the relevant display panels, plasma can easily leak from the sub-pixels encapsulated by the dam layer, especially when the display panel is bent and the dam layer deforms due to the bending. This issue affects the performance and driving stability of the relevant display panels.

[0057] Electrophoretic displays have limitations, particularly in terms of resolution and mechanical flexibility. These displays typically employ a single-layer isolation dam support structure or a double-dam cell structure to encapsulate electrophoretic particles within subpixels. While effective under static conditions, these structures are prone to particle spillage when subjected to bending or flexing, leading to compromised display integrity and degraded optical quality.

[0058] With the growing demand for high-resolution electronic displays capable of withstanding the wear and tear of everyday handling, there is a continuous need to improve the robustness of display architectures. Maintaining precise control over the electrophoretic particles within each subpixel, regardless of the physical deformation the display undergoes, remains a challenge that current technology has yet to fully address.

[0059] Therefore, this disclosure particularly provides a display panel and display device that substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides a display panel. In some embodiments, the display panel includes: a first substrate; a first electrode layer located on the first substrate; a first dam layer and a second dam layer located on the first electrode layer; a second electrode layer located on a side of the first and second dam layers away from the first substrate; and a second substrate located on a side of the second electrode layer away from the first substrate. Optionally, the first dam layer includes a plurality of first dam structures. Optionally, the second dam layer includes a plurality of second dam structures. Optionally, each of the plurality of first dam structures surrounds a plurality of plasma particles in a corresponding sub-pixel of a plurality of sub-pixels. Optionally, each of the first dam structures surrounds a corresponding second dam structure of a plurality of second dam structures. Optionally, each of the second dam structures surrounds at least a portion of the plurality of plasma particles in a corresponding sub-pixel.

[0060] This invention proposes a novel multi-point electronic paper packaging structure design. The purpose of this new design is to significantly improve the mechanical flexibility and refresh rate of the display, while reducing the influence of the driving electric field between pixels. This structural improvement addresses the shortcomings of related electrophoretic displays by preventing particle overflow and the resulting loss of display quality and resolution when the display is bent.

[0061] Figure 3 This is a perspective view of a display panel according to some embodiments of the present disclosure. Figure 4 This is a schematic diagram illustrating various layers in a portion of a display panel according to some embodiments of the present disclosure. Figure 5 This is a plan view of a display panel according to some embodiments of the present disclosure. Figure 6 It is along Figure 5 The cross-sectional view of line A-A' in the diagram. (Refer to...) Figure 3 The display panel includes a first substrate BS1, a first dam layer DL1 and a second dam layer DL2 located on the first substrate BS1.

[0062] Reference Figure 4In some embodiments, the display panel includes: a first substrate BS1; a first conductive layer CT1 located on the first substrate BS1; a gate insulating layer GI located on the side of the first conductive layer CT1 away from the first substrate BS1; a second conductive layer CT2 located on the side of the gate insulating layer GI away from the first substrate BS1; a first passivation layer PVX1 located on the side of the second conductive layer CT2 away from the first substrate BS1; a third conductive layer CT3 located on the side of the first passivation layer PVX1 away from the first substrate BS1; a second passivation layer PVX2 located on the side of the third conductive layer CT3 away from the first substrate BS1; and a first electrode layer E1 located on the side of the second passivation layer PVX2 away from the first substrate BS1.

[0063] In some embodiments, the first conductive layer CT1 includes a plurality of gate lines. In some embodiments, the second conductive layer CT2 includes a plurality of data lines. Figure 4 As shown, in some embodiments, the display panel further includes a third conductive layer CT3, which is configured to shield the first electrode layer E1 (and a plurality of plasma particles, the second electrode layer) from interference from signals transmitted in the second conductive layer CT2 and / or the first conductive layer CT1. The presence of the third conductive layer CT3 is particularly important in plasma display technology because the thickness of the dam layer is relatively small. The inventors of this disclosure have discovered that by providing the third conductive layer CT3, crosstalk between the first electrode layer E1 (and a plurality of plasma particles, the second electrode layer) and the signal lines in the second conductive layer CT2 and / or the first conductive layer CT1 can be significantly reduced.

[0064] In some embodiments, the third conductive layer CT3 extends substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) through the display area of ​​the display panel. As used herein, the term "display area" refers to the area of ​​the display panel that actually displays an image. Optionally, the display area may include subpixel areas and inter-subpixel areas. A subpixel area refers to the light-emitting area of ​​a subpixel, for example, the area corresponding to a pixel electrode in a liquid crystal display or the area corresponding to a light-emitting layer in an organic light-emitting display. An inter-subpixel area refers to the area between adjacent subpixel areas, for example, the area corresponding to a black matrix in a liquid crystal display or the area corresponding to a pixel defining layer in an organic light-emitting display. Optionally, an inter-subpixel area is the area between adjacent subpixel areas within the same pixel. Optionally, an inter-subpixel area is the area between two adjacent subpixel areas of two adjacent pixels.

[0065] In some embodiments, the third conductive layer CT3 is configured to be supplied with a constant voltage. In one example, the third conductive layer CT3 is configured to be supplied with a ground voltage. In another example, the third conductive layer CT3 is configured to be supplied with a voltage at the same level as the voltage supplied to the second electrode layer.

[0066] Reference Figure 5 and Figure 6 In some embodiments, the display panel includes: a first substrate BS1; a driving plate DP located on the first substrate BS1; a first electrode layer E1 located on the side of the driving plate DP away from the first substrate BS1; a first weir layer DL1 and a second weir layer DL2 located on the side of the first electrode layer E1 away from the first substrate BS1; a second electrode layer E2 located on the side of the first weir layer DL1 and the second weir layer DL2 away from the first substrate BS1; and a second substrate BS2 located on the side of the second electrode layer E2 away from the first substrate BS1.

[0067] In some embodiments, the display panel includes a plurality of first weir structures DS1 in a first weir layer DL1. Each of the plurality of first weir structures DS1 surrounds a plurality of plasma particles PP in a corresponding sub-pixel of a plurality of sub-pixels Sp of the display panel. Optionally, the plurality of first weir structures DS1 are part of an integral structure. Optionally, the first weir layer DL1 is in direct contact with a first electrode layer E1 and in direct contact with a second electrode layer E2. Optionally, the first electrode layer E1, the second electrode layer E2, and the respective first weir structures encapsulate the plurality of plasma particles PP in the corresponding sub-pixel.

[0068] In some embodiments, a plurality of first weir structures DS1 surround plasma particles of a plurality of sub-pixels. Each first weir structure surrounds plasma particles of a corresponding sub-pixel. Optionally, the ratio of the total number of the plurality of first weir structures DS1 to the total number of the plurality of sub-pixels is in the range of 0.9:1 to 1.1:1, for example 1:1.

[0069] In some embodiments, the display panel further includes a plurality of second weir structures DS2 in a second weir layer DL2. Each first weir structure in a plurality of first weir structures DS1 surrounds a corresponding second weir structure in a plurality of second weir structures DS2. Each second weir structure surrounds at least a portion of a plurality of plasma particles PP in a corresponding sub-pixel. In some embodiments, a first portion of the plurality of plasma particles PP in a corresponding sub-pixel is surrounded by a corresponding second weir structure, and a second portion of the plurality of plasma particles PP in a corresponding sub-pixel is located between the corresponding second weir structure and the corresponding first weir structure. Optionally, the second weir layer DL2 is in direct contact with the first electrode layer E1 and the second electrode layer E2. Optionally, the first electrode layer E1, the second electrode layer E2, and each second weir structure encapsulate at least a portion of the plurality of plasma particles PP in a corresponding sub-pixel.

[0070] In some embodiments, a plurality of second weir structures DS2 respectively surround portions of plasma particles of a plurality of sub-pixels. Each second weir structure surrounds a portion of plasma particles of a corresponding sub-pixel. Optionally, the ratio of the total number of the plurality of second weir structures DS2 to the total number of the plurality of sub-pixels is in the range of 0.9:1 to 1.1:1, for example 1:1.

[0071] In some embodiments, the plurality of second weir structures DS2 are spaced apart from each other. Two adjacent second weir structures among the plurality of second weir structures DS2 are separated by a portion of a single first weir structure among the plurality of first weir structures DS1.

[0072] In some embodiments, the display panel is a plasma display panel. Each sub-pixel within the plasma display panel contains plasma, a gas-like state of matter with several distinct properties, particularly its electrical conductivity and responsiveness to electromagnetic fields. In some embodiments, the plurality of plasma particles PP comprise one or more inert gases. Examples of inert gases include neon (Ne) and xenon (Xe). These inert gases were chosen because of their stable inert properties and their ability to emit light upon ionization.

[0073] In some embodiments, plasma is generated when an inert gas within a sub-pixel is ionized. This ionization process involves applying a voltage to the gas, stripping electrons from the gas atoms, and producing a mixture of free electrons and ionized gas atoms (ions). Despite the presence of charged particles (electrons and ions), the plasma itself remains generally electrically neutral because it contains an equal number of positively charged ions and negatively charged electrons.

[0074] In some embodiments, during the addressing phase, each sub-pixel is controlled by applying a voltage to electrodes adjacent to or surrounding the sub-pixel (e.g., a first electrode layer E1 and a second electrode layer E2). This voltage is modulated to ionize the gas in a particular sub-pixel, depending on the image to be displayed. When the gas is ionized, it creates a plasma state within the sub-pixel. Free electrons and ions collide with each other and with neutral gas atoms, causing excitation. When these excited atoms and ions return to their ground state, they emit ultraviolet (UV) light. The specific wavelength of the UV light depends on the gas composition. The UV light emitted by the plasma interacts with a phosphor material coated inside the display panel. Different phosphors are used to generate red, green, and blue light corresponding to the three primary colors used in display technology. By controlling which sub-pixels are ionized and the intensity of the ionization, the display panel can mix various intensities of red, green, and blue light to produce the full spectrum of visible colors. After the addressing phase, a sustaining voltage can be applied to maintain the plasma state and thus sustain light emission from the sub-pixels. The erasure phase includes eliminating the ionization state and preparing subpixels for the next image frame.

[0075] The inventors of this disclosure have discovered that by setting a first dam layer DL1 and a second dam layer DL2, an independent encapsulation structure is formed within each sub-pixel, enabling the individual driving of plasma particles within each sub-pixel. When the display panel according to this disclosure is bent, the encapsulation structure deforms as a whole in the same direction under stress. Electrophoretic particles do not overflow with changes in external force, improving the stability of the displayed image. Furthermore, since the plasma within each sub-pixel is divided into two parts, the influence of the driving electric field between sub-pixels is reduced. Especially during the refresh of complex images, this prevents lateral movement of plasma particles between different sub-pixels under edge electric fields, avoiding particle polarization between sub-pixels. This enhancement significantly improves the refresh life of the product.

[0076] Figure 7 This is a plan view of a display panel according to some embodiments of the present disclosure. Figure 8 This is a cross-sectional view along line B-B' in section 7. (Refer to...) Figure 7 and Figure 8 In some embodiments, the display panel is a twisted nematic display panel. When the display panel is driven by a twisted nematic electric field, plasma particles are configured to move in a direction parallel to the electric field. The inventors of this disclosure have discovered that the aperture ratio of the display panel can affect the contrast level and reflectivity of the display panel. The inventors of this disclosure have discovered that, based on microframe region of interest (ROI) encoded video technology, as the aperture ratio increases to a certain level, the change in display effect exceeds the region of interest of the human eye. Further increases in the aperture ratio lead to a decrease in the sensitivity of the human eye to changes in white level L, making the difference less perceptible.

[0077] Reference Figure 7 and Figure 8 In some embodiments, the display panel includes: a first substrate BS1; a first conductive layer CT1 located on the first substrate BS1; a gate insulating layer GI located on the side of the first conductive layer CT1 away from the first substrate BS1; a second conductive layer CT2 located on the side of the gate insulating layer GI away from the first substrate BS1; a first passivation layer PVX1 located on the side of the second conductive layer CT2 away from the first substrate BS1; and a third conductive layer CT3 located on the side of the first passivation layer PVX1 away from the first substrate BS1. Two passivation layers PVX2 are located on the side of the third conductive layer CT3 away from the first substrate BS1; a first electrode layer E1 is located on the side of the second passivation layer PVX2 away from the first substrate BS1; a first weir layer DL1 and a second weir layer DL2 are located on the side of the first electrode layer E1 away from the first substrate BS1; a second electrode layer E2 is located on the side of the first weir layer DL1 and the second weir DL2 away from the first substrate BS1; and a second substrate BS2 is located on the side of the second electrode layer E2 away from the first substrate BS1.

[0078] In some embodiments, the first conductive layer CT1 includes a plurality of gate lines. In some embodiments, the second conductive layer CT2 includes a plurality of data lines. Figure 7 As shown, in some embodiments, the display panel further includes a third conductive layer CT3, which is configured to shield the first electrode layer E1 (and a plurality of plasma particles, the second electrode layer) from interference from signals transmitted in the second conductive layer CT2 and / or the first conductive layer CT1. The presence of the third conductive layer CT3 is particularly important in plasma display technology because the thickness of the dam layer is relatively small. The inventors of this disclosure have discovered that by providing the third conductive layer CT3, crosstalk between the first electrode layer E1 (and a plurality of plasma particles, the second electrode layer) and the signal lines in the second conductive layer CT2 and / or the first conductive layer CT1 can be significantly reduced.

[0079] In some embodiments, the display panel includes a plurality of first weir structures DS1 in a first weir layer DL1. Each of the plurality of first weir structures DS1 surrounds a plurality of plasma particles PP in a corresponding sub-pixel of a plurality of sub-pixels Sp of the display panel. Optionally, the plurality of first weir structures DS1 are part of an integral structure. Optionally, the first weir layer DL1 is in direct contact with a first electrode layer E1 and in direct contact with a second electrode layer E2. Optionally, the first electrode layer E1, the second electrode layer E2, and the respective first weir structures encapsulate the plurality of plasma particles PP in the corresponding sub-pixel.

[0080] In some embodiments, the display panel further includes a plurality of second weir structures DS2 in a second weir layer DL2. Each first weir structure in a plurality of first weir structures DS1 surrounds a corresponding second weir structure in a plurality of second weir structures DS2. Each second weir structure surrounds at least a portion of a plurality of plasma particles PP in a corresponding sub-pixel. In some embodiments, a first portion of the plurality of plasma particles PP in a corresponding sub-pixel is surrounded by a respective second weir structure, and a second portion of the plurality of plasma particles PP in a corresponding sub-pixel is located between the corresponding second weir structure and the corresponding first weir structure.

[0081] Figure 9 The optical effects of display panels with different aperture ratios are shown. Figure 9 Display panels with an aperture ratio of 73% (represented as "(a)"), 78% (represented as "(b)"), and 90% (represented as "(c)") are shown. See reference. Figure 9 With a 90% aperture ratio, the brightness of the white screen becomes similar to that of paper, satisfying the area of ​​interest for the human eye. Further increasing the white level has a relatively small impact on the white level L of the display panel. Figure 10 This illustrates the correlation between the white value of the display panel and the aperture ratio of the display panel. For example... Figure 10 As shown, the white value increases sharply and begins to stabilize, approaching the asymptote when it nears the 90% mark on the aperture ratio axis, indicating that the white value reaches its peak effectiveness at this point.

[0082] Figure 11 This is a schematic diagram illustrating a weir structure in a display panel according to some embodiments of the present disclosure. Figure 12 This is a schematic diagram illustrating a weir structure in a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 11 and Figure 12 The aperture ratio of the display panel is related to the width of the weir structure. The width of the weir structure can be adjusted to achieve the optimal aperture ratio.

[0083] In some embodiments, the aperture ratio of the display panel is in the range of 50% to 99%, for example, 50% to 55%, 55% to 60%, 60% to 65%, 65% to 70%, 70% to 75%, 75% to 80%, 80% to 85%, 85% to 90%, 90% to 95%, or 95% to 99%. In one example, the aperture ratio of the display panel is 90%.

[0084] Figure 13 This is a plan view of a display panel according to some embodiments of the present disclosure. Figure 14 This is a cross-sectional view along line C-C' in section 13. (Refer to...) Figure 13 and Figure 14In some embodiments, the display panel includes: a first substrate BS1; a driving plate DP located on the first substrate BS1; a first electrode layer E1 located on the side of the driving plate DP away from the first substrate BS1; a first weir layer DL1, a second weir layer DL2, and a third weir layer DL3 located on the side of the first electrode layer E1 away from the first substrate BS1; a second electrode layer E2 located on the side of the first weir layer DL1, the second weir layer DL2, and the third weir layer DL3 away from the first substrate BS1; and a second substrate BS2 located on the side of the second electrode layer E2 away from the first substrate BS1.

[0085] In some embodiments, the driver board DP includes a plurality of transistors configured to drive a plurality of sub-pixels Sp to emit light. In some embodiments, each of the plurality of transistors is connected to a corresponding first electrode block among a plurality of first electrode blocks in the first electrode layer E1.

[0086] In some embodiments, the display panel includes a plurality of first weir structures DS1 in a first weir layer DL1. Each of the plurality of first weir structures DS1 surrounds a plurality of plasma particles PP in a corresponding sub-pixel of a plurality of sub-pixels Sp of the display panel. Optionally, the plurality of first weir structures DS1 are part of an integral structure. Optionally, the first weir layer DL1 is in direct contact with a first electrode layer E1 and in direct contact with a second electrode layer E2. Optionally, the first electrode layer E1, the second electrode layer E2, and the respective first weir structures encapsulate the plurality of plasma particles PP in the corresponding sub-pixel.

[0087] In some embodiments, a plurality of first weir structures DS1 surround plasma particles of a plurality of sub-pixels. Each first weir structure surrounds plasma particles of a corresponding sub-pixel. Optionally, the ratio of the total number of the plurality of first weir structures DS1 to the total number of the plurality of sub-pixels is in the range of 0.9:1 to 1.1:1, for example 1:1.

[0088] In some embodiments, the display panel further includes a plurality of second weir structures DS2 in a second weir layer DL2. Each first weir structure in a plurality of first weir structures DS1 surrounds a corresponding second weir structure in a plurality of second weir structures DS2. Each second weir structure surrounds at least a portion of a plurality of plasma particles PP in a corresponding sub-pixel. Optionally, the second weir layer DL2 is in direct contact with a first electrode layer E1 and a second electrode layer E2. Optionally, the first electrode layer E1, the second electrode layer E2, and each second weir structure encapsulate at least a portion of the plurality of plasma particles PP in a corresponding sub-pixel.

[0089] In some embodiments, a plurality of second weir structures DS2 respectively surround portions of plasma particles of a plurality of sub-pixels. Each second weir structure surrounds a portion of plasma particles of a corresponding sub-pixel. Optionally, the ratio of the total number of the plurality of second weir structures DS2 to the total number of the plurality of sub-pixels is in the range of 0.9:1 to 1.1:1, for example 1:1.

[0090] In some embodiments, the display panel further includes a plurality of third weir structures DS3 in a third weir layer DL3. Each first weir structure in a plurality of first weir structures DS1 surrounds a corresponding second weir structure in a plurality of second weir structures DS2. Each second weir structure in a plurality of second weir structures DS2 surrounds a corresponding third weir structure in a plurality of third weir structures DS3. Each third weir structure surrounds at least a portion of a plurality of plasma particles PP in a corresponding sub-pixel. Optionally, the third weir layer DL3 is in direct contact with the first electrode layer E1 and the second electrode layer E2. Optionally, the first electrode layer E1, the second electrode layer E2, and each third weir structure encapsulate at least a portion of the plurality of plasma particles PP in a corresponding sub-pixel.

[0091] In some embodiments, a plurality of third weir structures DS3 respectively surround portions of plasma particles of a plurality of sub-pixels. Each third weir structure surrounds a portion of plasma particles of a corresponding sub-pixel. Optionally, the ratio of the total number of the plurality of third weir structures DS3 to the total number of the plurality of sub-pixels is in the range of 0.9:1 to 1.1:1, for example 1:1.

[0092] In some embodiments, a first portion of a plurality of plasma particles PP in each sub-pixel is surrounded by a corresponding third weir structure, a second portion of a plurality of plasma particles PP in each sub-pixel is located between the corresponding third weir structure and the corresponding second weir structure, and a third portion of a plurality of plasma particles PP in each sub-pixel is located between the corresponding second weir structure and the corresponding first weir structure.

[0093] In some embodiments, the plurality of second weir structures DS2 are spaced apart from each other. Two adjacent second weir structures among the plurality of second weir structures DS2 are separated by a portion of a single first weir structure among the plurality of first weir structures DS1.

[0094] In some embodiments, the plurality of third weir structures DS3 are spaced apart from each other. Two adjacent third weir structures DS3 are separated by a portion of a single first weir structure in the plurality of first weir structures DS1 and a portion of a single second weir structure in the plurality of second weir structures DS2.

[0095] Figure 15 This is a schematic diagram illustrating the structure of a first electrode layer, a first dam layer, and a second dam layer according to some embodiments of the present disclosure. (Refer to...) Figure 15In some embodiments, the first electrode layer includes a plurality of first electrode blocks E1B. Each of the plurality of first electrode blocks E1B is located in a corresponding sub-pixel of a plurality of sub-pixels Sp. (Refer to...) Figure 6 and Figure 15 In some embodiments, the orthographic projection of the first weir layer DL1 onto the substrate does not overlap with the orthographic projection of the first electrode layer onto the substrate at least partially (e.g., at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%). In some embodiments, the orthographic projection of the first weir layer DL1 onto the substrate does not overlap with the orthographic projection of the corresponding first electrode block in the plurality of first electrode blocks E1B onto the substrate at least partially (e.g., at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%). In some embodiments, the orthographic projection of each first weir structure on the substrate does not overlap with the orthographic projection of the corresponding first electrode block in the plurality of first electrode blocks E1B on the substrate at least partially (e.g., at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%).

[0096] In some embodiments, the orthographic projections of two adjacent first electrode blocks in the plurality of first electrode blocks E1B on the substrate are separated by the orthographic projection of a portion of the first weir layer DL1 on the substrate. In some embodiments, the orthographic projections of each first electrode block in the plurality of first electrode blocks E1B on the substrate are substantially (e.g., at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%) surrounded by the orthographic projections of the corresponding first weir structure in the plurality of first weir structures DS1 on the substrate.

[0097] In some embodiments, the orthographic projection of each of the plurality of first electrode blocks E1B onto the substrate substantially (e.g., at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%) covers the orthographic projection of the corresponding second weir structure of the plurality of second weir structures DS2 onto the substrate.

[0098] In some embodiments, the orthographic projection of the first dam layer on the substrate does not overlap with the orthographic projection of the second dam layer on the substrate. Optionally, the orthographic projections of the plurality of first dam structures DS1 on the substrate do not overlap with the orthographic projections of the plurality of second dam structures DS2 on the substrate.

[0099] In some embodiments, the orthographic projection of the second electrode layer onto the substrate substantially (e.g., at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%) covers the orthographic projection of the first dam layer onto the substrate. In some embodiments, the orthographic projection of the second electrode layer onto the substrate substantially (e.g., at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%) covers the orthographic projection of the second dam layer onto the substrate.

[0100] Figure 16 This is a schematic diagram illustrating the structure of a first electrode layer, a first dam layer, a second dam layer, and a third dam layer according to some embodiments of the present disclosure. (Refer to...) Figure 16 In some embodiments, the first electrode layer includes a plurality of first electrode blocks E1B. Each of the plurality of first electrode blocks E1B is located in a corresponding sub-pixel of a plurality of sub-pixels Sp. (Refer to...) Figure 14 and Figure 16 In some embodiments, the orthographic projection of the first weir layer DL1 onto the substrate does not overlap with the orthographic projection of the first electrode layer onto the substrate at least partially (e.g., at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%). In some embodiments, the orthographic projection of the first weir layer DL1 onto the substrate does not overlap with the orthographic projection of the corresponding first electrode block in the plurality of first electrode blocks E1B onto the substrate at least partially (e.g., at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%).

[0101] In some embodiments, the orthographic projections of two adjacent first electrode blocks in the plurality of first electrode blocks E1B on the substrate are separated by the orthographic projection of a portion of the first weir layer DL1 on the substrate. In some embodiments, the orthographic projections of each of the first electrode blocks in the plurality of first electrode blocks E1B on the substrate are substantially (e.g., at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%) surrounded by the orthographic projections of the corresponding first weir structure in the plurality of first weir structures DS1 on the substrate.

[0102] In some embodiments, the orthographic projection of each of the plurality of first electrode blocks E1B onto the substrate substantially (e.g., at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%) covers the orthographic projection of the corresponding second weir structure of the plurality of second weir structures DS2 onto the substrate.

[0103] In some embodiments, the orthographic projection of each of the plurality of first electrode blocks E1B onto the substrate substantially (e.g., at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%) covers the orthographic projection of the corresponding third weir structure of the plurality of third weir structures DS3 onto the substrate.

[0104] Each first weir structure may have a variety of suitable shapes. In some embodiments, each first weir structure has a ring structure in a cross-section parallel to a plane parallel to both the first and second substrates. Each second weir structure may have a variety of suitable shapes. In some embodiments, each second weir structure has a ring structure in a cross-section parallel to both the first and second substrates. Each third weir structure may have a variety of suitable shapes. In some embodiments, each third weir structure has a ring structure in a cross-section parallel to both the first and second substrates. As used herein, the term "ring" or "ring structure" refers to a structure or part of a structure having a hole through it. The ring structure may be formed of a square, rectangular, triangular, or other shape having a hole through it, or may be substantially circular, such as a doughnut. In some embodiments, the ring structure is formed as a square or rectangular shape having a hole through it. Optionally, the ring is a square ring. Optionally, the ring is a rectangular ring.

[0105] Various suitable materials can be used to manufacture the first weir layer DL1. Examples of suitable materials for manufacturing the first weir layer DL1 include polyimide, polycarbonate, polyethersulfone, polyethylene terephthalate, polyethylene naphthalate, polyaryl compounds, and fiber-reinforced plastics. Optionally, the first weir layer DL1 is made of a flexible material.

[0106] Various suitable materials can be used to manufacture the second weir layer DL2. Examples of suitable materials for manufacturing the second weir layer DL2 include polyimide, polycarbonate, polyethersulfone, polyethylene terephthalate, polyethylene naphthalate, polyaryl compounds, and fiber-reinforced plastics. Optionally, the second weir layer DL2 is made of a flexible material.

[0107] Various suitable materials can be used to manufacture the third dam layer DL3. Examples of suitable materials for manufacturing the third dam layer DL3 include polyimide, polycarbonate, polyethersulfone, polyethylene terephthalate, polyethylene naphthalate, polyaryl compounds, and fiber-reinforced plastics. Optionally, the third dam layer DL3 is made of a flexible material.

[0108] The first electrode layer can be fabricated using a variety of suitable materials and manufacturing methods. For example, non-metallic transparent electrode materials can be deposited on a substrate using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable non-metallic transparent electrode materials include, but are not limited to, various transparent metal oxide electrode materials and transparent carbon nanotubes. Examples of transparent metal oxide materials include, but are not limited to, indium tin oxide, indium zinc oxide, indium gallium oxide, and indium gallium zinc oxide.

[0109] The second electrode layer can be fabricated using a variety of suitable materials and manufacturing methods. For example, non-metallic transparent electrode materials can be deposited on a substrate using plasma-enhanced chemical vapor deposition (PECVD). Examples of suitable non-metallic transparent electrode materials include, but are not limited to, various transparent metal oxide electrode materials and transparent carbon nanotubes. Examples of transparent metal oxide materials include, but are not limited to, indium tin oxide, indium zinc oxide, indium gallium oxide, and indium gallium zinc oxide.

[0110] Reference Figure 15 In some embodiments, each first weir structure DS1 surrounds a first opening AP1, and each second weir structure DS2 surrounds a second opening AP2. In some embodiments, multiple sub-pixels are arranged in an array having multiple rows and columns. In some embodiments, each row of sub-pixels is arranged along a first direction DR1, and each column of sub-pixels is arranged along a second direction DR2.

[0111] In some embodiments, the first opening AP1 has a first average width w1 along the first direction DR1, and the second opening AP2 has a second average width w2 along the first direction DR1. In some embodiments, the ratio of the first average width w1 to the second average width w2 is in the range of 1.2:1 to 5:1, for example, 1.2:1 to 1.5:1, 1.5:1 to 2.0:1, 2.0:1 to 2.5:1, 2.5:1 to 3.0:1, 3.0:1 to 3.5:1, 3.5:1 to 4.0:1, 4.0:1 to 4.5:1, or 4.5:1 to 5.0:1.

[0112] Reference Figure 16In some embodiments, each first weir structure DS1 surrounds a first opening AP1, each second weir structure DS2 surrounds a second opening AP2, and each third weir structure DS3 surrounds a third opening AP3. In some embodiments, multiple sub-pixels are arranged in an array having multiple rows and columns. In some embodiments, each row of sub-pixels is arranged along a first direction DR1, and each column of sub-pixels is arranged along a second direction DR2.

[0113] In some embodiments, the first opening AP1 has a first average width w1 along the first direction DR1, the second opening AP2 has a second average width w2 along the first direction DR1, and the third opening AP3 has a third average width w3 along the first direction DR1. In some embodiments, the ratio of the first average width w1 to the second average width w2 is in the range of 1.2:1 to 5:1, for example, 1.2:1 to 1.5:1, 1.5:1 to 2.0:1, 2.0:1 to 2.5:1, 2.5:1 to 3.0:1, 3.0:1 to 3.5:1, 3.5:1 to 4.0:1, 4.0:1 to 4.5:1, or 4.5:1 to 5.0:1. In some embodiments, the ratio of the second average width w2 to the third average width w3 is in the range of 1.2:1 to 5:1, for example, 1.2:1 to 1.5:1, 1.5:1 to 2.0:1, 2.0:1 to 2.5:1, 2.5:1 to 3.0:1, 3.0:1 to 3.5:1, 3.5:1 to 4.0:1, 4.0:1 to 4.5:1, or 4.5:1 to 5.0:1.

[0114] Figure 17 This is a schematic diagram illustrating the structure of a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 17 In some embodiments, the display panel includes: a first substrate BS1; a driving board DP located on the first substrate BS1; a light-emitting module LEM located on the side of the driving board DP away from the first substrate BS1; a color filter CF located on the side of the light-emitting module LEM away from the first substrate BS1; and a second substrate BS2 located on the side of the color filter CF away from the first substrate BS1.

[0115] In some embodiments, the driver board DP includes a plurality of transistors configured to drive a plurality of sub-pixels Sp to emit light. In some embodiments, each of the plurality of transistors is connected to a corresponding first electrode block among a plurality of first electrode blocks in the first electrode layer E1.

[0116] In some embodiments, the light-emitting module (LEM) includes a plurality of light-emitting elements located in a plurality of sub-pixels (Sp). In some embodiments, the respective light-emitting element located in each sub-pixel includes a plurality of plasma particles (PP).

[0117] Figure 18 This is a schematic diagram illustrating various layers in a portion of a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 18 In some embodiments, the display panel includes: a first substrate BS1; a first conductive layer CT1 located on the first substrate BS1; a gate insulating layer GI located on the side of the first conductive layer CT1 away from the first substrate BS1; a second conductive layer CT2 located on the side of the gate insulating layer GI away from the first substrate BS1; a second passivation layer PVX2 located on the side of the second conductive layer CT2 away from the first substrate BS1; and a first electrode layer E1 located on the side of the second passivation layer PVX2 away from the first substrate BS1.

[0118] In some embodiments, the second conductive layer CT2 includes one or more electrode connection lines ECL.

[0119] In some embodiments, the display panel further includes one or more vias V extending through the second passivation layer PVX2. The first electrode layer E1 is connected to one or more electrode connection lines ECL in the second conductive layer CT2 through one or more vias V.

[0120] Figure 19 This is a plan view of a display panel according to some embodiments of the present disclosure. Figure 20 It is along Figure 19 A cross-sectional view of line D-D' in the diagram. (Refer to...) Figure 19 and Figure 20 In some embodiments, the display panel includes: a first substrate BS1; a driving plate DP located on the first substrate BS1; a first electrode layer E1 located on the side of the driving plate DP away from the first substrate BS1; a first weir layer DL1 and a second weir layer DL2 located on the side of the first electrode layer E1 away from the first substrate BS1; a second electrode layer E2 located on the side of the first weir layer DL1 and the second weir layer DL2 away from the first substrate BS1; and a second substrate BS2 located on the side of the second electrode layer E2 away from the first substrate BS1. In some embodiments, the display panel further includes a plurality of recesses RS, each of the plurality of recesses RS being at least partially recessed into the first electrode layer E1.

[0121] Figure 21 This is a schematic diagram illustrating the structure of a first electrode layer, a first dam layer, a second dam layer, and a plurality of recesses according to some embodiments of the present disclosure. (Refer to...) Figure 19 to Figure 21In some embodiments, the display panel includes a plurality of first weir structures DS1 in a first weir layer DL1. Each of the multiple first weir structures DS1 surrounds a plurality of plasma particles PP in a corresponding sub-pixel of a plurality of sub-pixels Sp of the display panel. Optionally, the plurality of first weir structures DS1 are part of an integral structure. Optionally, the first weir layer DL1 is in direct contact with a first electrode layer E1 and a second electrode layer E2. Optionally, the first electrode layer E1, the second electrode layer E2, and the respective first weir structures encapsulate the plurality of plasma particles PP in the corresponding sub-pixel.

[0122] In some embodiments, a plurality of first weir structures DS1 surround plasma particles of a plurality of sub-pixels. Each first weir structure surrounds plasma particles of a corresponding sub-pixel. Optionally, the ratio of the total number of the plurality of first weir structures DS1 to the total number of the plurality of sub-pixels is in the range of 0.9:1 to 1.1:1, for example 1:1.

[0123] In some embodiments, the display panel further includes a plurality of second weir structures DS2 in a second weir layer DL2. Each first weir structure in a plurality of first weir structures DS1 surrounds a corresponding second weir structure in a plurality of second weir structures DS2. Each second weir structure surrounds at least a portion of a plurality of plasma particles PP in a corresponding sub-pixel. In some embodiments, a first portion of the plurality of plasma particles PP in each sub-pixel is surrounded by a corresponding second weir structure, and a second portion of the plurality of plasma particles PP in each sub-pixel is located between the corresponding second weir structure and the corresponding first weir structure. Optionally, the second weir layer DL2 is in direct contact with the first electrode layer E1 and the second electrode layer E2. Optionally, the first electrode layer E1, the second electrode layer E2, and each second weir structure encapsulate at least a portion of the plurality of plasma particles PP in a corresponding sub-pixel.

[0124] In some embodiments, a plurality of second weir structures DS2 respectively surround portions of plasma particles of a plurality of sub-pixels. Each second weir structure surrounds a portion of plasma particles of a corresponding sub-pixel. Optionally, the ratio of the total number of the plurality of second weir structures DS2 to the total number of the plurality of sub-pixels is in the range of 0.9:1 to 1.1:1, for example 1:1.

[0125] In some embodiments, the orthographic projection of each of the plurality of second weir structures DS2 onto the substrate BS surrounds the orthographic projection of the corresponding recess in the plurality of recesses RS onto the substrate BS.

[0126] In some embodiments, the plurality of second weir structures DS2 are spaced apart from each other. Two adjacent second weir structures among the plurality of second weir structures DS2 are separated by a portion of a single first weir structure among the plurality of first weir structures DS1.

[0127] The inventors of this disclosure have discovered that by setting a first weir layer DL1 and a second weir layer DL2, an independent encapsulation structure is formed within each sub-pixel, enabling individual driving of plasma particles within each sub-pixel. Each first weir structure is inserted into the gap between adjacent first electrode blocks, preventing plasma particles from flowing between adjacent sub-pixels. This unique structure reduces coupling crosstalk effects between adjacent first electrode blocks, avoids the blooming issue caused by small gaps between adjacent first electrode blocks, and improves display quality. Each second weir structure surrounds a corresponding recess, thereby separating the corresponding recessed area. Plasma particles with higher response speeds can be provided to the area surrounded by each second weir structure, preventing white spot defects caused by insufficient first electrode driving due to step differences caused by individual recesses.

[0128] In some embodiments, a first portion of a plurality of plasma particles PP in each sub-pixel is surrounded by a respective second weir structure, and a second portion of the plurality of plasma particles PP in each sub-pixel is located between a corresponding second weir structure and a corresponding first weir structure. In some embodiments, the first portion of the plurality of plasma particles PP has a higher response speed than the second portion of the plurality of plasma particles PP.

[0129] Figure 22 This is a plan view of a display panel according to some embodiments of the present disclosure. Figure 23 This is a cross-sectional view along line E-E' in section 22. (Refer to...) Figure 22 and Figure 23 In some embodiments, the display panel includes: a first substrate BS1; a first conductive layer CT1 located on the first substrate BS1; a gate insulating layer GI located on the side of the first conductive layer CT1 away from the first substrate BS1; a second conductive layer CT2 located on the side of the gate insulating layer GI away from the first substrate BS1; a first passivation layer PVX1 located on the side of the second conductive layer CT2 away from the first substrate BS1; a third conductive layer CT3 located on the side of the first passivation layer PVX1 away from the first substrate BS1; and a second passivation layer PVX2 located on the third conductive layer CT3. The first electrode layer E1 is located on the side of the second passivation layer E2 away from the first substrate BS1; the third passivation layer PVX3 is located on the side of the second passivation layer PVX2 away from the first substrate BS1; the first electrode layer E1 is located on the side of the third passivation layer PVX3 away from the first substrate BS1; the first dam layer DL1 and the second dam layer DL2 are located on the side of the first electrode layer E1 away from the first substrate BS1; the second electrode layer E2 is located on the side of the first dam layer DL1 and the second dam layer DL2 away from the first substrate BS1; and the second substrate BS2 is located on the side of the second electrode layer E2 away from the first substrate BS1.

[0130] In some embodiments, the first conductive layer CT1 includes a plurality of gate lines. In some embodiments, the second conductive layer CT2 includes a plurality of data lines. Figure 23 As shown, in some embodiments, the display panel further includes a third conductive layer CT3, which is configured to shield the first electrode layer E1 (and a plurality of plasma particles, the second electrode layer) from interference from signals transmitted in the second conductive layer CT2 and / or the first conductive layer CT1. The presence of the third conductive layer CT3 is particularly important in plasma display technology because the thickness of the dam layer is relatively small. The inventors of this disclosure have discovered that by providing the third conductive layer CT3, crosstalk between the first electrode layer E1 (and a plurality of plasma particles, the second electrode layer) and the signal lines in the second conductive layer CT2 and / or the first conductive layer CT1 can be significantly reduced.

[0131] In some embodiments, the display panel includes a plurality of first weir structures DS1 in a first weir layer DL1. Each of the plurality of first weir structures DS1 surrounds a plurality of plasma particles PP in a corresponding sub-pixel of a plurality of sub-pixels Sp of the display panel. Optionally, the plurality of first weir structures DS1 are part of an integral structure. Optionally, the first weir layer DL1 is in direct contact with a first electrode layer E1 and in direct contact with a second electrode layer E2. Optionally, the first electrode layer E1, the second electrode layer E2, and the respective first weir structures encapsulate the plurality of plasma particles PP in the corresponding sub-pixel.

[0132] In some embodiments, the display panel further includes a plurality of second weir structures DS2 in a second weir layer DL2. Each first weir structure in a plurality of first weir structures DS1 surrounds a corresponding second weir structure in a plurality of second weir structures DS2. Each second weir structure surrounds at least a portion of a plurality of plasma particles PP in a corresponding sub-pixel. In some embodiments, a first portion of the plurality of plasma particles PP in a respective sub-pixel is surrounded by a corresponding second weir structure, and a second portion of the plurality of plasma particles PP in a respective sub-pixel is located between the corresponding second weir structure and the corresponding first weir structure.

[0133] In some embodiments, the display panel further includes a plurality of recesses RS. Each of the plurality of recesses RS is at least partially recessed into one or more passivation layers. In one example, each recess is at least partially recessed into a third passivation layer PVX3. In another example, each recess is recessed into the third passivation layer PVX3 and at least partially recessed into a second passivation layer PVX2. In another example, each recess is recessed into the third passivation layer PVX3, recessed into the second passivation layer PVX2, and at least partially recessed into a first passivation layer PVX1. In yet another example, each recess is recessed into the third passivation layer PVX3, recessed into the second passivation layer PVX2, and recessed into the first passivation layer PVX1.

[0134] In some embodiments, each of the plurality of recesses RS is recessed into one or more passivation layers and at least partially recessed into a third conductive layer CT3. In one example, each recess is recessed into a third passivation layer PVX3, a second passivation layer PVX2, a first passivation layer PVX1, and at least partially recessed into a third conductive layer CT3. In another example, each recess is recessed into a third passivation layer PVX3, a second passivation layer PVX2, a first passivation layer PVX1, and a third conductive layer CT3.

[0135] In some embodiments, the orthographic projection of each of the plurality of second weir structures DS2 onto the substrate BS surrounds the orthographic projection of the corresponding recess in the plurality of recesses RS onto the substrate BS.

[0136] In some embodiments, a first portion of a plurality of plasma particles PP in each sub-pixel is surrounded by a corresponding second weir structure, and a second portion of the plurality of plasma particles PP in each sub-pixel is located between the corresponding second weir structure and the corresponding first weir structure. In some embodiments, the first portion of the plurality of plasma particles PP has a higher response speed than the second portion of the plurality of plasma particles PP.

[0137] Figure 24 The electric field and particle polarization are shown in a related display panel without a weir structure. (Refer to...) Figure 24 In a display panel without a weir structure, the edge electric field between different sub-pixels includes both horizontal and vertical components. In this case, the horizontal electric field between sub-pixels is relatively strong, and the particle polarization effect between sub-pixels is relatively large. The inventors of this disclosure have discovered that prolonged particle polarization can reduce the refresh lifetime of particles.

[0138] Figure 25 The electric field and particle polarization are shown in the relevant display panel, which only shows the first dam structure. (Refer to...) Figure 25 Compared to Figure 24 The display panel depicted in the image shows a relatively weak horizontal particle polarization effect between subpixels. However, due to thickness differences caused by the recesses within the subpixels, a significant difference in electric field was observed between the recessed and non-recessed areas. This non-uniform distribution of the electric field within the subpixels leads to a stronger particle effect, affecting the particle refresh lifespan.

[0139] Figure 26 The electric field and particle polarization in a display panel according to some embodiments of the present disclosure are illustrated. (Refer to...) Figure 26 By separating the concave and non-concave regions within a sub-pixel, the influence of the horizontal electric field affecting particle polarization within the pixel is reduced, further improving the refresh lifetime of the particles.

[0140] When the same external force is applied to the display panel, the larger the contact area between the dam structure and the electrode layer, the more contact points there are. Due to the external force, the smaller the diffusion range of plasma particles within each individual space defined by the dam structure, the better the stability of the display panel. This helps improve the overall pressure resistance of the display panel, especially for flexible display panels.

[0141] The inventors of this disclosure have discovered that the display panel and display device of this disclosure have several advantages over related display panels. First, the structure having multiple first weir structures and multiple second weir structures (and optionally multiple third weir structures) significantly reduces the influence of the edge electric field on particle polarization, thereby extending the refresh life of plasma particles. Second, by arranging each second weir structure around a corresponding recess, the electric field difference caused by the thickness difference of one or more layers between the recessed and non-recessed regions is reduced, reducing the occurrence of white spot defects at via locations, and also reducing the impact of non-uniform electric field driving within sub-pixels on the refresh life of particles. Third, due to the advantages of its multi-point packaging design, the structure of the display panel and display device of this disclosure increases the contact area between the electrodes and the weir structures. Particularly for large-size display panels and / or flexible display panels, this structure can prevent deformation of the weir structures due to external pressure on the display panel, thereby avoiding the problem of display discoloration.

[0142] On the other hand, this disclosure provides a display device including a display panel described herein or manufactured by the methods described herein, and one or more integrated circuits connected to the display panel. Figure 27 This is a schematic diagram illustrating the structure of a display device according to some embodiments of the present disclosure. (Refer to...) Figure 27 In some embodiments, the display device includes a display panel DPL, a first driver board DB1 connected to the display panel DPL, and a second driver board DB2 connected to the display panel DPL.

[0143] In some embodiments, the first driver board DB1 includes one or more first integrated circuits IC1 connected to the display panel DPL. In one example, the one or more first integrated circuits IC1 are one or more data driver integrated circuits.

[0144] In some embodiments, the first driver board DB1 further includes a timing controller TC, which is configured to set the timing to provide clock signals sequentially.

[0145] In some embodiments, the second driver board DB2 includes one or more second integrated circuits IC2 connected to the display panel DPL. In one example, the one or more second integrated circuits IC2 are one or more touch integrated circuits.

[0146] In some embodiments, the display device further includes a touch structure configured to detect touch. In some embodiments, the touch structure is a mutual capacitance touch structure. In some embodiments, the touch structure includes a plurality of first touch electrodes TE1 and a plurality of second touch electrodes TE2.

[0147] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. A display panel, comprising: First substrate; The first electrode layer is located on the first substrate. The first weir layer and the second weir layer are located on the first electrode layer; The second electrode layer is located on the side of the first dam layer and the second dam layer away from the first substrate. as well as The second substrate is located on the side of the second electrode layer away from the first substrate. The first weir layer includes multiple first weir structures; The second weir layer includes multiple second weir structures; Each of the plurality of first weir structures surrounds a plurality of plasma particles in a corresponding sub-pixel of a plurality of sub-pixels. Each of the first weir structures surrounds a corresponding second weir structure among the plurality of second weir structures; and The corresponding second weir structure surrounds at least a portion of the plurality of plasma particles in the corresponding sub-pixel.

2. The display panel according to claim 1, wherein, The first portion of the plurality of plasma particles in the corresponding sub-pixel is surrounded by the corresponding second weir structure, and the second portion of the plurality of plasma particles in the corresponding sub-pixel is located between the corresponding second weir structure and the corresponding first weir structure.

3. The display panel according to claim 1, wherein, The multiple first weir structures are part of the overall structure.

4. The display panel according to claim 1, wherein, The first weir layer is in direct contact with the first electrode layer and also in direct contact with the second electrode layer; The first electrode layer, the second electrode layer, and each of the first weir structures encapsulate the plurality of plasma particles in the corresponding sub-pixel; The second weir layer is in direct contact with the first electrode layer and also in direct contact with the second electrode layer; as well as The first electrode layer, the second electrode layer, and each second weir structure encapsulate at least a portion of the plurality of plasma particles in the respective sub-pixel.

5. The display panel according to claim 1, wherein, The multiple second weir structures are spaced apart from each other; as well as Two adjacent second weir structures in the plurality of second weir structures are separated by a portion of a single first weir structure in the plurality of first weir structures.

6. The display panel according to any one of claims 1 to 5, wherein, The first electrode layer includes a plurality of first electrode blocks; and Each of the plurality of first electrode blocks is located in a corresponding sub-pixel.

7. The display panel according to claim 6, wherein, The orthographic projection of the first weir layer on the substrate does not overlap with the orthographic projection of the first electrode layer on the substrate at least partially; as well as The orthographic projection of each of the first weir structures on the substrate does not at least partially overlap with the orthographic projection of the corresponding first electrode block among the plurality of first electrode blocks on the substrate.

8. The display panel according to claim 6, wherein, The orthographic projections of two adjacent first electrode blocks on the substrate are separated by the orthographic projection of a portion of the first weir layer on the substrate. as well as The orthographic projection of each of the plurality of first electrode blocks on the substrate is substantially surrounded by the orthographic projection of the corresponding first weir structure on the substrate.

9. The display panel according to claim 6, wherein, The orthographic projection of each of the plurality of first electrode blocks on the substrate substantially covers the orthographic projection of the corresponding second weir structure on the substrate.

10. The display panel according to any one of claims 1 to 9, wherein, Each of the first weir structures surrounds the first opening; Each of the second weir structures surrounds the second opening; The multiple sub-pixels are arranged in an array with multiple rows and columns; Each row of sub-pixels is arranged along the first direction; Each column of sub-pixels is arranged along the second direction; The first opening has a first average width along the first direction; The second opening has a second average width along the first direction; as well as The ratio of the first average width to the second average width is in the range of 1.2:1 to 5:

1.

11. The display panel according to any one of claims 1 to 10, comprising: A first conductive layer is located on the first substrate. A gate insulating layer is located on the side of the first conductive layer away from the first substrate. The second conductive layer is located on the side of the gate insulating layer away from the first substrate. A first passivation layer is located on the side of the second conductive layer away from the first substrate. A third conductive layer is located on the side of the first passivation layer away from the first substrate. as well as The second passivation layer is located on the side of the third conductive layer away from the first substrate. Wherein, the first electrode layer is located on the side of the second passivation layer away from the first substrate; and The third conductive layer is configured to be supplied with a constant voltage.

12. The display panel according to any one of claims 1 to 10, comprising: A first conductive layer is located on the first substrate. A gate insulating layer is located on the side of the first conductive layer away from the first substrate. The second conductive layer is located on the side of the gate insulating layer away from the first substrate. as well as The second passivation layer is located on the side of the second conductive layer away from the first substrate. Wherein, the first electrode layer is located on the side of the second passivation layer away from the first substrate; and The second conductive layer includes one or more electrode connection lines; The display panel further includes one or more vias extending through at least the second passivation layer; and The first electrode layer is connected to the one or more electrode connection lines in the second conductive layer through the one or more vias.

13. The display panel according to any one of claims 1 to 12, wherein, The orthographic projection of the first weir layer on the substrate does not overlap with the orthographic projection of the second weir layer on the substrate. as well as The orthographic projections of the plurality of first weir structures on the substrate do not overlap with the orthographic projections of the plurality of second weir structures on the substrate.

14. The display panel according to any one of claims 1 to 13, further comprising a plurality of recesses; in, The orthographic projection of each of the plurality of second weir structures on the first substrate surrounds the orthographic projection of the corresponding recess among the plurality of recesses on the first substrate.

15. The display panel according to claim 14, wherein, The first portion of the plurality of plasma particles in the corresponding sub-pixel is surrounded by the corresponding second weir structure; The second portion of the plurality of plasma particles in the corresponding sub-pixel is located between the corresponding second weir structure and the corresponding first weir structure; and The first portion of the plurality of plasma particles has a higher response speed than the second portion of the plurality of plasma particles.

16. The display panel according to claim 14, wherein, Each of the recesses is at least partially recessed into one or more passivation layers.

17. The display panel according to any one of claims 1 to 16, wherein, The ratio of the total number of multiple first weir structures to the total number of multiple sub-pixels is in the range of 0.9:1 to 1.1:

1.

18. The display panel according to any one of claims 1 to 17, wherein, The ratio of the total number of multiple second weir structures to the total number of multiple sub-pixels is in the range of 0.9:1 to 1.1:

1.

19. The display panel according to any one of claims 1 to 18, wherein, The aperture ratio of the display panel is in the range of 85% to 95%.

20. A display device comprising a display panel according to any one of claims 1 to 19, and one or more integrated circuits connected to the display panel.

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