Low-cost stable dry etching method and dry etching system for semiconductor cooler

Abstract

The invention discloses a low-cost stable dry etching method and dry etching system for a semiconductor cooler, and belongs to the field of integrated circuit manufacturing, and the method comprises the following steps: S1, taking a wafer which is subjected to metal patterning and photoresist removal; s2, mounting the wafer which is subjected to metal patterning and photoresist removal on a wafer bearing table, and placing the wafer bearing table in a dry etching working cavity; s3, the plasma particles impact one surface, facing the ion particles, of the wafer which is subjected to metal patterning and photoresist removal in a mode that the plasma particles move in the horizontal direction, and etching is carried out; the wafer bearing table comprises a rotary table and a wafer carrier, the wafer carrier is located in a cavity of the rotary table, the wafer carrier comprises a frame structure, the wafer bearing table further comprises an anti-dry-etching film layer, and the anti-dry-etching film layer is not consumed when being impacted by plasma particles. The back sputtering phenomenon caused by the fact that the surface of the cavity bottom of the concave cavity is etched to be rough is fundamentally eradicated, and the cleanliness and the yield of the back face of a product are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and more specifically, to a low-cost, stable dry etching method and dry etching system for semiconductor coolers. Background Technology

[0002] Semiconductor coolers (TECs) can be directly integrated into microsystems to provide active thermal management for temperature-sensitive components such as high-density chips, lasers, and sensors, solving the heat dissipation problem in compact spaces. Direct and rapid local temperature control significantly improves the performance stability and reliability of integrated devices, making it an indispensable solution for thermal management of miniaturized electronic systems. Dry etching is a key step in the fabrication process of TEC (semiconductor cooler) integrated circuit structures.

[0003] Current etching processes for semiconductor coolers involve etching a wafer that has already been patterned with metal and had its resist removed, such as... Figure 1 The seed metal is etched away within the working chamber 1 of the etching system. Figure 1 In the etching system, the working cavity 1 has an opening 2 on its cavity wall that communicates with the plasma generation cavity. The working cavity 1 is equipped with a gate system 4 and a wafer carrier stage 3. The gate system 4 is located between the opening 2 communicating with the plasma generation cavity and the wafer carrier stage 3. The wafer carrier stage 3 includes a turntable 5 and a wafer carrier 6. The wafer carrier 6 is located inside the turntable 5 (the wafer carrier 6 and the turntable 5 are integrated). The wafer that has been patterned with metal and has had its resist removed is installed in the wafer carrier 6 of the wafer carrier stage 3. During the dry etching process, the wafer carrier 6, the gate system 4, the turntable 5, and the wafer carrier 6 are all in a vertical state. The plasma etching particles coming from the gate system 4 collide with the vertical wafer surface in a horizontal motion.

[0004] Figure 2 and Figure 3 The top view of the wafer carrier 6 and the turntable 5 when they are placed horizontally. Figure 3 for Figure 2 The cross-sectional structure diagram of AA shows that the existing wafer carrier 6 includes a frame structure 7, which includes several longitudinal beams 8, several transverse beams 9, and several grid-like recesses 10 formed by the interconnection and intersection of the longitudinal beams 8 and the transverse beams 9. During dry etching, the wafer is installed in the recesses 10, with one recess 10 corresponding to one wafer.

[0005] The existing wafer carrier 6 has the following shortcomings: In the initial stage of use, the longitudinal beams 8 and transverse beams 9 of the frame structure 7 are in their initial state. After the wafer is mounted in the cavity 10, there is essentially no gap between the edge of the wafer and the longitudinal beams 8 or transverse beams 9. However, as dry etching progresses, plasma etching particles not only impact the surface of the wafer but also indiscriminately impact the surfaces of the longitudinal beams 8 or transverse beams 9, consuming the metal of these beams. The longer the wafer carrier 6 is used, the greater the consumption, and the rougher and more uneven the longitudinal beams 8 or transverse beams 9 become. This alters the size and shape of the cavity 10, rendering the wafer carrier 6 unusable. Typically, a new wafer carrier stage 3 needs to be replaced every 3 to 4 weeks. More seriously, the uneven surface of the longitudinal beams 8 or transverse beams 9 leads to two serious problems: First, the contact between the wafer and the wafer carrier 6 is no longer tight and uniform, resulting in uneven heat dissipation on the back side and affecting the etching effect. Second, and more fatally, the uneven surface of the wafer carrier 6 can trigger "backsputtering." The material atoms of the ejected wafer carrier 6 will redeposit on the back side of the wafer (partially visible at the bottom of the cavity 10), causing contamination, directly leading to product failure and reduced yield.

[0006] The above background information is provided to facilitate understanding of the present invention and is not intended to be publicly known technology disclosed to the general public prior to the application of this invention. Summary of the Invention

[0007] To address the aforementioned problems, this invention provides a low-cost, stable dry etching method and system for semiconductor coolers, fundamentally eliminating backsplashing caused by the rough etching of the cavity bottom surface, and significantly improving the cleanliness and yield of the product back side.

[0008] A low-cost, stable dry etching method for semiconductor coolers includes the following steps: S1, take the wafer that has been patterned with metal and has had its resist removed; S2, mount the wafer that has been patterned with metal and stripped of resist onto the wafer carrier stage, and place the wafer carrier stage into the dry etching working cavity; S3, plasma particles impact the side of the wafer that has been patterned and stripped of resist in a horizontal direction to etch the seed metal layer that is not covered by the patterned metal layer. The wafer carrier stage includes a turntable and a wafer carrier. The wafer carrier is located inside the cavity of the turntable. The wafer carrier includes a frame structure, which includes several longitudinal beams, several transverse beams, and several grid-like recesses formed by the interconnection and intersection of the longitudinal beams and transverse beams. The wafers that have been patterned with metal and have had their resist removed are installed in the recesses. The wafer carrier stage also includes an anti-drying coating layer, which is not consumed by plasma particle impact.

[0009] Optionally, the thickness of the anti-drying coating layer is 7.5 μm to 150 μm.

[0010] Optionally, the electrical breakdown strength of the anti-drying film layer is 100 kV / mm to 280 kV / mm, the tensile strength is 150 MPa to 400 MPa, and the Elmendorf tear strength is >5 N / mm.

[0011] Optionally, the anti-drying coating layer is made of aromatic polymer synthetic adhesive.

[0012] Optionally, the anti-drying film layer is formed by coating or thermal lamination.

[0013] Optionally, the anti-drying coating layer covers the upper surface of the area of ​​the turntable and wafer carrier where the metal patterning has not been completed and the resist has been removed.

[0014] Optionally, the anti-drying coating layer covers the upper surface of both the crossbeam and the longitudinal beam.

[0015] Optionally, the wafer that has been metal patterned and stripped of resist includes a ceramic substrate, the upper surface of which is covered with a seed metal layer, and a metal pattern layer is disposed on the seed metal layer.

[0016] The present invention also provides a dry etching system.

[0017] A dry etching system is provided for implementing the aforementioned low-cost and stable dry etching method. The dry etching system includes a wafer carrier stage, which includes a turntable, a wafer carrier, and an anti-dry etching film layer. The wafer carrier is located within the cavity of the turntable and includes a frame structure. The frame structure includes a plurality of longitudinal beams, a plurality of transverse beams, and a plurality of grid-like recesses formed by the interconnection and intersection of the longitudinal beams and transverse beams. The wafer is mounted in the recesses.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows: With the addition of the anti-drying etching layer, this invention eliminates the need for frequent replacement of the wafer stage. Even if the anti-drying etching layer is damaged due to aging or improper handling during wafer patterning and resist removal, only the anti-drying etching layer needs to be reformed, without replacing the wafer stage. More importantly, this invention fundamentally eliminates back sputtering caused by rough etching of the cavity bottom surface, significantly improving the cleanliness and yield of the product's back side.

[0019] This invention also improves the wafer uniformity and yield of the product by using different coating methods for the anti-drying coating layer. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the etching system structure in the background art of this invention; Figure 2 This is a top view of a wafer carrier mounted horizontally on a turntable, which is part of the background technology of this invention. Figure 3 This is in the background art of the present invention Figure 2 A schematic diagram of the cross-sectional structure of AA; Figure 4 In this invention Figure 2 A schematic diagram of a cross-sectional structure of AA; Figure 5 In this invention Figure 2 A schematic diagram of another cross-sectional structure of AA; Figure 6 This is a schematic diagram of the structure of a wafer that has been patterned with metal and has had its resist removed. Explanation of reference numerals in the attached drawings: 1. Working cavity, 2. Through port, 3. Wafer carrier stage, 4. Gate system, 5. Turntable, 6. Wafer carrier, 7. Frame structure, 8. Longitudinal beam, 9. Cross beam, 10. Cavity, 11. Anti-drying coating layer, 12. Wafer with completed metal patterning and resist removed, 13. Ceramic substrate, 14. Seed metal layer, 15. Metal patterning layer. Detailed Implementation

[0022] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, an indirect connection via an intermediate medium, or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0023] In the description of this invention, it should be understood that the terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In the description of this invention, "a plurality of" means two or more, unless otherwise precisely specified.

[0024] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0027] like Figure 2 , Figure 4 A wafer carrier stage 3 includes a turntable 5 and a wafer carrier 6. The wafer carrier 6 is located in the cavity of the turntable 5. The wafer carrier 6 includes a frame structure 7, which includes a plurality of longitudinal beams 8, a plurality of transverse beams 9, and a plurality of grid-like recesses 10 formed by the interconnection and intersection of the plurality of longitudinal beams 8 and the plurality of transverse beams 9. The wafer carrier stage 3 also includes an anti-dry etching layer 11, which covers the waferless areas of the turntable 5 and the wafer carrier 6. The anti-dry etching layer 11 is not consumed when bombarded by plasma particles.

[0028] In one or more specific embodiments of the present invention, the anti-drying film layer 11 is made of aromatic polymer synthetic adhesive, which can be purchased from the market.

[0029] In one or more embodiments of the present invention, the anti-drying film layer 11 can be formed on the fable-free area of ​​the wafer carrier 3 by coating or by thermal lamination.

[0030] In one or more embodiments of the present invention, the thickness of the anti-drying film layer 11 is 7.5 μm to 150 μm.

[0031] In one or more specific embodiments of the present invention, in order to balance anti-drying and service life, the electrical breakdown strength of the anti-drying film layer 11 is 100 kV / mm~280 kV / mm, the tensile strength is 150 MPa~400 MPa, and the Elmendorf tear strength is >5 N / mm.

[0032] like Figure 2 , Figure 5 A wafer carrier stage 3 includes a turntable 5 and a wafer carrier 6. The wafer carrier 6 is located in the cavity of the turntable 5. The wafer carrier 6 includes a frame structure 7, which includes a plurality of longitudinal beams 8, a plurality of transverse beams 9, and a plurality of grid-like recesses 10 formed by the interconnection and intersection of the plurality of longitudinal beams 8 and the plurality of transverse beams 9. The wafer carrier stage 3 also includes an anti-drying etching layer 11, which covers the upper surfaces of the transverse beams 9 and the longitudinal beams 8. The anti-drying etching layer 11 is not consumed when bombarded by plasma particles.

[0033] In one or more specific embodiments of the present invention, the anti-drying film layer 11 is made of aromatic polymer synthetic adhesive, which can be purchased from the market.

[0034] In one or more embodiments of the present invention, the anti-drying film layer 11 can be formed on the upper surfaces of the crossbeam 9 and the longitudinal beam 8 by coating or by thermal lamination.

[0035] In one or more embodiments of the present invention, the thickness of the anti-drying film layer 11 is 7.5 μm to 150 μm.

[0036] In one or more specific embodiments of the present invention, in order to balance anti-drying and service life, the electrical breakdown strength of the anti-drying film layer 11 is 100 kV / mm~280 kV / mm, the tensile strength is 150 MPa~400 MPa, and the Elmendorf tear strength is >5 N / mm.

[0037] Example 1 A low-cost, stable dry etching method for semiconductor coolers includes the following steps: S1, take wafer 12 that has been patterned with metal and has had its resist removed, such as Figure 6 The wafer 12, which has been patterned and stripped of its adhesive, includes a ceramic substrate 13. The upper surface of the ceramic substrate 13 is covered with a seed metal layer 14, and a metal pattern layer 15 is disposed on the seed metal layer 14.

[0038] S2, mount the patterned and de-adhesive-removed wafer 12 onto the... Figure 1 Working chamber 1 Figure 2 , Figure 4 The cavity 10 of the wafer carrier stage 3.

[0039] S3, plasma particles pass through Figure 1 After the gate system 4 is formed, the wafer carrier stage 3 is impacted on the side facing the ion particles (the ion particles move in a horizontal direction) to perform etching, which etches the seed metal layer 14 that is not covered by the metal pattern layer 15, and also etches a certain thickness of the metal pattern layer 15.

[0040] Example 2 Compared with Example 1, the only difference is that in S2, the wafer 12, which has been patterned with metal and has had its resist removed, is mounted on a location located Figure 1 Working chamber 1 Figure 2 , Figure 5 The cavity 10 of the wafer carrier stage 3.

[0041] The low-cost, stable dry etching method using the semiconductor cooler of Examples 1 and 2 etches a wafer 12 that has completed metal patterning and has had its resist removed. Because the anti-dry etching layer 11 is not consumed by plasma particle impact during the dry etching process, there is no metal loss on the longitudinal beam 8 or the transverse beam 9, and the cavity 10 does not deform. Therefore, there is no need to frequently replace the wafer carrier stage 3. Even if the anti-dry etching layer 11 is damaged due to aging or improper operation when etching the wafer 12, it is only necessary to reformat the anti-dry etching layer 11. More importantly, since there is no metal loss on the longitudinal beam 8 or the transverse beam 9, there is no gap between the cavity 10 and the wafer 12 that has completed metal patterning and has had its resist removed. The bottom of the cavity 10 always remains flat and smooth, fundamentally eliminating the back sputtering phenomenon caused by the rough etching of the bottom surface of the cavity 10, and significantly improving the cleanliness and yield of the back side of the product.

[0042] Compared with the dry etching method of Example 1 and Example 2, the product after dry etching using the anti-dry etching film layer 11 method in Example 1 has poorer wafer uniformity and lower yield than the product after dry etching using the anti-dry etching film layer 11 method in Example 2.

[0043] In this invention, the plasma can be, for example, Ar+, F-, etc., with Ar+ being preferred.

[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low-cost, stable dry etching method for a semiconductor cooler, characterized in that, Includes the following steps: S1, take the wafer that has been patterned with metal and has had its resist removed; S2, mount the wafer that has been patterned with metal and stripped of resist onto the wafer carrier stage, and place the wafer carrier stage into the dry etching working cavity; S3, plasma particles impact the side of the wafer that has been patterned and stripped of resist in a horizontal direction to etch the seed metal layer that is not covered by the patterned metal layer. The wafer carrier stage includes a turntable and a wafer carrier. The wafer carrier is located inside the cavity of the turntable. The wafer carrier includes a frame structure, which includes several longitudinal beams, several transverse beams, and several grid-like recesses formed by the interconnection and intersection of the longitudinal beams and transverse beams. The wafers that have been patterned with metal and have had their resist removed are installed in the recesses. The wafer carrier stage also includes an anti-drying coating layer, which is not consumed by plasma particle impact.

2. The low-cost, stable dry etching method for a semiconductor cooler according to claim 1, characterized in that, The thickness of the anti-drying coating layer is 7.5 μm to 150 μm.

3. The low-cost, stable dry etching method for semiconductor coolers according to claim 2, characterized in that, The electrical breakdown strength of the anti-drying film layer is 100kV / mm~280kV / mm, the tensile strength is 150MPa~400MPa, and the Elmendorf tear strength is >5 N / mm.

4. The low-cost, stable dry etching method for a semiconductor cooler according to claim 3, characterized in that, The anti-drying coating layer is made of aromatic polymer synthetic adhesive.

5. The low-cost, stable dry etching method for a semiconductor cooler according to any one of claims 1-4, characterized in that, The anti-drying film layer is formed by coating or thermal lamination.

6. The low-cost, stable dry etching method for a semiconductor cooler according to any one of claims 1-4, characterized in that, The anti-drying coating layer covers the upper surface of the area of ​​the turntable and wafer carrier where the metal patterning of the wafer has not been completed and the resist has been removed.

7. The low-cost, stable dry etching method for a semiconductor cooler according to claim 1, characterized in that, The anti-drying coating layer covers the upper surface of the crossbeam and the longitudinal beam.

8. The low-cost, stable dry etching method for a semiconductor cooler according to claim 1, characterized in that, The wafer that has been patterned and stripped of its adhesive includes a ceramic substrate, the upper surface of which is covered with a seed metal layer, and a metal pattern layer is disposed on the seed metal layer.

9. A dry etching system, characterized in that, This dry etching system is specifically designed to implement the low-cost, stable dry etching method as described in any one of claims 1-8. The dry etching system includes a wafer carrier stage, which includes a turntable, a wafer carrier, and an anti-dry etching film layer. The wafer carrier is located within the cavity of the turntable and includes a frame structure. The frame structure includes several longitudinal beams, several transverse beams, and several grid-like recesses formed by the interconnection and intersection of the longitudinal beams and transverse beams. The wafer is mounted in the recesses.

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