Fault diagnosis method, diagnosis device, and fault diagnosis apparatus

Abstract

The application provides a fault diagnosis method, a diagnosis device and a fault diagnosis equipment, and relates to the technical field of fault diagnosis. The fault diagnosis method comprises the following steps: in response to a model selection for a to-be-tested computing force board, a test firmware corresponding to the model of the to-be-tested computing force board is acquired, and a test interface corresponding to the to-be-tested computing force board is displayed; and in response to a detection operation for the to-be-tested computing force board, the test firmware is run, and the working state of the to-be-tested computing force board is determined. The application realizes efficient fault diagnosis through an automatic test process and a user interaction interface, and can improve efficiency and accuracy and reduce manual dependence.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of fault diagnosis, in particular to a fault diagnosis method, a diagnosis device and a fault diagnosis equipment. BACKGROUND

[0002] In the maintenance practice of the blockchain server, the maintenance process highly depends on manual operation, and the maintenance personnel need to detect the electronic component-intensive and complex structure of the computing power board manually by means of special tools, and check the fault points one by one. The detection process is time-consuming and long, and the positioning accuracy is insufficient. SUMMARY

[0003] The main purpose of the present application is to provide a fault diagnosis method, which aims to improve the fault diagnosis efficiency, reduce the dependence on manual operation, and improve the diagnosis accuracy.

[0004] To achieve the above purpose, the present application provides a fault diagnosis method applied to a fault diagnosis equipment, wherein the fault diagnosis equipment comprises a connection interface, and the connection interface is used for accessing a to-be-tested computing power board. The fault diagnosis method comprises the following steps:

[0005] In response to a model selection for the to-be-tested computing power board, a test firmware corresponding to the model of the to-be-tested computing power board is acquired, and a test interface corresponding to the to-be-tested computing power board is displayed.

[0006] In response to a detection operation for the to-be-tested computing power board, the test firmware is run, and the working state of the to-be-tested computing power board is determined.

[0007] Optionally, in response to the detection operation for the to-be-tested computing power board, the test firmware is run, and the working state of the to-be-tested computing power board is determined, which comprises the following steps:

[0008] In response to the detection operation, the test firmware is loaded and started to run.

[0009] A first detection signal in the test firmware is acquired, and the first detection signal is sent to the to-be-tested computing power board.

[0010] A response signal fed back by the to-be-tested computing power board is monitored, the working state of the to-be-tested computing power board is determined according to the comparison between the response signal and a preset normal response mode, and the working state is displayed on the test interface.

[0011] Optionally, the first detection signal is sent to the to-be-tested computing power board, and the specific process is as follows:

[0012] The chip code sequence of each chip corresponding to the to-be-tested computing power board is acquired.

[0013] According to a chip space layout topology sequence represented by the chip coding sequence and a signal transmission timing rule, the first detection signal is sequentially transmitted to the corresponding chip.

[0014] Optionally, the sending the first detection signal to the to-be-tested computing force board comprises:

[0015] Obtaining a chip array hardware topology architecture of the to-be-tested computing force board, and extracting physical address identification information of each chip in the chip array hardware topology architecture;

[0016] According to a signal transmission path determined by the physical address identification information, the first detection signal is transmitted to the corresponding chip in parallel.

[0017] Optionally, the monitoring the response signal fed back by the to-be-tested computing force board, comparing the response signal with a preset normal response mode, determining a working state of the to-be-tested computing force board, and displaying the working state on the test interface, comprises:

[0018] Timing analysis and level feature extraction are performed on the response signal to obtain high and low level duration periods and jump edge distribution of the response signal.

[0019] The high and low level duration periods and the jump edge distribution are matched with timing characteristics in the preset normal response mode one by one to generate a corresponding matching result.

[0020] If the matching result contains a mismatched item, it is determined that an abnormal chip exists in the to-be-tested computing force board, and the corresponding abnormal chip position and fault type are determined according to the mismatched item, and the abnormal chip position and fault type are displayed on the test interface.

[0021] If the matching result is consistent, it is determined that the working state of the to-be-tested computing force board is normal, and a normal operation identifier is displayed on the test interface.

[0022] Optionally, the connection interface has a control signal end for accessing a controllable direct current power supply, and an output end of the controllable direct current power supply is connected with a power input end of the to-be-tested computing force board.

[0023] After the test interface corresponding to the to-be-tested computing force board is displayed in response to the selection of the type of the to-be-tested computing force board, the method further comprises:

[0024] In response to an adjustment instruction for the electrical parameter, the power supply voltage, the power supply current and the delay time output by the controllable direct current power supply are adjusted.

[0025] In response to the detection operation on the to-be-tested computing force board, the test firmware is run, comprising:

[0026] In response to the detection operation on the to-be-tested computing power board, the controllable direct-current power supply is controlled to supply power to the to-be-tested computing power board according to the adjusted power supply voltage and power supply current, and a corresponding first detection signal is sent to the to-be-tested computing power board, and the power supply connection between the controllable direct-current power supply and the to-be-tested computing power board is disconnected within a delay time after the to-be-tested computing power board returns response data.

[0027] Optionally, the fault diagnosis method further comprises:

[0028] The working state of each detection is recorded, and the detection time sequence, the running state of each chip and the detection times in each record are extracted to generate a corresponding detection log;

[0029] The computing power board model data and the test data corresponding to each detection record in the detection log are obtained;

[0030] In response to a query instruction for the detection log, the computing power board model data and the test data are called and arranged in a corresponding time sequence, and then displayed on the test interface.

[0031] Optionally, the fault diagnosis method further comprises:

[0032] If the working state is abnormal, the abnormal chip, the abnormal position and the fault type in the computing power board are obtained;

[0033] The computing power board effect diagram corresponding to the to-be-tested computing power board is displayed, and the abnormal position is marked on the computing power board effect diagram;

[0034] In response to a selection operation on the abnormal position on the computing power board effect diagram, the fault type corresponding to the abnormal position and the recommended repair scheme are displayed.

[0035] In addition, to achieve the above-mentioned purposes, the present application also provides a diagnosis device, which comprises a memory, a processor and a fault diagnosis program stored in the memory and executable on the processor, and the fault diagnosis program is configured to implement the fault diagnosis method as described above.

[0036] In addition, to achieve the above-mentioned purposes, the present application also provides a fault diagnosis device, which comprises:

[0037] A display component is configured to present a test interface and a working state of a to-be-tested computing power board;

[0038] A connection interface is configured to access a to-be-tested computing power board; and

[0039] A diagnosis device as described above is electrically connected to the display component and the connection interface, respectively.

[0040] The diagnostic device is used to acquire test firmware corresponding to the model of the to-be-tested computing board in response to the user selecting the model of the to-be-tested computing board on the display component, and display a test interface corresponding to the to-be-tested computing board on the display component;

[0041] The diagnostic device is also used to run the test firmware in response to the user performing a detection operation on the to-be-tested computing board on the display component, and determine the working state of the to-be-tested computing board.

[0042] The fault diagnosis method of the embodiment of the application is applied to a fault diagnosis device, which comprises a connection interface for connecting a to-be-tested computing board, wherein the fault diagnosis method is used to acquire test firmware corresponding to the model of the to-be-tested computing board in response to selection of the model of the to-be-tested computing board, display a test interface corresponding to the to-be-tested computing board, run the test firmware in response to a detection operation on the to-be-tested computing board, and determine the working state of the to-be-tested computing board. In this way, efficient fault diagnosis is achieved through an automatic test process and a user interaction interface, which can improve efficiency and accuracy and reduce dependence on manual operation. BRIEF DESCRIPTION OF DRAWINGS

[0043] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application.

[0044] Figure 1 The figure is a flowchart of the fault diagnosis method of the embodiment of the application;

[0045] Figure 2 The figure is a flowchart of the method of step S200 in the embodiment of the application; Figure 1 The figure is a flowchart of the method of step S200 in the embodiment of the application;

[0046] Figure 3 The figure is a flowchart of the method of step S220 in the embodiment of the application; Figure 2 The figure is a flowchart of the method of step S220 in the embodiment of the application;

[0047] Figure 4 The figure is a flowchart of the fault diagnosis method of the embodiment of the application;

[0048] Figure 5 The figure is a flowchart of the method of step S230 in the embodiment of the application; Figure 2 The figure is a flowchart of the method of step S230 in the embodiment of the application;

[0049] Figure 6 The figure is a flowchart of the fault diagnosis method of the embodiment of the application;

[0050] Figure 7 The figure is a flowchart of the fault diagnosis method of the embodiment of the application;

[0051] Figure 8A flowchart of a fault diagnosis method according to an embodiment of the present application.

[0052] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0053] In the maintenance practice of the blockchain server, the fault diagnosis process of the existing technology algorithm board highly depends on manual operation. The maintenance personnel must manually locate the chip position according to the circuit diagram, and measure the voltage, signal and other parameters of each chip one by one with the help of a multimeter and other special tools. Then, the measurement data is analyzed to determine whether the fault exists according to the personal experience. This operation mode leads to extremely low test efficiency. When dealing with batch fault equipment, the maintenance cycle is significantly prolonged, which is difficult to meet the demand of rapid response. At the same time, the accuracy of fault positioning is seriously limited by the experience level of the operator. Due to the lack of standardized judgment basis, misjudgment or omission is frequent, which affects the reliability of the diagnosis result. In addition, this method requires high professional accomplishment of the operator, and long-term accumulation of circuit knowledge and practical experience is needed to complete the diagnosis task independently, which makes the personnel training cycle long and the cost high, which is not conducive to the rapid formation and capacity improvement of the maintenance team. The most prominent problem is the insufficient compatibility of the existing test tools. The special equipment is usually only suitable for a single brand or a specific type of algorithm board. When facing cross-brand or different types of algorithm boards, the tool must be frequently replaced and the test process must be reconfigured. The operation steps are complicated and prone to errors, which further reduces the overall test efficiency.

[0054] The main solution of the embodiment of the present application is: in response to the selection of the model of the to-be-tested algorithm board, the test firmware corresponding to the model of the to-be-tested algorithm board is acquired, and the test interface corresponding to the to-be-tested algorithm board is displayed. In response to the detection operation of the to-be-tested algorithm board, the test firmware is run, and the working state of the to-be-tested algorithm board is determined.

[0055] In the present embodiment, for the convenience of description, the following describes the diagnosis device as the execution subject.

[0056] The present application provides a solution, which realizes efficient fault diagnosis through automatic test process and user interaction interface, can improve efficiency and accuracy, and reduce manual dependence.

[0057] To this end, the present application proposes a fault diagnosis method; it can be understood that the fault diagnosis device is provided with a diagnosis device for storing and executing the following method, and the diagnosis device can be realized by a main controller such as MCU (Microcontroller Unit), DSP (Digital Signal Process), FPGA (Field Programmable Gate Array), SOC (System On Chip) and the like.

[0058] In the fault diagnosis process of the computing board, the prior art relies on manual operation for parameter measurement. The process involves manual positioning of chip location by the operator against the circuit diagram, and collecting voltage and signal data point by point through a special test tool. Then, the fault state is judged based on individual experience. Among them, the diagnosis efficiency is subject to the serial processing characteristics of manual operation, the fault positioning accuracy is limited by the operator's mastery of circuit knowledge, the operation threshold is significantly improved due to the need for long-term experience accumulation, and the hardware adaptation mechanism of the test tool leads to the non-universalization of the diagnosis process of computing boards across brands or types, thereby causing the overall diagnosis cycle of the system to be prolonged, the resource utilization rate to be reduced, and the availability of the equipment to be decreased.

[0059] For example, in the daily maintenance scene of a data center server cluster, maintenance personnel need to detect multiple fault computing boards of different brands. At this time, the physical location of each chip must be identified one by one according to the circuit diagram, and the voltage value and signal timing characteristics of each chip pin are measured using a multimeter and other tools. When dealing with new models of computing boards, the operator needs to replace the special test tool and re-familiarize himself with its operation specifications, resulting in frequent interruptions in the diagnosis process. In addition, due to the subjective bias of manual data reading, the voltage measurement results of the same chip are inconsistent among different operators, which further leads to fault misjudgment. The complexity of the chip space layout in this manual data reading scenario makes it difficult to accurately track the signal transmission path, and the operator cannot efficiently verify the multi-chip cooperative working state, ultimately resulting in a long diagnosis process and insufficient result reliability.

[0060] If the above problems are not solved, the computing board diagnosis process will be limited by the inherent defects of manual operation for a long time, the equipment downtime will continue to increase, the maintenance resources will be inefficiently occupied, and the overall stability of the system will be negatively affected. In addition, the fluctuation of the diagnosis results caused by the skill difference of the operators will expand the uncertainty of fault repair, hinder the standardized implementation of the maintenance process, thereby increasing the complexity of equipment management and pushing up the long-term operation and maintenance cost.

[0061] To this end, with reference to Figure 1In an embodiment of the present application, the fault diagnosis method is applied to a fault diagnosis device, which comprises a connection interface for connecting to a to-be-tested computing power board. The fault diagnosis method comprises steps S100-S200, wherein:

[0062] S100, in response to a model selection for the to-be-tested computing power board, obtaining a test firmware corresponding to the model of the to-be-tested computing power board, and displaying a test interface corresponding to the to-be-tested computing power board;

[0063] S200, in response to a detection operation for the to-be-tested computing power board, running the test firmware to determine the working state of the to-be-tested computing power board.

[0064] The fault diagnosis device refers to a hardware and software integrated system specially designed to execute the fault diagnosis method. The device usually contains an interface for physical or logical connection with the to-be-tested device, as well as a processing unit and a display unit for running the diagnosis program, processing data and displaying the results. The connection interface refers to the port or module on the fault diagnosis device for establishing physical or logical connection with the external to-be-tested device (such as a computing power board or a power supply or a fan). The interface can realize the transmission of data, signals or power, and is the bridge for information exchange between the fault diagnosis device and the to-be-tested device. The fault diagnosis device is configured with a connection interface designed to physically or logically connect to the to-be-tested computing power board. For example, the connection interface can be a universal serial bus (USB) interface that connects different types of computing power boards through an adapter; or the connection interface can be a special slot with multiple pins, which requires manual insertion of the to-be-tested computing power board. The to-be-tested computing power board refers to the computing power unit that needs to be diagnosed. The computing power board usually contains multiple computing chips, storage units and related circuits and interfaces, and its working state directly affects the performance of the entire blockchain server.

[0065] The model selection refers to the process of identifying and matching the specific model of the to-be-tested computing power board by the user or the system. Through model selection, it can be ensured that the subsequent diagnosis process and test parameters are consistent with the specifications of the to-be-tested computing power board, improving the accuracy of diagnosis. The test firmware refers to the diagnosis program specially designed and compiled for a specific model of to-be-tested computing power board. The test firmware is loaded into the fault diagnosis device for running, which evaluates the functions and performance of the to-be-tested computing power board by sending specific detection signals to it and receiving its responses. The test interface refers to the graphical user interface on the fault diagnosis device for showing the diagnosis process, real-time data and diagnosis results to the user. The test interface usually provides operation buttons, state indicators and information display areas to facilitate user interaction and obtain diagnosis information.

[0066] The detection operation refers to the instruction or action of the user starting the fault diagnosis process through the test interface or an automated program. This operation triggers the running of the test firmware, thereby starting the systematic detection of the connected to-be-tested computing board. The working state refers to the running condition of the to-be-tested computing board after the detection operation. The state can be normal running, existence of partial abnormality, or complete failure, etc., which is the final determination result of the fault diagnosis method.

[0067] In the fault diagnosis process, in response to the model selection of the to-be-tested computing board, the diagnosis device is configured to obtain the test firmware corresponding to the model of the to-be-tested computing board. The model selection can be realized in various ways. For example, the user can manually input the model code of the to-be-tested computing board on the fault diagnosis equipment, the diagnosis device retrieves the matched test firmware from the local storage or remote server according to the code, or selects the corresponding model option on the test interface and matches the corresponding test firmware; or automatically reads the identification information such as the device serial number or model label built-in the to-be-tested computing board, automatically identifies through the communication protocol, and calls the corresponding test firmware from the database. Or the diagnosis device presets a firmware list, and the user selects the firmware corresponding to the model of the to-be-tested computing board from the list.

[0068] In the process of obtaining the test firmware, the diagnosis device is configured to display the test interface corresponding to the to-be-tested computing board. The test interface can be a general diagnosis interface, the layout and function of which are the same for all models of computing boards, and only the specific data is adapted when displayed. Or the test interface can be a preset template interface, and corresponding interface elements and display areas are loaded according to the model of the computing board selected by the user.

[0069] Subsequently, in response to the detection operation of the to-be-tested computing board, the diagnosis device is configured to run the test firmware. The detection operation can be triggered by the user by clicking the "start detection" button on the test interface. After receiving the instruction, the fault diagnosis equipment will load and execute the test firmware obtained previously. The running of the test firmware can be a simple sequential execution process, which sends detection signals one by one according to the preset instruction set and waits for responses.

[0070] Finally, after the test firmware is run, the diagnosis device is configured to determine the working state of the to-be-tested computing board. The determination of the working state can be realized in various ways. For example, the test firmware collects the response data of the to-be-tested computing board during the running process, and compares these data with the preset normal threshold. If all data is within the normal range, it is determined that the working state is normal; if any data exceeds the threshold, it is determined that the working state is abnormal. The determination result is then displayed on the test interface.

[0071] In one specific implementation of the present embodiment, assume that on a certain production line, a batch of newly produced computing power boards need to be pre-shipment quality tested to ensure their normal working state. The fault diagnosis method of the present embodiment is applied to a fault diagnosis device which is placed beside the production line.

[0072] First, when a to-be-tested computing power board is placed on the fault diagnosis device by a production line worker, the to-be-tested computing power board is connected through a connection interface on the fault diagnosis device. For example, the connection interface can be a customized slot to ensure that the to-be-tested computing power board is correctly physically connected.

[0073] Subsequently, user A sees a prompt on the display screen of the fault diagnosis device to select the model of the to-be-tested computing power board. User A selects “Model X” on the test interface according to the identification on the to-be-tested computing power board. In response to the model selection, the processor inside the fault diagnosis device automatically acquires the test firmware corresponding to “Model X” from its memory. In addition, a test interface specially designed for “Model X” is immediately presented on the display screen, which can include the layout diagram of the computing power board of “Model X”, the indication of key detection points, and the “Start Detection” button, etc.

[0074] Next, user A clicks the “Start Detection” button on the test interface to trigger the detection operation on the to-be-tested computing power board. After receiving the operation instruction, the fault diagnosis device immediately starts the previously acquired “Model X” test firmware. The test firmware starts sending a series of preset detection signals to the to-be-tested computing power board, such as sending initialization instructions, data read-write instructions, or function test instructions to each chip of the computing power board through the connection interface. After receiving these instructions, the to-be-tested computing power board will respond according to its internal logic and feed back the response signals to the fault diagnosis device through the connection interface.

[0075] During the running of the test firmware, the fault diagnosis device continuously monitors and collects the response signals fed back by the to-be-tested computing power board. The test firmware analyzes and processes these response signals in real time, such as comparing the timing, level, data content, etc. of the signals with the normal working mode of “Model X”. Based on these comparison results, the fault diagnosis device finally determines the working state of the to-be-tested computing power board. For example, if all detection items conform to the normal mode, the working state is determined as “normal”; if the response signal of a certain chip is abnormal, the working state is determined as “abnormal” and the type of the abnormality can be indicated. Finally, the determined working state (e.g. “normal operation” or “chip A abnormality”) is clearly displayed on the test interface for user A to view.

[0076] Through the above process, the fault diagnosis method of the present embodiment realizes the automatic and standardized detection of computing power boards, without the need for manual point-by-point measurement and experience-based judgment, thereby improving the detection efficiency and accuracy.

[0077] In combination with the above-mentioned embodiments, in the prior art, the detection of the computing power board is highly dependent on the experience and manual operation of maintenance personnel, for example, manual comparison with circuit diagrams to locate the chip position, and the use of multimeters and other tools to detect voltage and signals point by point. This method not only has low efficiency, resulting in a long maintenance cycle for batch fault equipment, but also the accuracy of fault location is limited by the experience level of the operator.

[0078] In contrast, the present embodiment improves the diagnosis efficiency by introducing an automatic process of model selection, test firmware and test interface. In the above-mentioned embodiments, user A only needs to simply select the model and trigger the detection operation, and the fault diagnosis equipment can automatically obtain the matching test firmware and run without manual intervention in complex detection steps. This automatic process avoids the time-consuming manual measurement and judgment link in the traditional method, making it possible to quickly detect a large number of computing power boards.

[0079] In addition, the present embodiment improves the accuracy of fault diagnosis by pre-setting the test firmware and the standardized response signal comparison mechanism. The test firmware is designed to accurately detect the computing power board of a specific model, and the detection logic and normal response mode contained in it are strictly verified. This is in contrast to the method of relying on the personal experience of maintenance personnel for judgment in the prior art, effectively reducing human error and ensuring the objectivity and consistency of the diagnosis results.

[0080] Furthermore, the present embodiment reduces the operation threshold. In the above example, user A does not need to have deep circuit knowledge or years of maintenance experience, but only needs to make a simple model selection and operation trigger according to the instructions of the test interface to complete the diagnosis. This is in sharp contrast to the situation in the prior art where maintenance personnel need to accumulate years of industry experience to operate independently, shortening the personnel training period and reducing labor costs.

[0081] Finally, the present embodiment improves the compatibility of the fault diagnosis equipment through the model selection mechanism. The fault diagnosis equipment can dynamically load the corresponding test firmware and test interface according to different computing power board models, which means that one device can adapt to computing power boards of multiple brands and models without the need to replace special tools as in the prior art, thereby simplifying the operation process and improving the universality of the device.

[0082] The fault diagnosis method of the present embodiment effectively solves the problems of low efficiency, low precision, high operation threshold and low compatibility in the prior art through the technical concept of automation, standardization and intelligentization, and provides an efficient, accurate and easy-to-operate solution for the fault diagnosis of computing power boards.

[0083] The fault diagnosis method of the embodiment is applied to a fault diagnosis device, which comprises a connection interface for accessing a to-be-tested computing board. The fault diagnosis method acquires test firmware corresponding to the model of the to-be-tested computing board in response to selection of the model of the to-be-tested computing board, displays a test interface corresponding to the to-be-tested computing board, and determines the working state of the to-be-tested computing board by running the test firmware in response to a detection operation on the to-be-tested computing board. In this way, efficient fault diagnosis is achieved through an automated test process and a user interaction interface, which can improve efficiency and accuracy and reduce manual dependence.

[0084] Optionally, with reference to Figure 2 Another embodiment of the present application provides a fault diagnosis method based on the above Figure 1 In response to a detection operation on the to-be-tested computing board, the test firmware is run to determine the working state of the to-be-tested computing board, and the method comprises steps S210-S230, wherein:

[0085] S210, in response to the detection operation, loading the test firmware and starting running;

[0086] S220, acquiring a first detection signal in the test firmware and sending the first detection signal to the to-be-tested computing board;

[0087] S230, monitoring a response signal fed back by the to-be-tested computing board, comparing the response signal with a preset normal response mode, determining the working state of the to-be-tested computing board, and displaying the working state on the test interface.

[0088] In response to the detection operation, the test firmware is loaded and started to run, which aims to ensure that the test firmware is activated when needed and starts to perform a predetermined detection process. For example, the user can click a "start detection" button on the test interface to trigger the system to load and run the firmware; or the diagnosis device automatically loads and starts the firmware after receiving an external instruction (for example, through API calling).

[0089] The first detection signal in the test firmware is acquired and sent to the to-be-tested computing board, which aims to generate a specific excitation signal from the test firmware for detecting the function and response of the to-be-tested computing board. A series of detection signals can be preset in the test firmware, which are generated in sequence or on demand during running and sent to the to-be-tested computing board through the signal pins of the connection interface. In addition, the test firmware can also dynamically generate or read the first detection signal from the memory according to the model of the to-be-tested computing board and the current test stage, and send it to the to-be-tested computing board through a specific communication protocol (for example, SPI, I2C, JTAG, etc.).

[0090] The response signal fed back by the to-be-tested computing power board is monitored, which serves to capture the feedback of the to-be-tested computing power board to the first detection signal, which is the basis for judging the working state thereof. The fault diagnosis device can listen to and collect the electrical signal output by the to-be-tested computing power board in real time through the receiving pin of the connection interface. Alternatively, the fault diagnosis device can be configured with a high-speed data acquisition module, which can synchronously monitor the digital or analog signal returned by the to-be-tested computing power board within a specific time window.

[0091] The response signal is compared with the preset normal response mode, which serves to identify abnormal behavior by comparing with the known normal behavior mode. For example, the waveform, timing, and level characteristics of the collected response signal can be compared with the normal response mode of the computing power board of this type stored in the database point by point or by characteristics. For another example, as an upgraded version, the pattern recognition algorithm or machine learning model can be used to analyze the feature vector of the response signal and evaluate the matching degree with the pre-trained normal mode.

[0092] The working state of the to-be-tested computing power board is determined, which serves to draw a conclusion that the to-be-tested computing power board is normal or abnormal. This can be directly judged according to whether there is a mismatch item in the comparison result or whether the matching degree is lower than the threshold. In addition, the final working state can also be determined by comprehensively evaluating through logical judgment or decision tree model based on the response comparison results of multiple detection signals.

[0093] The working state is displayed on the test interface, which serves to intuitively present the diagnosis result to the user. For example, it can be displayed in the form of text (such as “normal” and “abnormal”) or color (such as green for normal and red for abnormal) in a specific area of the test interface. Alternatively, the real-time working state of the to-be-tested computing power board can be displayed through a graphical interface, such as a progress bar, a status indicator icon, or a detailed diagnosis report.

[0094] The scheme of the present application first loads and starts the test firmware in response to the detection operation on the to-be-tested computing power board, then generates and sends the first detection signal to the to-be-tested computing power board by the firmware, then monitors the response signal fed back by the to-be-tested computing power board, and finally determines the working state of the to-be-tested computing power board according to the comparison between the response signal and the preset normal response mode and displays it on the test interface. In this way, the fault diagnosis device can accurately obtain the internal running information of the to-be-tested computing power board and judge its health condition based on rigorous comparison logic. This makes the diagnosis process no longer a black box operation, but has clear input, output and judgment basis, greatly improving the accuracy and reliability of the diagnosis.

[0095] In an implementation form of the embodiment, it is assumed that the user selects the model of the accessed to-be-tested computing power board on the test interface of the fault diagnosis device, and the diagnosis device obtains and displays the corresponding test interface. When the user clicks the "start detection" button on the test interface, the fault diagnosis device responds to the detection operation, loads the test firmware matched with the to-be-tested computing power board into the processor inside the device and starts running. The test firmware generates a specific digital signal sequence as the first detection signal, for example, a read-write test sequence for testing the integrity of the memory bus, and sends it to the corresponding pin of the to-be-tested computing power board through the connection interface. The fault diagnosis device also continuously monitors the feedback, i.e., the response signal, of the to-be-tested computing power board to the read-write test sequence through the connection interface. The device compares the timing and level characteristics of the collected response signal with the response mode of the to-be-tested computing power board in the normal working state stored in advance. If the comparison result shows that the response signal is completely consistent with the normal mode, it is determined that the to-be-tested computing power board is in a normal working state, and the "normal operation" identifier is displayed on the test interface. If there is an inconsistent item in the comparison result, for example, the read-back data of a certain memory address does not match the expectation, it is determined that the to-be-tested computing power board has an abnormality, and the "abnormality" identifier is displayed on the test interface, and the corresponding abnormal type is prompted.

[0096] By the above technical solution, the abstract steps of running the test firmware and determining the working state in the fault diagnosis process are refined into specific signal interaction, data comparison and result presentation processes, so that the fault diagnosis device can perform more in-depth and accurate detection on the computing power board. This detailed diagnosis process can effectively identify the potential faults or abnormal behaviors of the to-be-tested computing power board, improving the accuracy and reliability of fault diagnosis. In addition, the working state is displayed on the test interface, so that the operator can quickly understand the diagnosis result, thereby improving the efficiency of fault troubleshooting and user experience.

[0097] In actual fault diagnosis process, the to-be-tested computing power board usually contains multiple chips. How to ensure that the first detection signal can be accurately and efficiently transmitted to each target chip in the to-be-tested computing power board, and considering the complex connection and signal transmission characteristics between chips, is a key challenge to realize accurate diagnosis. If the signal transmission method is improper, it may lead to low detection efficiency or failure to accurately identify the specific faulty chip.

[0098] Therefore, with reference to Figure 3 , another embodiment of the present application provides a fault diagnosis method based on the above Figure 2 indicated embodiment, the first detection signal is sent to the to-be-tested computing power board, specifically steps S221-S222, wherein:

[0099] S221, obtaining the chip code sequence of each chip corresponding to the to-be-tested computing power board;

[0100] S222, based on the chip space layout topology order represented by the chip code sequence and the signal transmission timing rules, the first detection signal is transmitted to the corresponding chip in turn.

[0101] Wherein, obtaining the chip code sequence of each chip in the to-be-tested computing force board is to identify and obtain the unique identification information of each chip on the to-be-tested computing force board by a specific way. These chip code sequences can include the model, batch, production date or internal unique ID of the chip, etc. Its role is to provide accurate addressing basis for subsequent signal transmission, and ensure that the detection signal can be sent to the expected target chip. For example, the fault diagnosis equipment can obtain these code sequences by reading the chip information burned in the pre-installed storage unit (such as EEPROM or Flash) on the to-be-tested computing force board; or the fault diagnosis equipment can obtain the code sequences of each chip connected by the master control chip on the to-be-tested computing force board by communicating with the master control chip.

[0102] Wherein, based on the chip space layout topology order represented by the chip code sequence and the signal transmission timing rules, is to use the information stored in advance or obtained dynamically by the fault diagnosis equipment to understand the physical arrangement, mutual connection mode of the chips on the to-be-tested computing force board and the time characteristics of signal transmission on these connections. The chip space layout topology order describes the position relationship and data flow direction of the chips on the board, and the signal transmission timing rules specify the time parameters such as delay, setup time, hold time, clock synchronization of signal transmission. Its role is to provide guidance on path and time for accurate transmission of the first detection signal, to avoid signal conflict, data loss or timing error. For example, the fault diagnosis equipment can store detailed topology structure diagram and timing rule database of different models of computing force board in the internal, and match and query according to the model and chip code sequence of the to-be-tested computing force board; or the fault diagnosis equipment can dynamically construct the connection relationship and timing characteristics between the chips on the to-be-tested computing force board before detection through a specific detection mechanism.

[0103] The first detection signal is sequentially transmitted to the corresponding chip, which means that the fault diagnosis equipment sends the first detection signal to each target chip on the to-be-tested computing power board according to the predetermined order and accurate timing based on the chip coding sequence, spatial layout topology order and signal transmission timing rules obtained above. The purpose is to ensure that each chip can independently and accurately receive the detection signal and respond according to its characteristics, thereby achieving accurate detection and fault positioning of a single chip. For example, the fault diagnosis equipment can select the target chip one by one through a multiplexer or a serial communication interface according to the chip coding sequence and topology order, and send the first detection signal; or the first detection signal can be transmitted to each chip in series by using a JTAG chain or similar daisy chain structure, and each chip receives and processes it and then transmits it to the next chip.

[0104] In the fault diagnosis process, in order to achieve accurate detection of the multi-chip to-be-tested computing power board, the scheme of the present application first obtains the chip coding sequence of each chip in the to-be-tested computing power board, which provides a unique identification for each chip. Subsequently, based on the chip spatial layout topology order represented by these chip coding sequences and the signal transmission timing rules, the fault diagnosis equipment can accurately understand the physical arrangement of the chips on the computing power board, the mutual connection relationship and the time characteristics required for signal transmission on these connections. By comprehensively utilizing these information, the fault diagnosis equipment can transmit the first detection signal to each corresponding chip in the to-be-tested computing power board according to the predetermined and accurate timing and path. This ordered and topology structure and timing rule-based transmission method ensures that each chip can independently and accurately receive the detection signal, thereby avoiding signal conflict or transmission error, laying a foundation for subsequent accurate monitoring of chip response and determination of its working state. Compared with simply sending a detection signal, the present scheme significantly improves the diagnosis accuracy and efficiency of complex multi-chip computing power boards by fine management of the transmission path and timing of the signal.

[0105] As an implementation, for example, when the fault diagnosis device accesses the to-be-tested computing power board, first, communication is established with the master control chip of the to-be-tested computing power board through the JTAG interface. The master control chip is programmed to be able to recognize and return the chip code sequence of each computing power chip (for example, an ASIC chip) connected thereto, which may include the physical address and function type of the chip. The fault diagnosis device internally pre-stores the chip layout diagram and signal transmission protocol of the computing power board of this type, which defines in detail the serial data link and clock synchronization requirements between chips, which constitutes the chip space layout topology sequence and signal transmission timing rules. For example, if the chips are connected in a daisy chain form, the fault diagnosis device will send the first detection signal (for example, a specific test vector) to the first chip through the JTAG chain according to the obtained chip code sequence in a chain topology structure, and after the first chip processes and transfers the result to the next chip, the next chip receives and processes it, and so on, until all chips on the chain are detected. This ensures that each chip can receive independent detection instructions at the correct timing.

[0106] Through the above technical solution, the fault diagnosis device can accurately obtain the unique identifier of each chip on the to-be-tested computing power board, and realize accurate and orderly transmission of the first detection signal in combination with the physical arrangement and signal transmission characteristics of the chip on the board. This transmission method based on the chip code sequence, the space layout topology sequence and the signal transmission timing rules effectively solves the problems of blindness and inefficiency in detection signal transmission in a multi-chip complex computing power board. It ensures that each chip can receive independent and correct detection signals, thereby greatly improving the detection accuracy and fault positioning ability of a single chip, avoiding misjudgment or omission caused by improper signal transmission, and further improving the efficiency and reliability of the entire fault diagnosis process.

[0107] In actual fault diagnosis process, if the to-be-tested computing power board contains a large number of chips, and all the chips need to be detected quickly and efficiently, the above Figure 3 The way of sending detection signals one by one or in sequence in the embodiment shown in the above

[0108] Therefore, with reference to the above Figure 4 , a fault diagnosis method is provided in another embodiment of the present application, which is based on the above Figure 2 , and the first detection signal is sent to the to-be-tested computing power board, specifically steps S223-S224, wherein:

[0109] S223, obtain the chip array hardware topology architecture of the to-be-tested computing power board, and traverse and extract the physical address identifier information of each chip in the chip array hardware topology architecture;

[0110] S224, transmit the first detection signal to the corresponding chip in parallel according to the signal transmission path determined by the physical address identification information.

[0111] Wherein, the chip array hardware topology architecture of the to-be-tested computing force board is obtained, which refers to obtaining the physical arrangement, interconnection relationship and bus structure information of the chips on the to-be-tested computing force board. The architecture information can be pre-stored in the firmware or configuration data of the to-be-tested computing force board, so the fault diagnosis device can obtain it by reading these data; or the fault diagnosis device can scan and identify the interconnection relationship of the chips by connecting to the JTAG interface or boundary scan interface of the to-be-tested computing force board, so as to dynamically build the hardware topology architecture. Traversing and extracting the physical address identification information of each chip in the chip array hardware topology architecture refers to identifying and recording the unique addressing information of each chip in the bus or interconnection network from the obtained hardware topology architecture. These physical address identification information can be the PCIe bus address of the chip, the SPI slave address, the I2C device address or the device ID on the self-defined bus, etc. These information can be obtained by parsing the pre-loaded chip layout file, or can be dynamically obtained by addressing the chip array through specific hardware scanning protocol (such as I2C, SPI, JTAG, etc.). Transmitting the first detection signal to the corresponding chip in parallel according to the signal transmission path determined by the physical address identification information refers to using the mechanism supported by the to-be-tested computing force board to send the detection signal to multiple chips in a concurrent manner. This can be achieved by using the high-speed parallel bus (such as PCIe, AXI bus, etc.) inside the to-be-tested computing force board, directly addressing and sending detection signals to multiple chips at the same time through physical address identification information; or the fault diagnosis device can configure multiple independent signal sending channels, each channel corresponding to the physical address of one or a group of chips, so as to realize the parallel transmission of detection signals.

[0112] The embodiment first obtains the chip array hardware topology architecture of the to-be-tested computing force board, which provides the physical layout and interconnection information of the chips on the board. Then, the physical address identification information of each chip is extracted, which is the key to uniquely identify the position of the chip in the hardware topology. Based on these physical address identification information, the diagnosis device can determine the signal transmission path to each chip. Unlike traditional sequential transmission, the embodiment uses these determined transmission paths to transmit the first detection signal to multiple corresponding chips in parallel. This parallel transmission mechanism significantly improves the efficiency of sending detection signals, allowing more chips to be detected in the same time, thereby speeding up the entire fault diagnosis process. In this way, the embodiment effectively solves the problem of low efficiency of serially transmitting detection signals in computing force boards containing a large number of chips, and can quickly monitor the response signal and determine the working state.

[0113] In one implementation of the embodiment, it is assumed that the to-be-tested computing power board is a computing power board of a blockchain server including multiple ASIC chips. When performing fault diagnosis, the fault diagnosis device first acquires the hardware topology architecture of the ASIC chip array of the computing power board by reading the firmware configuration of the computing power board, for example, the chips are connected through SPI buses or custom parallel buses and form a chained or matrix layout. Then, the diagnosis device traverses the topology architecture to extract the unique physical address identification information of each ASIC chip, for example, SPI slave addresses or device IDs on the bus. When the first detection signal needs to be sent, the fault diagnosis device sends the detection signal to multiple ASIC chips simultaneously through parallel bus interfaces or multiple independent SPI channels according to the physical address identification information. For example, the signal can be sent to the first group of chips simultaneously instead of waiting for the response of the previous chip before sending to the next one. This parallel transmission mode greatly shortens the transmission time of the detection signal, enabling the detection of the entire chip array to be completed quickly.

[0114] Through the above technical solution, the fault diagnosis device can efficiently acquire the chip array hardware topology architecture of the to-be-tested computing power board and the physical address identification information of each chip. Based on this information, the first detection signal can be transmitted in parallel to the corresponding chips according to the determined signal transmission path. This parallel transmission mode significantly improves the transmission efficiency of the detection signal, shortens the overall detection time, and is particularly suitable for complex computing power boards including a large number of chips. This makes the fault diagnosis process faster and enables the potential faulty chip to be located faster, thereby improving the overall efficiency and accuracy of fault diagnosis.

[0115] Optionally, with reference to Figure 5 , the present application also provides a fault diagnosis method based on the above Figure 2 indicated embodiment, monitors the response signal fed back by the to-be-tested computing power board, compares the response signal with the preset normal response mode, determines the working state of the to-be-tested computing power board, and displays the working state on the test interface, including steps S231-S234, wherein:

[0116] S231, time sequence analysis and level feature extraction are performed on the response signal to obtain the high-low level duration period and the jump edge distribution of the response signal;

[0117] S232, the high-low level duration period and the jump edge distribution are matched with the time sequence features in the preset normal response mode one by one to generate corresponding matching results;

[0118] S233, if there are unmatched items in the matching results, it is determined that the chip of the to-be-tested computing power board is abnormal, and the corresponding abnormal chip position and fault type are determined according to the unmatched items, and the abnormal chip position and fault type are displayed on the test interface;

[0119] S234. If the matching results are consistent, it is determined that the computing board under test is working normally, and the normal operation indicator is displayed on the test interface.

[0120] The timing analysis and level feature extraction of the response signal refers to analyzing the raw response signal received from the computing board under test to identify its key characteristics in the time and voltage level dimensions. This can include capturing the signal waveform using high-speed sampling technology and using digital signal processing algorithms, such as identifying the rising and falling edges of the signal, to accurately measure the duration the signal is held at different voltage levels (high or low), and to record the precise time points when these level transitions (jump edges) occur. In this way, the raw, potentially complex response signal can be transformed into a series of quantifiable timing and level features.

[0121] Obtaining the duration and transition edge distribution of the high and low levels of the response signal refers to, after completing timing analysis and level feature extraction, explicitly quantifying the duration of each high and low level state of the signal, as well as the precise time sequence of all signal level changes. For example, for a digital signal, one can measure how many nanoseconds it lasts after transitioning from low to high, and then how many nanoseconds it lasts after transitioning from high to low, recording the specific time of each level change. This periodicity and distribution data are key indicators for evaluating the proper functioning of the internal digital logic circuits and clock system of the computing board.

[0122] Matching the duration of high and low levels and the distribution of transition edges with the timing characteristics in the preset normal response mode involves a detailed, point-to-point comparison of the specific timing characteristics extracted from the actual response signal (such as the duration of high and low levels and the timing of transition edges) with the corresponding timing characteristics in a pre-stored reference mode representing the normal operating state. This matching process can employ precise time window comparison, numerical range judgment, or rule-based logical judgment to identify any discrepancies between the two.

[0123] Generating corresponding matching results means that after completing the above-mentioned step-by-step matching process, the diagnostic device will output a structured data set that clearly indicates whether each compared temporal feature matches a preset normal pattern. For example, a list or report can be generated, which includes the comparison status of each feature (such as "match" or "mismatch"), as well as the specific deviation value when there is a mismatch.

[0124] If the matching result contains unmatched items, it is determined that the chip of the to-be-tested computing power board has an abnormality, and the corresponding abnormal chip position and fault type are determined according to the unmatched items. It refers to that once the matching result shows that there are any items that do not match the preset normal mode, the diagnostic device will immediately determine that one or more chips of the to-be-tested computing power board have working abnormalities. Among them, the diagnostic device will infer the specific chip position (for example, a specific ASIC, memory chip or interface chip) and the type of fault (for example, clock signal error, data line open / short circuit, power voltage abnormality, response delay too large, etc.) that causes the abnormality according to the specific properties of the unmatched items (for example, which signal timing is abnormal, the degree and mode of abnormality), combined with the preset fault diagnosis rule library or fault mode database.

[0125] Displaying the abnormal chip position and fault type on the test interface refers to presenting the above diagnosed abnormal chip position and fault type information on the test interface of the fault diagnosis equipment in an intuitive and easy-to-understand manner. This can include highlighting the abnormal chip on the graphical layout of the computing power board, or clearly listing the fault description in text form, so that the operator can quickly understand and take subsequent measures.

[0126] If the matching result is consistent, it is determined that the to-be-tested computing power board is in a normal working state. It refers to that if all the extracted timing features completely match the timing features in the preset normal response mode, or match within an acceptable error range, the system determines that the to-be-tested computing power board is in a normal working state and has no obvious faults.

[0127] Displaying a normal operation identifier on the test interface refers to displaying a clear indication on the test interface of the fault diagnosis equipment when the to-be-tested computing power board is determined to be in a normal working state, such as "normal operation" "PASS" or a green indicator light icon, to inform the operator that the computing power board has passed the detection.

[0128] The scheme of the present application, after receiving the response signal fed back by the to-be-tested computing power board, first carries out fine timing analysis and level feature extraction on the response signal. Through this process, the duration period of the response signal in the high and low level states and the specific distribution of the signal transition edge can be accurately obtained. These detailed timing characteristics and level characteristics are key indicators reflecting the working state of the chips inside the computing power board. Then, the extracted high and low level duration period and transition edge distribution are matched one by one and in detail with the corresponding timing characteristics in the preset normal response mode. This one-by-one matching method can accurately identify any subtle differences in the response signal that do not conform to the normal mode, thereby generating detailed matching results. If there are any unmatched items in the matching results, it indicates that the specific chip of the to-be-tested computing power board may have an abnormality. Based on the nature and location of these unmatched items, the diagnostic device can infer the abnormal chip location and fault type, such as clock signal abnormality, data line level error, or response delay of a certain specific chip. Finally, these detailed diagnostic results, whether it is the abnormal chip location and fault type or the normal operation identifier, will be clearly displayed on the test interface. In this way, the present scheme refines the general "abnormal" state into specific fault information, greatly improving the accuracy and efficiency of fault diagnosis, enabling maintenance personnel to quickly locate the problem and take targeted measures, and solving the problem that the traditional method is difficult to accurately identify the fault location and type.

[0129] In one implementation of the embodiment, when the fault diagnosis device receives the response signal fed back by the to-be-tested force plate, the analog response signal can be digitized and sampled by using the built-in high-speed analog-to-digital converter (ADC), or the digital response signal can be directly processed. Then, the sampled data is time-series analyzed by the signal processing module running on the processor, for example, the rising edge and the falling edge of the signal are identified, and the duration of each high level or low level is accurately measured, so as to obtain the high-low level duration period of the response signal. In addition, the time points at which each jump edge occurs can also be recorded to form a jump edge distribution. For example, if the preset normal response mode requires a high-low level conversion of a certain signal to be completed within 100 ns, and the high level lasts for 50 ns and the low level lasts for 50 ns, the diagnosis device will accurately measure these parameters of the actual response signal. Then, the diagnosis device will compare these extracted high-low level duration periods and jump edge distribution with the standard time-series characteristics stored in the preset normal response mode one by one. For example, if the high level duration period of a certain signal is 20 ns shorter than the preset value, or a certain jump edge is delayed by 15 ns than the expected time, these will be marked as mismatched items. Based on these mismatched items, the system can determine the fault diagnosis rule library established in advance, for example, if a certain bit line of a data bus is continuously at a low level, it may indicate that the driving chip or the receiving chip corresponding to the bit line has a fault. The diagnosis device will determine the location of the abnormal chip, for example, "the 3rd pin of chip A", and identify the fault type, for example, "data line short circuit" or "insufficient driving capability". Finally, these detailed abnormal chip location and fault type information, or the "normal operation" identification when all the matched items are consistent, are intuitively displayed on the test interface of the fault diagnosis device for reference by the operator.

[0130] Through the above technical solution, the embodiment can time-series analyze and extract the level characteristics of the received response signal, so as to obtain the high-low level duration period and the jump edge distribution and other key time-series characteristics. This detailed feature extraction and one-by-one matching with the preset normal response mode enable the diagnosis device to accurately identify any subtle abnormalities in the response signal. When there are mismatched items, the embodiment can accurately determine the specific location of the abnormal chip in the to-be-tested force plate and the fault type according to the characteristics of these mismatched items, rather than only giving a general abnormality prompt. This greatly improves the accuracy and efficiency of fault diagnosis, enables the maintenance personnel to obtain specific and operable fault information, so as to quickly locate the problem and perform targeted maintenance, significantly shortens the fault elimination time, and reduces the maintenance cost. When all the characteristics are matched, the diagnosis device can also clearly display the normal operation identification, avoiding misjudgment.

[0131] In the above manner, the digital level response signal generated during the test firmware running process is mainly analyzed for high-precision timing, but the power supply aspect is not controlled, which may also cause the real working condition of the computing board under different power supply conditions to be unable to be simulated during the diagnosis process, so that it is difficult to find potential faults sensitive to voltage and current fluctuations or only appear under specific power supply timing, affecting the comprehensiveness and accuracy of fault diagnosis.

[0132] To this end, with reference to Figure 6 , another embodiment of the present application provides a fault diagnosis method based on the above Figure 1 The connection interface has a control signal end for connecting to a controllable DC power supply, and the output end of the controllable DC power supply is connected to the power input end of the computing board to be tested.

[0133] The connection interface is designed to include a control signal end, which is used for communication and control with a controllable DC power supply. The output end of the controllable DC power supply is directly connected to the power input end of the computing board to be tested. This configuration enables the fault diagnosis device to directly manage and regulate the power supply to the computing board to be tested. For example, the control signal end can be a digital communication interface through which instructions are sent to the controllable DC power supply; or it can be an analog control interface that regulates the power output through voltage or current signals. Through this connection, the fault diagnosis device can achieve precise control of the power supply to the computing board, rather than relying solely on a fixed external power supply.

[0134] In response to the selection of the model of the computing board to be tested, the test interface corresponding to the computing board to be tested is displayed, and then the step S300 of adjusting the power supply voltage, power supply current and delay time of the controllable DC power supply in response to an adjustment instruction for the electrical parameter is further included.

[0135] S300, in response to an adjustment instruction for the electrical parameter, adjusting the power supply voltage, power supply current and delay time of the controllable DC power supply.

[0136] Step S300 means that before fault diagnosis, the diagnosis device can adjust the output parameters of the controllable DC power supply according to specific instructions. The adjustment instruction can be manually input by the user on the test interface, or it can be a preset automatic test script. The adjustable electrical parameters include power supply voltage, power supply current and delay time. Adjustment of the power supply voltage allows the computing board to be tested to work stably under different voltage conditions (such as under-voltage, over-voltage or nominal voltage); adjustment of the power supply current can simulate different load conditions or test current limits; and the delay time can control the duration of power supply or the waiting time for power-off after a specific event (such as data return), which is crucial for testing transient response or ensuring the stability of the test environment. For example, adjustment can be achieved by sending specific digital commands to the controllable DC power supply, or by adjusting the analog control input end of the power supply.

[0137] In response to the detection operation for the to-be-tested computing power board, the test firmware is run, including step S240, wherein:

[0138] S240, in response to the detection operation for the to-be-tested computing power board, controlling the controllable direct current power supply to supply power to the to-be-tested computing power board according to the adjusted power supply voltage and power supply current, and sending a corresponding first detection signal to the to-be-tested computing power board, and disconnecting the power supply connection between the controllable direct current power supply and the to-be-tested computing power board within a delay time after the to-be-tested computing power board returns response data.

[0139] In step S240, how the fault diagnosis device cooperates with the power supply and the detection signal in the actual detection process is shown. When the detection operation is triggered, the fault diagnosis device instructs the controllable direct current power supply to provide power to the to-be-tested computing power board according to the pre-adjusted power supply voltage and power supply current. At the same time, the diagnosis device sends a first detection signal to the to-be-tested computing power board. This synchronous operation ensures that the detection signal is applied under precisely controlled power supply conditions. More importantly, after the to-be-tested computing power board returns response data, the fault diagnosis device quickly disconnects the power supply connection between the controllable direct current power supply and the computing power board within a preset delay time. This power timing control makes the start-up, shutdown behavior, transient response of the test computing power board, and ensures that each test is performed under consistent initial conditions. For example, the control can be achieved through a microcontroller or a field programmable gate array (FPGA) inside the diagnosis device, which can accurately manage the switching of the power supply and the sending of the detection signal.

[0140] The embodiment significantly enhances the depth and flexibility of fault diagnosis by introducing the integration and management of controllable DC power supply. The connection interface is designed to access a controllable DC power supply and realize command control of the power supply through a control signal end, and the power supply output is directly connected to the power input of the to-be-tested computing board. After the user selects the to-be-tested computing board model and displays the test interface, the diagnostic device allows the user or an automated program to adjust the output parameters of the controllable DC power supply according to the diagnostic requirements. The adjusted electrical parameters include the supply voltage, supply current, and supply delay time. The adjustment of these electrical parameters enables the diagnostic equipment to simulate the power supply environment of the computing board under various extreme or specific working conditions. When the actual detection operation starts, the fault diagnosis equipment precisely controls the controllable DC power supply to supply power to the to-be-tested computing board according to the preset adjustment parameters. During this power supply process, the diagnostic device sends a first detection signal to the computing board, ensuring that the detection signal is applied under stable and controlled power supply conditions. More importantly, after the to-be-tested computing board returns response data, the fault diagnosis equipment rapidly and accurately disconnects the power supply connection within a preset delay time. This power timing control, including the adjustment of the supply parameters and the timely disconnection of the power supply, enables the diagnostic process to comprehensively evaluate the performance, stability, and transient response of the computing board under different power supply conditions, thereby discovering potential faults that are difficult to expose under traditional fixed power supply testing, greatly improving the accuracy and reliability of fault diagnosis.

[0141] In one embodiment of the present embodiment, when diagnosing a certain type of to-be-tested computing board, it is first connected to the fault diagnosis equipment through the connection interface. On the test interface, the user can input adjustment instructions according to the characteristics of the computing board or specific test requirements. For example, the user can set the supply voltage of the controllable DC power supply to 1.05V (lower than the nominal voltage, used to test the undervoltage stability), the supply current limit to 8A, and set a delay time of 150 milliseconds to disconnect the power supply after the computing board returns response data.

[0142] When the user initiates a detection operation, the fault diagnosis device sends a command to the controllable DC power supply (e.g., a programmable precision power supply module) through its control signal terminal, instructing it to output a voltage of 1.05V and limit the maximum current to 8A, and then connects the power supply output to the to-be-tested computing power board. At the moment when the power supply is stable, the fault diagnosis device sends a preset first detection signal (e.g., a series of specific data sequences for testing the functions of internal registers or logic units of the computing power board) to the to-be-tested computing power board. The to-be-tested computing power board performs corresponding operations and returns response data. Once the fault diagnosis device receives and analyzes these response data, it immediately starts a timer and sends a power-off command to the controllable DC power supply after the 150ms delay time ends, thereby quickly cutting off the power supply to the computing power board. This power supply control and timing management enables the diagnosis device to simulate various power supply conditions that the computing power board may encounter in actual working environments, thereby more effectively discovering potential faults.

[0143] Through the above technical solutions, the present embodiment can accurately control the supply voltage, supply current, and supply duration provided by the fault diagnosis device to the to-be-tested computing power board. This enables the diagnosis process to simulate the working environment of the to-be-tested computing power board under different electrical parameters, such as operating conditions under undervoltage, overvoltage, or specific load conditions. By sending detection signals and monitoring responses under controlled power supply conditions, the performance and stability of the computing power board can be more comprehensively evaluated, thereby effectively identifying potential faults that are sensitive to power fluctuations or only appear under specific electrical parameters. In addition, the power-off timing helps to test the transient response and reset behavior of the computing power board, improving the depth and accuracy of fault diagnosis and avoiding missed or false diagnoses due to uncertain power supply conditions.

[0144] In actual applications, merely displaying the current working state of the to-be-tested computing power board may not meet the complex fault diagnosis requirements. For example, the user may need to understand the historical running status of the computing power board, the frequency of faults, the trend of fault types over time, or evaluate its stability after multiple repairs. The lack of effective management and presentation of historical diagnosis data makes it difficult for users to conduct in-depth fault analysis and long-term performance evaluation.

[0145] Optionally, with reference to Figure 7 , another embodiment of the present application provides a fault diagnosis method based on the above Figure 1 embodiment, the fault diagnosis method further comprises steps S400-S600, wherein:

[0146] S400, record the working state of each detection, extract the detection timing, each chip running state, and detection times in each record, and generate corresponding detection logs;

[0147] S500, obtain the computing power board model data and the corresponding test data of each detection record in the detection log;

[0148] S600, in response to the query instruction for the detection log, call the computing power board model data and the test data, and display them in the test interface in the corresponding time sequence.

[0149] Among them, step S400 aims to build a comprehensive historical diagnosis data storage mechanism. The detection log can be a structured database (such as a relational database or a NoSQL database), or a specific format file (such as JSON, XML or CSV) stored in the file system. Recording the working state of detection refers to saving the final working state (such as "normal", "abnormal: chip A01 temperature too high", "abnormal: communication error") of the to-be-tested computing power board determined by the test firmware after each diagnosis operation. This can be achieved by executing a data write operation by the processor in the fault diagnosis device at the end of the diagnosis process. Extracting the detection timing refers to obtaining and recording the exact time point of each detection, usually accurate to seconds or milliseconds, which can be achieved through the timestamp information provided by the system clock module. Extracting the running state of each chip refers to recording the specific performance of each chip on the to-be-tested computing power board during the detection process, such as the response state, error code, performance parameters, etc. of each chip, which can be obtained from the detailed diagnosis report returned by the test firmware. Extracting the detection times refers to the cumulative count of performing diagnosis on a specific to-be-tested computing power board or a specific test item, which can be achieved by maintaining a counter variable or by querying historical records dynamically. Generating the corresponding detection log integrates all the extracted information and stores it in the detection log in a predefined format, ensuring data integrity and traceability.

[0150] Among them, step S500 aims to associate the diagnosis results with specific computing power board models and test conditions. The computing power board model data refers to the unique identifier or product model information of the to-be-tested computing power board, which is usually captured by the system when the user selects the model and stored together with the subsequent detection records. The test data refers to the specific parameters and environmental information related to each detection operation, such as the test firmware version used, the test mode (such as full function test, local test), the characteristics of the input signal, the test duration, etc. These data are crucial for understanding the background of the diagnosis results and reproducing the test conditions, and can be collected before or during the test and saved together with the detection records.

[0151] Among them, step S600 aims to provide user-friendly historical data query and display functions. The query instruction of the detection log is the request issued by the user through the test interface, for example, the user may select a specific computing power board model, or specify a time range to view its historical diagnosis records. The query instruction can be triggered through interactive elements such as buttons, input boxes, left and right sliding screens, or drop-down menus on the user interface. Retrieving computing power board model data and test data means that the fault diagnosis device retrieves all records that meet the conditions from the stored detection log according to the query instruction. This can be achieved through database query language or file parsing algorithm. Arranging in corresponding time sequence in turn means arranging the retrieved multiple historical records in ascending or descending order according to their recorded detection time sequence (time stamp) to present a clear timeline. Displayed on the test interface means displaying the sorted historical diagnosis data on the user interface, for example, in the form of a list, table or chart, to facilitate the user to intuitively view and analyze the long-term performance and fault evolution of the computing power board.

[0152] The embodiment systematically records the working state of the to-be-tested computing power board, the detection time sequence, the running state of each chip and the detection times after each fault diagnosis operation is completed, and generates detailed detection logs in combination with the computing power board model data and the test data. When the user needs to review the historical diagnosis information, the fault diagnosis device can respond to the query instruction, efficiently retrieve the related data from the detection log, arrange them in time sequence, and finally present them to the user intuitively on the test interface. This mechanism makes fault diagnosis no longer limited to the immediate results of single detection, but can provide a comprehensive, time-sequenced diagnosis view. In this way, the user can clearly track the performance changes of the computing power board, the fault occurrence frequency, the fault type evolution and the effect evaluation after maintenance, thereby greatly improving the depth and breadth of fault diagnosis, and providing a more solid data foundation for the maintenance, fault analysis and life prediction of the computing power board.

[0153] In one embodiment of the present embodiment, assume that a fault diagnosis device is connected to a piece of computing power board to be tested. First, the user selects the model of the computing power board on the test interface, and the diagnosis device loads the corresponding test firmware. Then, the user initiates the detection operation, and the test firmware runs and determines the working state of the computing power board, for example, the detection result shows “Abnormal: Chip A01 temperature is too high”. At this time, the fault diagnosis device automatically records the detailed information of this detection, including the timestamp of the detection (for example, “2023-10-27 10:35:12”), the temperature abnormal state of chip A01 and the running state of other chips, the 5th detection of this computing power board, and the test firmware version and test mode used, etc. These data are structuredly stored in the internal database of the fault diagnosis device as part of the detection log. When the engineer needs to view the historical diagnosis records of the computing power board, he can select the “history query” function on the test interface, or slide the test interface left and right. The diagnosis device will immediately retrieve all historical records related to this model from the detection log and sort them from early to late according to the detection time. The test interface will then display a list, for example:

[0154] 2023-10-26 09:00:00 - Normal operation;

[0155] 2023-10-26 15:30:00 - Abnormal: Chip C03 communication error;

[0156] 2023-10-27 10:35:12 - Abnormal: Chip A01 temperature is too high.

[0157] The engineer can click on any record to view more detailed chip running state and test data, so as to fully understand the evolution of the health status of the computing power board.

[0158] Through the above technical solution, the fault diagnosis device can systematically record the detection result of each time of the computing power board, including the detailed detection time sequence, the running state of each chip and the detection times, and integrate it into the traceable detection log. When it is necessary to review or analyze historical data, the user can conveniently query and view all diagnosis records of a specific computing power board in chronological order. This not only enables the user to understand the current running state of the computing power board, but also enables the user to track the performance trend, identify intermittent fault patterns or evaluate the maintenance effect, thereby significantly improving the depth and efficiency of fault diagnosis, and providing more comprehensive and reliable data support for the maintenance, fault analysis and life prediction of the computing power board.

[0159] When the working state of the to-be-tested computing power board is determined to be abnormal, only knowing its abnormal state cannot directly guide the user to effectively locate and maintain the fault, and the user still needs to spend a lot of time to troubleshoot, and may not be able to accurately determine the fault point and the maintenance method due to lack of professional knowledge, thereby affecting the efficiency of fault diagnosis and the convenience of maintenance.

[0160] Therefore, with reference to Figure 8 , the present application and an embodiment provide a fault diagnosis method, based on the above Figure 1 The fault diagnosis method further includes steps S700-S900, as shown in the embodiment.

[0161] S700, if the working state is abnormal, the abnormal chip in the computing power board, the abnormal position and the fault type are obtained;

[0162] S800, the effect drawing of the computing power board corresponding to the to-be-tested computing power board is displayed, and the abnormal position is marked on the effect drawing of the computing power board;

[0163] S900, in response to a selection operation on the abnormal position on the effect drawing of the computing power board, the fault type corresponding to the abnormal position and the recommended maintenance scheme are displayed.

[0164] When it is determined that the working state of the to-be-tested computing power board is abnormal, specific fault information needs to be obtained. Among them, the abnormal chip refers to the integrated circuit or functional module that is detected to be abnormal on the to-be-tested computing power board; the abnormal position refers to the physical coordinates or identification area of the abnormal chip on the computing power board; the fault type refers to the specific fault mode exhibited by the abnormal chip, such as short circuit, open circuit, overheating, data transmission error, etc. These information can be obtained by analyzing the detailed diagnostic data collected by the test firmware during running. For example, the test firmware can send specific detection signals to each chip on the computing power board and receive responses, identify the abnormal chip and its physical address on the computing power board by comparing the response signal with the preset normal mode, and match the specific fault type according to the characteristic mode of the abnormal response and the preset fault library. Another way is that the test firmware, during the detection process, if it finds that the specific register value, state bit or output waveform of a chip deviates from the normal range, it can directly locate the abnormal position of the chip according to the preset mapping relationship, and classify it into the corresponding fault type according to the nature of the deviation.

[0165] The effect picture of the computing board is a graphical representation of the computing board to be tested, usually a two-dimensional or three-dimensional view of its physical layout, for intuitively showing the structure and component distribution of the computing board. The effect picture can be pre-stored in the memory of the fault diagnosis device and loaded and displayed according to the model of the computing board to be tested. After obtaining the abnormal position information, the fault diagnosis device visually highlights or marks the abnormal position on the effect picture of the computing board. For example, the abnormal position area can be marked by changing the color, flashing display, adding an arrow indication, or superimposing a text label above the abnormal chip, so that the user can quickly and accurately identify the specific physical location of the fault occurrence. The selection operation refers to the user's behavior of selecting the marked abnormal position on the effect picture of the computing board through the human-computer interaction interface. This can be achieved in various ways, for example, the user can use a mouse click, touch screen touch, or keyboard navigation to select the marked abnormal position. Once the user completes the selection operation, the fault diagnosis device immediately displays the detailed fault type description and the corresponding repair scheme associated with the abnormal position on the test interface. The repair scheme can be differentiated according to the user's experience level, for example, for novice users, detailed step-by-step and simple operation guidance can be provided, such as "check if the connection line is loose"; for experienced users, more professional and in-depth suggestions can be provided, such as "replace a specific model of capacitor" or "check the impedance of a specific signal line".

[0166] The embodiment provides detailed fault positioning and repair guidance after determining that the working state of the computing board to be tested is abnormal, thereby significantly improving the practicality and user experience of fault diagnosis. When the fault diagnosis device determines that the working state of the computing board to be tested is abnormal by running the test firmware, it no longer stops at the general conclusion of "abnormal", but further analyzes the diagnostic data returned by the test firmware to accurately obtain the specific chip causing the abnormality, the physical position of the chip on the computing board, and the fault type. Subsequently, in order to intuitively present these complex fault information to the user, the diagnostic device loads and displays the computing board effect picture matching the model of the computing board to be tested, and marks the abnormal position on the effect picture in a conspicuous manner. This visualization method enables users to quickly locate the fault point without deep professional knowledge. Furthermore, in order to provide actionable solutions, the diagnostic device allows the user to interact with the abnormal position on the effect picture through the selection operation, and once selected, the diagnostic device immediately displays the detailed fault type description corresponding to the abnormal position and provides recommended repair schemes for different levels of novice and experienced users according to pre-set rules or user configuration. This complete process from fault discovery, positioning to personalized repair guidance enables the fault diagnosis device to transform from a single "detection tool" to an "intelligent repair assistant", greatly reducing the threshold of fault troubleshooting and repair, and improving repair efficiency and accuracy.

[0167] As an implementation, when the fault diagnosis device detects an abnormal working state of the to-be-tested computing power board through the running test firmware, for example, the test firmware reports a data transmission error of a certain specific chip. At this time, the fault diagnosis device can identify the abnormal chip as an "ASIC chip", the abnormal position of which is located in the upper left corner area of the computing power board, and the fault type is "data bus error". Subsequently, the fault diagnosis device can load and display a two-dimensional plane effect diagram of the computing power board of this model on the display component thereof. In the effect diagram, the area of the "ASIC chip" is highlighted, and can be accompanied by a flashing red border, a "abnormal" word displayed above the chip, or a corresponding computing power value displayed above the chip, etc. The user can trigger a selection operation by touching or long-pressing the highlighted area on the display component. In response to this operation, the display component can pop up a dialog box, which lists in detail "fault type: ASIC chip data bus error, possible cause: pad virtual welding or chip internal logic error". In addition, the dialog box can provide two types of recommended repair solutions: for novice users, the recommended solution can be "1. Check whether the solder joints around the ASIC chip are loose or oxidized; 2. Try to plug in the computing power board to ensure stable connection"; for experienced users, the recommended solution can be "1. Measure the ground impedance of the ASIC chip data bus pin using a multimeter to check for short circuit or open circuit; 2. Use a hot air gun to perform BGA repair or replacement of the ASIC chip".

[0168] Through the above technical solutions, when the working state of the to-be-tested computing power board is determined to be abnormal, the fault diagnosis device can provide more detailed and intuitive fault information. The user not only knows the existence of the fault, but also can intuitively locate the specific abnormal chip and abnormal position through the computing power board effect diagram, greatly shortening the fault troubleshooting time. In addition, the diagnostic device provides detailed fault type description according to the abnormal position and recommended repair solutions for users of different experience levels, so that the maintenance personnel can quickly understand the nature of the fault and obtain operable repair guidance, effectively reducing the professional threshold and trial and error cost of maintenance, thereby significantly improving the efficiency of fault diagnosis and the success rate of maintenance.

[0169] The application further provides a diagnostic device, which comprises a memory, a processor, and a fault diagnosis program stored in the memory and executable on the processor, and the fault diagnosis program is configured to implement the fault diagnosis method.

[0170] In this context, a diagnostic device refers to a hardware system specifically designed to perform fault diagnosis tasks, aiming to provide a stable, efficient, and user-friendly diagnostic environment. Memory is a hardware component used to store data and instructions, providing the processor with program code and the data required for runtime. Memory can include, but is not limited to, Random Access Memory (RAM), Read-Only Memory (ROM), Flash Memory, or Hard Disk Drive (HDD). The processor is the core computing unit of the diagnostic device, responsible for executing instructions in memory, performing data operations, and controlling the entire diagnostic process. The processor can be a Central Processing Unit (CPU), Microcontroller (MCU), Field-Programmable Gate Array (FPGA), or Application-Specific Integrated Circuit (ASIC). A fault diagnosis program is a pre-written set of instructions that guides the processor to execute fault diagnosis methods according to specific logic and steps. Fault diagnosis programs can exist in the form of firmware, applications within the operating system, or scripts. The fault diagnosis program is stored in memory, meaning the program code is persistently or temporarily loaded into the storage medium so that the processor can access and read these instructions. The fault diagnosis program can run on the processor, indicating that the processor can parse and execute the program instructions in memory, thereby driving the diagnostic device to complete its various functions. The fault diagnosis program is configured to implement the above fault diagnosis method, meaning that the program's design and coding fully follow the logic and steps of the above fault diagnosis method, ensuring that the diagnostic device can accurately and completely execute all aspects of the method.

[0171] It is worth noting that since the diagnostic device of the present invention is based on the above-described fault diagnosis method, the embodiments of the diagnostic device of the present invention include all the technical solutions of all embodiments of the above-described fault diagnosis method, and the technical effects achieved are exactly the same, so they will not be repeated here.

[0172] The present invention also proposes a fault diagnosis device, which includes a display component, a connection interface, and a diagnostic device as described in all the embodiments above, wherein:

[0173] The display component is used to present the test interface and the working status of the computing board under test; the connection interface is used to connect the computing board under test; the diagnostic device is electrically connected to the display component and the connection interface respectively; the diagnostic device is used to respond to the user's selection of the model of the computing board under test on the display component, obtain the test firmware corresponding to the model of the computing board under test, and display the test interface corresponding to the computing board under test on the display component; the diagnostic device is also used to respond to the user's detection operation on the display component for the computing board under test, run the test firmware, and determine the working status of the computing board under test.

[0174] The core innovation of the embodiment is that the display component, the connection interface and the diagnostic device are combined in an integrated manner, thereby realizing an automatic fault diagnosis process for different types of computing power boards. In the specific implementation process, the user only needs to select the type of the computing power board to be tested through the display component, and the diagnostic device can automatically obtain the matching test firmware and display the special test interface. When the user triggers the detection operation, the diagnostic device runs the test firmware to complete the diagnosis, without the need for manual comparison of circuit diagrams to locate the chip position or the use of a multimeter to detect voltage signals point by point. This design avoids the disadvantages of manual operation relying on the experience of maintenance personnel in the traditional method, significantly improving the diagnosis efficiency and accuracy. At the same time, since the test firmware can be dynamically loaded according to the type, the device can be compatible with computing power boards of various brands and types, solving the problem of poor adaptability of special tools. Through the above technical solutions, the present application effectively reduces the operation threshold, shortens the maintenance cycle, and improves the fault positioning accuracy to more than 95%, providing an efficient and reliable solution for batch detection of computing power boards.

[0175] It is worth noting that since the fault diagnosis device of the present application is based on the above-mentioned diagnostic device, the embodiments of the fault diagnosis device of the present application include all the technical solutions of all the embodiments of the above-mentioned diagnostic device, and the technical effects achieved are also exactly the same, which will not be repeated here.

[0176] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation using the content of the specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A failure diagnosis method applied to a failure diagnosis device, the failure diagnosis device comprising a connection interface for accessing a to-be-tested power board, characterized in that, The fault diagnosis method includes: In response to the selection of the model of the computing board under test, the test firmware corresponding to the model of the computing board under test is obtained, and the test interface corresponding to the computing board under test is displayed. In response to the testing operation on the computing board under test, the test firmware is run to determine the working status of the computing board under test; The step of running the test firmware in response to a detection operation on the computing board under test and determining the working state of the computing board under test includes: In response to the detection operation, the test firmware is loaded and started running; Obtain the first detection signal from the test firmware and send the first detection signal to the computing board under test; Monitor the response signal fed back by the computing board under test, compare the response signal with the preset normal response mode, determine the working status of the computing board under test, and display the working status on the test interface; The step of sending the first detection signal to the computing board under test specifically involves: Obtain the chip code sequence of each chip in the computing board under test; Based on the chip space layout topology order and signal transmission timing rules represented by the chip encoding sequence, the first detection signal is transmitted sequentially to the corresponding chip.

2. The failure diagnosis method according to claim 1, characterized by, The process of monitoring the response signal fed back by the computing board under test, comparing the response signal with a preset normal response mode to determine the working status of the computing board under test, and displaying the working status on the test interface includes: The response signal is subjected to timing analysis and level feature extraction to obtain the high and low level duration period and transition edge distribution of the response signal; The duration of the high and low levels and the distribution of the transition edges are matched one by one with the timing features in the preset normal response mode to generate corresponding matching results. If there are mismatches in the matching results, it is determined that the chip of the computing board under test is abnormal, and the location and fault type of the abnormal chip are determined according to the mismatches, and the location and fault type of the abnormal chip are displayed on the test interface. If the matching results are consistent, it is determined that the computing board under test is in normal working condition, and a normal operation indicator is displayed on the test interface.

3. The failure diagnosing method according to claim 1, wherein The connection interface has a control signal terminal for connecting to a controllable DC power supply, and the output terminal of the controllable DC power supply is connected to the power input terminal of the computing board under test. After responding to the selection of the model of the computing power board under test and displaying the test interface corresponding to the computing power board under test, the method further includes: In response to adjustment commands for electrical parameters, the supply voltage, supply current, and delay time of the controllable DC power supply are adjusted. The step of running the test firmware in response to a detection operation on the computing board under test includes: In response to the detection operation on the computing board under test, the controllable DC power supply is controlled to supply power to the computing board under test according to the adjusted supply voltage and supply current, and a corresponding first detection signal is sent to the computing board under test. Within the delay time after the computing board under test returns response data, the power supply connection between the controllable DC power supply and the computing board under test is disconnected.

4. The fault diagnosis method as described in claim 1, characterized in that, The fault diagnosis method further includes: Record the working status of each test, extract the test timing, chip operating status and test count from each record, and generate the corresponding test log; Obtain the computing board model data and corresponding test data for each test record in the test log; In response to a query command for the test log, the computing board model data and the test data are retrieved, arranged in the corresponding time order, and displayed on the test interface.

5. The fault diagnosis method as described in claim 1, characterized in that, The fault diagnosis method further includes: If the working state is abnormal, obtain the abnormal chip, abnormal location and fault type in the computing board; Display the rendering of the computing board corresponding to the computing board under test, and mark the abnormal locations on the rendering of the computing board; In response to the selection of an abnormal location on the computing board rendering, the fault type and suggested repair solution corresponding to the abnormal location are displayed.

6. A diagnostic device, characterized in that, The diagnostic device includes: a memory, a processor, and a fault diagnosis program stored in the memory and executable on the processor, the fault diagnosis program being configured to implement the fault diagnosis method as described in any one of claims 1 to 5.

7. A fault diagnosis device, characterized in that, The fault diagnosis equipment includes: The display component is used to present the test interface and the working status of the computing board under test. A connection interface, wherein the connection interface is used to connect to the computing board under test; and The diagnostic device as claimed in claim 6, wherein the diagnostic device is electrically connected to the display component and the connection interface respectively; The diagnostic device is used to respond to the user's selection of the model of the computing board under test on the display component, obtain the test firmware corresponding to the model of the computing board under test, and display the test interface corresponding to the computing board under test on the display component. The diagnostic device is also used to run the test firmware in response to a user's detection operation on the display component for the computing board under test, and to determine the working status of the computing board under test.

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