Communication control method, device and storage medium based on I2C bus

Abstract

This application discloses a communication control method, apparatus, and storage medium based on the I2C bus, relating to the field of communication technology. The disclosed communication control method based on the I2C bus includes: sequentially writing high-priority data and low-priority data into a first priority FIFO; sending the high-priority data to the first slave device buffer corresponding to the first priority FIFO via the first priority FIFO; synchronizing the high-priority data in the first slave device buffer to the first slave device corresponding to the first priority FIFO via a synchronization arbitration module based on the I2C bus; sending low-priority data to the first slave device buffer via the first priority FIFO; and synchronizing the low-priority data in the first slave device buffer to the first slave device via the synchronization arbitration module based on the I2C bus. This application can reduce the switching delay of the I2C switch during I2C bus communication, thereby effectively improving the communication efficiency of communication using the I2C bus.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a communication control method, apparatus and storage medium based on the I2C bus. Background Technology

[0002] Currently, when multiple I2C master devices, such as BIOS (Basic Input Output System) and BMC (Baseboard Management Controller), access multiple slave devices on the same I2C bus, a single I2C switch is typically used for path switching. For example... Figure 2 As shown, when a master device needs to access a slave device, such as when the BIOS accesses slave device 1, the I2C switch switches the BIOS's physical path to the I2C bus branch connected to slave device 1. After the BIOS completes the communication, the I2C switch disconnects from slave device 1, so that the master device can switch to other slave devices, or other master devices can connect to slave device 1.

[0003] However, since each I2C switch requires a certain delay, in scenarios where multiple master and slave devices frequently cross-access each other, the frequent switching operations will accumulate a large amount of delay, which seriously restricts the overall communication efficiency and data throughput of the bus, resulting in low communication efficiency.

[0004] Therefore, how to improve the communication efficiency of communication using the I2C bus is a problem that urgently needs to be solved.

[0005] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0006] The main objective of this application is to provide a communication control method, device, and storage medium based on the I2C bus, aiming to solve the technical problem of how to improve the communication efficiency of communication using the I2C bus.

[0007] To achieve the above objectives, this application proposes a communication control method based on the I2C bus, applied to an I2C communication system. The I2C communication system includes multiple master devices, multiple slave devices, and a synchronization arbitration module. The I2C communication system also includes a slave interface corresponding to each master device, a slave device buffer corresponding to each slave device, and a priority first-in-first-out (FIFO) queue. Each slave device is connected to the I2C master device interface via the I2C bus. The communication control method based on the I2C bus includes:

[0008] If the first priority FIFO in the priority FIFO simultaneously receives the first data to be written and the second data to be written, then the high-priority data and low-priority data in the first data to be written and the second data to be written are written sequentially in the first priority FIFO. The first master device in each master device sends the first data to be written to the first priority FIFO through the corresponding slave interface, and the second master device in each master device sends the second data to be written to the first priority FIFO through the corresponding slave interface.

[0009] The high-priority data is sent to the first slave device cache corresponding to the first priority FIFO through the first priority FIFO;

[0010] The synchronization arbitration module synchronizes the high-priority data in the first slave device's cache to the first slave device corresponding to the first priority FIFO via the I2C bus.

[0011] When the high-priority data synchronization is completed, the low-priority data is sent to the first slave device cache through the first priority FIFO;

[0012] The synchronization arbitration module synchronizes low-priority data in the cache of the first slave device to the first slave device via the I2C bus.

[0013] In one embodiment, the I2C master device interface is provided with an I2C bus FIFO, and the step of synchronizing high-priority data in the first slave device cache to the first slave device corresponding to the first priority FIFO via the synchronization arbitration module based on the I2C bus includes:

[0014] The first device sends a transmission request to the synchronization arbitration module through the first device cache, so that the synchronization arbitration module determines the timing of the first data transmission based on a preset arbitration strategy.

[0015] Based on the synchronization signal of the synchronization arbitration module during the first data transmission timing, the high-priority data in the buffer of the first slave device is sent to the I2C bus via the I2C bus FIFO, so that the first slave device can obtain the high-priority data through the I2C bus.

[0016] In one embodiment, if the first priority FIFO in the priority FIFO simultaneously receives first data to be written and second data to be written, then the step of sequentially writing high-priority data and low-priority data from the first data to be written and the second data to be written into the first priority FIFO includes:

[0017] If the first priority FIFO simultaneously receives the first data to be written and the second data to be written, then the first priority of the first master device and the second priority of the second master device are obtained.

[0018] Based on the first priority and the second priority, high-priority data and low-priority data are determined from the first data to be written and the second data to be written.

[0019] The high-priority data and the low-priority data are written sequentially into the first priority FIFO.

[0020] In one embodiment, the I2C bus-based communication control method further includes:

[0021] The received third data to be written is written to the second priority FIFO in the priority FIFO, wherein the third master device in each master device sends the third data to be written to the second priority FIFO through the corresponding slave interface;

[0022] The third data to be written is sent to the second slave device cache corresponding to the second priority FIFO through the second priority FIFO;

[0023] The second transmission request is sent from the device cache to the synchronization arbitration module, so that the synchronization arbitration module determines the timing of the second data transmission based on a preset arbitration strategy.

[0024] Based on the second data transmission timing, the third data to be written in the second slave device's cache is sent to the I2C bus via the I2C bus FIFO through the synchronous arbitration module, so that the second slave device corresponding to the second priority FIFO can obtain the third data to be written through the I2C bus.

[0025] In one embodiment, the I2C bus-based communication control method further includes:

[0026] If the third priority FIFO in the priority FIFO receives both the first read request and the second read request at the same time, then the first read request and the second read request are written into the third priority FIFO in sequence. Among them, the fourth master device in each master device sends the first read request to the third priority FIFO through the corresponding slave interface, and the fifth master device in each master device sends the second read request to the third priority FIFO through the corresponding slave interface.

[0027] The read requests from the head of the third priority FIFO queue are sequentially sent to the third slave device cache corresponding to the third priority FIFO. The synchronous arbitration module synchronizes the read requests in the third slave device cache to the third slave device corresponding to the third priority FIFO via the I2C bus. The third slave device caches the read data corresponding to the current read request in the third slave device cache.

[0028] When the first read data corresponding to the first read request and the second read data corresponding to the second read request are cached in the third slave device cache, based on the sending time corresponding to the first read request and the sending time of the second read request, the first read data and the second read data are sequentially written into the third priority FIFO, and the read data at the head of the third priority FIFO queue is sent to the corresponding master device.

[0029] In one embodiment, the step of sequentially writing the first read data and the second read data into the third priority FIFO based on the sending time corresponding to the first read request and the sending time of the second read request, and sending the read data at the head of the third priority FIFO queue to the corresponding master device includes:

[0030] Based on the sending time of the first read request and the sending time of the second read request, the first target data of the master device is to be read first and the second target data of the master device is to be read later in the first read data and the second read data.

[0031] The first target data and the second target data are sequentially written into the third priority FIFO;

[0032] The first target data of the third priority FIFO head is sent to the first-read master device through the corresponding slave interface;

[0033] The second target data of the third priority FIFO head is sent to the master device for subsequent reading through the corresponding slave interface.

[0034] In one embodiment, the step of sequentially sending the read requests from the head of the third priority FIFO queue to the third slave device cache corresponding to the third priority FIFO, and synchronizing the read requests in the third slave device cache to the third slave device corresponding to the third priority FIFO via the synchronization arbitration module based on the I2C bus, wherein the third slave device caches the read data corresponding to the current read request in the third slave device cache, includes:

[0035] The read request from the head of the third priority FIFO queue is sent to the third slave device cache corresponding to the third priority FIFO;

[0036] The first device sends a transmission request to the synchronization arbitration module through its cache, so that the synchronization arbitration module determines the timing of the third data transmission based on a preset arbitration strategy.

[0037] Based on the third data transmission timing, the read request in the first slave device cache is sent to the I2C bus via the synchronization signal of the synchronization arbitration module through the I2C bus FIFO, so that the first slave device can obtain the read request through the I2C bus and cache the read data corresponding to the current read request in the third slave device cache;

[0038] Return to the step of sending the read request of the third priority FIFO head to the third slave device cache corresponding to the third priority FIFO.

[0039] In one embodiment, the I2C bus-based communication control method further includes:

[0040] The received third read request is written to the fourth priority FIFO in the priority FIFO, wherein the sixth master device in each master device sends the third read request to the fourth priority FIFO through the corresponding slave interface;

[0041] The third read request is sent to the fourth slave device cache corresponding to the fourth priority FIFO through the fourth priority FIFO;

[0042] The fourth slave device sends a transmission request to the synchronization arbitration module, so that the synchronization arbitration module determines the timing of the fourth data transmission based on a preset arbitration strategy.

[0043] Based on the data transmission timing, the third read request in the fourth slave device cache is sent to the I2C bus via the I2C bus FIFO through the synchronous arbitration module, so that the second slave device corresponding to the fourth priority FIFO can obtain the third read request through the I2C bus and cache the third target number corresponding to the third read request in the fourth slave device cache.

[0044] The third target data in the fourth slave device's cache is written into the fourth priority FIFO, and the third target data at the head of the fourth priority FIFO queue is sent to the sixth master device through the corresponding slave interface.

[0045] In addition, to achieve the above objectives, this application also proposes a communication control device based on an I2C bus, the I2C bus-based communication control device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the aforementioned I2C bus-based communication control method.

[0046] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the aforementioned communication control method based on the I2C bus.

[0047] One or more technical solutions proposed in this application have at least the following technical effects:

[0048] This application presents a communication control method based on the I2C bus. When multiple master devices simultaneously write data to the same slave device, the written data is added to the corresponding priority FIFO according to the priority of the master device, and the written data is cached to the corresponding slave device cache through the priority FIFO. The synchronous arbitration module synchronizes each written data to the corresponding slave device, thereby reducing the switching delay of the I2C switch during I2C bus communication and effectively improving the communication efficiency of I2C bus communication.

[0049] This application avoids the physical switching delay of the I2C switch by establishing an independent buffer and interface for each slave device. The synchronous arbitration mechanism enables the bus to achieve a near-seamless transition between busy and idle states, greatly improving bus utilization and the overall data throughput of the system. The buffer mechanism effectively prevents data loss due to bus congestion. Synchronous arbitration ensures the priority transmission of critical task data, significantly reducing communication latency and meeting the real-time requirements of multi-master systems. Attached Figure Description

[0050] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0051] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a flowchart illustrating an embodiment of the communication control method based on the I2C bus in this application.

[0053] Figure 2 This is a schematic diagram of the system framework of an I2C communication system in related technologies;

[0054] Figure 3 This is a schematic diagram of the system framework of the I2C communication system of this application;

[0055] Figure 4 This is a schematic diagram of the device structure of the hardware operating environment involved in the communication control method based on the I2C bus in the embodiments of this application.

[0056] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0057] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0058] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0059] The main solution of this application embodiment is as follows: If the first priority FIFO in the priority FIFO simultaneously receives first data to be written and second data to be written, then in the first priority FIFO, high-priority data and low-priority data from the first data to be written and the second data to be written are written sequentially. Specifically, the first master device in each master device sends the first data to be written to the first priority FIFO through its corresponding slave interface, and the second master device in each master device sends the second data to be written to the first priority FIFO through its corresponding slave interface. The high-priority data is then sent down to the first slave device buffer corresponding to the first priority FIFO through the first priority FIFO. The high-priority data in the first slave device buffer is synchronized to the first slave device corresponding to the first priority FIFO via the synchronization arbitration module based on the I2C bus. When the high-priority data synchronization is complete, the low-priority data is sent down to the first slave device buffer via the first priority FIFO. The low-priority data in the first slave device buffer is synchronized to the first slave device via the synchronization arbitration module based on the I2C bus.

[0060] In this embodiment, for ease of description, the following description will focus on identifying the communication control device based on the I2C bus as the execution subject.

[0061] Currently, when multiple I2C master devices, such as BIOS (Basic Input Output System) and BMC (Baseboard Management Controller), access multiple slave devices on the same I2C bus, a single I2C switch is typically used for path switching. For example... Figure 2 As shown, when a master device needs to access a slave device, such as when the BIOS accesses slave device 1, the I2C switch switches the BIOS's physical path to the I2C bus branch connected to slave device 1. After the BIOS completes the communication, the I2C switch disconnects from slave device 1, so that the master device can switch to other slave devices, or other master devices can connect to slave device 1.

[0062] However, since each I2C switch requires a certain delay, in scenarios with frequent cross-access by multiple master and slave devices, frequent switching operations accumulate significant delays, severely limiting the overall communication efficiency and data throughput of the bus, resulting in low communication efficiency. Simultaneously, because only one communication path is connected at a time, when multiple master devices simultaneously initiate access requests, unconnected master devices must wait, causing data transmission delays, potentially leading to data loss or response delays, resulting in low real-time data transmission performance. Furthermore, the entire system's communication link heavily relies on a single I2C switch; if this switch fails, communication between all master and slave devices will be interrupted, leading to poor system reliability.

[0063] Therefore, how to improve the communication efficiency of communication using the I2C bus is a problem that urgently needs to be solved.

[0064] This application provides a solution that, when multiple master devices are simultaneously writing data to the same slave device, adds the written data to the corresponding priority FIFO according to the priority of the master device, and caches the written data to the corresponding slave device cache through the priority FIFO. The synchronous arbitration module synchronizes each written data to the corresponding slave device, thereby reducing the switching delay of the I2C switch during I2C bus communication and effectively improving the communication efficiency of I2C bus communication.

[0065] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device capable of performing the above functions, such as an I2C bus-based communication control device. The following description uses an I2C bus-based communication control device as an example to illustrate this embodiment and the subsequent embodiments.

[0066] Based on this, embodiments of this application provide a communication control method based on the I2C bus, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the communication control method based on the I2C bus of this application.

[0067] In this embodiment, as Figure 3 As shown, the communication control method based on the I2C bus is applied to an I2C communication system. The I2C communication system includes multiple master devices, multiple slave devices, and a synchronous arbitration module. The I2C communication system also has a slave interface corresponding to each master device, a slave device buffer corresponding to each slave device, and a priority first-in-first-out queue (FIFO). Each slave device is connected to the I2C master device interface through the I2C bus.

[0068] In this embodiment, the master device includes a BIOS (Basic Input Output System), a BMC (Baseboard Manager Controller), etc., and the I2C (Inter Integrated Circuit) communication system also includes a slave interface module, a cache module, and a priority FIFO module.

[0069] The caching module configures an independent slave device cache for each slave device interface. The slave device cache is used to temporarily store data to be sent to the corresponding slave device or to temporarily store data read from the slave device. The slave device cache realizes the buffering of data between the high-level application and the low-level I2C bus, decoupling the speed difference between the two communicating parties.

[0070] The priority FIFO module configures a priority FIFO (FirstInput First Output) for each slave device to handle instruction priority. The priority FIFO module is used to write instructions into the corresponding priority FIFO in the order they are issued. If instructions arrive at the same priority FIFO at the same time, they are written into the corresponding priority FIFO in the order of priority of the master device.

[0071] This slave interface module configures a slave interface for each master device. Each slave interface is connected to the priority FIFO of all slave devices, and the virtualization management of the physical slave devices is realized through the slave interface.

[0072] The synchronization arbitration module is connected to the slave device caches and I2C master interface of the cache module via a "bidirectional synchronization" signal line. This module monitors data transmission requests from the slave device caches in real time, determines the next slave device allowed to access the I2C bus based on a preset arbitration strategy, and sends synchronization control signals (synchronization signals) to the allowed slave devices and the I2C master interface to coordinate data transmission and reception timing, ensuring the atomicity and correctness of bus access. The preset arbitration strategies include priority strategies, polling strategies, and fair queuing strategies.

[0073] The I2C master interface is equipped with an I2C bus FIFO. The I2C master interface interacts with the physical I2C bus. The I2C master interface receives instructions from the synchronization arbitration module and executes the specific I2C protocol timing. The I2C bus FIFO serves as an internal data buffer for the I2C master interface, further optimizing the continuity of data transmission.

[0074] The communication control method based on the I2C bus includes steps S110~S150:

[0075] Step S110: If the first priority FIFO in the priority FIFO simultaneously receives the first data to be written and the second data to be written, then in the first priority FIFO, the high-priority data and low-priority data in the first data to be written and the second data to be written are written sequentially. In this case, the first master device in each master device sends the first data to be written to the first priority FIFO through the corresponding slave interface, and the second master device in each master device sends the second data to be written to the first priority FIFO through the corresponding slave interface.

[0076] In this embodiment, when the master device writes data to the slave device, the master device sends the data to be written to the corresponding priority FIFO through the corresponding slave interface. In practical applications, there may be situations where two or more master devices simultaneously write data to the same slave device. For example, the first priority FIFO in the priority FIFO simultaneously receives the first data to be written and the second data to be written. The first data to be written is sent to the first priority FIFO by the first master device through the corresponding slave interface, and the second data to be written is sent to the first priority FIFO by the second master device through the corresponding slave interface. At this time, the I2C communication system writes the high-priority data and low-priority data from the first data to be written and the second data to be written to the first priority FIFO in sequence according to the priorities of the first master device and the second master device. Further, in a feasible implementation, step S110 may include steps S111 to S113:

[0077] Step S111: If the first priority FIFO simultaneously receives the first data to be written and the second data to be written, then obtain the first priority of the first master device and the second priority of the second master device.

[0078] Step S112: Based on the first priority and the second priority, determine high-priority data and low-priority data from the first data to be written and the second data to be written;

[0079] Step S113: Write the high-priority data and the low-priority data sequentially into the first priority FIFO.

[0080] In this embodiment of the application, if the first priority FIFO simultaneously receives the first data to be written and the second data to be written, then the first priority of the first master device and the second priority of the second master device are obtained; and based on the first priority and the second priority, high-priority data and low-priority data are determined from the first data to be written and the second data to be written. For example, if the first priority is greater than the second priority, then the high-priority data is determined to be the first data to be written and the low-priority data is determined to be the second data to be written; if the first priority is less than the second priority, then the high-priority data is determined to be the second data to be written and the low-priority data is determined to be the first data to be written; if the first priority and the second priority are the same, then the high-priority data is either the first data to be written or the second data to be written, and the other data is the low-priority data.

[0081] After determining the high-priority and low-priority data, write the high-priority data and low-priority data sequentially into the first-priority FIFO.

[0082] Step S120: Send the high-priority data to the first slave device cache corresponding to the first priority FIFO through the first priority FIFO;

[0083] In this embodiment, after writing high-priority data and low-priority data into the first priority FIFO, the high-priority data in the first priority FIFO is sent to the first slave device cache corresponding to the first priority FIFO based on the first-in-first-out strategy.

[0084] Step S130: The high-priority data in the first slave device's cache is synchronized to the first slave device corresponding to the first priority FIFO via the synchronization arbitration module based on the I2C bus;

[0085] In this embodiment of the application, after high-priority data is cached in the first slave device cache, the high-priority data in the first slave device cache is synchronized to the first slave device corresponding to the first priority FIFO via the synchronization arbitration module based on the I2C bus. Further, in a feasible implementation, step S130 may include steps S131~S132:

[0086] Step S131: Send a transmission request to the synchronization arbitration module through the first slave device cache, so that the synchronization arbitration module determines the first data transmission timing based on a preset arbitration strategy;

[0087] Step S132: Based on the synchronization signal of the synchronization arbitration module during the first data transmission, the high-priority data in the buffer of the first slave device is sent to the I2C bus via the I2C bus FIFO, so that the first slave device can obtain the high-priority data through the I2C bus.

[0088] In this embodiment of the application, after high-priority data is cached in the first slave device cache, the cache module sends the transmission request of the first slave device cache to the synchronization arbitration module. The synchronization arbitration module determines the first data transmission timing based on a preset arbitration strategy, that is, the first data transmission timing is the timing when the synchronization arbitration module allows the first slave device cache to upload data to the I2C bus.

[0089] The preset arbitration strategy can be a priority strategy, such as processing transmission requests with higher priority first; a polling strategy, such as the synchronous arbitration module polling each slave device's buffer, with the first data transmission timing being the moment the poll reaches the first slave device's buffer; or a fair queuing strategy, with the first data transmission timing being the moment the queue reaches the first slave device's buffer. Alternatively, the first data transmission timing can be when the I2C bus is idle.

[0090] Next, based on the synchronization signal of the synchronization arbitration module during the first data transmission, the high-priority data in the first slave device buffer is sent to the I2C bus via the I2C bus FIFO. Specifically, when the first slave device buffer is allowed to upload data to the I2C bus, the synchronization arbitration module sends a synchronization signal to the first slave device buffer and the I2C master device interface. At this time, the first slave device buffer sends the high-priority data to the I2C bus FIFO of the I2C master device interface. The I2C bus FIFO uploads the high-priority data to the I2C bus through the I2C master device interface, and the first slave device obtains the high-priority data through the I2C bus.

[0091] Step S140: When the high-priority data synchronization is completed, the low-priority data is sent to the first slave device cache through the first priority FIFO;

[0092] In this embodiment of the application, when the high-priority data synchronization is completed, the low-priority data in the first priority FIFO is sent to the first slave device cache corresponding to the first priority FIFO based on the first-in-first-out strategy.

[0093] Step S150: The low-priority data in the cache of the first slave device is synchronized to the first slave device via the synchronization arbitration module based on the I2C bus.

[0094] In this embodiment of the application, after caching low-priority data in the first slave device cache, the cache module sends the transmission request of the first slave device cache to the synchronization arbitration module. The synchronization arbitration module determines the first data transmission timing based on a preset arbitration strategy, that is, the first data transmission timing is the timing when the synchronization arbitration module allows the first slave device cache to upload data to the I2C bus.

[0095] Next, based on the synchronization signal of the synchronization arbitration module during the first data transmission, the low-priority data in the first slave device buffer is sent to the I2C bus via the I2C bus FIFO. Specifically, when the first slave device buffer is allowed to upload data to the I2C bus, the synchronization arbitration module sends a synchronization signal to the first slave device buffer and the I2C master device interface. At this time, the first slave device buffer sends the low-priority data to the I2C bus FIFO of the I2C master device interface. The I2C bus FIFO uploads the low-priority data to the I2C bus through the I2C master device interface, and the first slave device obtains the low-priority data through the I2C bus.

[0096] Furthermore, in one feasible implementation, the I2C bus-based communication control method further includes A110~A140:

[0097] Step A110: Write the received third data to be written into the second priority FIFO in the priority FIFO, wherein the third master device in each master device sends the third data to be written to the second priority FIFO through the corresponding slave interface;

[0098] Step A130: The third data to be written is sent to the second slave device cache corresponding to the second priority FIFO through the second priority FIFO;

[0099] Step A130: Send a transmission request to the synchronization arbitration module through the second slave device cache, so that the synchronization arbitration module determines the timing of the second data transmission based on a preset arbitration strategy;

[0100] Step A140: Based on the second data transmission timing, the third data to be written in the second slave device cache is sent to the I2C bus via the I2C bus FIFO through the synchronous arbitration module, so that the second slave device corresponding to the second priority FIFO can obtain the third data to be written through the I2C bus.

[0101] In this embodiment, when the third master device needs to write data to the slave device, the third master device sends the third data to be written to the second priority FIFO through the corresponding slave interface. The second priority FIFO then writes the received third data to be written. Next, the third data to be written is sent to the second slave device's cache through the second priority FIFO.

[0102] After the third data to be written is cached in the second slave device cache, the cache module sends a transmission request from the second slave device cache to the synchronization arbitration module, so that the synchronization arbitration module determines the timing of the second data transmission based on the preset arbitration strategy. That is, the timing of the second data transmission is the timing when the synchronization arbitration module allows the first slave device cache to upload data to the I2C bus.

[0103] Next, based on the second data transmission timing, the third data to be written in the second slave device buffer is sent to the I2C bus via the synchronization signal of the synchronization arbitration module through the I2C bus FIFO. Specifically, when the second slave device buffer is allowed to upload data to the I2C bus, the synchronization arbitration module sends a synchronization signal to the second slave device buffer and the I2C master device interface. At this time, the second slave device buffer sends the third data to be written to the I2C bus FIFO of the I2C master device interface. The I2C bus FIFO uploads the third data to be written to the I2C bus through the I2C master device interface, and the first slave device obtains the third data to be written through the I2C bus.

[0104] It should be noted that if the synchronous arbitration module receives transmission requests from two or more slave device caches at the same time, the synchronous arbitration module can determine the data transmission timing of each transmission request based on the priority of the master device corresponding to the multiple transmission requests. If the master device corresponding to the multiple transmission requests is the same master device, the data transmission timing of each transmission request is determined according to the polling strategy, which can be based on the number of the slave device cache.

[0105] Furthermore, in one feasible implementation, the I2C bus-based communication control method further includes steps B110-B130:

[0106] Step B110: If the third priority FIFO in the priority FIFO receives both the first read request and the second read request at the same time, then the first read request and the second read request are written into the third priority FIFO in sequence. In this case, the fourth master device in each master device sends the first read request to the third priority FIFO through the corresponding slave interface, and the fifth master device in each master device sends the second read request to the third priority FIFO through the corresponding slave interface.

[0107] Step B120: The read requests of the head of the third priority FIFO are sequentially sent to the third slave device cache corresponding to the third priority FIFO, and the read requests in the third slave device cache are synchronized to the third slave device corresponding to the third priority FIFO through the synchronization arbitration module based on the I2C bus. The third slave device caches the read data corresponding to the current read request in the third slave device cache.

[0108] In step B130, when the first read data corresponding to the first read request and the second read data corresponding to the second read request are cached in the third slave device cache, based on the sending time corresponding to the first read request and the sending time of the second read request, the first read data and the second read data are sequentially written into the third priority FIFO, and the read data at the head of the third priority FIFO is sent to the corresponding master device.

[0109] In this embodiment, when multiple master devices simultaneously read data from the same slave device, for example, the fourth master device sends a first read request to the third priority FIFO through its corresponding slave interface, and the fifth master device sends a second read request to the third priority FIFO through its corresponding slave interface. At this time, the third priority FIFO receives both the first and second read requests simultaneously, and then writes the first and second read requests into the third priority FIFO sequentially. In this embodiment, the first and second read requests can be written sequentially according to the priorities of the fourth and fifth master devices, that is, the higher priority read request is written first. Alternatively, the first and second read requests can be written randomly into the third priority FIFO.

[0110] After writing the first read request and the second read request into the third priority FIFO, the read requests at the head of the third priority FIFO queue are sequentially sent to the third slave device buffer corresponding to the third priority FIFO. The read requests in the third slave device buffer are synchronized to the third slave device corresponding to the third priority FIFO via the I2C bus through the synchronization arbitration module. The third slave device buffers the read data corresponding to the current read request in its buffer. For example, the third slave device buffers the corresponding read data in its buffer via a "bidirectional synchronization" signal line. Further, in a feasible implementation, step B120 may include steps B121~B124:

[0111] Step B121: Send the read request of the head of the third priority FIFO to the third slave device cache corresponding to the third priority FIFO;

[0112] Step B122: Send a transmission request to the synchronization arbitration module through the first slave device cache, so that the synchronization arbitration module can determine the timing of the third data transmission based on a preset arbitration strategy;

[0113] Step B123: Based on the third data transmission timing, the read request in the first slave device cache is sent to the I2C bus via the synchronization signal of the synchronization arbitration module through the I2C bus FIFO, so that the first slave device can obtain the read request through the I2C bus and cache the read data corresponding to the current read request in the third slave device cache;

[0114] Step B124, return to the step of sending the read request of the third priority FIFO head to the third slave device cache corresponding to the third priority FIFO.

[0115] In this embodiment, after writing the first read request and the second read request to the third priority FIFO, the read request at the head of the third priority FIFO queue is sent to the third slave device cache corresponding to the third priority FIFO. Then, the cache module sends the transmission request of the first slave device cache to the synchronization arbitration module. The synchronization arbitration module determines the third data transmission timing based on a preset arbitration strategy. The arbitration of the third data transmission timing is the same as the arbitration process of the first data transmission timing in the above embodiment.

[0116] Based on the third data transmission timing, the synchronization arbitration module sends the read request in the first slave device cache to the I2C bus via the I2C bus FIFO through the synchronization signal. Specifically, when the third slave device cache is allowed to upload data to the I2C bus during the third data transmission, the synchronization arbitration module sends a synchronization signal to the third slave device cache and the I2C master device interface. At this time, the third slave device cache sends the read request to the I2C bus FIFO of the I2C master device interface. The I2C bus FIFO uploads the read request to the I2C bus through the I2C master device interface. The third slave device obtains the read request through the I2C bus and caches the read data corresponding to the current read request in the third slave device cache. For example, the third slave device caches the corresponding read data in the third slave device cache through the "bidirectional synchronization" signal line.

[0117] After caching the corresponding read data in the third slave device cache, the process returns to the step of sending the read request of the head of the third priority FIFO to the third slave device cache corresponding to the third priority FIFO, so as to cache the read data of another read request in the third slave device cache.

[0118] In this embodiment, when the first read data corresponding to the first read request and the second read data corresponding to the second read request are cached in the third slave device cache, based on the sending time of the first read request and the sending time of the second read request, the first read data and the second read data are sequentially written into the third priority FIFO, that is, the first read data and the second read data are written into the third priority FIFO according to the order in which the master device sends the read requests, and the read data at the head of the third priority FIFO queue is sent to the corresponding master device. In a feasible implementation, step B130 may include steps B131~B134:

[0119] Step B131: Based on the sending time corresponding to the first read request and the sending time of the second read request, determine the first target data of the master device to be read first and the second target data of the master device to be read later from the first read data and the second read data;

[0120] Step B132: Write the first target data and the second target data sequentially into the third priority FIFO;

[0121] Step B133: The first target data of the third priority FIFO head is sent to the first-read master device through the corresponding slave interface;

[0122] Step B134: The second target data of the third priority FIFO head is sent to the master device for subsequent reading through the corresponding slave interface.

[0123] In this embodiment, based on the sending time corresponding to the first read request and the sending time of the second read request, the first target data of the master device to be read first and the second target data of the master device to be read later are determined from the first read data and the second read data. The master device to be read first is the master device with the earlier sending time between the fourth master device and the fifth master device, and the master device to be read later is the master device with the later sending time between the fourth master device and the fifth master device.

[0124] After determining the first target data and the second target data, the caching module sequentially writes the first target data and the second target data into the third priority FIFO. At this time, the first target data at the head of the third priority FIFO is sent to the first read master device through the corresponding slave interface. After being sent to the first read master device, the data at the head of the third priority FIFO is the second target data. Then, the second target data at the head of the third priority FIFO is sent to the next read master device through the corresponding slave interface.

[0125] Furthermore, in one feasible implementation, the I2C bus-based communication control method further includes steps C110 to C150:

[0126] Step C110: Write the received third read request into the fourth priority FIFO in the priority FIFO, wherein the sixth master device in each master device sends the third read request to the fourth priority FIFO through the corresponding slave interface;

[0127] Step C120: The third read request is sent to the fourth slave device cache corresponding to the fourth priority FIFO through the fourth priority FIFO;

[0128] Step C130: Send a transmission request to the synchronization arbitration module through the fourth slave device buffer, so that the synchronization arbitration module determines the timing of the fourth data transmission based on a preset arbitration strategy;

[0129] Step C140: Based on the data transmission timing, through the synchronous arbitration module, the third read request in the fourth slave device cache is sent to the I2C bus via the I2C bus FIFO, so that the second slave device corresponding to the fourth priority FIFO can obtain the third read request through the I2C bus and cache the third target number corresponding to the third read request in the fourth slave device cache;

[0130] Step C150: Write the third target data in the fourth slave device's cache into the fourth priority FIFO, and send the third target data at the head of the fourth priority FIFO queue to the sixth master device through the corresponding slave interface.

[0131] In this embodiment, when a master device reads data from a slave device, the sixth master device among the master devices sends a third read request to the fourth priority FIFO through the corresponding slave interface. The fourth priority FIFO is the priority FIFO corresponding to the slave device that needs to be read. The received third read request is written into the fourth priority FIFO. Then, the third read request is sent to the fourth slave device buffer corresponding to the fourth priority FIFO through the fourth priority FIFO. That is, when the third read request is at the head of the queue of the fourth priority FIFO, the third read request at the head of the fourth priority FIFO queue is sent to the fourth slave device buffer.

[0132] Next, the caching module sends the fourth transmission request corresponding to the device cache to the synchronization arbitration module. The synchronization arbitration module determines the fourth data transmission timing based on a preset arbitration strategy. The arbitration of the fourth data transmission timing is the same as the arbitration process of the first data transmission timing in the above embodiment.

[0133] Based on the timing of data transmission, the synchronous arbitration module sends the third read request from the fourth slave device's cache to the I2C bus via the I2C bus FIFO.

[0134] Specifically, when the fourth slave device buffer is allowed to upload data to the I2C bus during the third data transmission, the synchronization arbitration module sends a synchronization signal to the fourth slave device buffer and the I2C master device interface. At this time, the fourth slave device buffer sends the third read request to the I2C bus FIFO of the I2C master device interface. The I2C bus FIFO uploads the third read request to the I2C bus through the I2C master device interface. The fourth slave device obtains the third read request through the I2C bus and caches the read data corresponding to the third read request in the fourth slave device buffer. For example, the fourth slave device caches the corresponding read data in the fourth slave device buffer through the "bidirectional synchronization" signal line.

[0135] Subsequently, the caching module writes the third target data from the fourth slave device's cache into the fourth priority FIFO, and sends the third target data at the head of the fourth priority FIFO queue to the sixth master device through the corresponding slave interface.

[0136] This application presents a communication control method based on the I2C bus. When multiple master devices simultaneously write data to the same slave device, the written data is added to the corresponding priority FIFO according to the priority of the master device, and the written data is cached to the corresponding slave device cache through the priority FIFO. The synchronous arbitration module synchronizes each written data to the corresponding slave device, thereby reducing the switching delay of the I2C switch during I2C bus communication and effectively improving the communication efficiency of I2C bus communication.

[0137] This application avoids the physical switching delay of the I2C switch by establishing an independent buffer and interface for each slave device. The synchronous arbitration mechanism enables the bus to achieve a near-seamless transition between busy and idle states, greatly improving bus utilization and the overall data throughput of the system. The buffer mechanism effectively prevents data loss due to bus congestion. Synchronous arbitration ensures the priority transmission of critical task data, significantly reducing communication latency and meeting the real-time requirements of multi-master systems.

[0138] If so, the system no longer relies on a single I2C switch. Even if a slave device interface or buffer fails, it usually will not affect the normal communication of other slave devices, thus enhancing the system's fault tolerance and reliability.

[0139] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the communication control method based on the I2C bus in this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0140] This application provides a communication control device based on an I2C bus. The I2C bus-based communication control device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the I2C bus-based communication control method in the above embodiment 1.

[0141] The following is for reference. Figure 4 This document illustrates a schematic diagram of a communication control device based on the I2C bus suitable for implementing embodiments of this application. The I2C bus-based communication control device in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), and in-vehicle terminals (e.g., in-vehicle navigation terminals), as well as fixed terminals such as digital TVs and desktop computers. Figure 4 The communication control device based on the I2C bus shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0142] like Figure 4As shown, the I2C bus-based communication control device may include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1003 into random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the I2C bus-based communication control device. The processing device 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the I2C bus-based communication control device to exchange data with other devices wirelessly or via wired communication. Although the figure shows I2C bus-based communication control devices with various systems, it should be understood that it is not required to implement or possess all the systems shown. More or fewer systems can be implemented alternatively.

[0143] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0144] The I2C bus-based communication control device provided in this application, employing the I2C bus-based communication control method in the above embodiments, can solve the technical problem of improving the communication efficiency when using the I2C bus. Compared with the prior art, the beneficial effects of the I2C bus-based communication control device provided in this application are the same as those of the I2C bus-based communication control method provided in the above embodiments, and other technical features in this I2C bus-based communication control device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0145] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0146] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0147] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the I2C bus-based communication control method in the above embodiments.

[0148] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0149] The aforementioned computer-readable storage medium may be included in an I2C bus-based communication control device; or it may exist independently and not assembled into an I2C bus-based communication control device.

[0150] The aforementioned computer-readable storage medium carries one or more programs. When these programs are executed by an I2C bus-based communication control device, the I2C bus-based communication control device performs the following actions: If a first priority FIFO in a priority FIFO simultaneously receives first data to be written and second data to be written, then, in the first priority FIFO, it sequentially writes high-priority data from the first data to be written and low-priority data from the second data to be written. Specifically, a first master device sends the first data to be written to the first priority FIFO via a corresponding slave interface, and a second master device sends the second data to be written to the first priority FIFO via a corresponding slave interface; the high-priority data is then sent down to the first slave device buffer corresponding to the first priority FIFO via the first priority FIFO; the high-priority data in the first slave device buffer is synchronized to the first slave device corresponding to the first priority FIFO via the synchronization arbitration module based on the I2C bus; when the high-priority data synchronization is complete, the low-priority data is sent down to the first slave device buffer via the first priority FIFO; and the low-priority data in the first slave device buffer is synchronized to the first slave device via the synchronization arbitration module based on the I2C bus.

[0151] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0152] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0153] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0154] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described I2C bus-based communication control method, thereby solving the technical problem of improving communication efficiency when using the I2C bus. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the I2C bus-based communication control method provided in the above embodiments, and will not be repeated here.

[0155] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the communication control method based on the I2C bus described above.

[0156] The computer program product provided in this application can solve the technical problem of improving the communication efficiency of communication using the I2C bus. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as the beneficial effects of the communication control method based on the I2C bus provided in the above embodiments, and will not be repeated here.

[0157] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A communication control method based on an I2C bus, characterized by, The application is applied to an I2C communication system, the I2C communication system comprises a plurality of master devices, a plurality of slave devices and a synchronous arbitration module, the I2C communication system is also provided with a slave interface corresponding to each master device, a slave device cache corresponding to each slave device and a priority first-in-first-out queue (FIFO), each slave device is connected with an I2C master device interface through an I2C bus; the communication control method based on the I2C bus comprises: If a first priority FIFO in the priority FIFO simultaneously receives first to-be-written data and second to-be-written data, then in the first priority FIFO, high-priority data and low-priority data in the first to-be-written data and the second to-be-written data are sequentially written, wherein a first master device in each master device sends first to-be-written data to the first priority FIFO through a corresponding slave interface, and a second master device in each master device sends second to-be-written data to the first priority FIFO through a corresponding slave interface; The high-priority data is sent to a first slave device cache corresponding to the first priority FIFO through the first priority FIFO; The high-priority data in the first slave device cache is synchronized to the first slave device corresponding to the first priority FIFO based on the I2C bus through the synchronous arbitration module; When the synchronization of the high-priority data is completed, the low-priority data is sent to the first slave device cache through the first priority FIFO; The low-priority data in the first slave device cache is synchronized to the first slave device based on the I2C bus through the synchronous arbitration module; The I2C master device interface is provided with an I2C bus FIFO, and the step of synchronizing the high-priority data in the first slave device cache to the first slave device corresponding to the first priority FIFO based on the I2C bus through the synchronous arbitration module comprises: A transmission request is sent to the synchronous arbitration module through the first slave device cache, so that the synchronous arbitration module determines a first data transmission opportunity based on a preset arbitration strategy; The high-priority data in the first slave device cache is sent to the I2C bus through the I2C bus FIFO based on the synchronous signal of the synchronous arbitration module based on the first data transmission opportunity, so that the first slave device obtains the high-priority data through the I2C bus.

2. The communication control method based on the I2C bus according to Claim 1, characterized by, The step of sequentially writing the high-priority data and the low-priority data in the first to-be-written data and the second to-be-written data in the first priority FIFO if the first priority FIFO in the priority FIFO simultaneously receives the first to-be-written data and the second to-be-written data comprises: If the first priority FIFO simultaneously receives the first to-be-written data and the second to-be-written data, a first priority of the first master device and a second priority of the second master device are obtained; Based on the first priority and the second priority, high-priority data and low-priority data are determined in the first to-be-written data and the second to-be-written data; The high-priority data and the low-priority data are sequentially written in the first priority FIFO.

3. The communication control method based on the I2C bus according to Claim 1, wherein The I2C bus-based communication control method further comprises: writing the received third data to be written in a second priority FIFO in the priority FIFOs, wherein a third master device in each master device sends third data to be written to the second priority FIFO through a corresponding slave interface; downlinking the third data to be written in the second priority FIFO to a second slave device cache corresponding to the second priority FIFO through the second priority FIFO; sending a transmission request to the synchronization arbitration module through the second slave device cache, so that the synchronization arbitration module determines a second data transmission opportunity based on a preset arbitration strategy; based on the second data transmission opportunity, sending the third data to be written in the second slave device cache to the I2C bus through the I2C bus FIFO through the synchronization arbitration module, so that the second slave device corresponding to the second priority FIFO acquires the third data to be written through the I2C bus.

4. The communication control method based on the I2C bus according to Claim 1, characterized by, The I2C bus-based communication control method further comprises: if a third priority FIFO in the priority FIFOs simultaneously receives a first read request and a second read request, sequentially writing the first read request and the second read request in the third priority FIFO, wherein a fourth master device in each master device sends the first read request to the third priority FIFO through a corresponding slave interface, and a fifth master device in each master device sends the second read request to the third priority FIFO through a corresponding slave interface; sequentially downlinking the read request at the head of the third priority FIFO to a third slave device cache corresponding to the third priority FIFO, and synchronizing the read request in the third slave device cache to the third slave device corresponding to the third priority FIFO through the synchronization arbitration module based on the I2C bus, wherein the third slave device caches read data corresponding to the current read request in the third slave device cache; when the first read data corresponding to the first read request and the second read data corresponding to the second read request are cached in the third slave device cache, sequentially writing the first read data and the second read data in the third priority FIFO based on the sending time of the first read request and the sending time of the second read request, and sending the read data at the head of the third priority FIFO to the corresponding master device.

5. The communication control method based on the I2C bus according to Claim 4, characterized by, The step of sequentially writing the first read data and the second read data in the third priority FIFO based on the sending time of the first read request and the sending time of the second read request, and sending the read data at the head of the third priority FIFO to the corresponding master device comprises: determining first target data of a first master device and second target data of a second master device in the first read data and the second read data based on the sending time of the first read request and the sending time of the second read request; write the first target data and the second target data into the third priority FIFO in sequence; send the first target data at the head of the third priority FIFO to the first master device through the corresponding slave interface; send the second target data at the head of the third priority FIFO to the second master device through the corresponding slave interface.

6. The communication control method based on an I2C bus according to Claim 4, wherein, The read request at the head of the third priority FIFO is sent to the third slave device cache corresponding to the third priority FIFO, and the read request in the third slave device cache is synchronized to the third slave device corresponding to the third priority FIFO based on the I2C bus through the synchronization arbitration module, wherein the third slave device caches the read data corresponding to the current read request in the third slave device cache, including: sending the read request at the head of the third priority FIFO to the third slave device cache corresponding to the third priority FIFO; sending a transmission request to the synchronization arbitration module through the third slave device cache, so that the synchronization arbitration module determines a third data transmission opportunity based on a preset arbitration strategy; based on the third data transmission opportunity, the read request in the third slave device cache is sent to the I2C bus through the I2C bus FIFO based on the synchronization signal of the synchronization arbitration module, so that the third slave device acquires the read request through the I2C bus and caches the read data corresponding to the current read request in the third slave device cache; return to the step of sending the read request at the head of the third priority FIFO to the third slave device cache corresponding to the third priority FIFO.

7. The communication control method based on an I2C bus according to any one of claims 1 to 6, characterized by, The I2C bus-based communication control method further includes: writing a received third read request into a fourth priority FIFO in the priority FIFO, wherein a sixth master device in each master device sends a third read request to the fourth priority FIFO through a corresponding slave interface; sending the third read request to the fourth slave device cache corresponding to the fourth priority FIFO through the fourth priority FIFO; sending a transmission request to the synchronization arbitration module through the fourth slave device cache, so that the synchronization arbitration module determines a fourth data transmission opportunity based on a preset arbitration strategy; based on the data transmission opportunity, the third read request in the fourth slave device cache is sent to the I2C bus through the I2C bus FIFO based on the synchronization signal of the synchronization arbitration module, so that the fourth slave device corresponding to the fourth priority FIFO acquires the third read request through the I2C bus and caches the third target data corresponding to the third read request in the fourth slave device cache; write the third target data in the fourth slave device cache into the fourth priority FIFO, and send the third target data at the head of the fourth priority FIFO to the sixth master device through the corresponding slave interface.

8. A communication control device based on an I2C bus, characterized by comprising: The I2C bus-based communication control device comprises a memory, a processor, and a computer program stored on the memory and executable on the processor, and the computer program is configured to implement the steps of the I2C bus-based communication control method according to any one of claims 1 to 7.

9. A storage medium, characterized by The storage medium is a computer readable storage medium, and the storage medium stores a computer program, and the computer program is executed by the processor to implement the steps of the I2C bus-based communication control method according to any one of claims 1 to 7.

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