A uvm verification method for dynamically configuring i2c bus timing parameters

Abstract

The application discloses a kind of UVM verification methods of dynamically configuring I2C bus timing parameter, setting timing parameter, and the interval range of the limit value of timing parameter communication is obtained by first round of cyclic simulation, then the upper and lower limit values of timing parameter communication are obtained after adjusting timing parameter and carrying out second round of cyclic simulation, to supply UVM to I2C bus system for verification.The application can dynamically adjust output different delay signals according to the I2C bus timing parameter controller adjustment function, to construct the working scene of I2C bus as much as possible real and effective, and carry out upper limit and lower limit delay offset processing to signal, solve the deficiency of prior art.

Description

Technical Field

[0001] This invention relates to a UVM verification method, and more particularly to a UVM verification method for dynamically configuring I2C bus timing parameters, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] I2C (Inter-Integrated Circuit) is a widely used two-wire serial communication protocol developed by Philips (now NXP). Universal Verification Methodology (UVM) is the standard verification methodology in the field of integrated circuit design. It uses the SystemVerilog language to build a verification environment to improve the automation level of the verification process and shorten the chip verification cycle.

[0003] However, due to differences in integrated circuit manufacturing processes, signal quality and latency can be greatly affected, especially in fast mode (400kbps) and high-speed mode (3.4Mbps). Signal delay may cause changes in the I2C bus level, resulting in timing violations when I2C communication devices receive data, ultimately leading to I2C bus communication failure. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a UVM verification method for dynamically configuring I2C bus timing parameters, which meets the different communication rate requirements of I2C bus in the chip pre- and post-simulation verification process and solves the problem of inflexible signal delay in the verification system.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A UVM verification method for dynamically configuring I2C bus timing parameters includes the following steps: S1. The timing parameters of the initial I2C are at their default values. Based on the verification scenario, the timing limit scenario parameters i, simulation number j, timing upper limit scenario parameter step 1, and timing lower limit scenario parameter step 2 are dynamically input. S2. If i is 0, this simulation is a timing upper limit scenario; if i is not 0, this simulation is a timing lower limit scenario. S3. Configure the first timing parameter cfg_time1: If this simulation is a timing upper limit scenario, then the first timing parameter cfg_time1 = spec_time + m * step1, where m is the loop variable and spec_time is the minimum value of the timing parameter specified by spec; if this simulation is a timing lower limit scenario, then the first timing parameter cfg_time1 = spec_time - n * step2, where n is the loop variable. S4. If the simulation result is successful and m < j at this time, then jump to step S3 and start the simulation again. S5. If the simulation fails, and m=k and m≤j, then the upper limit time tmax of the timing parameter or the middle of the lower limit time tmin of the timing parameter is located at the first timing parameter time cfg_time of the k-th simulation. k-1 The first timing parameter cfg_time in the (k+1)th simulation k between; S6. Set the upper limit of the timing scenario parameter step size step1 = step1 / s, the lower limit of the timing scenario parameter step size step2 = step2 / s, and the number of simulations j = s; S7. Configure the second timing parameter cfg_time2: If this simulation is a timing limit scenario, then the second timing parameter cfg_time2 = cfg_time k-1 +p*step1, where p is the loop variable; if this simulation is a lower time-limit scenario, then the second time-series parameter time cfg_time2=cfg_time k -p*step2; S8. If the simulation result is successful and p < s at this time, then jump to step S7 to start the simulation again. S9. If the simulation fails, and m = q and m ≤ s, then the upper limit of the timing parameter tmax = cfg_time q-1 The lower limit time for the timing parameter tmin = cfg_time q-1 cfg_time q-1 It is the second timing parameter time in the q-th simulation; S10. Verify the I2C bus design scheme based on the obtained upper limit time tmax and lower limit time tmin of the timing parameters.

[0006] Furthermore, the default value of the timing limit scenario selection parameter i is 0, the default value of the simulation number j is 0, the default value of the timing upper limit scenario parameter step1 is 10ns, and the default value of the timing lower limit scenario parameter step2 is 10ns.

[0007] Furthermore, the initial value of the loop variable m is 0.

[0008] Furthermore, in step S6, the default value of s is 10.

[0009] Furthermore, in step S4, if the simulation result is successful and m=j at this time, then let the simulation number j=j+x, where x is a constant, and jump to step S3 to start the simulation again.

[0010] Furthermore, the value of step1 / s is less than the accuracy requirement of the upper limit time tmax of the timing parameter, and the value of step2 / s is less than the accuracy requirement of the lower limit time tmin of the timing parameter.

[0011] Compared with the prior art, the present invention has the following advantages and effects: 1. This invention provides a UVM verification method for dynamically configuring I2C bus timing parameters. Based on the adjustment function of the I2C bus timing parameter controller, the system can dynamically adjust the output of different delay signals to construct the working scenario of the I2C bus in the most realistic and effective way, and perform upper and lower limit delay offset processing on the signals. 2. This invention provides dynamically configurable communication timing parameters, greatly expanding the working scenarios for asynchronous signal timing and solving asynchronous problems such as signal metastability, signal oversampling, and signal non-sampling; 3. When the present invention uses the lowest standard timing parameters of the I2C bus specification for communication, it can verify the chip's ability to process I2C read and write frames under the extreme timing conditions, and solve the problem of frame loss and frame errors caused by slow response in the design. 4. This invention uses a large number of random timing parameters step1 and step2, a large number of simulation times j, and a large number of verification scenarios i to generate different working scenarios for I2C, thereby solving the abnormal communication problem caused by random signals. Attached Figure Description

[0012] Figure 1 This is an I2C bus timing parameter diagram of a UVM verification method for dynamically configuring I2C bus timing parameters according to the present invention. Detailed Implementation

[0013] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0014] like Figure 1 As shown, some timing parameters according to the I2C bus 400K communication frequency specification are as follows: t0 is the I2C start time (min: 600ns); t1 is the I2C SDA setup time (min 100ns); t2 is I2C SCL low period time (min:1300ns); t3 is I2C SCL high period time (min: 600ns); t4 is the I2C stop time (min: 600ns); t5 is the I2C bus free time (min: 1300ns).

[0015] Therefore, this invention aims to limit the normal communication timing of the I2C bus under different verification scenarios.

[0016] The present invention provides a UVM verification method for dynamically configuring I2C bus timing parameters, comprising the following steps: S1. The timing parameters of the initial I2C are at their default values. Based on the verification scenario, the timing limit scenario selects parameters i, simulation number j, timing upper limit scenario parameter step1, and timing lower limit scenario parameter step2.

[0017] The default values ​​for parameter i in the timing limit scenario are 0, the default values ​​for the number of simulations j are 0, the default values ​​for the parameter step size step1 in the timing upper limit scenario are 10ns, and the default values ​​for the parameter step size step2 in the timing lower limit scenario are 10ns.

[0018] S2. If i is 0, this simulation is a timing upper limit scenario; if i is not 0, this simulation is a timing lower limit scenario.

[0019] S3. Configure the first timing parameter cfg_time1: If this simulation is a timing upper limit scenario, then the first timing parameter cfg_time1 = spec_time + m * step1, where m is the loop variable and spec_time is the minimum value of the timing parameter specified in the spec; if this simulation is a timing lower limit scenario, then the first timing parameter cfg_time1 = spec_time - n * step2, where n is the loop variable. The initial value of the loop variable m is 0, that is, when communicating with the lowest standard timing parameters of the I2C bus spec at the beginning, the chip's ability to process I2C read and write frames under this extreme timing can be verified, solving the problem of frame loss and frame errors caused by slow response in the design.

[0020] S4. If the simulation is successful and m < j, then proceed to step S3 to restart the simulation. Continue until the simulation fails. The time interval of the timing parameters obtained from the last successful simulation and the failed simulation is the interval containing the limit value we are looking for.

[0021] In step S4, if the simulation result is successful and m=j at this point, then let the simulation count j=j+x, where x is a constant, and jump to step S3 to restart the simulation. The initial value of the simulation count is 0, and the default setting is usually 100. When the limit value is large, if the limit value is not reached after 100 simulations, then the simulation count j is increased and the simulation is repeated until the range of the limit value found in step S4 can be reached normally.

[0022] S5. If the simulation fails, and m=k and m≤j, then the upper limit time tmax of the timing parameter or the middle of the lower limit time tmin of the timing parameter is located at the first timing parameter time cfg_time of the k-th simulation. k-1 The first timing parameter cfg_time in the (k+1)th simulation k The range of the limit value is obtained by considering the initial step size. Since the initial step size is relatively large, the range is still relatively large.

[0023] S6. Set the upper limit of the timing scenario parameter step size to step1 = step1 / s, the lower limit of the timing scenario parameter step size to step2 = step2 / s, and the number of simulations j = s. The default value of s is 10, that is, the default precision is 1ns.

[0024] The value of step1 / s is less than the accuracy requirement of the upper limit time tmax of the timing parameter, and the value of step2 / s is less than the accuracy requirement of the lower limit time tmin of the timing parameter.

[0025] S7. Configure the second timing parameter cfg_time2: If this simulation is a timing limit scenario, then the second timing parameter cfg_time2 = cfg_time k-1 +p*step1, where p is the loop variable; if this simulation is a lower time-limit scenario, then the second time-series parameter time cfg_time2=cfg_time k -p*step2.

[0026] S8. If the simulation result is successful and p < s at this time, then jump to step S7 to start the simulation again.

[0027] S9. If the simulation fails, and m = q and m ≤ s, then the upper limit of the timing parameter tmax = cfg_time q-1 The lower limit time for the timing parameter tmin = cfg_time q-1 cfg_time q-1This is the second timing parameter time in the q-th simulation. At this point, we have obtained the limit value within the required accuracy range. The first time, we obtain the interval where the limit value is located. The second time, we perform a second loop within this interval to find the limit value. This reduces the number of simulations and improves the efficiency of finding the limit value.

[0028] S10. Verify the I2C bus design scheme based on the obtained upper limit time tmax and lower limit time tmin of the timing parameters.

[0029] This invention provides a UVM verification method for dynamically configuring I2C bus timing parameters. Based on the I2C bus timing parameter controller adjustment function, the system can dynamically adjust the output of different delay signals to construct the I2C bus working scenario as realistically and effectively as possible, and perform upper and lower limit delay offset processing on the signals. This invention provides dynamically configurable communication timing parameters, greatly providing working scenarios for asynchronous signal timing, solving asynchronous problems such as signal metastability, signal oversampling, and signal non-sampling. When using the lowest standard timing parameters of the I2C bus specification for communication, this invention can verify the chip's ability to process I2C read / write frames under extreme timing conditions, solving the problem of frame loss and frame errors caused by slow response in the design. This invention uses a large number of random timing parameters (step1 and step2), a large number of simulation times (j), and a large number of verification scenarios (i) to generate different I2C working scenarios, solving the abnormal communication problem caused by random signals.

[0030] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A UVM verification method for dynamically configuring I2C bus timing parameters, characterized in that... Includes the following steps: S1. The timing parameters of the initial I2C are at their default values. Based on the verification scenario, the timing limit scenario parameters i, simulation number j, timing upper limit scenario parameter step 1, and timing lower limit scenario parameter step 2 are dynamically input. S2. If i is 0, this simulation is a timing upper limit scenario; if i is not 0, this simulation is a timing lower limit scenario. S3. Configure the first timing parameter cfg_time1: If this simulation is a timing limit scenario, then the first timing parameter cfg_time1 = spec_time + m Step 1, where m is the loop variable and spec_time is the minimum value of the timing parameter specified by spec; if this simulation is a timing lower limit scenario, then the first timing parameter time cfg_time1 = spec_time - n Step 2, where n is the loop variable; S4. If the simulation result is successful and m < j, then jump to step S3 to restart the simulation. In step S4, if the simulation result is successful and m = j, then let the number of simulations j = j + x, where x is a constant, and jump to step S3 to restart the simulation. S5. If the simulation fails, and m=k and m≤j, then the upper limit time tmax of the timing parameter or the middle of the lower limit time tmin of the timing parameter is located at the first timing parameter time cfg_time of the k-th simulation. k-1 The first timing parameter cfg_time in the (k+1)th simulation k between; S6. Set the upper limit of the timing scenario parameter step size step1 = step1 / s, the lower limit of the timing scenario parameter step size step2 = step2 / s, the number of simulations j = s, and the default value of s is 10. S7. Configure the second timing parameter cfg_time2: If this simulation is a timing limit scenario, then the second timing parameter cfg_time2 = cfg_time k-1 +p Step 1, where p is the loop variable; if this simulation is a lower time-limit scenario, then the second time-series parameter time cfg_time2 = cfg_time k -p Step 2; S8. If the simulation result is successful and p < s at this time, then jump to step S7 to start the simulation again. S9. If the simulation fails, and p = q and p ≤ s, then the upper limit of the timing parameter tmax = cfg_time q-1 The lower limit time for the timing parameter tmin = cfg_time q-1 cfg_time q-1 It is the second timing parameter time in the q-th simulation; S10. Verify the I2C bus design scheme based on the obtained upper limit time tmax and lower limit time tmin of the timing parameters.

2. The UVM verification method for dynamically configuring I2C bus timing parameters according to claim 1, characterized in that: The default value of parameter i for the time-limited scenario selection is 0, the initial value of simulation number j is 0, the default value of parameter step1 for the upper limit scenario is 10ns, and the default value of parameter step2 for the lower limit scenario is 10ns.

3. The UVM verification method for dynamically configuring I2C bus timing parameters according to claim 1, characterized in that: The initial value of the loop variable m is 0.

4. The UVM verification method for dynamically configuring I2C bus timing parameters according to claim 1, characterized in that: The value of step1 / s is less than the accuracy requirement of the upper limit time tmax of the timing parameter, and the value of step2 / s is less than the accuracy requirement of the lower limit time tmin of the timing parameter.

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