Control circuit, image compensation control device and display panel

Abstract

This application belongs to the field of display driver technology, specifically relating to a control circuit, an image compensation control device, and a display panel. The control circuit includes a screen monitoring unit that outputs a voltage signal corresponding to the current refresh rate when the current displayed screen is determined to be an abnormal screen based on multiple display parameters; a delay control unit configured to compare the voltage signal with an on threshold and an off threshold respectively, and output a switch control signal based on the comparison result; and a switch unit configured to respond to the switch control signal by turning on or off the signal path between the image compensation output terminal and the subsequent driving circuit. Therefore, this application, through the coordinated work of the screen monitoring unit, the delay control unit, and the switch unit, sets a stable buffer for the start and stop of the ICA function, eliminating the problem of frequent switching of the ICA function and screen flickering caused by fluctuations in parameters such as refresh rate near critical values.

Description

Technical Field

[0001] This disclosure belongs to the field of display driving technology, specifically relating to a control circuit, an image compensation control device, and a display panel. Background Technology

[0002] In the field of display technology, crosstalk, green screen, and other abnormal image problems are common display defects. To address these issues, existing technologies typically integrate ICA (Image Compensation Algorithm) into the timing controller. This involves dynamically adjusting the polarity arrangement of the liquid crystals when abnormal images are detected to suppress in-plane coupling effects and thus improve image quality.

[0003] Currently, the ICA (Interactive Color Assist) function's activation and deactivation mechanism relies on real-time detection of the area and grayscale value of abnormal screen regions, comparing them with preset thresholds. Since crosstalk is more pronounced at high refresh rates, ICA typically needs to be activated when the refresh rate reaches a certain threshold. However, due to the instability of front-end data transmission, the refresh rate tends to fluctuate frequently near critical values ​​(e.g., when the setting is M, both M and M-1 are critical points), causing the ICA function to repeatedly switch between on and off states. This frequent state change can cause screen flickering, severely impacting the user experience.

[0004] It is evident that the ICA function of the relevant technology frequently turns on and off when the refresh rate is near the critical value, resulting in screen flickering and reducing the stability of the displayed image. Summary of the Invention

[0005] This application provides a control circuit, an image compensation control device, and a display panel. Through the coordinated operation of the screen monitoring unit, the delay control unit, and the switching unit, this application sets a stable buffer zone for the start and stop of the ICA function, which greatly improves the stability and reliability of the start and stop of the ICA function, eliminates the problem of frequent switching of the ICA function and screen flicker caused by the fluctuation of parameters such as refresh rate near the critical value, and thus significantly improves the visual experience and user experience of the display screen.

[0006] In a first aspect, embodiments of this application provide a control circuit, the control circuit comprising: a screen monitoring unit configured to detect multiple display parameters of the currently displayed screen, and when determining that the current displayed screen is an abnormal screen based on the multiple display parameters, outputting a voltage signal corresponding to the current refresh rate; a delay control unit connected to the screen monitoring unit, the delay control unit being configured to compare the voltage signal with an on threshold and an off threshold respectively, and output a switch control signal based on the comparison result; wherein the on threshold is greater than the off threshold; and a switch unit, the control terminal of the switch unit being connected to the output terminal of the delay control unit. The first connection terminal of the switching unit is connected to the image compensation output terminal, and the second connection terminal of the switching unit is connected to the subsequent driving circuit. The switching unit is configured to respond to the switching control signal to turn on or off the signal path between the image compensation output terminal and the subsequent driving circuit. The delay control unit is configured to: switch the switching control signal to a first state when the voltage signal is greater than or equal to the on threshold; switch the switching control signal to a second state when the voltage signal is less than or equal to the off threshold; and maintain the current state of the switching control signal when the voltage signal is between the on threshold and the off threshold.

[0007] Secondly, embodiments of this application provide an image compensation control device applied to a display panel, the display panel including N display zones, and each display zone corresponding to a data driving circuit; the image compensation control device includes: a main control circuit, the main control circuit being the control circuit, configured to generate a whole-zone control signal based on the display parameters of the display panel; N zone control circuits, each zone control circuit being the control circuit; each zone control circuit being configured to generate a zone control signal based on the display parameters of the corresponding display zone; a mode switching circuit coupled to a mode output terminal, the main control circuit, the N zone control circuits, and the N data driving circuits; the mode switching circuit is configured to input the whole-zone control signal to the N data driving circuits in response to an externally input first mode selection signal; and to input the zone control signal generated by the i-th zone control circuit to the i-th data driving circuit in response to an externally input second mode selection signal, where i=1,...,N.

[0008] Thirdly, embodiments of this application provide a display panel including a display area and a non-display area. The display area includes a pixel array; the non-display area includes a timing controller, a source drive circuit, and an image compensation control device, wherein the image compensation control device is electrically connected to the timing controller and the source drive circuit, respectively.

[0009] The technical solution provided in this application has at least the following beneficial effects:

[0010] This application uses a screen monitoring unit to detect and determine in real time whether there are any abnormalities in the current display screen. When an abnormal screen is detected, the refresh rate parameter of that screen is converted into a corresponding voltage signal and output to the delay control unit. The delay control unit introduces a hysteresis range with upper and lower thresholds to perform anti-jitter judgment on the voltage signal, effectively filtering out frequent fluctuations in the refresh rate near the critical value and outputting a stable switching control signal. The switching unit responds to this control signal, precisely turning on or off the signal path from the image compensation output to the subsequent drive circuit, achieving hard enable control of the ICA function. Therefore, this application integrates screen detection, intelligent decision-making, and precise execution through the collaborative work of the screen monitoring unit, delay control unit, and switching unit, constructing a closed-loop control that is responsive, stable in judgment, and reliable in execution. Furthermore, by introducing a refresh rate-based hysteresis comparison control mechanism, a stable buffer zone is set for the start and stop of the ICA function, greatly improving the stability and reliability of ICA function start and stop, eliminating the frequent switching of the ICA function and screen flickering caused by fluctuations in parameters such as refresh rate near the critical value, thereby significantly improving the visual experience and user experience of the display screen. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0012] Figure 1 The diagram shown is a schematic diagram of a control circuit provided in an embodiment of this application.

[0013] Figure 2 The diagram shown is a circuit diagram of the first delay control unit provided in an embodiment of this application.

[0014] Figure 3 The diagram shown is a schematic diagram of the first voltage transmission characteristic provided in the embodiment of this application.

[0015] Figure 4 The diagram shown is a schematic diagram of the first type of hysteresis interval provided in the embodiment of this application.

[0016] Figure 5 The diagram shown is a circuit diagram of a second delay control unit provided in an embodiment of this application.

[0017] Figure 6 The diagram shown is a schematic diagram of the second voltage transmission characteristic provided in the embodiment of this application.

[0018] Figure 7 The diagram shown is a schematic diagram of the second type of hysteresis interval provided in the embodiments of this application.

[0019] Figure 8 The diagram shown is a circuit diagram of a third delay control unit provided in an embodiment of this application.

[0020] Figure 9 The diagram shown is a structural schematic of the first image compensation control device provided in the embodiment of this application.

[0021] Figure 10 The diagram shown is a structural schematic of the second image compensation control device provided in the embodiment of this application.

[0022] Figure 11 The diagram shown is a structural schematic of the third image compensation control device provided in the embodiments of this application.

[0023] Figure 12 The diagram shown is a circuit diagram of a frequency comparator provided in an embodiment of this application.

[0024] Figure 13 The diagram shown is a structural schematic of the fourth image compensation control device provided in the embodiments of this application.

[0025] Explanation of reference numerals in the attached figures:

[0026] 100. Control circuit; 110. Image monitoring unit; 120. Delay control unit; 121. Latch; 130. Switching unit; 200. Image compensation output terminal; 210. Whole area compensation output terminal; 220. First zone compensation output terminal; 230. Second zone compensation output terminal; 240. Third zone compensation output terminal;

[0027] 300, Image compensation control device; 310, Main control circuit; 320, Zone control circuit; 330, Mode switching circuit; 340, First frequency comparator; 350, Second frequency comparator; 360, First frequency hysteresis unit; 370, Second frequency hysteresis unit;

[0028] 400, Mode output terminal; 500, Data drive circuit; 600, Post-stage drive circuit;

[0029] T0, Switching transistor; T1, First transistor; T2, Second transistor; A1, First comparator; A2, Second comparator; G1, First NOR gate; G2, Second NOR gate; U1, First NAND gate; U2, Second NAND gate; U3, Third NAND gate; U4, Fourth NAND gate; U5, Fifth NAND gate; U6, Sixth NAND gate; U7, Seventh NAND gate; U8, AND gate; Vf1, Refresh rate output of the first display zone; Vf2, Refresh rate output of the second display zone; Vf3, Refresh rate output of the third display zone; D1, First diode; D2, Second diode; UH, Enable threshold output; UL, Disable threshold output; EN, Latch control terminal. Detailed Implementation

[0030] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0031] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0032] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0033] Firstly, embodiments of this application provide a control circuit, specifically including the following embodiments:

[0034] Figure 1 The diagram shown is a structural schematic of a control circuit 100 provided in an embodiment of this application; as follows: Figure 1 As shown, the control circuit 100 includes a screen monitoring unit 110, which is configured to detect multiple display parameters of the current display screen, and when it is determined that the current display screen is an abnormal screen based on the multiple display parameters, convert the refresh rate of the multiple display parameters into a corresponding voltage signal.

[0035] It should be noted that the control circuit 100 in this embodiment can be applied in the display panel, mainly controlling the opening and closing of the ICA function; the screen monitoring unit 110 can be integrated in the timing controller, and through the built-in algorithm or hardware circuit, it can detect multiple display parameters of the current display screen in real time. The multiple display parameters include at least the area of ​​the abnormal area, the grayscale value of the area, and the screen refresh rate.

[0036] Optionally, the image monitoring unit 110 internally presets an area threshold and a grayscale threshold. Only when the detected area and grayscale simultaneously exceed their respective thresholds will the image monitoring unit 110 determine that the current displayed image is an abnormal image; otherwise, it determines that the current displayed image is a normal image. Further, after determining that it is an abnormal image, the image monitoring unit 110 linearly converts the refresh rate into an analog voltage signal (Ui) through a data converter (e.g., a digital-to-analog converter DAC or a voltage-controlled oscillator VCO). For example, the higher the refresh rate, the higher the value of the output voltage signal Ui. It can be seen that this embodiment integrates the information of whether image compensation is needed and the refresh rate into a single voltage signal through the image monitoring unit 110, realizing the transformation from complex image parameters to a single, quantifiable electrical signal, laying the foundation for subsequent accurate judgment.

[0037] like Figure 1 As shown, the control circuit 100 of this embodiment further includes a delay control unit 120. The input terminal of the delay control unit 120 is connected to the screen monitoring unit 110. The delay control unit 120 is configured to receive a voltage signal, compare the voltage signal with an on threshold voltage and an off threshold voltage respectively, and output a switch control signal based on the comparison result. Specifically, when the voltage signal is greater than or equal to the on threshold voltage, the switch control signal switches to a first state; when the voltage signal is less than or equal to the off threshold voltage, the switch control signal switches to a second state; when the voltage signal is between the on threshold voltage and the off threshold voltage, the current state of the switch control signal is maintained. The on threshold voltage is greater than the off threshold voltage. The first state can be a high level, and the second state can be a low level. Optionally, the first state can also be a low level, and the second state can be a high level.

[0038] It should be noted that the delay control unit 120 in this embodiment receives a voltage signal Ui from the screen monitoring unit 110 and compares it with a preset hysteresis interval. The preset hysteresis interval is defined by an on threshold voltage (V_high) and an off threshold voltage (V_low), where V_high > V_low. Specifically, when the voltage signal Ui rises from low and first reaches or exceeds the on threshold voltage V_high, the module's output state flips, outputting a first-state switch control signal (e.g., a low-level transition to a high-level transition). Thereafter, if Ui fluctuates between V_high and V_low, the output state remains unchanged. Only when Ui falls from high and first reaches or falls below V_low does the module's output state flip again, outputting a second-state switch control signal (e.g., a high-level transition to a low-level transition). By introducing the preset hysteresis interval, frequent switching caused by minute signal fluctuations at a single critical point is eliminated, thereby preventing screen flicker.

[0039] In this embodiment, the control circuit 100 further includes a switching unit 130. The control terminal of the switching unit 130 is connected to the output terminal of the delay control unit 120. The first connection terminal of the switching unit 130 is connected to the image compensation output terminal 200, and the second connection terminal of the switching unit 130 is connected to the subsequent driving circuit 600. The switching unit 130 is configured to respond to a switching control signal to turn on or off the signal path between the image compensation output terminal 200 and the subsequent driving circuit 600.

[0040] It should be noted that the switching unit 130 in this embodiment can be implemented by a switching device, such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Its control terminal receives the switching control signal output from the delay control unit 120, its first connection terminal is connected to the image compensation output terminal 200, which is directly connected to the hardware output of the ICA function algorithm within the system, and its second connection terminal is connected to the subsequent driving circuit 600, which can be the corresponding control pin of the source driver chip (Source IC). When the switching control signal is valid (e.g., high level), the switching unit 130 is turned on, establishing a signal path; when the signal is invalid (e.g., low level), the switching unit 130 is turned off, disconnecting the signal path.

[0041] In this embodiment, the switching unit 130 is connected in series between the ICA function module and the source driver chip that ultimately performs compensation, acting as an electronic switch; it realizes hard on / off control of the ICA function output signal. Its direct effect is that when the switch is off, even if the ICA algorithm is still running internally, its compensation signal cannot be applied to the panel, thereby ensuring that compensation is only enabled when necessary, avoiding the side effects and power consumption that may be caused by unnecessary compensation.

[0042] The specific working principle of the control circuit 100 provided in this embodiment is as follows:

[0043] (1) After the system is powered on, the screen monitoring unit 110 continuously monitors the display screen.

[0044] (2) When a large area of ​​abnormal image with high grayscale appears, the module determines that compensation is required and converts the current refresh rate into a voltage signal Ui for output.

[0045] (3) The delay control unit 120 compares Ui with the hysteresis interval [V_low, V_high]; if the refresh rate is very high, Ui≥V_high, the delay control unit 120 outputs a high-level signal, the switching unit 130 is turned on, so that the output signal of the ICA function can be transmitted to the subsequent driving circuit 600 (source driving chip) through the turned-on switching unit 130, driving the liquid crystal molecules to change the polarity arrangement and implement image compensation.

[0046] (4) If the picture quality improves or the refresh rate drops slightly, causing Ui to fall back, but as long as Ui is still above V_low, the delay control unit 120 will maintain a high level output, the switch will remain on, and the ICA function will continue to be effective; only when the refresh rate drops significantly, making Ui ≤ V_low, will the delay control unit 120 output a low level, the switch unit 130 will turn off, completely cutting off the transmission path of the ICA signal, and the compensation will stop.

[0047] (5) After that, if the refresh rate increases again, it must reach V_high again before compensation will be enabled again.

[0048] In summary, this application uses the screen monitoring unit 110 to detect and determine in real time whether there is an abnormality in the current display screen. When an abnormal screen is determined, the refresh rate parameter of the screen is converted into a corresponding voltage signal and output to the delay control unit 120. The delay control unit 120 uses a hysteresis range with upper and lower thresholds to perform anti-jitter judgment on the voltage signal, effectively filtering out frequent fluctuations in the refresh rate near the critical value, and outputting a stable switching control signal. The switching unit 130 responds to the control signal, precisely turning on or off the signal path from the image compensation output to the subsequent drive circuit, thereby realizing hard enable control of the ICA function. Therefore, this application integrates screen detection, intelligent decision-making, and precise execution through the coordinated operation of the screen monitoring unit 110, the delay control unit 120, and the switching unit 130, constructing a closed-loop control that is responsive, stable in judgment, and reliable in execution. Furthermore, by introducing a hysteresis comparison control mechanism based on refresh rate, a stable buffer is set for the start and stop of the ICA function, which greatly improves the stability and reliability of the start and stop of the ICA function and eliminates the problem of frequent switching of the ICA function and screen flicker caused by fluctuations in parameters such as refresh rate near the critical value, thereby significantly improving the visual experience and user experience of the displayed screen.

[0049] In one embodiment, the screen monitoring unit 110 is further configured to: when it is determined that the current display screen is a normal screen based on multiple display parameters, output a preset voltage to the delay control unit 120, so that the delay control unit 120 controls the switching unit 130 to disconnect the signal path according to the preset voltage.

[0050] It should be noted that the screen monitoring unit 110 in this embodiment has dual judgment logic, which includes a primary decision unit (e.g., composed of a comparator U0 and logic gates) for determining whether the screen is abnormal. This decision unit continuously performs logical operations (such as AND operations) on the comparison results of the detected abnormal area area and grayscale value with their respective thresholds. Specifically, when the screen is determined to be abnormal: the module performs the operation as described in the above embodiment and outputs a voltage signal Ui corresponding to the refresh rate; when the screen is determined to be normal (i.e., either the area or grayscale value does not meet the standard): the module ignores the current refresh rate value and forcibly outputs a fixed preset voltage. This preset voltage is set to a value much lower than the shutdown threshold of the delay control unit 120, such as 0V or a constant low-level voltage V_low - ΔV.

[0051] The screen monitoring unit 110 in this embodiment ensures that in any non-abnormal screen scenario, no matter how high the refresh rate, as long as the screen content itself does not have any abnormalities that need to be compensated, the ICA function will not be activated. This conforms to the fundamental principle of on-demand compensation in display drivers, thereby achieving higher reliability, lower power consumption, and better overall image quality.

[0052] In one embodiment, as Figure 2 and Figure 5 shown, the delay control unit 120 includes a first comparator A1, a second comparator A2, and a latch 121; specifically, a first input terminal of the first comparator A1 is connected to the turn-on threshold output terminal UH, and a second input terminal of the first comparator A1 is connected to an output terminal of the video monitoring unit; a first input terminal of the second comparator A2 is connected to the output terminal of the video monitoring unit, and a second input terminal of the second comparator A2 is connected to the turn-off threshold output terminal UL; a first input terminal of the latch 121 is connected to an output terminal of the first comparator A1, a second input terminal of the latch 121 is connected to an output terminal of the second comparator A2, and an output terminal of the latch 121 serves as an output terminal of the delay control unit 120.

[0053] In one embodiment, as Figure 2 shown, the latch 121 includes a first NOR gate G1 and a second NOR gate G2; a first input terminal of the first NOR gate G1 serves as a first input terminal of the latch 121; a first input terminal of the second NOR gate G2 is connected to an output terminal of the first NOR gate G1, a second input terminal of the second NOR gate G2 serves as a second input terminal of the latch 121, and an output terminal of the second NOR gate G2 is connected to a second input terminal of the first NOR gate G1; wherein, an output terminal of the first NOR gate G1 or an output terminal of the second NOR gate G2 serves as an output terminal of the latch 121.

[0054] It should be noted that, as Figure 2 shown, Ui is a voltage signal corresponding to the current refresh rate output by the video monitoring unit, UH is the turn-on threshold voltage, and UL is the turn-off threshold voltage; when Ui < UL < UH, the output of the first comparator A1 is negative, and the output of the second comparator A2 is positive; when UL < Ui < UH, the output of the first comparator A1 is negative, and the output of the second comparator A2 is negative; when UL < UH < Ui, the output of the first comparator A1 is positive, and the output of the second comparator A2 is negative; its voltage transfer characteristic is as Figure 3 shown.

[0055] In this embodiment, the outputs of the first comparator A1 and the second comparator A2 are respectively given to the first input terminal R1 and the second input terminal S1 of the latch 121 composed of two NOR gates; the input and output conditions of the latch 121 in this embodiment are shown in Table 1:

[0056] Table 1. The first input-output condition table of the latch 121

[0057]

[0058] Taking the output terminal of the first NOR gate G1 as the output terminal of the latch 121 as an example, the switching transistor T0 is a P-type MOS transistor at this time; referring to Table 1, from the positive direction, when Ui < UL < UH, R1 is 0, S1 is 1, Q1 is 1, the switching transistor T0 is turned off, and the ICA function is turned off; when UL < Ui < UH, R1 is 0, S1 is 0, Q1 remains unchanged, the switching transistor T0 is turned off, and the ICA function remains turned off; when UL < UH < Ui, R1 is 1, S1 is 0, Q1 is 0, the switching transistor T0 is turned on, and the ICA function is turned on.

[0059] Optionally, from the negative direction, when UL < UH < Ui, R1 is 1, S1 is 0, Q1 is 0, the switching transistor T0 is turned on, and the ICA function is turned on; when UL < Ui < UH, R1 is 0, S1 is 0, Q1 remains unchanged, the switching transistor T0 is turned on, and the ICA function is turned on; when Ui < UL < UH, R1 is 0, S1 is 1, Q1 is 1, the switching transistor T0 is turned off, and the ICA function is turned off.

[0060] It should be noted that 0 and 1 in Table 1 above represent different states respectively. For example, a negative voltage or 0 voltage is set as state 0, and a voltage higher than a certain positive voltage is set as state 1.

[0061] In an embodiment, the delay control unit 120 further includes a first diode D1 and a second diode D2; the anode of the first diode D1 is connected to the output terminal of the first comparator A1, and the cathode of the first diode D1 is connected to the first input terminal of the latch 121; the anode of the second diode D2 is connected to the output terminal of the second comparator A2, and the cathode of the second diode D2 is connected to the second input terminal of the latch 121; that is, when the first comparator A1 outputs a negative value, the first diode D1 is turned off, and the voltage of the first input terminal R1 of the latch 121 is almost 0, so R1 is set as state 0; conversely, when the first comparator A1 outputs a voltage higher than the turn-on voltage of the diode, the diode conducts, and the first input terminal R1 of the latch 121 is set as state 1.

[0062] In summary, in this embodiment, a hysteresis interval as shown in Figure 4 is formed by the turn-on threshold voltage UH and the turn-off threshold voltage UL. The specific working principle of the delay control unit 120 in this embodiment is as follows:

[0063] (1)When the abnormal screen is detected by the screen monitoring unit and the voltage signal Ui converted according to the current refresh rate satisfies Ui < UL < UH, the latch 121 outputs a high level, the switching transistor T0 is turned off, and the ICA is turned off; when UL < Ui < UH, the latch 121 maintains a high level, the switching transistor T0 is turned off, and the ICA is turned off; when it increases to UL < UH < Ui, the latch 121 outputs a low level, the switching transistor T0 is turned on, and the ICA is turned on; if it continues to increase, it remains in the on state.

[0064] (2)If the refresh rate gradually decreases at this time, when it decreases to UL < UH < Ui, the latch 121 outputs a low level, so the ICA is turned on; when it decreases to UL < Ui < UH, the latch 121 maintains a low level, the switching transistor T0 is turned off, and the ICA is turned off; only when it continues to decrease to Ui < UL < UH, the latch 121 outputs a high level, the switching transistor T0 is turned off, and the ICA is turned off; if it continues to decrease, it remains in the off state.

[0065] (3)If the refresh rate of the display screen rises again, step (1) will be repeated.

[0066] In this embodiment, different hysteresis intervals can be achieved by modifying the values of the turn-on threshold voltage UH and the turn-off threshold voltage UL, so as to achieve different hysteresis magnitudes.

[0067] In another embodiment, the output terminal of the second NOR gate G2 can also be used as the output terminal of the latch 121 (not shown in the figure). At this time, the switching transistor T0 needs to be correspondingly replaced with an N-type MOS transistor.

[0068] In another embodiment, as Figure 5 shown, the latch 121 includes a first NAND gate U1 and a second NAND gate U2; the first input terminal of the first NAND gate U1 is used as the first input terminal of the latch 121, and the output terminal of the first NAND gate U1 is used as the output terminal of the latch 121; the first input terminal of the second NAND gate U2 is connected to the output terminal of the first NAND gate U1, the second input terminal of the second NAND gate U2 is used as the second input terminal of the latch 121, and the output terminal of the second NAND gate U2 is connected to the second input terminal of the first NAND gate U1.

[0069] It should be noted that Figure 5 the delay control unit 120 shown in Figure 2 is different from Figure 2 in that the latch 121 in Figure 5The latch 121 uses two NAND gates, and the first input terminal of each corresponding comparator serves as the non-inverting input terminal; in this embodiment, when Ui < UL < UH, the output of the first comparator A1 is positive, and the output of the second comparator A2 is negative; when UL < Ui < UH, the output of the first comparator A1 is positive, and the output of the second comparator A2 is positive; when UL < UH < Ui, the output of the first comparator A1 is negative, and the output of the second comparator A2 is positive; its voltage transfer characteristic is as Figure 6 shown.

[0070] In this embodiment, the outputs of the first comparator A1 and the second comparator A2 are respectively fed to the first input terminal R2 and the second input terminal S2 of the latch 121 composed of two NAND gates; the input and output conditions of the latch 121 in this embodiment are shown in Table 2:

[0071] Table 2. The second input and output condition table of the latch 121

[0072]

[0073] Here, taking the output terminal of the first NAND gate U1 as the output terminal of the latch 121 as an example, at this time, the switching transistor T0 is a P-type MOS transistor; referring to Table 2, from the positive direction, when Ui < UL < UH, R2 is 0, S2 is 1, Q1 is 1, the switching transistor T0 is turned off, and the ICA function is disabled; when UL < Ui < UH, R2 is 1, S2 is 1, Q1 remains unchanged, the switching transistor T0 is turned off, and the ICA function is disabled; when UL < UH < Ui, R2 is 1, S2 is 0, Q1 is 0, the switching transistor T0 is turned on, and the ICA is enabled.

[0074] Optionally, from the negative direction, when UL < UH < Ui, R2 is 1, S2 is 0, Q1 is 0, the switching transistor T0 is turned on, and the ICA is enabled; when UL < Ui < UH, R2 is 1, S2 is 1, Q1 remains unchanged, the switching transistor T0 is turned on, and the ICA is enabled; when Ui < UL < UH, R2 is 0, S2 is 1, Q1 is 1, the switching transistor T0 is turned off, and the ICA is disabled.

[0075] In summary, in this embodiment, the hysteresis interval as shown in Figure 7 is formed by the turn-on threshold voltage UH and the turn-off threshold voltage UL. The specific working principle of the delay control unit 120 in this embodiment is:

[0076] (1)When the abnormal screen is detected by the screen monitoring unit and the voltage signal Ui converted according to the current refresh rate satisfies Ui < UL < UH, the latch 121 outputs a high level, the switching transistor T0 is turned off, and the ICA is turned off; when UL < Ui < UH, the latch 121 remains at a high level, the switching transistor T0 is turned off, and the ICA is turned off; when it increases to UL < UH < Ui, the latch 121 outputs a low level, the switching transistor T0 is turned on, and the ICA is turned on; if it continues to increase, it maintains the on state.

[0077] (2)If the refresh rate decreases at this time, when it decreases to UL < UH < Ui, the latch 121 outputs a low level, so the ICA is turned on; when it decreases to UL < Ui < UH, the latch 121 remains at a low level, the switching transistor T0 is turned off, and the ICA is turned off; only when it continues to decrease to Ui < UL < UH, Uo outputs a high level, the switching transistor T0 is turned off, and the ICA is turned off; if it continues to decrease, it maintains the off state.

[0078] (3)If the refresh rate of the display screen rises again, step (1) will be repeated.

[0079] In this embodiment, different hysteresis intervals can be achieved by modifying the values of the turn-on threshold voltage UH and the turn-off threshold voltage UL, so as to achieve different hysteresis magnitudes.

[0080] In another embodiment, the output terminal of the second NAND gate U2 can also be used as the output terminal of the latch 121 (not shown in the figure). At this time, the switching transistor T0 needs to be correspondingly replaced with an N-type MOS transistor.

[0081] Figure 8 The following shows the structural schematic diagram of the third delay control unit 120 provided by the embodiment of the present application; as Figure 8 shown, the delay control unit 120 of this embodiment includes a third NAND gate U3 and a fourth NAND gate U4; the first input terminal of the third NAND gate U3 is connected to the output terminal of the first comparator A1, the second input terminal of the third NAND gate U3 is connected to the latch control terminal EN, and the output terminal of the third NAND gate U3 is connected to the first input terminal of the latch 121; the first input terminal of the fourth NAND gate U4 is connected to the latch control terminal EN, the second input terminal of the fourth NAND gate U4 is connected to the output terminal of the second comparator A2, and the output terminal of the fourth NAND gate U4 is connected to the second input terminal of the latch 121.

[0082] It should be noted that based on the delay control unit 120 shown in Figure 2 the following, a gating circuit composed of the third NAND gate U3 and the fourth NAND gate U4 is added, and its working principle is as follows:

[0083] (1) When the latch control terminal ENEN is low, regardless of the output of the first comparator A1 and the second comparator A2, the outputs of the third NAND gate U3 and the fourth NAND gate U4 are forced to be high. This makes the first input terminal S1 and the second input terminal R1 of latch 121 both high, latch 121 enters the holding state, the output remains unchanged, and the entire hysteresis control function is disabled.

[0084] (2) When the latch control terminal ENEN is high, the third NAND gate U3 and the fourth NAND gate U4 are "enabled", which function as inverters; at this time, the output signal of the first comparator A1 (after inversion) is passed to the first input terminal R1 of the latch 121, and the output signal of the second comparator A2 (after inversion) is passed to the second input terminal S1 of the latch 121, and the circuit is restored as follows. Figure 2 The normal hysteresis comparison function of the embodiment shown.

[0085] The gate control circuit composed of the third NAND gate U3 and the fourth NAND gate U4 in this embodiment has the following functions, including but not limited to: (1) Preventing false triggering: During system startup, mode switching, or specific working modes (such as standby or non-display period), the state of the ICA function can be forcibly locked by pulling the EN signal low, avoiding the ICA from being falsely turned on or off due to unstable or invalid detection signals, which greatly improves the reliability of the system; (2) Realizing energy saving and intelligent management: The system master controller can intelligently enable or disable the ICA control circuit according to the global state. For example, when it is determined that the current display content does not require ICA compensation, the control circuit can be turned off to reduce system power consumption; (3) Enhancing system synergy: The ICA hysteresis control is no longer completely autonomous, but can work in coordination with other functional modules of the timing controller (Tcon), accept the unified scheduling of the upper-level logic, and adapt to more complex application scenarios.

[0086] It should also be noted that the gate control circuit composed of the third NAND gate U3 and the fourth NAND gate U4 can also be applied to... Figure 5 The circuit shown operates on the same principle and function as the above embodiments, and will not be described again here.

[0087] Secondly, embodiments of this application provide an image compensation control device, specifically including the following embodiments:

[0088] Figure 9 The diagram shown is a structural schematic of the first image compensation control device provided in this application embodiment; as follows: Figure 9As shown, the image compensation control device 300 of this embodiment is applied to a display panel, which includes N display zones, and each display zone corresponds to a data drive circuit 500. With the increasing sophistication of current market products, more display devices adopt zone refresh rates, using different refresh rates in different areas according to image requirements to achieve better energy efficiency. Image distortion is more severe at high refresh rates, while it is slight or nonexistent at low refresh rates. Therefore, this embodiment adds separate control functions to the ICA of different refresh areas, allowing them to switch between a global unified mode and a zone-specific mode as needed. The image compensation output terminal 200 of this embodiment includes, but is not limited to, a whole-zone compensation output terminal 210, a first zone compensation output terminal 220, a second zone compensation output terminal 230, and a third zone compensation output terminal 240.

[0089] Specifically, the image compensation control device 300 in this embodiment includes a main control circuit 310, which is a specific instance of the control circuit 100 in the above embodiment. It is configured to generate a whole-area control signal based on the display parameters of the display panel. It should be noted that the screen monitoring unit 110 in the main control circuit 310 of this embodiment detects the area of ​​abnormal regions, grayscale, and global refresh rate (when all zone refresh rates are consistent) or representative refresh rate of the entire display panel. Its delay control unit 120 generates a whole-area control signal based on this comprehensive information. This whole-area control signal represents a global perspective on whether and when to enable the ICA function. Therefore, the main control circuit 310 provides a unified ICA control strategy based on the global screen condition, ensuring that the ICA state of the entire screen is synchronized when the full-screen refresh rate is consistent. This not only avoids visual fragmentation caused by inconsistent compensation in different areas but also reduces power consumption.

[0090] Optionally, the image compensation control device 300 of this embodiment further includes N partition control circuits 320, each partition control circuit 320 being a specific instance of the control circuit 100 in the above embodiment; each partition control circuit 320 is configured to generate a partition control signal based on the display parameters of the corresponding display partition. It should be noted that each partition control circuit 320 is a complete and autonomous ICA decision unit, configured to work only based on the display parameters of the specific display partition it is responsible for: that is, the image monitoring unit 110 of each partition control circuit 320 only detects the abnormal area area, grayscale, and local refresh rate of the corresponding partition; the delay control unit 120 of each partition control circuit 320 independently generates a partition control signal for that partition; therefore, the N partition control circuits 320 enable each display partition to independently decide whether to enable ICA compensation based on its own actual situation (whether there is an anomaly, the refresh rate), realizing fine control of the ICA function with on-demand allocation and precise compensation, which is particularly suitable for partition refresh scenarios.

[0091] Optionally, the image compensation control device 300 of this embodiment further includes a mode switching circuit 330, coupled to the mode output terminal 400, the main control circuit 310, the N partition control circuits 320, and the N data driving circuits 500; the mode switching circuit 330 is configured to input the whole area control signal to the N data driving circuits 500 in response to a first mode selection signal input from an external source; and to input the partition control signal generated by the i-th partition control circuit 320 to the i-th data driving circuit 500 in response to a second mode selection signal input from an external source, where i=1,...,N.

[0092] It should be noted that the mode output terminal 400 in this embodiment can be the output terminal of an external circuit or another output terminal with mode recognition function in the image compensation control device 300; the mode selection signal output by the mode output terminal 400 includes a first mode selection signal for indicating that the display panel is currently in the whole area refresh mode, and a second mode selection signal for indicating that the display panel is currently in the partition refresh mode.

[0093] In this embodiment, the mode switching circuit 330 routes the correct control signal to the corresponding data driving circuit 500 based on the mode selection signal. Specifically:

[0094] (1) When the first mode selection signal is valid, the mode switching circuit 330 simultaneously inputs the whole area control signal generated by the main control circuit 310 to all N data drive circuits 500. At this time, the ICA state of the entire screen is uniformly determined by the main control circuit 310.

[0095] (2) When the second mode selection signal is valid, the mode switching circuit 330 inputs the partition control signal generated by the i-th partition control circuit 320 to the i-th data drive circuit 500. At this time, the ICA state of each partition is independently controlled by its own partition control circuit 320.

[0096] Therefore, this embodiment enables the ICA control system to dynamically adapt to different operating modes of the display device (global refresh or partition refresh) through the mode switching circuit 330, always maintaining the optimal compensation strategy; and supports two operating modes through a single hardware architecture, eliminating the need to design independent control circuits 100 for each mode, thus saving chip area and cost. This embodiment ensures a smooth transition of ICA function control in different display modes, avoiding screen jitter or flickering caused by mode switching.

[0097] The specific working principle of the image compensation control device 300 provided in this embodiment is as follows:

[0098] (1) After system initialization, the main control circuit 310 and all partition control circuits 320 work in parallel, continuously generating their respective whole-area control signals and partition control signals based on global and local information.

[0099] (2) The timing controller determines and outputs the corresponding mode selection signal to the mode switching circuit 330 based on the current display content and working status.

[0100] (3) The mode switching circuit 330 switches the signal path in real time according to the received mode command: ① In whole-area refresh scenarios such as watching movies or browsing web pages, the mode switching circuit 330 broadcasts the command of the main control circuit 310 to all partitions to achieve unified control. ② In partition refresh scenarios such as games or videos, the mode switching circuit 330 sends the decisions of each partition control circuit 320 to the area it is responsible for to achieve independent control.

[0101] (4) Finally, the control signal selected by the mode switching circuit 330 reaches the data driving circuit 500 to control the final execution of the ICA function.

[0102] This embodiment constructs an intelligent image compensation control device 300 that combines centralized management and distributed control through the coordinated operation of the main control circuit 310, multiple partition control circuits 320, and mode switching circuit 330. It creatively solves the control adaptation problem of ICA function in the new generation of partition refresh display technology, enabling the ICA function to intelligently select the optimal control strategy in both global unified refresh and partition independent refresh modes. While effectively eliminating crosstalk and flicker, it achieves the best balance between power consumption and image quality, greatly improving the overall user experience of partition refresh display devices.

[0103] Figure 10 The diagram shown is a structural schematic of the second image compensation control device provided in an embodiment of this application; as shown Figure 10 As shown, the mode switching circuit 330 includes: N first transistors T1, the control terminal of the first transistor T1 is connected to the mode output terminal 400, the first terminal of the first transistor T1 is connected to the output terminal of the partition control circuit 320, and the second terminal of the first transistor T1 is connected to the data driving circuit 500.

[0104] Optionally, the mode switching circuit 330 of this embodiment further includes N-1 second transistors T2. The control terminal of each second transistor T2 is connected to the mode output terminal 400. The first terminal of the first second transistor T2 is connected to the output terminal of the main control circuit 310 and the first data driving circuit 500, respectively. The first terminal of the j-th second transistor T2 is connected to the second terminal of the (j-1)-th second transistor T2 and the j-th data driving circuit 500, respectively. The second terminal of the (N-1)-th second transistor T2 is connected to the N-th data driving circuit 500; where j=2,...,N-1; the turn-on voltages of the first transistor T1 and the second transistor T2 are opposite.

[0105] Here, taking N=3, with the first transistor T1 being a PMOS transistor and the second transistor T2 being an NMOS transistor as an example, combined with... Figure 11 The working principle of the mode switching circuit 330 in this embodiment will be described in detail below:

[0106] (1) Global control mode, that is: the output signal S of the mode output terminal 400 is high level (that is, the first mode selection signal is valid).

[0107] All first transistors T1 are disconnected when the control terminal is high, thereby disconnecting the signal paths between all partition control circuits 320 and partition data drive circuits 500; all second transistors T2 are turned on when the control terminal is high, and the whole-area control signal generated by the main control circuit 310 acts on the data drive circuit 500 corresponding to each display partition, realizing the ICA function to be turned on or off uniformly throughout the entire screen.

[0108] (2) Partition control mode, that is: the output signal S of the mode output terminal 400 is low (that is, the second mode selection signal is valid).

[0109] All second transistors T2 are turned off when the control terminal is low, thus disconnecting the signal path between the main control circuit 310 and the partition data drive circuit 500; all first transistors T1 are turned on when the control terminal is low, so that the partition control signal generated by each partition control circuit 320 is sent to the corresponding partition data drive circuit 500, so that each display partition receives its own independent partition control signal, and the ICA function is independently controlled in each partition without affecting each other.

[0110] This embodiment provides a specific and feasible implementation of the mode switching circuit 330. By using N first transistors T1 and N-1 second transistors T2 connected in a chain, and in conjunction with complementary control signals, a reliable switching between global unified control and zone-independent control is clearly and clearly achieved.

[0111] Figure 11 The diagram shown is a structural schematic of the third image compensation control device provided in this application embodiment; as follows: Figure 11 As shown, when the N display partitions include a first display partition, a second display partition, and a third display partition, the image compensation control device 300 further includes: a first frequency comparator 340, the first input terminal of the first frequency comparator 340 is connected to the refresh rate output terminal Vf1 of the first display partition, the second input terminal of the first frequency comparator 340 is connected to the refresh rate output terminal Vf2 of the second display partition, and the output terminal of the first frequency comparator 340 is connected to the control terminal of the first transistor T1, the control terminal of the second transistor T1, and the control terminal of the first transistor T2, respectively.

[0112] Optionally, the image compensation control device 300 further includes: a second frequency comparator 350, the first input terminal of the second frequency comparator 350 being connected to the refresh rate output terminal Vf2 of the second display zone, the second input terminal of the second frequency comparator 350 being connected to the refresh rate output terminal Vf3 of the third display zone, and the output terminal of the second frequency comparator 350 being connected to the control terminal of the third first transistor T1 and the control terminal of the second second transistor T2, respectively.

[0113] It should be noted that each frequency comparator in this implementation compares the refresh rates of two adjacent partitions in real time. When the refresh rates of the two partitions are the same, it outputs a valid control signal to trigger the following intelligent behaviors: (1) When the refresh rates are the same: the frequency comparator outputs a valid level to control the corresponding first transistor T1 to turn off and the second transistor T2 to turn on; (2) When the refresh rates are different: the frequency comparator outputs an invalid level to control the corresponding first transistor T1 to turn on and the second transistor T2 to turn off.

[0114] This embodiment is in Figure 10Based on the two basic modes shown, a more intelligent dynamic group control is implemented. The specific working principle is as follows:

[0115] (1) Scenario 1: All partitions have the same refresh rate

[0116] The first frequency comparator 340 detects that the refresh rates of the first display partition and the second display partition are the same and outputs a valid signal C_AB. The second frequency comparator 350 detects that the refresh rates of the second display partition and the third display partition are the same and outputs a valid signal C_BC. Then all the first transistors T1 are turned off and all the second transistors T2 are turned on. The image compensation control device 300 automatically enters the global control mode, and the three partitions share the whole-area control signal of the total control circuit 310.

[0117] (2) Scenario 2: The first and second display partitions have the same refresh rate, while the third display partition has a different refresh rate.

[0118] The first frequency comparator 340 outputs a valid signal C_AB, and the second frequency comparator 350 outputs an invalid signal C_BC. As a result, the first and second first transistors T1 are both turned off, the third first transistor T1 is turned on, the first second transistor T2 is turned on, and the second second transistor T2 is turned off. Therefore, the first and second display zones share the overall control signal through the turned-on first second transistor T2, and the third display zone receives the corresponding independent control signal through the turned-on third first transistor T1, thereby realizing a hybrid mode of unified control of the first and second display zones and independent control of the third display zone.

[0119] (3) Scenario 3: The refresh rates of the three display partitions are different.

[0120] The first frequency comparator 340 outputs an invalid signal C_AB, the second frequency comparator 350 outputs an invalid signal C_BC, all first transistors T1 are turned on, all second transistors T2 are turned off, and the image compensation control device 300 automatically enters the full partition control mode, where each partition is independently controlled by its own control circuit 100.

[0121] This embodiment introduces a frequency comparator U0 to achieve a technical improvement in switching from a fixed mode to intelligent dynamic grouping. This adaptive control strategy not only improves the system's efficiency but also significantly enhances the display device's image quality and power consumption control capabilities in different application scenarios, representing a new direction in the development of image compensation control technology.

[0122] In one embodiment, such as Figure 12As shown, the first frequency comparator 340 includes: a fifth NAND gate U5, a sixth NAND gate U6, a seventh NAND gate U7, and an AND gate U8; the first input terminal of the fifth NAND gate U5 serves as the first input terminal of the first frequency comparator 340, and the second input terminal of the fifth NAND gate U5 serves as the second input terminal of the first frequency comparator 340; the first input terminal of the sixth NAND gate U6 is connected to the first input terminal of the fifth NAND gate U5, and the second input terminal of the sixth NAND gate U6 is connected to the output terminal of the fifth NAND gate U5; the first input terminal of the seventh NAND gate U7 is connected to the second input terminal of the sixth NAND gate U6, and the second input terminal of the seventh NAND gate U7 is connected to the second input terminal of the fifth NAND gate U5; the first input terminal of the AND gate U8 is connected to the output terminal of the sixth NAND gate U6, and the second input terminal of the AND gate U8 is connected to the output terminal of the seventh NAND gate U7, and the output terminal of the AND gate U8 serves as the output terminal of the first frequency comparator 340.

[0123] It should be noted that the first frequency comparator 340 consists of three NAND gates and one AND gate U8. Specifically, the fifth NAND gate U5 receives two input signals Vf1 and Vf2, the sixth NAND gate U6 and the seventh NAND gate U7 are cross-connected to form a detection network, and the AND gate U8 performs a logical AND operation on the outputs of the two detection branches. The state truth values ​​of the first frequency comparator 340 in this embodiment are shown in Table 3.

[0124] Table 3. State Truth Table

[0125]

[0126] As shown in Table 3, when the refresh rate states of the two partitions are the same (both are high refresh or both are low refresh), the output of the first frequency comparator 340 is low; when the refresh rate states of the two partitions are different (one is high refresh and the other is low refresh), the output of the first frequency comparator 340 is high.

[0127] In the image compensation control device 300: input signals Vf1 and Vf2 represent the refresh rate states of two display zones (high level = high refresh rate, low level = low refresh rate); when the output of the first frequency comparator 340 is high, it indicates that the refresh rate states of the two zones are inconsistent. This signal controls the corresponding transistors, causing the two zones to enter independent ICA control mode; when the output of the first frequency comparator 340 is low, the two zones are allowed to share the same ICA control signal; in this embodiment, the first frequency comparator 340, through logic gate combination, realizes rapid detection of the consistency of the refresh rate states of the two zones, providing a key judgment basis for intelligent decision-making of zone ICA control.

[0128] In one embodiment, the second frequency comparator 350 includes a fifth NAND gate U5, a sixth NAND gate U6, a seventh NAND gate U7, and an AND gate U8; the first input terminal of the fifth NAND gate U5 serves as the first input terminal of the second frequency comparator 350, and the second input terminal of the fifth NAND gate U5 serves as the second input terminal of the second frequency comparator 350; the first input terminal of the sixth NAND gate U6 is connected to the first input terminal of the fifth NAND gate U5, and the second input terminal of the sixth NAND gate U6 is connected to the output terminal of the fifth NAND gate U5; the first input terminal of the seventh NAND gate U7 is connected to the second input terminal of the sixth NAND gate U6, and the second input terminal of the seventh NAND gate U7 is connected to the second input terminal of the fifth NAND gate U5; the first input terminal of the AND gate U8 is connected to the output terminal of the sixth NAND gate U6, and the second input terminal of the AND gate U8 is connected to the output terminal of the seventh NAND gate U7, and the output terminal of the AND gate U8 serves as the output terminal of the second frequency comparator 350.

[0129] It should be noted that the specific structure, working principle and function of the second frequency comparator 350 in this embodiment are the same as those of the first frequency comparator 340, and will not be described again here.

[0130] Figure 13 The diagram shown is a structural schematic of the fourth image compensation control device provided in this application embodiment; as follows: Figure 13 As shown, the image compensation control device in this embodiment... Figure 11 In addition, it also includes: a first frequency hysteresis unit 360, the input terminal of the first frequency hysteresis unit 360 is connected to the output terminal of the first frequency comparator 340, and the output terminal of the first frequency hysteresis unit 360 is connected to the control terminal of the first first transistor T1, the control terminal of the second first transistor T1 and the control terminal of the first second transistor T2 respectively. It is configured to compare the frequency difference value output by the first frequency comparator 340 with the first frequency difference value and the second frequency difference value respectively, and output the corresponding switching control signal based on the comparison result.

[0131] The image compensation control device in this embodiment further includes a second frequency hysteresis unit 370. The input terminal of the second frequency hysteresis unit 370 is connected to the output terminal of the second frequency comparator 350. The output terminal of the second frequency hysteresis unit 370 is connected to the control terminal of the third first transistor T1 and the control terminal of the second second transistor T2, respectively. It is configured to compare the frequency difference value output by the second frequency comparator 350 with the first frequency difference value and the second frequency difference value, respectively, and output a corresponding switch control signal based on the comparison result; wherein, the first frequency difference value is greater than the second frequency difference value.

[0132] It should be noted that this embodiment adds a secondary hysteresis judgment mechanism to the first frequency comparator 340 and the second frequency comparator 350. Here, the working principle of the first frequency hysteresis unit 360 is explained in detail as an example:

[0133] (1) Signal conversion and input: The first frequency comparator 340 detects the refresh rate of the first display partition (abbreviated as A area) and the second display partition (abbreviated as B area), and outputs a voltage signal that is proportional to the difference between the refresh rates of the two areas. This difference signal is input to the first frequency hysteresis unit 360.

[0134] (2) Dual threshold hysteresis judgment: The first frequency hysteresis unit 360 contains a hysteresis comparator with two thresholds: the first frequency difference (high threshold, such as 30Hz) and the second frequency difference (low threshold, such as 15Hz); when the refresh rate difference is ≥30Hz, an effective signal is output, forcing A and B partitions to enter independent ICA control; when the refresh rate difference is ≤15Hz, the output signal is flipped, allowing A and B partitions to use unified ICA control; when the difference is between 15Hz and 30Hz, the existing control state remains unchanged.

[0135] (3) Output control: The output of the first frequency hysteresis unit 360 directly takes over the control of the corresponding transistor in the mode switching circuit.

[0136] This embodiment forms a decision buffer within the 15Hz-30Hz difference range through the first frequency hysteresis unit, completely avoiding frequent mode switching caused by fluctuations in the partition refresh rate near the critical point; therefore, by adding a hysteresis judgment layer to the frequency comparison, an upgrade from simple comparison to intelligent decision-making is achieved, enabling multi-partition ICA control to maintain a stable and optimal working state under refresh rate changes in a large dynamic range.

[0137] It should be noted that the specific structure, working principle, and function of the second frequency hysteresis unit in this embodiment are the same as those of the first frequency hysteresis unit, and will not be repeated here; wherein, the first frequency hysteresis unit and the second frequency hysteresis unit in this embodiment can be Figure 2 , Figure 5 and Figure 8 The delay control unit shown in any one of them.

[0138] Thirdly, embodiments of this application provide a display panel including a display area and a non-display area. The display area includes a pixel array; the non-display area includes a timing controller, a source drive circuit, and the aforementioned image compensation control device. The image compensation control device is electrically connected to the timing controller and the source drive circuit, respectively.

[0139] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0140] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0141] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A control circuit, characterized by The control circuit comprises: a picture monitoring unit configured to detect a plurality of display parameters of a current display picture, and output a voltage signal corresponding to a current refresh rate when it is determined that the current display picture is an abnormal picture according to the plurality of display parameters; wherein the picture monitoring unit linearly converts the refresh rate into an analog voltage signal through a data converter; a delay control unit connected to the picture monitoring unit, the delay control unit being configured to compare the voltage signal with an on threshold voltage and an off threshold voltage respectively, and output a switch control signal based on a comparison result; wherein the on threshold voltage is greater than the off threshold voltage; a switch unit, a control end of the switch unit being connected to an output end of the delay control unit, a first connection end of the switch unit being connected to an image compensation output end, and a second connection end of the switch unit being connected to a subsequent stage driving circuit, the switch unit being configured to turn on or turn off a signal path between the image compensation output end and the subsequent stage driving circuit in response to the switch control signal; wherein the delay control unit is configured to switch the switch control signal to a first state when the voltage signal is greater than or equal to the on threshold voltage, switch the switch control signal to a second state when the voltage signal is less than or equal to the off threshold voltage, and maintain a current state of the switch control signal when the voltage signal is between the on threshold voltage and the off threshold voltage.

2. The control circuit of claim 1, wherein, The delay control unit comprises: a first comparator, a first input end of the first comparator being connected to an on threshold output end, and a second input end of the first comparator being connected to an output end of the picture monitoring unit; a second comparator, a first input end of the second comparator being connected to the output end of the picture monitoring unit, and a second input end of the second comparator being connected to an off threshold output end; a latch, a first input end of the latch being connected to an output end of the first comparator, a second input end of the latch being connected to an output end of the second comparator, and an output end of the latch serving as an output end of the delay control unit.

3. The control circuit of claim 2, wherein, The latch comprises: a first NOR gate, a first input end of the first NOR gate serving as a first input end of the latch, a second NOR gate, a first input end of the second NOR gate being connected to an output end of the first NOR gate, a second input end of the second NOR gate serving as a second input end of the latch, and an output end of the second NOR gate being connected to a second input end of the first NOR gate, wherein an output end of the first NOR gate or an output end of the second NOR gate serves as an output end of the latch; alternatively, the latch comprises: a first NAND gate, a first input end of the first NAND gate serving as a first input end of the latch, a second NAND gate, a first input end of the second NAND gate being connected to an output end of the first NAND gate, a second input end of the second NAND gate serving as a second input end of the latch, and an output end of the second NAND gate being connected to a second input end of the first NAND gate, The output terminal of the first NAND gate or the output terminal of the second NAND gate is taken as the output terminal of the latch.

4. The control circuit of claim 2, wherein, The delay control unit further comprises: a third NAND gate, a first input terminal of the third NAND gate being connected with the output terminal of the first comparator, a second input terminal of the third NAND gate being connected with the latch control terminal, and an output terminal of the third NAND gate being connected with the first input terminal of the latch; a fourth NAND gate, a first input terminal of the fourth NAND gate being connected with the latch control terminal, a second input terminal of the fourth NAND gate being connected with the output terminal of the second comparator, and an output terminal of the fourth NAND gate being connected with the second input terminal of the latch.

5. An image compensation control device, characterized by comprising: The display panel comprises N display sub-regions, and one display sub-region corresponds to one data driving circuit. The image compensation control device comprises: a total control circuit, which is the control circuit of any one of claims 1-4, and is configured to generate a whole-region control signal based on display parameters of the display panel; N sub-region control circuits, each of which is the control circuit of any one of claims 1-4, and each of which is configured to generate a sub-region control signal based on display parameters of a corresponding display sub-region; a mode switching circuit, which is coupled to a mode output terminal, the total control circuit, the N sub-region control circuits, and N data driving circuits, and is configured to input the whole-region control signal to the N data driving circuits in response to an externally input first mode selection signal, and input a sub-region control signal generated by an i-th sub-region control circuit to an i-th data driving circuit in response to an externally input second mode selection signal, where i = 1,...,N.

6. The image compensation control device according to claim 5, characterized by The mode switching circuit comprises: N first transistors, a control terminal of each of the first transistors being connected with the mode output terminal, a first terminal of each of the first transistors being connected with an output terminal of the sub-region control circuit, and a second terminal of each of the first transistors being connected with the data driving circuit; wherein the N first transistors are connected with the N sub-region control circuits and the N data driving circuits in a one-to-one correspondence; N-1 second transistors, a control terminal of each of the second transistors being connected with the mode output terminal, a first terminal of a first second transistor being connected with an output terminal of the total control circuit and a first data driving circuit respectively, a first terminal of a j-th second transistor being connected with a second terminal of a (j-1)-th second transistor and a j-th data driving circuit respectively, and a second terminal of an (N-1)-th second transistor being connected with an N-th data driving circuit; wherein j = 2,...,N-1; the turn-on voltages of the first transistors and the second transistors are opposite.

7. The image compensation control device according to claim 6, characterized by When the N display sub-regions comprise a first display sub-region, a second display sub-region, and a third display sub-region, the image compensation control device further comprises: a first frequency comparator, a first input terminal of the first frequency comparator being connected with the refresh rate output terminal of the first display area, a second input terminal of the first frequency comparator being connected with the refresh rate output terminal of the second display area, and an output terminal of the first frequency comparator being connected with the control terminal of the first first transistor, the control terminal of the second first transistor and the control terminal of the first second transistor respectively; a second frequency comparator, a first input terminal of the second frequency comparator being connected with the refresh rate output terminal of the second display area, a second input terminal of the second frequency comparator being connected with the refresh rate output terminal of the third display area, and an output terminal of the second frequency comparator being connected with the control terminal of the third first transistor and the control terminal of the second second transistor respectively.

8. The image compensation control device according to claim 7, characterized by the first frequency comparator comprises: a fifth NAND gate, a first input terminal of the fifth NAND gate being used as the first input terminal of the first frequency comparator, and a second input terminal of the fifth NAND gate being used as the second input terminal of the first frequency comparator, a sixth NAND gate, a first input terminal of the sixth NAND gate being connected with the first input terminal of the fifth NAND gate, and a second input terminal of the sixth NAND gate being connected with the output terminal of the fifth NAND gate, a seventh NAND gate, a first input terminal of the seventh NAND gate being connected with the second input terminal of the sixth NAND gate, and a second input terminal of the seventh NAND gate being connected with the second input terminal of the fifth NAND gate, an AND gate, a first input terminal of the AND gate being connected with the output terminal of the sixth NAND gate, a second input terminal of the AND gate being connected with the output terminal of the seventh NAND gate, and an output terminal of the AND gate being used as the output terminal of the first frequency comparator; or / and, the second frequency comparator comprises: a fifth NAND gate, a first input terminal of the fifth NAND gate being used as the first input terminal of the second frequency comparator, and a second input terminal of the fifth NAND gate being used as the second input terminal of the second frequency comparator, a sixth NAND gate, a first input terminal of the sixth NAND gate being connected with the first input terminal of the fifth NAND gate, and a second input terminal of the sixth NAND gate being connected with the output terminal of the fifth NAND gate, a seventh NAND gate, a first input terminal of the seventh NAND gate being connected with the second input terminal of the sixth NAND gate, and a second input terminal of the seventh NAND gate being connected with the second input terminal of the fifth NAND gate, an AND gate, a first input terminal of the AND gate being connected with the output terminal of the sixth NAND gate, a second input terminal of the AND gate being connected with the output terminal of the seventh NAND gate, and an output terminal of the AND gate being used as the output terminal of the second frequency comparator.

9. The image compensation control device according to claim 7, wherein the image compensation control device further comprises: a first frequency hysteresis unit, an input terminal of the first frequency hysteresis unit being connected with the output terminal of the first frequency comparator, and an output terminal of the first frequency hysteresis unit being connected with the control terminal of the first first transistor, the control terminal of the second first transistor and the control terminal of the first second transistor respectively, and being configured to compare the frequency difference value output by the first frequency comparator with the first frequency difference value and the second frequency difference value respectively, and output corresponding switch control signals based on the comparison result. a second frequency hysteresis unit, an input end of the second frequency hysteresis unit being connected with an output end of the second frequency comparator, an output end of the second frequency hysteresis unit being connected with a control end of a third first transistor and a control end of a second second transistor respectively, and being configured to compare the frequency difference output by the second frequency comparator with the first frequency difference and the second frequency difference respectively, and output corresponding switch control signals based on the comparison results; wherein the first frequency difference is greater than the second frequency difference.

10. A display panel comprising a display area and a non-display area, characterized in that, The display area includes a pixel array. The non-display area includes a timing controller, a source driving circuit, and the image compensation control device of any one of claims 5-9, the image compensation control device being electrically connected with the timing controller and the source driving circuit respectively.

Images