Inverter control method and three-phase four-wire inverter

Abstract

The application discloses an inverter control method and a three-phase four-wire inverter. The method comprises the following steps: generating a first adjustment amount corresponding to each phase according to a current DC component expected value and an actual value of the current DC component of each phase in three phases; generating a current average value of each phase according to a current instantaneous value of each phase in three phases, and generating an average current parameter according to the current average value of each phase; generating a second adjustment amount according to the average current parameter and the positive and negative of the voltage offset of the bus midpoint; and generating a driving signal corresponding to each phase based on the second adjustment amount and the first adjustment amount corresponding to each phase. The sum of three-phase inductor currents flowing into the bus midpoint is zero based on the current DC component of each phase and the offset of the bus midpoint. The sum of the three-phase inductor currents flowing into the bus midpoint is associated and coordinated, which not only ensures that the DC component output by each phase is within the standard requirement, but also can inhibit the fluctuation and offset of the bus midpoint.

Description

Technical Field

[0001] This invention relates to the field of inverter technology, and more particularly to inverter control methods and three-phase four-wire inverters. Background Technology

[0002] Since single-phase loads are typically required in residential and commercial applications, standalone three-phase three-wire inverters are unsuitable. While adding a transformer can enable single-phase load connection, this increases application costs and size, making installation and maintenance more difficult. Three-phase four-wire inverters, however, can connect to single-phase loads without a transformer, making them a more economical and practical solution. Currently, three-phase four-wire inverters are widely used in residential and commercial inverter applications, such as in residential photovoltaic systems, residential photovoltaic-storage systems, and integrated commercial and industrial energy storage systems.

[0003] Unlike three-phase three-wire inverters, three-phase four-wire inverters require the bus neutral point and grid neutral point to be connected via a neutral wire. Therefore, when the three-phase load is unbalanced or when there is a DC component in the three-phase current, it will be conducted to the bus neutral point through the neutral wire. This will cause the bus neutral point to shift, which in turn increases the DC component output by the inverter. As the DC component increases, it will be conducted to the bus neutral point through the neutral wire, causing the bus neutral point to shift further, forming a positive feedback vicious cycle, which will eventually lead to the inverter disconnecting from the grid or even being damaged. Summary of the Invention

[0004] This invention provides an inverter control method and a three-phase four-wire inverter to solve the problem of bus midpoint offset caused by DC component.

[0005] According to one aspect of the present invention, an inverter control method is provided. The inverter includes a first bus capacitor, a second bus capacitor, and an inverter circuit. The connection point of the first bus capacitor and the second bus capacitor connected in series is connected to the neutral line. The input terminal of the inverter circuit is connected to the first bus capacitor and the second bus capacitor. The output terminal of the inverter circuit is connected to the power grid through three phase lines and the neutral line. The inverter control method includes:

[0006] The first adjustment amount is generated for each phase based on the expected value of the DC component of the current and the actual value of the DC component of the current in each of the three phases.

[0007] The average current value of each phase is generated based on the instantaneous current value of each phase in the three phases, and the average current parameter is generated based on the average current value of each phase.

[0008] The second adjustment amount is generated based on the average current parameter and the sign of the voltage offset at the bus midpoint; the bus midpoint is the connection point where the first bus capacitor and the second bus capacitor are connected in series.

[0009] Each corresponding drive signal is generated based on the second adjustment amount and each corresponding first adjustment amount.

[0010] Optionally, the first end of the first bus capacitor is connected to the positive bus, the second end of the first bus capacitor is connected to the first end of the second bus capacitor, and the second end of the second bus capacitor is connected to the negative bus, with the second end of the first bus capacitor serving as the midpoint of the bus.

[0011] Before generating the second adjustment amount based on the average current parameter and the sign of the voltage offset at the bus midpoint, the method further includes:

[0012] Obtain the first voltage of the first bus capacitor and the second voltage of the second bus capacitor;

[0013] Based on the first voltage and the second voltage, determine the sign of the voltage offset at the midpoint of the busbar;

[0014] When the first voltage is greater than the second voltage, the voltage offset at the midpoint of the busbar is positive;

[0015] When the first voltage is less than the second voltage, the voltage offset at the midpoint of the bus is negative.

[0016] Optionally, generating the second adjustment amount based on the average current parameter and the sign of the voltage offset at the bus midpoint includes:

[0017] The average current parameter is PI-adjusted to generate a first intermediate value;

[0018] When the voltage offset at the midpoint of the busbar is determined to be positive, the first intermediate value is used as the second adjustment value; when the voltage offset at the midpoint of the busbar is determined to be negative, the opposite of the first intermediate value is used as the second adjustment value.

[0019] Optionally, the step of generating the average current value of each phase based on the instantaneous current value of each phase in the three phases, and generating the average current parameter based on the average current value of each phase, includes:

[0020] Within the sampling period, for each of the three phases, the average current of that phase is calculated based on the instantaneous current value of that phase at each sampling time within the sampling period;

[0021] The average current parameter is generated by summing the average current values ​​of each phase and then averaging the sums.

[0022] Optionally, the average current parameter is updated once every sampling period.

[0023] Optionally, generating the first adjustment amount for each corresponding phase based on the expected value of the DC component of the current and the actual value of the DC component of the current in each of the three phases includes:

[0024] For each of the three phases, the corresponding current deviation is generated based on the actual value of the DC component of the current in that phase and the expected value of the DC component of the current.

[0025] The corresponding current deviation is adjusted using a PI controller to generate the corresponding first adjustment amount.

[0026] Optionally, before generating the first adjustment amount for each corresponding phase based on the expected value of the DC component of the current and the actual value of the DC component of the current in each of the three phases, the method further includes:

[0027] Sample the instantaneous current value of each of the three phases;

[0028] The instantaneous current value of each phase is filtered to generate the actual DC component value of the current of each phase.

[0029] Optionally, the update period of the second adjustment amount is longer than the update period of the first adjustment amount.

[0030] Optionally, generating each corresponding drive signal based on the second adjustment amount and each corresponding first adjustment amount includes:

[0031] For each of the three phases, the second adjustment amount is summed with the corresponding first adjustment amount to obtain the corresponding third intermediate amount;

[0032] The corresponding third intermediate quantity is superimposed with the corresponding initial modulation wave to generate the corresponding intermediate modulation wave;

[0033] The corresponding intermediate modulation wave is modulated to obtain the corresponding driving signal.

[0034] According to another aspect of the present invention, a three-phase four-wire inverter is provided, comprising:

[0035] The system comprises a first bus capacitor, a second bus capacitor, and an inverter circuit. The connection point of the first bus capacitor and the second bus capacitor, which are connected in series, is connected to the neutral line. The input terminal of the inverter circuit is connected to the first bus capacitor and the second bus capacitor. The output terminal of the inverter circuit is connected to the power grid through three phase lines and the neutral line. A controller is also included, connected to the inverter circuit. The controller is used to output the drive signal to the inverter circuit according to the inverter control method described above.

[0036] In this embodiment, a first adjustment amount is generated based on the actual value of the DC component of the current in each phase, and a second adjustment amount is generated based on the average current parameter and the sign of the voltage offset at the bus midpoint. Then, a corresponding drive signal is generated based on the second adjustment amount and the first adjustment amount. This coordinates the DC component of the current in each phase and the offset of the bus midpoint. The offset direction of the bus midpoint is correlated with the input amount of the modulated drive signal when adjusting the DC component of the current in each phase, ensuring that the sum of the three-phase inductor currents flowing into the bus midpoint is zero. If the input amount of the modulated drive signal is not correlated with the offset direction of the bus midpoint and the DC component of the current in each phase, the bus midpoint will be fixed in one direction, and the offset will increase with power, making it impossible to coordinate the control of the DC component of the current and the bus midpoint. By coordinating the bus midpoint offset with the sum of the three-phase inductor currents injected into the midpoint, it ensures that the DC component of the current output in each phase is within the standard requirement range (less than or equal to 0.5%In, where In is the rated current), and also suppresses fluctuations and offsets at the bus midpoint.

[0037] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of the structure of an inverter provided in an embodiment of the present invention;

[0040] Figure 2 A flowchart of an inverter control method provided in an embodiment of the present invention;

[0041] Figure 3 A flowchart of another inverter control method provided in an embodiment of the present invention;

[0042] Figure 4 A schematic diagram of a modulation ring structure provided in an embodiment of the present invention;

[0043] Figure 5 This is a schematic diagram of a bus midpoint coordination control loop provided in an embodiment of the present invention. Detailed Implementation

[0044] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0045] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0046] Figure 1 This is a schematic diagram of an inverter provided in an embodiment of the present invention, with reference to... Figure 1The inverter includes a first bus capacitor C1, a second bus capacitor C2, and an inverter circuit 10. The connection point of the first bus capacitor C1 and the second bus capacitor C2, which are connected in series, is connected to the neutral line. The input terminal of the inverter circuit 10 is connected to the first bus capacitor C1 and the second bus capacitor C2. The output terminal of the inverter circuit 10 is connected to the power grid 11 through three phase lines and the neutral line. Specifically: the first terminal of the first bus capacitor C1 is connected to the positive bus BUS+, the second terminal of the first bus capacitor C1 is connected to the first terminal of the second bus capacitor C2, and the second terminal of the second bus capacitor C2 is connected to the negative bus BUS-. The second terminal of the first bus capacitor C1 or the first terminal of the second bus capacitor C2 is used as the bus midpoint. The inverter circuit 10 includes a three-phase inverter bridge. Each phase of the three-phase inverter bridge includes four switching transistors connected in series between the positive bus BUS+ and the negative bus BUS-. The four switching transistors of phase A are designated as the first switching transistor T1, the second switching transistor T2, the third switching transistor T3, and the fourth switching transistor T4. The four switching transistors of phase B are designated as the fifth switching transistor T5, the sixth switching transistor T6, the seventh switching transistor T7, and the eighth switching transistor T8. The four switching transistors of phase C are designated as the ninth switching transistor T9, the tenth switching transistor T10, the eleventh switching transistor T11, and the twelfth switching transistor T12. Phase A also includes a first diode D1 and a second diode D2. The first terminal of the first diode D1 is connected to the common terminal of the third switching transistor T3 and the fourth switching transistor T4. The second terminal of the first diode D1 is connected to the first terminal of the second diode D2. The second terminal of the second diode D2 is connected to the common terminal of the first switching transistor T1 and the second switching transistor T2. Phase B includes diodes D3 and D4. The first terminal of diode D3 is connected to the common terminal of switches T7 and T8. The second terminal of diode D3 is connected to the first terminal of diode D4. The second terminal of diode D4 is connected to the common terminal of switches T5 and T6. Phase C includes diodes D5 and D6. The first terminal of diode D5 is connected to the common terminal of switches T11 and T12. The second terminal of diode D5 is connected to the first terminal of diode D6. The second terminal of diode D6 is connected to the common terminal of switches T9 and T10. The inverter's output is connected to the power grid 11 via three phase lines. Specifically, the common terminal connecting the second switch T2 and the third switch T3 is connected to phase A of the power grid via the first inductor L1; the common terminal connecting the sixth switch T6 and the seventh switch T7 is connected to phase B of the power grid via the second inductor L2; and the common terminal connecting the tenth switch T10 and the eleventh switch T11 is connected to phase C of the power grid via the third inductor L2. Each inductor is also connected to the grid's neutral point N via a capacitor. The bus midpoint is connected to the grid's neutral point N via a neutral line.

[0047] Figure 2 A flowchart of an inverter control method provided in an embodiment of the present invention is shown below. Figure 1 and Figure 2 Optionally, the method includes:

[0048] S110: Generate the first adjustment amount for each phase based on the expected value of the DC component of the current and the actual value of the DC component of the current in each of the three phases.

[0049] Because the DC component in a three-phase four-wire inverter can cause a voltage shift at the bus midpoint, significantly affecting the inverter's performance, reliability, and efficiency, it is desirable that the inverter have no DC component under normal circumstances. Therefore, the desired value for the DC component of the current is set to 0, or a preset value that can be approximately 0, with each of the three phases corresponding to the same desired DC component value. The instantaneous current value of each phase can be collected using current sensors. Each phase's instantaneous current value includes both AC and DC components, and the DC component of the current in each phase, i.e., the actual value of the DC component, can then be obtained based on the collected current data.

[0050] For any one of the three phases, a corresponding first adjustment amount is generated based on the expected value of the DC current component and the actual value of the DC current component of that phase. Specifically, for phase A, the deviation between the actual value and the expected value of the DC current component of phase A is used as input. A fuzzy rule base is used for inference to output an adjustment amount with a small vector action time as the first adjustment amount corresponding to phase A. The process of generating the first adjustment amount for phases B and C is similar to that for phase A, and will not be elaborated further. In other optional implementations, besides using a fuzzy controller to generate the first adjustment amount based on the deviation between the actual value and the expected value of the DC current component, PI, sliding diaphragm, predictive, or other controllers can also be used to generate the first adjustment amount; no specific limitation is made in this regard.

[0051] S120: Generate the average current value of each phase based on the instantaneous current value of each phase in the three phases, and generate the average current parameter based on the average current value of each phase.

[0052] Each of the three phases has a current sampling point: phase A current sampling point 12 samples the instantaneous current value of phase A, phase B current sampling point 13 samples the instantaneous current value of phase B, and phase C current sampling point 14 samples the instantaneous current value of phase C. A current sensor, such as a Hall effect sensor, can be used for each phase to collect the instantaneous current value of that phase. The specific current sensor can be installed on the line connected to the inductor in the corresponding phase, and the current of the inductor in that phase can be used as the instantaneous current value of that phase. The instantaneous current value of each of the three phases can be sampled at a single sampling moment. After multiple sampling moments, the average value of the instantaneous current of each phase can be calculated, and the average current value is obtained by adding the three phase average current values ​​and dividing by 3.

[0053] S130: Generate a second adjustment amount based on the average current parameters and the sign of the voltage offset at the bus midpoint; the bus midpoint is the connection point where the first bus capacitor C1 and the second bus capacitor C2 are connected in series.

[0054] like Figure 1 As shown, when the three-phase load is balanced, the bus midpoint voltage is equal to the bus voltage V. BUS Half of that, that is, the voltage V of the first bus capacitor C1. BUSP Equal to the voltage V of the second bus capacitor C2 BUSN When the three-phase load is unbalanced or when there is a DC component in the three-phase current, it will be conducted to the bus midpoint through the neutral line connected to zero point N, causing the bus midpoint to shift.

[0055] By using the positive and negative signs of the average current parameter and the offset of the bus midpoint voltage, the coordinated control part for balancing the bus midpoint and suppressing the DC component is completed. Furthermore, the average current parameter can be input into sliding mode, predictive, and fuzzy controllers to generate a first intermediate quantity. This first intermediate quantity is coordinated with the bus midpoint control. When the voltage V of the first bus capacitor C1... BUSP The voltage V greater than that of the second bus capacitor C2 BUSN When the first intermediate signal is used as positive feedback, it is superimposed on each corresponding initial modulation wave, and then modulated to generate each corresponding PWM drive signal. When the voltage V of the first bus capacitor C1... BUSP The voltage V less than that of the second bus capacitor C2 BUSN In this process, the first intermediate quantity is used as a negative feedback quantity, subtracted from each corresponding initial modulation wave, and then modulated to generate each corresponding PWM drive signal. The specific process of modulating to generate the PWM drive signal is the same as the existing technology and will not be described in detail here.

[0056] The input of the modulation drive signal is adjusted according to the offset direction of the bus midpoint, so that the sum of the three-phase inductor currents flowing into the bus midpoint is zero. If the input of the modulation drive signal is not correlated with the offset direction of the bus midpoint, the bus midpoint will be fixed in one direction, and the offset will be greater as the power increases, making it impossible to achieve coordinated control of the DC component and the bus midpoint. The control method in this embodiment is applicable to bidirectional converters with charging and discharging functions.

[0057] S140: Generate each corresponding drive signal based on the second adjustment amount and each corresponding first adjustment amount.

[0058] Specifically, for phase A of the three-phase system, the sum of the second adjustment amount and the first adjustment amount corresponding to A is superimposed on the initial modulation wave corresponding to A to generate an updated modulation wave. This updated modulation wave is then input into the PWM modulation module to generate the corresponding drive signal. Similarly, for phase B of the three-phase system, the sum of the second adjustment amount and the first adjustment amount corresponding to B is superimposed on the initial modulation wave corresponding to B to generate an updated modulation wave. This updated modulation wave is then input into the PWM modulation module to generate the corresponding drive signal. For phase C of the three-phase system, the sum of the second adjustment amount and the first adjustment amount corresponding to C is superimposed on the initial modulation wave corresponding to C to generate an updated modulation wave. This updated modulation wave is then input into the PWM modulation module to generate the corresponding drive signal. The drive signal for phase A is used to connect to the four switching transistors corresponding to A in the inverter circuit 10. The same applies to phases B and C.

[0059] In this embodiment, a first adjustment amount is generated for each phase based on the actual value of the DC component of the current in each phase. A second adjustment amount is generated based on the average current parameter and the sign of the voltage offset at the bus midpoint. Then, a corresponding drive signal is generated based on the second adjustment amount and the corresponding first adjustment amount. This coordinates the DC component of the current in each phase and the offset of the bus midpoint. The offset direction of the bus midpoint is correlated with the input amount of the modulated drive signal when adjusting the DC component of each phase, ensuring that the sum of the three-phase inductor currents flowing into the bus midpoint is zero. If the input amount of the modulated drive signal is not correlated with the offset direction of the bus midpoint and the DC components of each phase, the bus midpoint will be fixed in one direction, and the offset will increase with increasing power, making it impossible to coordinate the control of the DC components and the bus midpoint. By coordinating the bus midpoint offset with the sum of the three-phase inductor currents injected into the midpoint, it ensures that the output DC component of each phase is within the standard requirement range (less than or equal to 0.5%In, where In is the rated current) and suppresses fluctuations and offsets at the bus midpoint.

[0060] Figure 3 A flowchart of another inverter control method provided in an embodiment of the present invention is shown below. Figure 1 and Figure 3 The method includes:

[0061] S111: Generate the first adjustment amount for each phase based on the expected value of the DC component of the current and the actual value of the DC component of the current in each of the three phases.

[0062] Prior to S111, it also included:

[0063] Step a1: Sample the instantaneous current value of each of the three phases.

[0064] The instantaneous current value of each phase in the three phases is sampled at a fixed first sampling frequency. That is, there are multiple first sampling times corresponding to the first sampling frequency. The instantaneous current value of each phase is sampled at each first sampling time, that is, the instantaneous current value of the three phases is sampled once at a first set time interval. The first set time interval is the time interval between any two adjacent first sampling times.

[0065] Step a2: Filter the instantaneous current value of each phase to generate the actual value of the DC component of the current of each phase.

[0066] For a first sampling moment, the instantaneous current value of phase A sampled at the first sampling moment is filtered by a low-pass filter circuit to obtain the actual value of the DC component of the current of phase A. The instantaneous current value of phase B sampled at the first sampling moment is filtered by a low-pass filter circuit to obtain the actual value of the DC component of the current of phase B. The instantaneous current value of phase C sampled at the first sampling moment is filtered by a low-pass filter circuit to obtain the actual value of the DC component of the current of phase C.

[0067] Optionally, step S111 includes:

[0068] Step b1: For each of the three phases, generate the corresponding current deviation based on the actual and expected values ​​of the DC current component of that phase. Specifically, generate the current deviation corresponding to phase A based on the actual and expected values ​​of the DC current component of phase A, generate the current deviation corresponding to phase B based on the actual and expected values ​​of the DC current component of phase B, and generate the current deviation corresponding to phase C based on the actual and expected values ​​of the DC current component of phase C.

[0069] At a first sampling moment, for phase A, the current deviation corresponding to phase A is generated based on the expected value of the DC component of the current and the actual value of the DC component of the current in phase A at that first sampling moment. That is, the difference between the expected value of the DC component of the current and the actual value of the DC component of the current in phase A at that first sampling moment is taken as the current deviation of phase A at that first sampling moment. The process of generating the current deviation for phases B and C is similar to that for phase A, and will not be described in detail here.

[0070] Step b2: Perform PI adjustment on the corresponding current deviation to generate the corresponding first adjustment amount. Specifically, perform PI adjustment on the current deviation corresponding to A to generate the first adjustment amount corresponding to A, perform PI adjustment on the current deviation corresponding to B to generate the first adjustment amount corresponding to B, and perform PI adjustment on the current deviation corresponding to C to generate the first adjustment amount corresponding to C.

[0071] Figure 4 This is a schematic diagram of a modulation ring structure provided in an embodiment of the present invention, with reference to... Figure 4 The modulation loop includes a DC component control loop 17 and a PWM modulation module 18. The DC component control loop 17 includes a three-phase DC component control loop. In the A-phase DC component control loop, the expected value of the current DC component is compared with the actual value of the current DC component i in phase A. A0 The input is to the first subtraction operator 171, and the current deviation of phase A output by the first subtraction operator 171 is input to the second PI controller 172. The output of the second PI controller 172 is the first adjustment amount corresponding to phase A. In the phase B DC component control loop, the expected value of the current DC component and the actual value i of the current DC component of phase B are compared. B0 The input is processed by the second subtraction operator 173, and the current deviation of phase B output by the second subtraction operator 173 is input into the third PI controller 174. The output of the third PI controller 174 is the first adjustment amount corresponding to phase B. In the phase C DC component control loop, the expected value of the current DC component and the actual value of the current DC component i of phase C are compared. C0 The current deviation of phase C output by the third subtraction arithmetic unit 175 is input into the fourth PI controller 176, and the output of the fourth PI controller 176 is the first adjustment amount corresponding to phase C.

[0072] Each phase in the DC component control loop 17 uses a PI controller. The expected value of the DC component of the current is set to zero, and the actual value of the DC component of the current in each phase is a negative feedback quantity. After the expected value and the actual value pass through the PI controller, the first adjustment quantity corresponding to each of the three phases is output. This loop is for independent control of the DC component of each phase so that they are all within the standard requirements.

[0073] S121: Within the sampling period, for each of the three phases, calculate the average current of that phase based on the instantaneous current values ​​at each sampling moment within the sampling period. Specifically, calculate the average current of phase A based on the instantaneous current values ​​at each sampling moment within the sampling period, calculate the average current of phase B based on the instantaneous current values ​​at each sampling moment within the sampling period, and calculate the average current of phase C based on the instantaneous current values ​​at each sampling moment within the sampling period.

[0074] The sampling period can be set by the user, such as 20ms per sampling period. In S121, the instantaneous current value of each phase in the three phases is sampled at a fixed second sampling frequency. That is, there are multiple second sampling times corresponding to the second sampling frequency. The instantaneous current value of each phase is sampled at each second sampling time. In other words, the instantaneous current value of each phase is sampled at intervals of a second set duration in S121. The second set duration is the time interval between any two adjacent second sampling times.

[0075] For example, the sampling period includes m second sampling moments. For phase A, the instantaneous current values ​​of phase A obtained at the m second sampling moments are added together and then divided by m to obtain the average current value of phase A. The same applies to phases B and C, and will not be repeated here. m is a positive integer.

[0076] The second sampling frequency is greater than the first sampling frequency, meaning the second set duration is less than the first set duration. Furthermore, there is an interval of n second sampling times between two adjacent first sampling times, where n is a positive integer and less than m. For example, with a sampling period of 20ms and a second set duration of 1ms, the instantaneous current value of each phase is collected every 1ms, and the average current value of each phase is generated within one sampling period, thus generating the average current parameter and further generating the second adjustment amount, i.e., the second adjustment amount is updated every 20ms. The first adjustment amount of each phase is calculated every 5ms by sampling the instantaneous current value of each phase. For example, the first first adjustment amount is calculated based on the instantaneous current values ​​of each phase sampled at the fifth second sampling time, and then the second first adjustment amount is calculated based on the instantaneous current values ​​of each phase sampled at the tenth second sampling time, and so on, i.e., the first adjustment amount is updated every 5ms.

[0077] S131: Sum the average current values ​​of each phase and then calculate the average value to generate the average current parameter.

[0078] The average current parameter is generated by summing the average current values ​​of each phase and dividing by 3. The average current parameter is updated every sampling period. That is, every sampling period, the average current parameter is calculated based on the average current value of each of the three phases within that sampling period, and then the subsequent second adjustment is updated. The first adjustment is updated every first set time interval, and the update period for the second adjustment is longer than that for the first adjustment.

[0079] S141: Obtain the first voltage of the first bus capacitor and the second voltage of the second bus capacitor.

[0080] Voltage sensors can be used to obtain the voltage of the first bus capacitor C1 and the voltage of the second bus capacitor C2 respectively. The voltage of the first bus capacitor C1 is recorded as the first voltage, and the voltage of the second bus capacitor C2 is recorded as the second voltage.

[0081] S151: Determine the sign of the voltage offset at the midpoint of the busbar based on the first voltage and the second voltage.

[0082] When the first voltage is greater than the second voltage, the voltage offset at the midpoint of the bus is positive;

[0083] When the first voltage is less than the second voltage, the voltage offset at the midpoint of the bus is negative.

[0084] S161: The average current parameter is PI-regulated to generate the first intermediate quantity. PI regulation is proportional-integral regulation, which means that the average current parameter can be input into the PI controller, and the output of the PI controller is the first intermediate quantity.

[0085] S171: When the voltage offset at the midpoint of the busbar is determined to be positive, the first intermediate value is used as the second adjustment value; when the voltage offset at the midpoint of the busbar is determined to be negative, the opposite of the first intermediate value is used as the second adjustment value.

[0086] Figure 5 This is a schematic diagram of a bus midpoint coordination control loop provided in an embodiment of the present invention. Steps S161 and S171 can be implemented through the bus midpoint coordination control loop. The bus midpoint coordination control loop consists of two parts, directly controlling the average current parameter i. L0 The PI element, i.e., the average current parameter i L0 The input to the first PI controller 15, based on the positive or negative value of the bus midpoint offset direction, completes the coordinated control part for bus midpoint balance and DC component suppression. Average current parameter i L0 After the PI stage, the first intermediate quantity is input into the value-taking function module 16, which coordinates with the midpoint of the bus for control. The value-taking function module 16 includes Sign(V) BUSP -V BUSN The function is used when the voltage V of the first bus capacitor C1 is... BUSP The voltage V greater than that of the second bus capacitor C2 BUSN At that time, the offset of the bus midpoint voltage is positive, and the loop output is positive. When the voltage V of the first bus capacitor C1 is positive... BUSP The voltage V less than that of the second bus capacitor C2 BUSN When the offset of the bus midpoint voltage is negative, the loop output is negative, and the output of the bus midpoint coordination control loop is denoted as the second adjustment amount V. L0 The purpose is to correlate the offset direction adjustment loop of the bus midpoint so that the sum of the average values ​​of the three-phase inductor currents flowing into the bus midpoint is zero. If the output of this loop is not correlated with the offset direction of the bus midpoint, the bus midpoint will be fixed in one direction, and the offset will become larger as the power increases, making it impossible to achieve coordinated control of the DC component and the bus midpoint. The principle is as follows:

[0087] 1. When the average current parameter i L0 When the voltage is greater than 0, the midpoint of the bus is in a charging state. According to the capacitor ampere-second balance principle, this will cause the voltage V of the second bus capacitor C2 to increase. BUSN To maintain busbar balance, the discharge time at the busbar midpoint should be increased (only relative to the previously mentioned average current parameter i). L0 For values ​​greater than 0, this means allowing the busbar more time to enter the discharge state. At this point:

[0088] If V BUSP >V BUSN The discharge time of the first bus capacitor C1 needs to be extended to reduce the first voltage. In the bus midpoint coordination control loop: V L1 ·Sign (V BUSP -V BUSN )=V L1 ·1=V L0 V L1 The first intermediate quantity is the output second adjustment quantity V. L0 The value is positive, which makes the initial modulation wave superimposed on each of the three phases a positive bias, thereby lengthening the discharge time of the first bus capacitor C1 to reduce the first voltage and thus maintain bus balance.

[0089] Conversely, if V BUSP <V BUSN The discharge time of the second bus capacitor C2 needs to be extended to bring the second voltage, i.e., the voltage V of the second bus capacitor C2, to a higher level. BUSN Reduce. In the bus midpoint coordinated control loop: V L1 ·Sign(V BUSP -V BUSN )=V L1 ·(-1)=-V L1 =V L0 The second adjustment value V output L0 The value is negative, which results in a negative bias on the initial modulation wave superimposed on each of the three phases, thereby lengthening the discharge time of the second bus capacitor C2 to reduce the second voltage and maintain bus balance.

[0090] 2. When i L0 When the voltage is less than 0, the bus midpoint is in a discharging state. According to the capacitor ampere-second balance principle, this will cause the second voltage to decrease. To maintain bus balance, the charging time at the bus midpoint should be increased. At this time:

[0091] If V BUSP >V BUSN The charging time of the second bus capacitor C2 needs to be extended to reduce the first voltage. In the bus midpoint coordination control loop: V L1 ·Sign (VBUSP -V BUSN )=V L1 ·1=V L0 The second adjustment value V output L0 Negative (because i) L0 If V is negative, then L1 Since the value itself is negative, the initial modulation wave superimposed on each of the three phases is a negative bias, which in turn increases the charging time of the second bus capacitor C2 to reduce the first voltage and thus maintain bus balance.

[0092] Conversely, if V BUSP <V BUSN The charging time of the first bus capacitor C1 needs to be extended to reduce the second voltage. To reduce the second voltage, a positive bias needs to be superimposed on the initial modulation wave of each of the three phases. In the bus midpoint coordination control loop: V L1 ·Sign (V BUSP -V BUSN )=V L1 ·(-1)=-V L1 =V L0 The second adjustment value V output L0 Positive (because i) L0 If V is negative, then L1 Since it is negative, V L0 (If positive), this results in a positive bias on the initial modulation wave superimposed on each of the three phases, which in turn lengthens the charging time of the first bus capacitor C1 to reduce the second voltage and thus maintain bus balance.

[0093] S181: Generate each corresponding drive signal based on the second adjustment amount and each corresponding first adjustment amount.

[0094] Further S181 includes:

[0095] Step d1: For each of the three phases, sum the second adjustment amount with the corresponding first adjustment amount to obtain the corresponding third intermediate amount. For a specific phase of the three phases, sum the second adjustment amount with the corresponding first adjustment amount to obtain the corresponding third intermediate amount. Specifically, sum the second adjustment amount with the first adjustment amount corresponding to A to obtain the third intermediate amount corresponding to A, sum the second adjustment amount with the first adjustment amount corresponding to B to obtain the third intermediate amount corresponding to B, and sum the second adjustment amount with the first adjustment amount corresponding to C to obtain the third intermediate amount corresponding to C.

[0096] Step d2: Superimpose the corresponding third intermediate quantity with the corresponding initial modulation wave to generate the corresponding intermediate modulation wave. Specifically, superimpose the third intermediate quantity corresponding to A with the corresponding initial modulation wave to generate the intermediate modulation wave corresponding to A; superimpose the third intermediate quantity corresponding to B with the corresponding initial modulation wave to generate the intermediate modulation wave corresponding to B; and superimpose the third intermediate quantity corresponding to C with the corresponding initial modulation wave to generate the intermediate modulation wave corresponding to C.

[0097] Step d3: Modulate the corresponding intermediate modulation wave to obtain the corresponding driving signal. Specifically, modulate the intermediate modulation wave corresponding to A to obtain the driving signal corresponding to A, modulate the intermediate modulation wave corresponding to B to obtain the driving signal corresponding to B, and modulate the intermediate modulation wave corresponding to C to obtain the driving signal corresponding to C.

[0098] Specifically, such as Figure 4 As shown in the figure, A corresponds to the first adjustment amount and the second adjustment amount V. L0 The third intermediate quantity corresponding to A is generated in the first adder 19. The third intermediate quantity corresponding to A is the same as the initial modulation wave V corresponding to A. apwm The intermediate modulation wave corresponding to A is generated in the second adder 20. The first and second adjustment values ​​V corresponding to B are also generated. L0 The third intermediate quantity corresponding to B is generated in the third adder 21. The third intermediate quantity corresponding to B is the same as the initial modulation wave V corresponding to B. bpwm The intermediate modulation wave corresponding to B is generated in the fourth adder 22. The first and second adjustment values ​​V corresponding to C are also input. L0 The third intermediate quantity corresponding to C is generated in the fifth adder 23. The third intermediate quantity corresponding to C is the same as the initial modulation wave V corresponding to C. cpwm The intermediate modulation wave corresponding to C is generated in the sixth adder 24.

[0099] In this embodiment, the first adjustment amount and the second adjustment amount V for each corresponding phase in the three phases are... L0After superposition, the output quantities of the complete three-phase current components and the bus midpoint coordinated control are obtained. The second adjustment quantity is output at a first frequency, and the first adjustment quantity is output at a second frequency. The first frequency is less than or equal to the second frequency, meaning the control period of the DC component control loop 17 needs to be less than or equal to the control period of the bus midpoint coordinated control loop. For example, the period of the DC component control loop can be 10ms or 5ms, and the control period of the bus midpoint coordinated control loop can be 20ms. The third intermediate quantity corresponding to each of the three phases is superimposed on the initial modulation waves of the three phases. The initial modulation wave is the output quantity of the inverter current loop (the control frequency of the inverter current loop is usually 3KHz-20KHz in practical applications, much larger than that of the bus midpoint coordinated control loop). The inverter current loop is the current loop in existing technology, and no specific limitation is made. The intermediate modulation wave of each phase is finally modulated and output by the PWM modulation module 18, serving as the drive signal for each switch in the inverter circuit 10. Specifically, when the intermediate modulation wave of each phase generates the drive signal through the PWM modulation module 18, the initial modulation wave of each phase can first be normalized by a factor of 2 / V. BUS After being mapped to the range [-1, 1], the signal is output to a comparator and compared with a triangular carrier wave to generate a corresponding drive signal.

[0100] This embodiment eliminates the need for an additional balancing bridge circuit, reducing costs, improving conversion efficiency, and mitigating risks. Furthermore, it eliminates the need for sector and small vector calculations, reducing software computational resource consumption. The solution does not require changes to existing hardware sampling points, making it simple, effective, and highly compatible. By coordinating and controlling the sum of the average values ​​of the bus midpoint offset and the injected midpoint three-phase inductor currents, it ensures that the DC output components of each phase are within standard requirements while suppressing bus midpoint fluctuations and offsets. It is also applicable to bidirectional converters with charging and discharging capabilities.

[0101] This invention also provides a three-phase four-wire inverter, such as... Figure 1 As shown, it includes:

[0102] The first bus capacitor C1, the second bus capacitor C2, and the inverter circuit 10 are connected together. The connection point of the first bus capacitor C1 and the second bus capacitor C2 connected in series is connected to the neutral line. The input terminal of the inverter circuit 10 is connected to the first bus capacitor C1 and the second bus capacitor C2. The output terminal of the inverter circuit 10 is connected to the power grid 11 through three phase lines and the neutral line.

[0103] A controller is connected to the inverter circuit 10 and is used to output a drive signal to the inverter circuit 10 according to the inverter control method in any of the above embodiments.

[0104] The three-phase four-wire inverter has the same beneficial effects as the inverter control method, so it will not be repeated here.

[0105] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0106] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. An inverter control method, characterized in that, The inverter includes a first bus capacitor, a second bus capacitor, and an inverter circuit. The connection point of the first bus capacitor and the second bus capacitor, which are connected in series, is connected to the neutral line. The input terminal of the inverter circuit is connected to the first bus capacitor and the second bus capacitor. The output terminal of the inverter circuit is connected to the power grid through three phase lines and the neutral line. The first terminal of the first bus capacitor is connected to the positive bus, the second terminal of the first bus capacitor is connected to the first terminal of the second bus capacitor, and the second terminal of the second bus capacitor is connected to the negative bus. The inverter control method includes: The first adjustment amount is generated for each phase based on the expected value of the DC component of the current and the actual value of the DC component of the current in each of the three phases. The average current value of each phase is generated based on the instantaneous current value of each phase in the three phases. The average current values ​​of each phase are summed and then averaged to generate the average current parameter. Obtain the first voltage of the first bus capacitor and the second voltage of the second bus capacitor; Based on the first voltage and the second voltage, determine the sign of the voltage offset at the midpoint of the busbar; the midpoint of the busbar is the connection point where the first busbar capacitor and the second busbar capacitor are connected in series. The average current parameter is PI-adjusted to generate a first intermediate value; When the voltage offset at the midpoint of the busbar is determined to be positive, the first intermediate value is used as the second adjustment value; when the voltage offset at the midpoint of the busbar is determined to be negative, the opposite of the first intermediate value is used as the second adjustment value. Each corresponding drive signal is generated based on the second adjustment amount and each corresponding first adjustment amount.

2. The inverter control method according to claim 1, characterized in that, When the first voltage is greater than the second voltage, the voltage offset at the midpoint of the busbar is positive; When the first voltage is less than the second voltage, the voltage offset at the midpoint of the bus is negative.

3. The inverter control method according to claim 1, characterized in that, The process of generating the average current value of each phase based on the instantaneous current value of each phase in the three phases includes: Within the sampling period, for each of the three phases, the average current value of that phase is calculated based on the instantaneous current value of that phase at each sampling time within the sampling period.

4. The inverter control method according to claim 3, characterized in that, The average current parameter is updated once at each sampling interval.

5. The inverter control method according to claim 1, characterized in that, The process of generating the first adjustment amount for each phase based on the expected value of the DC component of the current and the actual value of the DC component of the current in each of the three phases includes: For each of the three phases, the corresponding current deviation is generated based on the actual value of the DC component of the current in that phase and the expected value of the DC component of the current. The corresponding current deviation is adjusted using a PI controller to generate the corresponding first adjustment amount.

6. The inverter control method according to claim 1, characterized in that, Before generating the first adjustment amount for each corresponding phase based on the expected value of the DC component of the current and the actual value of the DC component of the current in each of the three phases, the method further includes: Sample the instantaneous current value of each of the three phases; The instantaneous current value of each phase is filtered to generate the actual DC component value of the current of each phase.

7. The inverter control method according to claim 1, characterized in that, The update cycle of the second adjustment is longer than that of the first adjustment.

8. The inverter control method according to claim 1, characterized in that, The step of generating each corresponding drive signal based on the second adjustment amount and each corresponding first adjustment amount includes: For each of the three phases, the second adjustment amount is summed with the corresponding first adjustment amount to obtain the corresponding third intermediate amount; The corresponding third intermediate quantity is superimposed with the corresponding initial modulation wave to generate the corresponding intermediate modulation wave; The corresponding intermediate modulation wave is modulated to obtain the corresponding driving signal.

9. A three-phase four-wire inverter, characterized in that, include: A first bus capacitor, a second bus capacitor, and an inverter circuit are included. The connection point of the first bus capacitor and the second bus capacitor, which are connected in series, is connected to the neutral line. The input terminal of the inverter circuit is connected to the first bus capacitor and the second bus capacitor. The output terminal of the inverter circuit is connected to the power grid through three phase lines and the neutral line. A controller, connected to the inverter circuit, is configured to output the drive signal to the inverter circuit according to any one of claims 1-8.

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