Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and the semiconductor device comprises a plurality of storage units which are distributed in different layers and are stacked in a direction perpendicular to a substrate; the bit lines penetrate through the storage units of different layers and extend in the direction perpendicular to the substrate; the plurality of word lines are distributed on different layers, the word lines and the bit lines are distributed along a first direction parallel to the substrate, the word lines extend along a second direction parallel to the substrate, and the first direction and the second direction are crossed; the memory unit comprises a transistor, the transistor comprises a semiconductor layer, the semiconductor layer surrounds the word line, one side, facing the bit line, of the semiconductor layer is perpendicular to the side wall of the substrate and is connected with the bit line, and a plurality of semiconductor layers of a plurality of transistors at the same position of different layers are connected with the same bit line. According to the scheme provided by the embodiment, the bit lines vertically extend, the word lines horizontally extend, the word lines are small in thickness, and parasitic capacitance between the word lines and the bit lines can be reduced.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This application provides a semiconductor device and its manufacturing method, as well as an electronic device, which reduces parasitic capacitance.

[0006] This application provides a semiconductor device, including:

[0007] Multiple memory cells are stacked along the vertical substrate direction, distributed across different layers;

[0008] Bit lines extend through the memory cells in different layers along a direction perpendicular to the substrate;

[0009] Multiple word lines are distributed in different layers. The word lines and the bit lines are distributed along a first direction parallel to the substrate, and the word lines extend along a second direction parallel to the substrate. The first direction and the second direction intersect.

[0010] The memory cell includes a transistor, the transistor including a semiconductor layer surrounding the word line, the sidewall of the semiconductor layer facing the bit line and perpendicular to the substrate being connected to the bit line, and multiple semiconductor layers of multiple transistors at the same position on different layers being connected to the same bit line.

[0011] In some embodiments, the transistor further includes a first electrode disposed on the word line away from the bit line and connected to a sidewall of the semiconductor layer away from the bit line and perpendicular to the substrate.

[0012] The first electrode forms an annular groove, the annular groove including a bottom wall perpendicular to the substrate and two side walls parallel to the substrate, the bottom wall including an inner bottom wall located within the annular groove and an outer bottom wall located outside the annular groove, and a portion of the semiconductor layer is connected to the outer bottom wall.

[0013] In some embodiments, the memory cell further includes a capacitor, wherein the capacitor and the transistor in the same memory cell are distributed along the first direction;

[0014] The capacitor includes a first capacitor electrode and a second capacitor electrode; the first electrode is reused as the first capacitor electrode of the capacitor; the second capacitor electrode includes a first sub-electrode, the first capacitor electrode surrounds the first sub-electrode, and a first dielectric layer is disposed between the first capacitor electrode and the first sub-electrode; the first sub-electrode is distributed on the inner wall of the annular groove formed by the first electrode; the first sub-electrodes of the storage cells at the same position in different layers are connected to form an integral structure.

[0015] In some embodiments, the sidewall of the annular groove includes an inner sidewall located within the annular groove and an outer sidewall located outside the annular groove, and the first sub-electrode is also distributed on the outer sidewall of the annular groove.

[0016] In some embodiments, the outer bottom wall of the annular groove includes a first region and a second region spaced apart along the circumferential direction of the annular groove, and two intermediate regions spaced apart from the first region, respectively disposed on both sides of the first region. The first region is located on the side of the annular groove facing the bit line, the word line is distributed on the first region, and the semiconductor layer is connected to a portion of the first region. The second capacitor electrode further includes a second sub-electrode, which is distributed on the second region of the outer bottom wall of the annular groove.

[0017] In some embodiments, a second dielectric layer is disposed between the first capacitor electrode and the second sub-electrode, and the second dielectric layers of capacitors at the same position in different layers are spaced apart along a direction perpendicular to the substrate.

[0018] In some embodiments, memory cells in the same layer are arrayed along the first direction and the second direction, and the second sub-electrodes of multiple memory cells in the same layer and column distributed along the second direction are connected to form an integrated structure.

[0019] In some embodiments, the integral structure formed by connecting the second sub-electrodes, the two first capacitor electrodes adjacent along the second direction, and the region defined by the word line adjacent to the first electrode are filled with a first isolation layer, and the first isolation layers at the same position in different layers are connected to form an integral structure extending along the direction perpendicular to the substrate, and the first isolation layer is connected to the middle region of the outer bottom wall of the two first capacitor electrodes adjacent along the second direction.

[0020] In some embodiments, the first isolation layer is also distributed in the region of the first region that is not connected to the semiconductor layer.

[0021] In some embodiments, the semiconductor device further includes:

[0022] An insulating layer and a conductive layer are alternately distributed along a direction perpendicular to the substrate;

[0023] A first hole penetrating the insulating layer and the conductive layer; the first hole includes a first sub-hole located in the insulating layer and a second sub-hole located in the conductive layer, the second sub-hole having a groove extending in a direction parallel to the substrate relative to the first sub-hole;

[0024] The first electrode is distributed on the inner wall of the groove, and the first electrode, the first dielectric layer, and the first sub-electrode are distributed sequentially from the outside to the inside in the first hole.

[0025] In some embodiments, the semiconductor layers of a plurality of memory cells in the same column distributed along a second direction are spaced apart along the second direction and surround the same word line.

[0026] In some embodiments, two adjacent memory cells in each pair of columns along a first direction are connected to the same bit line.

[0027] In some embodiments, multiple semiconductor layers of memory cells in the same column distributed along the second direction are respectively connected to different bit lines distributed at intervals along the second direction.

[0028] In some embodiments, a second isolation layer is provided between different bit lines spaced apart along a second direction, penetrating the memory cells of different layers and extending along a direction perpendicular to the substrate.

[0029] This disclosure provides a method for manufacturing a semiconductor device, including:

[0030] A stacked structure comprising alternating first insulating layers and first sacrificial layers is formed on a substrate;

[0031] A plurality of second holes are formed that are spaced apart along a second direction through the stacked structure perpendicular to the substrate direction, and a plurality of bit lines are filled in the plurality of second holes;

[0032] A plurality of first holes are formed that penetrate the stacked structure along a second direction perpendicular to the substrate, and the first holes and second holes are spaced apart along a first direction. Based on the first holes, the first sacrificial layer is etched along a direction parallel to the substrate to form a first lateral groove. A first electrode is formed distributed on the inner wall of the first lateral groove. The first direction and the second direction intersect.

[0033] A first groove is formed on the side of the first hole opposite to the second hole, penetrating the stacked structure and extending along the second direction;

[0034] Based on the first trench, word lines extending in a second direction are formed between adjacent fourth insulating layers, between a plurality of first holes and a plurality of second holes, and a plurality of semiconductor layers spaced apart in the second direction around the word lines, the semiconductor layers respectively connecting the first electrode and the bit lines.

[0035] In some embodiments, based on the first trench, word lines extending in a second direction are formed between adjacent fourth insulating layers, between a plurality of first holes and a plurality of second holes, and a plurality of semiconductor layers spaced apart in the second direction surrounding the word lines include:

[0036] Based on the first trench etching to remove the first insulating layer, the first insulating layer is replaced by a fourth insulating layer and a second sacrificial layer. The second sacrificial layer is located between adjacent first sacrificial layers and between adjacent bit lines along the second direction, and is connected to adjacent bit lines along the second direction.

[0037] Based on the removal of the first sacrificial layer by the first trench etching, a third sacrificial layer connected to the second sacrificial layer is formed between adjacent second sacrificial layers located in the direction perpendicular to the substrate and between adjacent bit lines located in the second direction.

[0038] A semiconductor thin film, a gate insulating film, and a first conductive film are sequentially deposited. The semiconductor thin film, gate insulating film, and first conductive film covering the side of the first electrode away from the bit line and the side of the first electrode facing the first electrode adjacent to the second direction are etched away. The semiconductor thin film, gate insulating film, and first conductive film covering the side of the first electrode facing the bit line are retained to form multiple semiconductor layers and multiple gate insulating layers of multiple transistors, as well as word lines, wherein the gate insulating layers surround the word lines and the semiconductor layers surround the gate insulating layers.

[0039] A fourth sacrificial layer is formed between adjacent fourth insulating layers to connect word lines and adjacent first electrodes along the second direction; a fifth sacrificial layer connected to the fourth sacrificial layers is formed between adjacent fourth sacrificial layers along a direction perpendicular to the substrate.

[0040] The second and third sacrificial layers are etched away to form a third hole; the fourth and fifth sacrificial layers are etched away to form a fourth hole; the plurality of semiconductor layers are etched along a direction parallel to the substrate based on the third and fourth holes, thereby disconnecting the plurality of semiconductor layers.

[0041] In some embodiments, the method further includes: exposing the first hole and the first lateral groove, and forming a first sub-electrode within the first hole and the first lateral groove.

[0042] In some embodiments, before forming the first sub-electrode in the first hole and the first lateral groove, the method further includes: exposing the side of the first electrode away from the substrate and the side facing the substrate to form a second lateral groove;

[0043] Forming a first sub-electrode within the first hole and the first transverse groove includes: forming a first sub-electrode within the first hole, the first transverse groove, and the second transverse groove.

[0044] In some embodiments, after forming a fourth sacrificial layer connecting word lines and adjacent first electrodes along the second direction between adjacent fourth insulating layers, and before forming a fifth sacrificial layer connected to the fourth sacrificial layers between adjacent fourth sacrificial layers along a direction perpendicular to the substrate, the method further includes:

[0045] A second sub-electrode is formed on the side of the first electrode opposite to the bit line;

[0046] After forming a fifth sacrificial layer connected to the fourth sacrificial layer between adjacent fourth sacrificial layers along a direction perpendicular to the substrate, the method further includes:

[0047] A connecting electrode is formed that fills the first trench and is connected to the second sub-electrode.

[0048] This disclosure provides an electronic device, including the semiconductor device described in any of the above embodiments, or a semiconductor device formed according to the manufacturing method of the semiconductor device described in any of the above embodiments.

[0049] This application includes a semiconductor device and a method for manufacturing the same, as well as an electronic device. The semiconductor device includes: a plurality of memory cells stacked in different layers along a direction perpendicular to a substrate; bit lines extending through the memory cells in different layers along a direction perpendicular to the substrate; and a plurality of word lines distributed in different layers, the word lines and the bit lines being distributed along a first direction parallel to the substrate, the word lines extending along a second direction parallel to the substrate, the first direction and the second direction intersecting; each memory cell includes a transistor, each transistor including a semiconductor layer, the semiconductor layer surrounding the word line, and a sidewall of the semiconductor layer facing the bit line and perpendicular to the substrate being connected to the bit line; multiple semiconductor layers of multiple transistors at the same position in different layers are connected to the same bit line. In this embodiment, the bit lines extend vertically, the word lines extend horizontally, and the semiconductor layer surrounds the word lines. Compared to a scheme where the bit lines extend horizontally and the word lines extend vertically, when the word lines extend horizontally, the word line thickness is less than when the bit lines extend horizontally, resulting in a smaller parasitic capacitance between the word lines and the bit lines.

[0050] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0051] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0052] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0053] Figure 1A A cross-sectional view of a semiconductor device provided for some embodiments along the AA' direction parallel to the substrate. Figure 1B A cross-sectional view of a semiconductor device provided for some embodiments along the BB' direction parallel to the substrate. Figure 1C For along Figure 1A Cross-sectional view in the CC' direction. Figure 1D For along Figure 1A Cross-sectional view in the DD' direction. Figure 1E For along Figure 1A Cross-sectional view in the EE' direction. Figure 1F For along Figure 1A Cross-sectional view in the FF' direction; Figure 1G A schematic diagram of the first capacitor electrode provided for some embodiments;

[0054] Figure 2A A cross-sectional view along the AA' direction after the bit line is formed, provided for some embodiments. Figure 2B A cross-sectional view along the CC' direction after the bit line is formed, provided for some embodiments; Figure 2C A cross-sectional view along the DD' direction after the bit line is formed, provided for some embodiments;

[0055] Figure 3A A cross-sectional view along the AA' direction after the formation of the first capacitor electrode, provided for some embodiments. Figure 3B A cross-sectional view along the CC' direction after the formation of the first capacitor electrode, provided for some embodiments. Figure 3C A cross-sectional view along the FF' direction after the formation of the first capacitor electrode, provided for some embodiments;

[0056] Figure 4A A cross-sectional view along the AA' direction after the formation of the first trench, provided in some embodiments. Figure 4B A cross-sectional view along the CC' direction after the formation of the first trench, provided in some embodiments. Figure 4C A cross-sectional view along the FF' direction after the formation of the first trench, provided for some embodiments;

[0057] Figure 5A A cross-sectional view along the AA' direction after the formation of the second sacrificial layer, provided for some embodiments. Figure 5B A cross-sectional view along the CC' direction after the formation of the second sacrificial layer, provided for some embodiments. Figure 5C A cross-sectional view along the DD' direction after the formation of the second sacrificial layer, provided for some embodiments. Figure 5D A cross-sectional view along the FF' direction after the formation of the second sacrificial layer, provided for some embodiments;

[0058] Figure 6A Cross-sectional views along the AA' direction after the formation of the semiconductor layer, gate insulating layer, and word line are provided for some embodiments. Figure 6B Cross-sectional views along the CC' direction after the formation of the semiconductor layer, gate insulating layer, and word line are provided for some embodiments. Figure 6C Cross-sectional views along the DD' direction provided in some embodiments after the formation of the semiconductor layer, gate insulating layer, and word line. Figure 6D A cross-sectional view along the EE' direction after the formation of the semiconductor layer, gate insulating layer and word line is provided for some embodiments;

[0059] Figure 7A Cross-sectional views along the AA' direction provided for some embodiments after the formation of the second dielectric layer and the second sub-electrode. Figure 7B A cross-sectional view along the CC' direction after the formation of the second dielectric layer and the second sub-electrode, provided for some embodiments. Figure 7C A cross-sectional view along the EE' direction after the formation of the second dielectric layer and the second sub-electrode, provided for some embodiments;

[0060] Figure 8AA cross-sectional view along the AA' direction after the connection electrode has been formed, provided for some embodiments. Figure 8B A cross-sectional view along the CC' direction after the connection electrodes have been formed, as provided in some embodiments. Figure 8C A cross-sectional view along the EE' direction after the connection electrode has been formed, provided for some embodiments;

[0061] Figure 9A A cross-sectional view along the AA' direction after disconnecting the semiconductor layers of different transistors in the same column, as provided in some embodiments. Figure 9B A cross-sectional view along the CC' direction after disconnecting the semiconductor layers of different transistors in the same column, as provided in some embodiments. Figure 9C A cross-sectional view along the EE' direction after disconnecting the semiconductor layers of different transistors in the same column, as provided in some embodiments;

[0062] Figure 10A A cross-sectional view along the AA' direction after the formation of the isolation layer is provided in some embodiments. Figure 10B A cross-sectional view along the CC' direction after the formation of the isolation layer is provided in some embodiments. Figure 10C A cross-sectional view along the EE' direction after the formation of the isolation layer is provided for some embodiments;

[0063] Figure 11A A cross-sectional view along the AA' direction after the formation of the first dielectric layer and the first sub-electrode, provided for some embodiments. Figure 11B A cross-sectional view along the CC' direction after the formation of the first dielectric layer and the first sub-electrode, provided for some embodiments. Figure 11C A cross-sectional view along the EE' direction after the formation of the first dielectric layer and the first sub-electrode, provided for some embodiments. Detailed Implementation

[0064] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0065] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0066] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0067] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0068] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0069] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0070] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0071] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0072] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0073] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0074] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.

[0075] In this embodiment of the disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0076] Figure 1A A cross-sectional view of a semiconductor device provided for some embodiments along the AA' direction parallel to the substrate. Figure 1B A cross-sectional view of a semiconductor device provided for some embodiments along the BB' direction parallel to the substrate. Figure 1C For along Figure 1A Cross-sectional view in the CC' direction. Figure 1D For along Figure 1A Cross-sectional view in the DD' direction. Figure 1E For along Figure 1A Cross-sectional view in the EE' direction. Figure 1F For along Figure 1A A cross-sectional view along the FF' direction. (See attached image.) Figures 1A to 1F As shown, this disclosure provides a semiconductor device including a multilayer memory cell array vertically stacked on a substrate 1.

[0077] The memory cell array may include multiple memory cells, multiple bit lines 30, and multiple word lines 40. Each layer of the memory cell array may include multiple memory cells distributed along a first direction X parallel to the substrate 1 and a second direction Y parallel to the substrate 1. The first direction X and the second direction Y may intersect.

[0078] The bit line 30 can extend in a direction perpendicular to the substrate 1, and multiple memory cells stacked in the vertical direction at the same position in different layers are connected to the same bit line 30.

[0079] In some embodiments, adjacent memory cells along the first direction X are connected to the same bit line 30. Every two columns of memory cells can be grouped together, and memory cells within the same group are connected to the same bit line 30.

[0080] The word lines 40 can extend along a second direction Y parallel to the substrate 1. Multiple word lines 40 of the same memory cell array can be spaced apart from each other, and the multiple word lines 40 of the same memory cell array can be distributed at intervals along a first direction X. Word lines 40 of different layers of memory cell arrays can be stacked in a direction perpendicular to the substrate 1.

[0081] The storage unit can be a 1T1C storage unit, or it can be a storage unit with other structures.

[0082] Taking a 1T1C memory cell as an example, the memory cell may include a transistor and a capacitor connected to the transistor. The transistor and capacitor in the same memory cell may be distributed along a first direction X. The capacitor, the word line 40, and the bit line 30 are distributed along the first direction X. The transistor may include a gate electrode 26, a first electrode 51, and a second electrode 52. The gate electrode 26 may be part of the word line 40, and the gate electrodes 26 of transistors in the same column of the same layer may be connected to form a single word line 40 structure.

[0083] The second electrode 52 may be connected to the bit line 30, or the second electrode 52 may be a part of the bit line 30. The second electrodes 52 of the transistors of memory cells at the same location in different layers may be connected to the same bit line 30. The second electrodes 52 of the transistors at the same location in different layers are connected to form a bit line 30 of an integral structure extending perpendicular to the substrate 1.

[0084] The following description uses a semiconductor device comprising multiple vertically stacked transistors at the same location as an example, with a memory cell of 1T1C as an example.

[0085] like Figures 1A to 1F As shown, this disclosure provides a semiconductor device, the semiconductor device comprising:

[0086] Multiple memory cells are stacked along the direction perpendicular to substrate 1, distributed across different layers;

[0087] Bit line 30 extends through the memory cells in different layers along a direction perpendicular to the substrate 1;

[0088] Multiple word lines 40 are distributed in different layers. The word lines 40 and the bit lines 30 are distributed along a first direction X parallel to the substrate 1. The word lines 40 extend along a second direction Y parallel to the substrate 1. The first direction X and the second direction Y intersect.

[0089] The memory cell includes a transistor, the transistor includes a semiconductor layer 23, the semiconductor layer 23 surrounds the word line 40, the sidewall of the semiconductor layer 23 facing the bit line 30 and perpendicular to the substrate 1 is connected to the bit line 30, and multiple semiconductor layers 23 of multiple transistors at the same position in different layers are connected to the same bit line 30.

[0090] In the solution provided in this embodiment, the bit line 30 extends vertically, the word line 40 extends horizontally, and the semiconductor layer 23 surrounds the word line 40. Compared with the solution where the bit line extends horizontally and the word line extends vertically, the thickness of the bit line is greater when the bit line extends horizontally than the thickness of the word line when the word line extends horizontally (the area where the bit line is located is occupied by the word line, the semiconductor layer, and the gate insulating layer between the word line and the semiconductor layer. When the transistor thickness is the same, the thickness of the word line will be less when the word line extends horizontally than the thickness of the bit line when the bit line extends horizontally), thus the parasitic capacitance between the word line and the bit line is smaller.

[0091] In some embodiments, multiple semiconductor layers 23 of memory cells in the same column distributed along the second direction Y are respectively connected to different bit lines 30 distributed at intervals along the second direction Y.

[0092] In some embodiments, a second isolation layer 602 is provided between adjacent bit lines 30 spaced apart along the second direction Y, penetrating the memory cells of different layers and extending along a direction perpendicular to the substrate 1. That is, adjacent bit lines 30 along the second direction Y are spaced apart by the second isolation layer 602.

[0093] In some embodiments, multiple semiconductor layers 23 of multiple memory cells in the same column of the same layer are spaced apart along the second direction Y and surround the same word line 40. That is, multiple semiconductor layers 23 of multiple transistors in the same column are distributed in different regions of the sidewall of the same word line 40.

[0094] In some embodiments, the transistor may further include: a gate insulating layer 24 disposed between the word line 40 and the semiconductor layer 23, wherein a plurality of gate insulating layers 24 of a plurality of transistors in the same column of the same layer are connected to form an integral structure, and the gate insulating layer 24 extends continuously on the side of the word line 40 toward the bit line 30, and has an opening on the side of the word line 40 away from the bit line 30 to expose the word line 40.

[0095] In some embodiments, the first electrode 51 of the transistor is disposed on the word line 40 away from the bit line 30, and is connected to the sidewall of the semiconductor layer 23 away from the bit line 30 and perpendicular to the substrate 1.

[0096] In some embodiments, the first electrode 51 may form an annular groove, which may include a bottom wall perpendicular to the substrate 1 and two side walls parallel to the substrate 1. The bottom wall includes an inner bottom wall located within the annular groove and an outer bottom wall located outside the annular groove. The semiconductor layer 23 is connected to a portion of the outer bottom wall. The orthographic projection of the annular groove onto the substrate 1 may be a closed ring.

[0097] In some embodiments, the capacitor includes a first capacitor electrode 41 and a second capacitor electrode 42, wherein the first electrode 51 is reused as the first capacitor electrode 41.

[0098] In some embodiments, the second capacitor electrode 42 may include a first sub-electrode 421, the first capacitor electrode 41 surrounding the first sub-electrode 421, and a first dielectric layer 431 disposed between the first capacitor electrode 41 and the first sub-electrode 421; the first sub-electrode 421 extends along a direction perpendicular to the substrate 1 and fills the annular groove formed by the first electrode 51; the first sub-electrodes 421 of memory cells at the same position in different layers may be connected to form an integral structure extending along a direction perpendicular to the substrate 1. That is, the first sub-electrode 421 is disposed in the region surrounded by the first electrode 51.

[0099] In some embodiments, the first dielectric layer 431 of capacitors at the same location on different layers is connected to form an integral structure.

[0100] In some embodiments, the sidewall of the annular groove includes an inner sidewall located within the annular groove and an outer sidewall located outside the annular groove, and the first sub-electrode 421 is also distributed on the outer sidewall of the annular groove. That is, the first sub-electrode 421 can be distributed on the inner wall (including the inner bottom wall and the inner sidewall) of the annular groove, or it can be distributed on the outer sidewall of the annular groove, thereby maximizing the area facing the first capacitor electrode 41 and increasing the capacitance of the capacitor. However, the embodiments of this disclosure are not limited to this, and the first sub-electrode 421 may not be distributed on the outer sidewall surrounding the groove.

[0101] In some embodiments, the second capacitor electrode 42 may further include a second sub-electrode 422, which is distributed on the outer bottom wall of the annular groove, and a second dielectric layer 432 is disposed between the first capacitor electrode 41 and the second sub-electrode 422. The solution provided in this embodiment, by disposing an electrode outside the first capacitor electrode 41, can further increase the capacitance of the capacitor.

[0102] In some embodiments, the second sub-electrodes 422 of a plurality of memory cells distributed in the same layer and column along the second direction Y are connected to form an integral structure.

[0103] In some embodiments, the second sub-electrode 422 fills the region between adjacent first capacitor electrodes 41 along the second direction.

[0104] In some embodiments, second sub-electrodes 422 of multiple memory cells at the same location in different layers are connected. The multiple second sub-electrodes 422 can be connected by a connecting electrode 424 extending perpendicular to the substrate 1. The connecting electrode 424 can be disposed in a trench extending along the second direction Y and perpendicular to the substrate 1. The connecting electrode 424 can be a planar film extending perpendicular to the substrate 1 and the second direction Y, connecting the second sub-electrodes 422 of multiple memory cells in the same layer and column, and connecting the second sub-electrodes of multiple memory cells at the same location in different layers.

[0105] In some embodiments, the second dielectric layers 432 of capacitors distributed in the same layer and column along the second direction Y are connected to form an integral structure.

[0106] In some embodiments, the second dielectric layers 432 of capacitors at the same location on different layers are disconnected, for example, physically disconnected.

[0107] Figure 1G This is a schematic diagram of a first capacitor electrode 41 or a first electrode 51 provided in some embodiments. In some embodiments, such as Figure 1G As shown, the outer bottom wall of the annular groove includes a first region 511 and a second region 512 spaced apart along the circumferential direction of the annular groove, and two intermediate regions spaced apart from the first region 511 and the second region 512, respectively, which are referred to as the first intermediate region 513 and the second intermediate region 514. The first region 511 is located on the side of the annular groove facing the bit line 30, the word line 40 is distributed on the first region 511, and the semiconductor layer 23 is connected to a portion of the first region 511.

[0108] In some embodiments, the second sub-electrode 422 is distributed on the second region 512 of the outer bottom wall of the annular groove.

[0109] In some embodiments, a first isolation layer 601 is disposed between the integral structure formed by the connection of the second sub-electrodes 422, the word line 40, and the region defined by the first capacitor electrodes 41 of two adjacent capacitors along the second direction Y. Furthermore, the first isolation layers 601 at the same positions in different layers are connected to form an integral structure extending perpendicular to the substrate 1. With this structure, the word line can be implemented without a photomask, thereby reducing the need for photomasks and lowering costs. Additionally, the device can be more compact, increasing device density.

[0110] A first isolation layer 601 is filled between the two intermediate regions of the outer bottom wall of the annular groove and the word line 40. The first isolation layer 601 is also distributed in the region of the first region 511 that is not connected to the semiconductor layer 23. That is, the first isolation layer 601 is filled between the first intermediate region 513 and the word line 40, and the first isolation layer 601 is filled between the second intermediate region 514 and the word line 40. The first isolation layer 601 is connected to the word line 40 through an opening in the gate insulating layer 24.

[0111] In some embodiments, the first isolation layer 601 is connected to the adjacent intermediate regions of the annular grooves of the first capacitor electrodes 41 of two adjacent memory cells along the second direction Y. That is, the first isolation layer 601 is connected to the first intermediate region 513 of the first capacitor electrode 41 of one capacitor and to the second intermediate region 514 of the first capacitor electrode 41 of the other capacitor. The first isolation layer 601 is also connected to the second dielectric layer 432.

[0112] In some embodiments, the first isolation layer 601 connects to the middle region on the same side of the outer bottom wall of the first capacitor electrode 41 of multiple capacitors at the same position in different layers. That is, the first isolation layer 601 can connect to the first middle region 513 of the outer bottom wall of the first capacitor electrode 41 of multiple capacitors at the same position in different layers, or connect to the second middle region 514 of the outer bottom wall of the first capacitor electrode 41 of multiple capacitors at the same position in different layers.

[0113] In some embodiments, the end face of the word line 40 connected to the first isolation layer 601 includes a recessed region that is recessed toward the bit line 30.

[0114] In some embodiments, the semiconductor device may further include:

[0115] An insulating layer and a conductive layer are alternately distributed along a direction perpendicular to substrate 1;

[0116] A first hole penetrating the insulating layer and the conductive layer; the first hole includes a first sub-hole located in the insulating layer and a second sub-hole located in the conductive layer, the second sub-hole having a groove extending in a direction parallel to the substrate 1 relative to the first sub-hole;

[0117] The first electrode 41 is distributed on the inner wall of the groove, and the first electrode 41, the first dielectric layer 431, and the first sub-electrode 421 are distributed sequentially from the outside to the inside in the first hole. The solution provided in this embodiment can form the first electrode 41 of multiple capacitors, the first dielectric layer 431 of multiple capacitors, and the first sub-electrode 421 of multiple capacitors in one step, simplifying the process.

[0118] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. The "patterning process" mentioned in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes film coating, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."

[0119] In one exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0120] 1) Form bit line 30;

[0121] A substrate 1 is provided, and a first insulating film and a first sacrificial layer film are alternately deposited on the substrate 1 to form a stacked structure comprising a plurality of alternately arranged first insulating layers 11 and first sacrificial layers 10;

[0122] The stacked structure is etched from the top layer to the bottom layer along a direction perpendicular to the substrate 1 (etching stops on the substrate 1) to form multiple rows of second holes K2, each row including multiple second holes K2 spaced apart along the second direction Y;

[0123] After depositing the first conductive film, it is smoothed to form the bit line 30 that fills the second hole K2; as shown. Figure 2A , Figure 2B and Figure 2C As shown. Among them, Figure 2A A cross-sectional view along the AA' direction after forming bit line 30, provided for some embodiments. Figure 2B A cross-sectional view along the CC' direction after forming bit line 30, provided for some embodiments; Figure 2C A cross-sectional view along the DD' direction after forming bit line 30, provided for some embodiments. Figure 2A , Figure 2B and Figure 2C Only one row of the second hole K2 is shown.

[0124] In some embodiments, the first conductive film may be one or more of the following different types of materials:

[0125] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can also be a metal alloy containing these metals.

[0126] Alternatively, it can be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and aluminum-doped zinc oxide (AZO); or metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0127] Alternatively, it could be polycrystalline silicon, conductive doped semiconductor materials, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; or other materials that exhibit conductivity.

[0128] The materials of the second to sixth conductive films are similar to those of the first conductive film, and will not be described in detail here.

[0129] In some embodiments, the bit line 30 may include a first sub-layer 31 and a second sub-layer 32. The first sub-layer 31 may be a conductive material with good adhesion to other film layers, such as TiN, and the second sub-layer 32 may be a conductive material with low resistivity, such as tungsten. The first sub-layer 31 covers the bottom wall and sidewalls of the second hole K2, and the second sub-layer 32 fills the second hole K2.

[0130] In some embodiments, substrate 1 may be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

[0131] In some embodiments, the first insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2), etc. The materials of the subsequent second to fifth insulating films are similar and will not be described in detail.

[0132] In some embodiments, the first sacrificial layer film may be a film layer that has an etching selectivity ratio with the first insulating film, such as silicon nitride (SiN).

[0133] In some embodiments, the second hole K2 along a cross section parallel to the substrate 1 can be circular, square, or the like.

[0134] 2) Form the first capacitor electrode 41;

[0135] A second insulating film is deposited to form a second insulating layer 12, which covers the bit line 30 and the topmost first sacrificial layer 10.

[0136] The stacked structure is etched from the top layer to the bottom layer along a direction perpendicular to the substrate 1 (etching stops on the substrate 1) to form a plurality of first initial holes K1 spaced apart along the second direction Y; the first initial holes K1 and the second holes K2 are spaced apart along the first direction X;

[0137] Based on the first initial hole K1, the first sacrificial layer 10 is laterally etched to form a first lateral groove V1. The first initial hole K1 and the first lateral groove V1 constitute a first hole. The orthographic projection of the first hole on the first insulating layer 11 onto the substrate 1 falls into the orthographic projection of the first hole on the first sacrificial layer 10 onto the substrate 1.

[0138] A second conductive film and a first dummy layer film are deposited sequentially to form a first capacitor electrode 41 and a first dummy layer 9. The second conductive film covers the inner wall of the first initial hole K1 and the inner wall of the first transverse groove V1, and the first dummy layer film fills the first initial hole K1 and the first transverse groove V1.

[0139] The first capacitor electrode 41 and the first dummy layer 9 in the first initial hole K1 are removed by etching, while the first capacitor electrode 41 and the first dummy layer 9 in the first transverse groove V1 are retained. Figure 3A , Figure 3B and Figure 3C As shown. Among them, Figure 3A A cross-sectional view along the AA' direction after the formation of the first capacitor electrode 41 is provided in some embodiments. Figure 3B A cross-sectional view along the CC' direction provided in some embodiments after the formation of the first capacitor electrode 41. Figure 3C A cross-sectional view along the FF' direction after the formation of the first capacitor electrode 41 is provided for some embodiments.

[0140] In some embodiments, the first dummy layer film may be a film layer such as polysilicon and having an etching selectivity ratio with the first insulating film and the first sacrificial layer film.

[0141] In some embodiments, the first initial hole K1 along a cross section parallel to the substrate 1 can be circular, square, or the like.

[0142] 3) Form the first trench T1;

[0143] A second dummy layer film is deposited to form a second dummy layer 8 that fills the first initial hole K1;

[0144] The second dummy layer film is wet-etched to remove a portion of the second dummy layer film at the top of the first initial hole K1, and a third insulating film is deposited. The second insulating layer 12 is then smoothed and removed to form a third insulating layer 13. The third insulating layer 13 is flush with the topmost first sacrificial layer 10. The third insulating layer 13 forms the top cover of the first initial hole K1, covering the second dummy layer 8. That is, the second dummy layer 8 is covered by the third insulating layer 13 and is not connected to the subsequently formed first hard mask layer 7.

[0145] A first hard mask layer thin film is deposited to form a first hard mask layer 7 covering the bit line 30, the third insulating layer 13, and the first sacrificial layer 10; the first hard mask layer 7 serves as the hard mask layer for subsequent etching.

[0146] The stacked structure is etched along a direction perpendicular to the substrate 1 to form a plurality of first trenches T1 that penetrate the stacked structure; the first trenches T1 extend along a second direction Y, and adjacent first trenches T1 define a group of memory cells, each group of memory cells including two columns of memory cells.

[0147] The first insulating layer 11 is removed by lateral etching based on the first trench T1, such as Figure 4A , Figure 4B and Figure 4C As shown. Among them, Figure 4A A cross-sectional view along the AA' direction after the formation of the first trench T1, provided in some embodiments. Figure 4B A cross-sectional view along the CC' direction after the formation of the first trench T1, provided in some embodiments. Figure 4C A cross-sectional view along the FF' direction after the formation of the first trench T1 is provided for some embodiments.

[0148] In some embodiments, the second dummy layer film and the first hard mask layer film may be polycrystalline silicon, etc.

[0149] 4) Formation of a second sacrificial layer 61;

[0150] A second sacrificial layer film is deposited, which fills the region between adjacent first sacrificial layers 10. The second sacrificial layer film is then etched laterally, leaving the second sacrificial layer film between adjacent bit lines 30 along the second direction Y, forming a second sacrificial layer 61. The second sacrificial layer 61 can provide support after the first sacrificial layer 10 is subsequently etched.

[0151] A fourth insulating film is deposited, which fills the area between adjacent first sacrificial layers 10 and the first trench T1. The fourth insulating film in the first trench T1 is etched away to expose the sidewall of the first sacrificial layer 10 facing the first trench T1, forming a fourth insulating layer 14.

[0152] Based on the first trench T1, the first sacrificial layer 10 is removed by lateral etching, such as Figure 5A , Figure 5B , Figure 5C and Figure 5D As shown. Among them, Figure 5A A cross-sectional view along the AA' direction after the formation of the second sacrificial layer 61, provided in some embodiments. Figure 5B A cross-sectional view along the CC' direction after the formation of the second sacrificial layer 61, provided in some embodiments. Figure 5C A cross-sectional view along the DD' direction after the formation of the second sacrificial layer 61, provided in some embodiments. Figure 5D A cross-sectional view along the FF' direction after the formation of the second sacrificial layer 61, provided for some embodiments.

[0153] In some embodiments, the second sacrificial layer film may be a film layer with an etching selectivity ratio to the first sacrificial layer film and the first insulating film, such as aluminum oxide. The materials of the subsequent third, fourth, and fifth sacrificial layer films are similar and will not be described in detail.

[0154] 5) Forming semiconductor layer 23, gate insulating layer 24 and word line 40;

[0155] A third sacrificial layer film is deposited, which fills the area between adjacent fourth insulating layers 14. The third sacrificial layer film is then etched laterally, leaving the third sacrificial layer film between adjacent bit lines 30 along the second direction Y, to form a third sacrificial layer 62.

[0156] A semiconductor thin film, a gate insulating film, and a third conductive film are sequentially deposited. The semiconductor thin film, gate insulating film, and third conductive film in the first trench T1 are etched away. The semiconductor thin film, gate insulating film, and third conductive film are etched laterally based on the first trench T1. The semiconductor thin film, gate insulating film, and third conductive film between adjacent first initial holes K1 along the second direction Y are removed. The semiconductor thin film, gate insulating film, and third conductive film covering the side of the first capacitor electrode 41 facing the first trench T1 are removed, while the semiconductor thin film, gate insulating film, and third conductive film covering the side of the first capacitor electrode 41 facing the bit line are retained, forming a semiconductor layer 23, a gate insulating layer 24, and a word line 40. Figure 6A , Figure 6B , Figure 6C and Figure 6D As shown. Among them, Figure 6A A cross-sectional view along the AA' direction provided for some embodiments after the formation of semiconductor layer 23, gate insulating layer 24 and word line 40. Figure 6B A cross-sectional view along the CC' direction provided for some embodiments after the formation of semiconductor layer 23, gate insulating layer 24 and word line 40. Figure 6CA cross-sectional view along the DD' direction provided for some embodiments after the formation of semiconductor layer 23, gate insulating layer 24 and word line 40. Figure 6D This is a cross-sectional view along the EE' direction after the formation of the semiconductor layer 23, gate insulating layer 24, and word line 40 in some embodiments. It can be seen that the semiconductor layer 23 covers the first capacitor electrode 41 facing the bit line 30. At this time, the semiconductor layers 23 of the transistors in the same column are interconnected. The etching amounts of the semiconductor thin film, gate insulating film, and third conductive film can be set as needed.

[0157] In some embodiments, the material of the semiconductor thin film may be silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or it may be a wide band gap material, such as a metal oxide material with a band gap of greater than 1.65 eV.

[0158] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0159] In some embodiments, the material of the metal oxide semiconductor layer or channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), and indium tungsten oxide (InWO4). Materials such as IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) can be used. As long as the leakage current of the transistor meets the requirements, it is acceptable. The specific requirements can be adjusted according to the actual situation.

[0160] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0161] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0162] In some embodiments, the material of the gate insulating layer 24 may comprise one or more high-K dielectric materials. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0163] 6) Form the second dielectric layer 432 and the second sub-electrode 422;

[0164] A fourth sacrificial layer film is deposited, which fills the area between adjacent fourth insulating layers 14; the fourth sacrificial layer film is laterally etched to retain a fourth sacrificial layer film of a preset width to form a fourth sacrificial layer 63. The fourth sacrificial layer 63 is distributed on the side of the word line 40 away from the bit line 30 and covers the area of ​​the word line 40 not covered by the gate insulating layer 24.

[0165] A second dielectric film and a fourth conductive film are deposited sequentially, and the second dielectric film and the fourth conductive film in the first trench T1 are etched away to form a second dielectric layer 432 and a second sub-electrode 422; at this time, a fourth sacrificial layer 63 separates the second sub-electrode 422 and the word line 40; as shown Figure 7A , Figure 7B , Figure 7C As shown. Among them, Figure 7A A cross-sectional view along the AA' direction provided for some embodiments after the formation of the second dielectric layer 432 and the second sub-electrode 422. Figure 7B A cross-sectional view along the CC' direction after the formation of the second dielectric layer 432 and the second sub-electrode 422, provided for some embodiments. Figure 7C A cross-sectional view along the EE' direction after the formation of the second dielectric layer 432 and the second sub-electrode 422, provided for some embodiments.

[0166] In some embodiments, the second dielectric film may be a high-K dielectric material. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials. The subsequent description of the first dielectric film is similar to that of the second dielectric film and will not be repeated.

[0167] 7) Form connecting electrode 424;

[0168] Based on the first trench T1, the fourth insulating layer 14 is etched laterally until the fourth sacrificial layer 63 is exposed on the side facing the substrate 1.

[0169] A fifth sacrificial layer film is deposited, which fills the area where the fourth insulating layer 14 is etched away; the fifth sacrificial layer film is laterally etched to retain a fifth sacrificial layer film of a predetermined width, forming a fifth sacrificial layer 64; the fifth sacrificial layer 64 and the fourth sacrificial layer 63 are connected to form a film layer extending in a direction perpendicular to the substrate 1.

[0170] A fifth insulating film is deposited, and the fifth insulating film in the first trench T1 is etched away to expose the second sub-electrode 422 facing the first trench T1, forming a fifth insulating layer 15; the fifth insulating layer 15 fills the area where the etched fourth insulating layer 14 is located, that is, a fifth sacrificial layer 64 is formed in a part of the area where the fourth insulating layer 14 is etched away, and a fifth insulating layer 15 is formed in another part of the area.

[0171] A fifth conductive thin film is deposited to form a connecting electrode 424. The connecting electrode 424 fills the first trench T1 and is connected to the second sub-electrode 422. The second sub-electrode 422 of a capacitor located at the same position in a different layer is also connected to the connecting electrode. Figure 8A , Figure 8B , Figure 8C As shown. Among them, Figure 8A A cross-sectional view along the AA' direction after forming the connecting electrode 424, provided for some embodiments. Figure 8B A cross-sectional view along the CC' direction after forming the connecting electrode 424, provided for some embodiments. Figure 8C A cross-sectional view along the EE' direction after forming the connecting electrode 424, provided for some embodiments.

[0172] 8) Disconnect the semiconductor layers 23 of different transistors in the same column;

[0173] Wet etching removes the second sacrificial layer 61 and the third sacrificial layer 62, as well as the fourth sacrificial layer 63 and the fifth sacrificial layer 64, forming a plurality of third holes K3 and a plurality of fourth holes K4; the third holes K3 are the areas formed after the second sacrificial layer 61 and the third sacrificial layer 62 are etched, and the fourth holes K4 are the areas formed after the fifth sacrificial layer 64 and the fourth sacrificial layer 63 are etched.

[0174] Based on the third hole K3 and the fourth hole K4, the semiconductor layer 23 is wet-etched to disconnect the semiconductor layers 23 of transistors in the same column of the same layer; the semiconductor layer 23 exposed in the third hole K3 can be etched away, and the portion of the semiconductor layer 23 located in the second hole K2 adjacent to the semiconductor layer 23 located in the third hole K3 can be etched away, and the portion of the semiconductor layer 23 located in the first hole can be etched away; such as Figure 9A , Figure 9B , Figure 9C As shown. Among them, Figure 9A A cross-sectional view along the AA' direction after disconnecting the semiconductor layers 23 of different transistors in the same column, as provided in some embodiments. Figure 9B A cross-sectional view along the CC' direction after disconnecting the semiconductor layers 23 of different transistors in the same column, as provided in some embodiments. Figure 9C A cross-sectional view along the EE' direction after disconnecting the semiconductor layer 23 of different transistors in the same column, as provided in some embodiments.

[0175] 9) Formation of isolation layer 6;

[0176] After depositing the isolation layer film, it is polished to form the isolation layer 6. The isolation layer 6 fills the third hole K3, the fourth hole K4, and the area formed after the semiconductor layer 23 is etched in step 8.

[0177] Etching removes the first dummy layer 9, the second dummy layer 8, and the third insulating layer 13 from the first initial hole K1 and the first transverse groove V1;

[0178] Based on the first initial hole K1 and the first lateral groove V1, the isolation layer 6, the fourth insulating layer 14, and the fifth insulating layer 15 are etched laterally to expose the inner wall of the first capacitor electrode 41, the outer wall facing the substrate 1, and the outer wall away from the substrate 1, forming a second lateral groove located between adjacent first capacitor electrodes 41 along a direction perpendicular to the substrate 1; Figure 10A , Figure 10B , Figure 10C As shown. Among them, Figure 10A A cross-sectional view along the AA' direction after the formation of the isolation layer 6, provided in some embodiments. Figure 10B A cross-sectional view along the CC' direction after the formation of the isolation layer 6, provided in some embodiments. Figure 10CThis is a cross-sectional view along the EE' direction after the formation of the isolation layer 6, as provided in some embodiments. In this step, the first capacitor electrode 41 is exposed except for the area in contact with the semiconductor layer 23, thereby increasing the area facing the subsequently formed first sub-electrode 421 and increasing the capacitance of the capacitor. However, the embodiments of this disclosure are not limited to this. For example, the outer wall of the first capacitor electrode 41 facing the substrate 1 and the outer wall of the first capacitor electrode 41 away from the substrate 1 may not be exposed; that is, the first sub-electrode 421 may only be distributed on the inner wall of the first capacitor electrode 41. The isolation layer 6 includes a first isolation layer 601 and a second isolation layer 602.

[0179] In some embodiments, the isolation layer film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2).

[0180] 10) Form the first dielectric layer 431 and the first sub-electrode 421;

[0181] A first dielectric film and a sixth conductive film are deposited sequentially to form a first dielectric layer 431 and a first sub-electrode 421; the first dielectric layer 431 covers the inner wall of the first capacitor electrode 41 and the inner wall of the second lateral groove (including the outer wall of the first capacitor electrode 41 facing the substrate 1 and the outer wall of the first capacitor electrode 41 away from the substrate 1); the first sub-electrode 421 fills the first initial hole K1 and the first lateral groove V1 and the second lateral groove.

[0182] In some embodiments, the first sub-electrode 421 may include a third sub-layer 33 and a fourth sub-layer 34. The third sub-layer 33 may be a film with good adhesion, such as TiN, and the fourth sub-layer 34 may be a conductive material with low resistivity, such as tungsten. The third sub-layer 33 is distributed on the bottom wall and inner sidewall of the first capacitor electrode 41, as well as on the outer sidewall facing the substrate 1 and the outer sidewall facing away from the substrate 1. The fourth sub-layer 34 fills the first initial hole K1, the first lateral groove V1, and the second lateral groove. Figure 11A , Figure 11B , Figure 11C As shown. Among them, Figure 11A A cross-sectional view along the AA' direction provided for some embodiments after the formation of the first dielectric layer 431 and the first sub-electrode 421. Figure 11B A cross-sectional view along the CC' direction provided for some embodiments after the formation of the first dielectric layer 431 and the first sub-electrode 421. Figure 11C A cross-sectional view along the EE' direction after the formation of the first dielectric layer 431 and the first sub-electrode 421, provided for some embodiments. Figure 11A , Figure 11B and Figure 11CIn the first transverse groove V1 and the second transverse groove, the first dielectric layer 431 has already filled the first transverse groove V1 and the second transverse groove, so the first sub-electrode 421 is not distributed in the first transverse groove V1 and the second transverse groove. However, it is not limited to this. When the thickness of the first dielectric layer 431 is small and it does not fill the first transverse groove V1 and the second transverse groove, the first sub-electrode 421 fills the first transverse groove V1 and the second transverse groove. That is, the first sub-electrode 421 fills the area formed by the first initial hole K1, the first transverse groove V1 and the second transverse groove of the first dielectric layer 431.

[0183] The semiconductor device manufacturing method provided in this embodiment only requires photomasks when forming the first initial hole, the second hole, and the first trench. The word line manufacturing does not require photomasks, the required number of photomasks is small, the process is simple, and the cost is low. In addition, the word line manufacturing does not require photomasks, so the device is not affected by the size limitation of the photomask, which can reduce the device size and increase the storage array density. Furthermore, the word line thickness in the formed semiconductor device is small, and the parasitic capacitance between the word line and the bit line is small.

[0184] This disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments, or a semiconductor device formed by the manufacturing method of the semiconductor device described in any of the foregoing embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0185] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Multiple memory cells are stacked along the vertical substrate direction, distributed across different layers; Bit lines extend through the memory cells in different layers along a direction perpendicular to the substrate; Multiple word lines are distributed in different layers. The word lines and the bit lines are distributed along a first direction parallel to the substrate, and the word lines extend along a second direction parallel to the substrate. The first direction and the second direction intersect. The memory cell includes a transistor, the transistor including a semiconductor layer surrounding the word line, the sidewall of the semiconductor layer facing the bit line and perpendicular to the substrate being connected to the bit line, and multiple semiconductor layers of multiple transistors at the same position on different layers being connected to the same bit line.

2. The semiconductor device according to claim 1, characterized in that, The transistor further includes a first electrode, which is disposed on the word line away from the bit line and connected to the sidewall of the semiconductor layer away from the bit line and perpendicular to the substrate. The first electrode forms an annular groove, the annular groove including a bottom wall perpendicular to the substrate and two side walls parallel to the substrate, the bottom wall including an inner bottom wall located within the annular groove and an outer bottom wall located outside the annular groove, and a portion of the semiconductor layer is connected to the outer bottom wall.

3. The semiconductor device according to claim 2, characterized in that, The storage unit also includes a capacitor, and the capacitor and the transistor in the same storage unit are distributed along the first direction; The capacitor includes a first capacitor electrode and a second capacitor electrode; the first electrode is reused as the first capacitor electrode of the capacitor; the second capacitor electrode includes a first sub-electrode, the first capacitor electrode surrounds the first sub-electrode, and a first dielectric layer is disposed between the first capacitor electrode and the first sub-electrode; the first sub-electrode is distributed on the inner wall of the annular groove formed by the first electrode; the first sub-electrodes of the storage cells at the same position in different layers are connected to form an integral structure.

4. The semiconductor device according to claim 3, characterized in that, The sidewall of the annular groove includes an inner sidewall located inside the annular groove and an outer sidewall located outside the annular groove, and the first sub-electrode is also distributed on the outer sidewall of the annular groove.

5. The semiconductor device according to claim 3, characterized in that, The outer bottom wall of the annular groove includes a first region and a second region spaced apart along the circumferential direction of the annular groove, and two intermediate regions spaced apart from the first region, respectively disposed on both sides of the first region. The first region is located on the side of the annular groove facing the bit line, the word line is distributed on the first region, and the semiconductor layer is connected to a portion of the first region. The second capacitor electrode also includes a second sub-electrode, which is distributed on the second region of the outer bottom wall of the annular groove.

6. The semiconductor device according to claim 5, characterized in that, A second dielectric layer is disposed between the first capacitor electrode and the second sub-electrode, and the second dielectric layers of capacitors at the same position in different layers are spaced apart along a direction perpendicular to the substrate.

7. The semiconductor device according to claim 5, characterized in that, The memory cells in the same layer are arrayed along the first direction and the second direction, and the second sub-electrodes of multiple memory cells in the same layer and column distributed along the second direction are connected to form an integrated structure.

8. The semiconductor device according to claim 5, characterized in that, The integrated structure formed by connecting the second sub-electrodes, the two adjacent first capacitor electrodes along the second direction, and the region defined by the word line adjacent to the first electrode are filled with a first isolation layer, and the first isolation layers at the same position in different layers are connected to form an integrated structure extending along the direction perpendicular to the substrate. The first isolation layer is connected to the middle region of the outer bottom wall of the two adjacent first capacitor electrodes along the second direction.

9. The semiconductor device according to claim 8, characterized in that, The first isolation layer is also distributed in the area of ​​the first region that is not connected to the semiconductor layer.

10. The semiconductor device according to claim 5, characterized in that, The semiconductor device further includes: An insulating layer and a conductive layer are alternately distributed along a direction perpendicular to the substrate; A first hole penetrating the insulating layer and the conductive layer; the first hole includes a first sub-hole located in the insulating layer and a second sub-hole located in the conductive layer, the second sub-hole having a groove extending in a direction parallel to the substrate relative to the first sub-hole; The first electrode is distributed on the inner wall of the groove, and the first electrode, the first dielectric layer, and the first sub-electrode are distributed sequentially from the outside to the inside in the first hole.

11. The semiconductor device according to claim 7, characterized in that, The semiconductor layers of a plurality of memory cells in the same column distributed along the second direction are spaced apart along the second direction and surround the same word line.

12. The semiconductor device according to claim 11, characterized in that, In each pair of columns, two adjacent memory cells along the first direction are connected to the same bit line.

13. The semiconductor device according to claim 11, characterized in that, Multiple semiconductor layers of memory cells in the same column distributed along the second direction are respectively connected to different bit lines distributed at intervals along the second direction.

14. The semiconductor device according to claim 13, characterized in that, A second isolation layer is disposed between different bit lines spaced apart along the second direction, penetrating the memory cells of different layers and extending along a direction perpendicular to the substrate.

15. A method for manufacturing a semiconductor device, characterized in that, include: A stacked structure comprising alternating first insulating layers and first sacrificial layers is formed on a substrate; A plurality of second holes are formed that are spaced apart along a second direction through the stacked structure perpendicular to the substrate direction, and a plurality of bit lines are filled in the plurality of second holes; A plurality of first holes are formed that penetrate the stacked structure along a second direction perpendicular to the substrate, and the first holes and second holes are spaced apart along a first direction. Based on the first holes, the first sacrificial layer is etched along a direction parallel to the substrate to form a first lateral groove. A first electrode is formed distributed on the inner wall of the first lateral groove. The first direction and the second direction intersect. A first groove is formed on the side of the first hole opposite to the second hole, penetrating the stacked structure and extending along the second direction; Based on the first trench, word lines extending in a second direction are formed between adjacent fourth insulating layers, between a plurality of first holes and a plurality of second holes, and a plurality of semiconductor layers spaced apart in the second direction around the word lines, the semiconductor layers respectively connecting the first electrode and the bit lines.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that, Based on the first trench, word lines extending in a second direction are formed between adjacent fourth insulating layers, between a plurality of first holes and a plurality of second holes, and a plurality of semiconductor layers spaced apart in the second direction surrounding the word lines include: Based on the first trench etching to remove the first insulating layer, the first insulating layer is replaced by a fourth insulating layer and a second sacrificial layer. The second sacrificial layer is located between adjacent first sacrificial layers and between adjacent bit lines along the second direction, and is connected to adjacent bit lines along the second direction. Based on the removal of the first sacrificial layer by the first trench etching, a third sacrificial layer connected to the second sacrificial layer is formed between adjacent second sacrificial layers located in the direction perpendicular to the substrate and between adjacent bit lines located in the second direction. A semiconductor thin film, a gate insulating film, and a first conductive film are sequentially deposited. The semiconductor thin film, gate insulating film, and first conductive film covering the side of the first electrode away from the bit line and the side of the first electrode facing the first electrode adjacent to the second direction are etched away. The semiconductor thin film, gate insulating film, and first conductive film covering the side of the first electrode facing the bit line are retained to form multiple semiconductor layers and multiple gate insulating layers of multiple transistors, as well as word lines, wherein the gate insulating layers surround the word lines and the semiconductor layers surround the gate insulating layers. A fourth sacrificial layer is formed between adjacent fourth insulating layers to connect word lines and adjacent first electrodes along the second direction; a fifth sacrificial layer connected to the fourth sacrificial layers is formed between adjacent fourth sacrificial layers along a direction perpendicular to the substrate. The second and third sacrificial layers are etched away to form a third hole; the fourth and fifth sacrificial layers are etched away to form a fourth hole; the plurality of semiconductor layers are etched along a direction parallel to the substrate based on the third and fourth holes, thereby disconnecting the plurality of semiconductor layers.

17. The method for manufacturing a semiconductor device according to claim 16, characterized in that, The method further includes: exposing the first hole and the first transverse groove, and forming a first sub-electrode within the first hole and the first transverse groove.

18. The method for manufacturing a semiconductor device according to claim 17, characterized in that, Before forming the first sub-electrode in the first hole and the first transverse groove, the method further includes: exposing the side of the first electrode away from the substrate and the side facing the substrate to form a second transverse groove; Forming a first sub-electrode within the first hole and the first transverse groove includes: forming a first sub-electrode within the first hole, the first transverse groove, and the second transverse groove.

19. The method for manufacturing a semiconductor device according to claim 16, characterized in that, After forming a fourth sacrificial layer connecting word lines and adjacent first electrodes along the second direction between adjacent fourth insulating layers, and before forming a fifth sacrificial layer connected to the fourth sacrificial layers between adjacent fourth sacrificial layers along a direction perpendicular to the substrate, the method further includes: A second sub-electrode is formed on the side of the first electrode opposite to the bit line; After forming a fifth sacrificial layer connected to the fourth sacrificial layer between adjacent fourth sacrificial layers along a direction perpendicular to the substrate, the method further includes: A connecting electrode is formed that fills the first trench and is connected to the second sub-electrode.

20. An electronic device, characterized in that, This includes the semiconductor device as described in any one of claims 1 to 14, or the semiconductor device formed by the manufacturing method of the semiconductor device as described in any one of claims 15 to 19.

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