Local layer removing method for chip

Abstract

The invention provides a chip local layer removing method. The method comprises the steps that after a chip is uncovered, a non-conductive layer is adjacent to the lower portion of a surface metal layer; filling a test pad region corresponding to the surface metal layer with a protective layer, and exposing a to-be-removed region; removing the surface metal layer of the to-be-removed area, and exposing the lower structure layer below the surface metal layer of the to-be-removed area; and removing the protective layer, and positioning the electrical fault point of the chip by using the test bonding pad. According to the method, the surface of the uncovered chip is filled with the hot melt wax to protect the test bonding pad, subsequent chip cleaning is facilitated, and the electrical fault point positioning effect is improved; meanwhile, local layer removal is carried out on the chip without a conducting layer under the surface metal layer, so that the fault point can still be accurately positioned under the condition that hot spot analysis of the surface metal layer is difficult, and failure analysis of a special chip is facilitated; in addition, a fault area is obtained through an electrical performance test before filling of the protective layer, and the efficiency and accuracy of subsequent electrical fault point positioning are improved; and finally, the passivation layer in the fault area is thinned and then removed, so that the influence of the passivation layer and reactive ion etching on fault point positioning is avoided, and the fault point positioning effectiveness is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and in particular relates to a method for partial chip delamination. Background Technology

[0002] In failure analysis (FA), delayering technology is not only a core means of locating fatal defects such as short circuits, leakage, and burnout, but also the only verifiable bridge between electrical failures and physical defects. As advanced processes evolve from 28nm to 7nm, 5nm, and even 3nm nodes, the number of metal stacks has exceeded 15 layers, and the thickness of a single layer has shrunk to below 30nm. Simultaneously, ultra-low dielectric constant dielectrics, air-gap structures, and novel metal interconnect materials such as Co and Ru have been introduced. Traditional top-down wet or dry layer-by-layer peeling processes for failure analysis are approaching physical limits in terms of material selection ratios, lateral uniformity, and endpoint control, making it difficult to simultaneously meet the triple requirements of high-fidelity morphology, high conductivity, and high spatial resolution.

[0003] Meanwhile, for optimization requirements such as anti-EM (Electro-Migration) and Rds(on), the top metal thickness of some special architecture power or high-voltage MOS chips is designed to be 3-5 times or greater than 3µm of conventional logic, and the surface is covered by Cu pillars or Al bond pads. At the same time, process iteration has eliminated the TiN / Ti composite layer, which is commonly used as a "conductive buffer layer" below the traditional 45nm node. This leads to: 1) If the existing hot spot analysis method is used directly, the laser pulse energy decays rapidly in the thick metal, which cannot excite sufficient carrier density. The hot spot signal is drowned out by background noise, the spatial resolution is greatly reduced, and the failure location function is lost; 2) If the traditional RIE and wet chemical delamination route is used, although the thick metal can be peeled off, the exposed ULK dielectric or n-ESL (non-conductive Etch Stop) is exposed. The high surface resistivity of the non-conductive stop layer makes it impossible to provide the necessary conductive circuit for nano-probes or e-beam absorb current (EBAC); 3) Due to the lack of a TiN conductive relay layer, a Schottky contact will form between the conventional FIB-Pt deposition pad and the underlying metal via, with a contact resistance >1MΩ. This leads to distortion of the IV curve obtained during failure analysis measurement, loss of failure characteristic signals, and forced interruption of the analysis process. The above-mentioned "thick metal shielding" and "conductive break" together constitute the break in the traditional delamination-electrical verification link, which is no longer able to meet the needs of automotive, industrial, and high-reliability packaging fields for ppm-level failure root cause tracing.

[0004] Therefore, there is an urgent need for a method to perform failure analysis on chips with a thick surface metal layer and no underlying conductive layer.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating the understanding of those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because these solutions have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art, the purpose of this invention is to provide a chip local delamination method to solve the problem that chips with thick surface metal layers and no underlying conductive layer are difficult to effectively perform failure analysis.

[0007] To achieve the above objectives, the present invention provides a method for partial chip delamination, the method comprising:

[0008] Provided is a chip that has been opened, wherein the non-conductive structural layer is located below the surface metal layer to be partially removed after the chip has been opened;

[0009] A protective layer is filled at least in the test pad area corresponding to the surface of the surface metal layer to expose the surface metal layer of the area to be removed.

[0010] Remove the surface metal layer of the area to be removed to expose the underlying structural layer beneath the surface metal layer.

[0011] Remove the protective layer, clean and dry the chip surface to expose the test pads in the test pad area;

[0012] Electrical fault points in the chip are located by testing the test pads in the test pad area.

[0013] Optionally, before filling the protective layer, an electrical performance test is performed to locate the fault area where the chip has an electrical fault; when filling the protective layer, only the fault area is exposed.

[0014] Optionally, when a passivation layer exists on the surface of the metal layer of the chip that has been opened, and the passivation layer is located in the corresponding area above the fault area, the passivation layer is removed before removing the surface metal layer or before filling the protective layer.

[0015] Optionally, when removing the passivation layer, the passivation layer is first thinned by reactive ion etching, and then completely removed by wet etching.

[0016] Alternatively, the passivation layer thickness can be reduced by half using reactive ion etching.

[0017] Optionally, the protective layer is a hot melt wax; when filling the protective layer, the temperature is heated to above 180°C and below 300°C to melt the protective layer on the chip surface; when the protective layer is evenly covered on the chip surface, it is cooled to room temperature until the protective layer solidifies and takes shape; the protective layer in the area to be removed is removed to expose the surface metal layer of the area to be removed.

[0018] Alternatively, the chip after being filled with the protective layer can be placed in an acid- and alkali-resistant beaker for chemical removal.

[0019] Optionally, the chemical solution in the acid and alkali resistant beaker may be either an acidic solution or an alkaline solution.

[0020] Optionally, the alkaline solution includes either ammonia or sodium hydroxide, and the acidic solution includes either hydrochloric acid or phosphoric acid.

[0021] Alternatively, the chip can be placed in an acid- or alkali-resistant beaker for 3 to 5 minutes.

[0022] As described above, the chip partial delamination method of the present invention has the following beneficial effects:

[0023] This invention uses hot melt wax to fill the surface of the opened chip, which can protect the test pads and facilitate subsequent cleaning of the chip surface, thus improving the effectiveness of locating electrical fault points.

[0024] This invention removes the conductive layer from the chip below the surface metal layer in a partial manner, avoiding the lack of electrical connections for fault location after the entire surface metal layer is removed. This allows for accurate fault location even when hotspot analysis is difficult to perform directly on the surface metal layer, which is beneficial for failure analysis of special chips.

[0025] This invention improves the efficiency and accuracy of subsequent electrical fault location by performing electrical performance tests before the protective layer is filled to obtain the fault area.

[0026] This invention improves the effectiveness of locating electrical fault points by thinning and removing the passivation layer in advance within the fault area, thus avoiding the passivation layer's presence from affecting the location of electrical fault points. At the same time, it avoids the reactive ion etching process from affecting the internal structure of the chip during the passivation layer removal process. Attached Figure Description

[0027] Figure 1 The diagram shown is a side view of the structure of the chip with the cap opened, provided in step 1 of the chip partial de-capping method of the present invention.

[0028] Figure 2 The diagram shown is a top view of the structure of the chip with the cap opened, provided in step 1 of the chip partial de-capping method of the present invention.

[0029] Figure 3 The diagram shows a top view of the structure of the chip partial de-layering method of the present invention, which is a step 3 of removing the surface metal layer of the area to be removed, revealing the underlying structural layer beneath the surface metal layer of the area to be removed.

[0030] Explanation of icon numbers

[0031] 1. Chip; 11. Substrate; 12. Gate oxide; 13. Top metal layer; 14. Underlying structural layer;

[0032] 2. Test pad area; 3. Area to be removed. Detailed Implementation

[0033] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0034] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0035] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the accompanying drawings for devices in use or operation.

[0036] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0037] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex. The quantity range given in the present invention includes the two boundary values ​​of the quantity range by default unless otherwise specified.

[0038] In failure analysis (FA), delayering plays a crucial role. It not only helps locate critical issues leading to fatal defects such as short circuits, leakage, and burnout, but it also serves as the only verifiable bridge connecting electrical failures and physical defects. However, it presents unique challenges when dealing with certain specialized power or high-voltage MOS chips. To optimize electromagnetic migration resistance and reduce on-resistance, the top metal layer of these chips is designed to be 3 to 5 times thicker than that of conventional logic chips, sometimes exceeding 3 micrometers. Furthermore, the surface of these chips is typically covered with copper pillars or aluminum bond pads. With continuous process iterations, the traditional use of TiN / Ti composite layers as conductive buffer layers below 45 nanometer nodes has been abandoned. This leads to a problem: if existing hotspot analysis methods are directly applied, the laser pulse energy attenuates rapidly within these thick metal layers, failing to excite sufficient carrier density. This causes the hotspot signal to be overwhelmed by background noise, significantly reducing spatial resolution and rendering the failure localization function ineffective. While traditional reactive ion etching (RIE) and wet chemical delamination methods can remove thick metal layers, the exposed surface exhibits extremely high resistivity due to the lack of a TiN / Ti composite layer. This prevents the provision of a necessary conductive path for nanoprobes or electron beam current absorption. Furthermore, the absence of a TiN conductive relay layer leads to high-resistivity Schottky contacts between the conventional focused ion beam (FIB)-platinum (Pt) deposition pads and the underlying metal vias. This distortion in the current-voltage (IV) curves during failure analysis results in the loss of failure characteristic signals, hindering accurate failure analysis. Therefore, for special MOS chips with thick surface metal layers and no underlying TiN / Ti composite layer as a conductive buffer, traditional delamination techniques for electrical verification are no longer applicable. This poses a significant challenge to the automotive, industrial, and high-reliability packaging sectors' need for root cause analysis of ppm-level failure rates.

[0039] To address the above problems, this invention provides a method for partial chip delamination, which includes:

[0040] Step 1: Provide a chip that has been decapped, wherein the non-conductive structural layer is located below the surface metal layer to be partially removed after the chip has been decapped.

[0041] Step 2: Fill the surface of the surface metal layer with a protective layer at least corresponding to the test pad area to expose the surface metal layer of the area to be removed;

[0042] Step 3: Remove the surface metal layer of the area to be removed to expose the underlying structural layer beneath the surface metal layer.

[0043] Step 4: Remove the protective layer, clean and dry the chip surface to expose the test pads in the test pad area;

[0044] Step 5: Locate electrical fault points in the chip using the test pads in the test pad area.

[0045] The chip partial delamination method of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above order does not strictly represent the order of the chip partial delamination method protected by the present invention, and those skilled in the art can make changes according to the actual chip partial delamination steps.

[0046] First, proceed to step 1, as follows: Figures 1-2 As shown, where Figure 1 This is a side view of chip 1. Figure 2 The image shows a top view of chip 1 with the cap removed, and the non-conductive structural layer below the surface metal layer 13 to be partially removed after the chip 1 is decapped.

[0047] Specifically, the technical problem of being unable to locate electrical fault points by means of probe electrical connection arises because the adjacent structural layer below the surface metal layer 13 is a non-conductive layer. Therefore, the unique effect of solving this technical problem can only be demonstrated when the chip 1 used in this invention has a non-conductive structural layer below the surface metal layer 13. However, the solution of this invention can also be applied to the chip 1 with a non-conductive structural layer below the surface metal layer 13, and both are within the protection scope of this invention.

[0048] In one embodiment, the surface metal layer 13 can be any metal layer that needs to be subjected to failure analysis, and it is not necessarily the outermost metal layer of the entire chip 1. As long as it is an adjacent non-conductive layer below it and probes need to be set on the test pads of that metal layer for failure analysis, it can be used as the surface metal layer 13 described herein. Specifically, when the surface metal layer 13 that needs to be subjected to failure analysis is not the outermost metal layer of the entire chip 1, it is necessary to first use a conventional delamination technique to expose the surface metal layer 13 before proceeding to step 2 of this invention.

[0049] In one embodiment, the chip 1 is a MOS (Metal-Oxide-Semiconductor) chip 1.

[0050] Specifically, the chip type 1 for solving the failure analysis problem in this invention mainly occurs in the application of MOS chip 1, but it can also be applied to other types of chip 1 that cannot be analyzed using hotspot analysis and traditional delamination techniques, all of which are within the protection scope of this invention.

[0051] In one embodiment, chip 1 is encapsulated in plastic or ceramic. Specifically, chip 1 can also be encapsulated in other types of packages, all of which are within the scope of protection of this invention.

[0052] In one embodiment, the surface metal layer 13 is an aluminum layer. Specifically, it can also be other metal layers, all of which are within the scope of protection of this invention.

[0053] In one embodiment, titanium nitride (TiN) is not disposed beneath the surface metal layer 13. Specifically, other metal layers that are eliminated during process iterations can also be used, all of which are within the scope of protection of this invention.

[0054] In one embodiment, such as Figure 1 As shown, the chip 1 includes a substrate 11, a gate oxide 12, and a surface metal layer 13 from bottom to top.

[0055] In one embodiment, the electrical performance of chip 1 is tested before and after the chip is opened to determine whether the electrical performance of chip 1 changes before and after the chip is opened; if no change is made, the protective layer can be filled; if a change is made, the specific information of the change in electrical performance is recorded and comprehensively evaluated with the information obtained after locating the electrical fault point.

[0056] This invention compares the electrical performance of chip 1 before and after capping to confirm that capping does not cause additional damage to chip 1, thereby avoiding the invalidity of failure analysis results due to the capping process causing the fault points obtained. Specifically, when multiple chips 1 with the same problem need to be located for electrical fault points, if capping affects the electrical performance, other chips 1 can be replaced to remove the chips 1 whose electrical fault point location results are affected; when only a single chip 1 needs to be located for electrical fault points, if capping affects the electrical performance, the final electrical fault point location result needs to be judged by combining the electrical performance before and after capping to reduce the impact of capping damage on the validity of the electrical fault point location result.

[0057] Then, in step 2, a protective layer is filled on at least the test pad area 2 corresponding to the surface of the surface metal layer 13, exposing the surface metal layer of the area to be removed 3.

[0058] This invention utilizes a protective layer filling technique, specifically targeting the test pad region 2. This method involves precisely applying a protective layer to at least the area corresponding to the test pads, ensuring that the protective layer completely covers the surface metal layer 13 of the test pads where electrical fault location is required in subsequent processes. This treatment effectively prevents the test pads from losing their original conductive probe points after the surface metal layer 13 is removed, thus avoiding the problem of being unable to perform probe detection analysis. This technique significantly improves the adaptability to failure analysis of chips with special chip 1 structures. Furthermore, the easy-to-remove nature of the protective layer makes cleaning the chip 1 surface after electrical fault location is more convenient and faster. This convenience not only simplifies subsequent processing but also helps improve the accuracy and efficiency of electrical fault location.

[0059] In one embodiment, before filling the protective layer, an electrical performance test is performed to locate the fault area where the chip 1 has an electrical fault; when filling the protective layer, only the fault area is exposed.

[0060] This invention performs an electrical performance test before filling the protective layer. This effectively identifies fault areas, narrowing down the scope for subsequent electrical fault location. This process not only improves the efficiency of subsequent electrical fault location but also significantly enhances its accuracy. This method ensures a clear understanding of potential fault points before protective layer filling, avoiding additional problems that may arise during the filling process and ensuring a smooth production flow and product quality.

[0061] In one embodiment, when a passivation layer exists on the surface of the top metal layer 13 of the chip 1 that has been opened, and the passivation layer is located in the corresponding area above the fault area, the passivation layer is removed before removing the top metal layer 13 or before filling the protective layer.

[0062] Specifically, a passivation layer is typically applied to the edge of chip 1 for protection. Therefore, when the fault area is located at the edge of chip 1, the passivation layer usually needs to be removed.

[0063] In one embodiment, when removing the passivation layer, the passivation layer is first thinned by reactive ion etching (RIE) and then completely removed by wet etching.

[0064] This invention thins and removes the passivation layer in the fault area in advance, enabling reactive ion etching to precisely remove the passivation layer without damaging the surface metal layer 13. At the same time, wet etching makes the surface after reactive ion etching smooth and crystallized, and improves the overall passivation layer removal rate. It also avoids the reactive ion etching affecting the internal structure of the chip 1 during the passivation layer removal process, thereby improving the effectiveness of the judgment of electrical fault location.

[0065] In one embodiment, the remaining passivation layer is removed using a wet etching process (B). Alternatively, other suitable reagents can be used to wet etch the passivation layer.

[0066] In one embodiment, the passivation layer thickness is reduced by half using a reactive ion etching method.

[0067] Preferably, the protective layer is hot melt wax; when filling the protective layer, the heating temperature is raised to above 180°C and below 300°C to melt the protective layer on the surface of chip 1; when the protective layer is uniformly covered on the surface of chip 1, it is cooled to room temperature until the protective layer solidifies and takes shape; the protective layer of the area to be removed 3 is removed to expose the surface metal layer of the area to be removed 3.

[0068] By setting the protective layer as hot melt wax and setting the temperature range of the hot melt wax, the present invention can achieve uniform distribution of the protective layer on the surface of chip 1, avoid affecting the internal structure of chip 1, and at the same time, after cooling, the hot melt wax can be tightly adhered to the surface of chip 1, further improving the protective effect of the hot melt wax on the test pad area 2.

[0069] Specifically, "normal temperature cooling" generally refers to the temperature under normal pressure where the heat is dissipated naturally without the need for additional temperature control equipment, and can be 25℃±5℃.

[0070] Next, proceed to step 3, as follows: Figure 3 As shown, the surface metal layer 13 of the region to be removed is removed, revealing the underlying structural layer 14 beneath the surface metal layer 13 of the region to be removed.

[0071] In one embodiment, the underlying structural layer 14 includes a substrate 11 and a gate oxide 12.

[0072] In one embodiment, the chip 1, after being filled with a protective layer, is placed in an acid- and alkali-resistant beaker for chemical removal.

[0073] In one embodiment, the chemical solution in the acid- and alkali-resistant beaker includes either an acidic solution or an alkaline solution.

[0074] Specifically, other suitable solutions can also be selected to remove the surface metal layer 13. As long as the solution does not affect the chip 1 and the protective layer, it is within the protection scope of this invention.

[0075] In one embodiment, the alkaline solution includes either ammonia or sodium hydroxide, and the acidic solution includes either hydrochloric acid or phosphoric acid.

[0076] In one embodiment, chip 1 is placed in an acid- and alkali-resistant beaker for 3 to 5 minutes.

[0077] This invention improves overall processing efficiency by setting the time range for placing chip 1 in the beaker, while ensuring the removal of all exposed surface metal layers 13.

[0078] Then, proceed to step 4 to remove the protective layer, clean and dry the surface of chip 1 to expose the test pads in test pad area 2.

[0079] This invention cleans and dries the chip 1 after the protective layer is removed, thereby obtaining a clean test pad and ensuring that the accuracy of the electrical fault location results is not affected.

[0080] Finally, step 5 is performed to locate the electrical fault point of the chip 1 using the test pads in the test pad area 2.

[0081] Specifically, such as Figure 3 As shown in the figure, region A is the area where a fixed test pad is located, and region B is the area on the surface of chip 1 where the surface metal layer 13 has not been removed. Either region can be used as another test pad. The test pad region 2 includes region A and region B. By electrically connecting the two test pads in region A and region B, the probe can perform failure analysis operations to locate electrical fault points on chip 1.

[0082] In summary, the chip partial delamination method of the present invention can protect the test pads by filling the surface of the decapped chip with hot melt wax, and facilitate subsequent cleaning of the chip surface, thus improving the accuracy of electrical fault location. Simultaneously, by partially delaminating the chip without a conductive layer beneath the surface metal layer, it avoids the situation where there are no electrical connections for fault location after removing the entire surface metal layer, enabling accurate fault location even when hotspot analysis is difficult directly on the surface metal layer, which is beneficial for failure analysis of special chips. Furthermore, by performing electrical performance testing to identify the fault area before filling the protective layer, the efficiency and accuracy of subsequent electrical fault location are improved. Finally, by thinning and removing the passivation layer in advance within the fault area, the presence of the passivation layer avoids affecting the electrical fault location in the fault area, and also avoids the reactive ion etching process during passivation layer removal affecting the internal structure of the chip, thus improving the effectiveness of electrical fault location judgment.

[0083] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0084] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for partial chip delamination, characterized in that, The chip local delayer removal method includes: Provided is a chip that has been opened, wherein the non-conductive structural layer is located below the surface metal layer to be partially removed after the chip has been opened; A protective layer is filled at least in the test pad area corresponding to the surface of the surface metal layer to expose the surface metal layer of the area to be removed. Remove the surface metal layer of the area to be removed to expose the underlying structural layer beneath the surface metal layer. Remove the protective layer, clean and dry the chip surface to expose the test pads in the test pad area; Electrical fault points in the chip are located by testing the test pads in the test pad area.

2. The chip partial delamination method according to claim 1, characterized in that, Before filling the protective layer, electrical performance tests are performed to locate the fault area where the chip has an electrical fault; during the filling of the protective layer, only the fault area is exposed.

3. The chip partial delamination method according to claim 2, characterized in that, When a passivation layer exists on the surface of the metal layer of an opened chip, and the passivation layer is located in the corresponding area above the fault area, the passivation layer should be removed before removing the surface metal layer or before filling with a protective layer.

4. The chip partial delamination method according to claim 3, characterized in that, When removing the passivation layer, the passivation layer is first thinned by reactive ion etching, and then completely removed by wet etching.

5. The chip partial delamination method according to claim 4, characterized in that, The passivation layer thickness can be reduced by half using reactive ion etching.

6. The chip partial delamination method according to claim 1, characterized in that, The protective layer is a hot melt wax. When filling the protective layer, the temperature is heated to above 180°C and below 300°C to melt the protective layer on the chip surface. When the protective layer is evenly covered on the chip surface, it is cooled to room temperature until the protective layer solidifies and takes shape. The protective layer of the area to be removed is removed to expose the surface metal layer of the area to be removed.

7. The chip partial delamination method according to claim 1, characterized in that, The chip, after being filled with a protective layer, is placed in an acid- and alkali-resistant beaker for chemical removal.

8. The chip partial delamination method according to claim 7, characterized in that, The chemical solution in the acid and alkali resistant beaker includes either an acidic solution or an alkaline solution.

9. The chip partial delamination method according to claim 8, characterized in that, Alkaline solutions include either ammonia or sodium hydroxide, while acidic solutions include either hydrochloric acid or phosphoric acid.

10. The chip partial delamination method according to claim 7, characterized in that, Place the chip in an acid- and alkali-resistant beaker for 3-5 minutes.

Images