Whole wafer thickness map reflection measurement technology

Abstract

A method of measuring a thickness of a semiconductor structure includes illuminating the semiconductor structure with incoherent, non-collimated light from at least one light source and capturing at least one image of the semiconductor structure illuminated by light from the light source using a camera. The at least one image includes separate first, second, and third color images, the first, second, and third colors being different from each other. Thickness maps of at least two layers of the semiconductor structure are generated based on the first, second, and third color images and reference first, second, and third color images of a reference silicon wafer.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 505,750, filed June 2, 2023, the entirety of which is hereby incorporated by reference. TECHNICAL FIELD

[0003] The present application relates to a thickness map of a semiconductor wafer, and more specifically, the art relates to methods, systems, and apparatuses for full wafer thickness map reflectometry techniques for silicon-on-insulator (“SOI”) and thick oxide wafers. BACKGROUND

[0004] Silicon-on-insulator structures (“SOI structures”) generally include a handle wafer, a silicon layer (also characterized as a “device layer”), and a dielectric layer (e.g., an oxide layer) between the handle wafer and the silicon layer. Many silicon semiconductor device designs benefit from the use of SOI substrates rather than bulk silicon polished wafers or epitaxial layer-coated substrates. Applications in high-volume manufacturing generally benefit from improved isolation of the device layer also enabling high-bandwidth transistors with reduced electromagnetic crosstalk between adjacent cells within the device.

[0005] SOI structures can be prepared from silicon wafers sliced from monocrystalline silicon ingots grown according to the Czochralski (Cz) method. In one method for preparing SOI substrates, a dielectric layer is deposited on a polished front surface of a donor wafer. Ions are implanted at a specified depth below the front surface of the donor wafer to form a damage layer in the donor wafer at the specified implantation depth. The front surface of the donor wafer is then bonded to a handle wafer and the two wafers are pressed to form a bonded wafer pair. The bonded wafer pair is then cleaved along a cleave plane within the damage layer to remove portions of the donor wafer below the damage layer to leave a thin silicon layer (i.e., device layer) on top of the handle wafer to form an SOI layered substrate.

[0006] Mechanical cleaving of a bonded wafer pair can result in non-uniform device layer thickness as the cleave front, where cleaving begins, progresses toward the back, where the bonded wafer pair is completely separated. Further, in some instances, the cleave can fail and the bonded wafer structure is not cleaved along the desired cleave plane or the bonded wafer structure is not cleaved at all. Variations in cleaving are conventionally monitored by observation by an operator at a downstream process, which can not provide timely feedback to monitor or adjust proper processes at upstream or at cleaving.

[0007] This section is intended to introduce the reader to various aspects of art that can be related to various aspects of the present disclosure described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art. SUMMARY

[0008] One aspect is a thickness measurement system comprising a camera positioned above a center of a semiconductor structure to capture light reflected by the semiconductor structure, at least one light source providing incoherent, non-collimated light, and a controller comprising a processor and a memory. The controller is operatively coupled to the RGB camera and the at least one light source. The memory comprises instructions that, when executed by the processor, cause the controller to illuminate the semiconductor structure with the incoherent, non-collimated light from the at least one light source and cause the camera to capture at least one image of the semiconductor structure illuminated by the light from the light source. The at least one image comprises separate first, second, and third color images, the first, second, and third colors being different from one another. The instructions further cause the processor to generate a thickness map of at least two layers of the semiconductor structure based on the first, second, and third color images and reference first, second, and third color images of a reference silicon wafer.

[0009] Another aspect is a method of measuring thickness of a semiconductor structure. The method comprises illuminating the semiconductor structure with the incoherent, non-collimated light from at least one light source and capturing at least one image of the semiconductor structure illuminated by the light from the light source using a camera. The at least one image comprises separate first, second, and third color images, the first, second, and third colors being different from one another. A thickness map of at least two layers of the semiconductor structure is generated based on the first, second, and third color images and reference first, second, and third color images of a reference silicon wafer.

[0010] There are various improvements to features relative to the above-mentioned aspects. Further features can also be incorporated into the above-mentioned aspects. These improvements and additional features can exist individually or in any combination. For example, various features discussed below with respect to any of the embodiments illustrated in the figures can be incorporated into the above aspects, alone or in any combination. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a schematic diagram of a cleave system for separating a bonded wafer structure along a cleave plane;

[0012] Figure 2 is a cross-sectional view of a donor structure having a donor wafer with a dielectric layer thereon;

[0013] Figure 3 is a cross-sectional view of a donor structure during ion implantation therein;

[0014] Figure 4is a cross-sectional view of a bonded wafer structure after cleaving the handle structure at the cleave plane;

[0015] Figure 5 is a cross-sectional view of a bonded wafer structure after cleaving the handle structure at the cleave plane;

[0016] Figure 6 is a cross-sectional view of a bonded wafer structure with a chuck and a leaf for propagating a cleave;

[0017] Figure 7 is an example imaging station for performing reflectometry techniques; and

[0018] Figure 8 is a plot of an example RGB camera filter spectrum.

[0019] Figure 9 is a plot of an example white spectrum of an LED.

[0020] Figure 10 is a plot of the resulting channel spectra when an example RGB camera from Figure 8 is used with an example white LED from Figure 9 .

[0021] Figure 11 is a plot of an example RGB LED spectrum.

[0022] Figure 12 is a plot of the resulting channel spectra when an example RGB camera from Figure 8 is used with an example RGB LED from Figure 11 .

[0023] Figure 13 is a plot of the resulting channel spectra and wavelength dependent SOI and BOX bias sensitivity from Figure 12 .

[0024] Figure 14 is a plot of the resulting channel spectra and wavelength dependent SOI and BOX bias sensitivity from Figure 11 .

[0025] Figure 15 is an example method to reduce illumination defects and produce a calibration free layer thickness map.

[0026] Figure 16 is a plot of the modeled ratios rGR and rBR as a function of dSOI and dBOX.

[0027] Figure 17 is a plot of the measurement ratios rGR and rBR for a given measurement pair versus the weight function of the modeled ratios rGR and rBR.

[0028] Figure 18 is the ratio of the dSOI to the dBOX. Figure 16 In the narrower dSOI and dBOX range, plots of rGR and rBR as a function of dSOI and dBOX are modeled.

[0029] Figure 19 is a block diagram of an example embodiment of a computing device.

[0030] Throughout the drawings, corresponding element symbols indicate corresponding parts. DETAILED DESCRIPTION

[0031] Referring to Figure 1 , a cleaving system 100 for separating a bonded wafer structure is schematically illustrated. The cleaving system 100 includes a cleaving device 110 for cleaving a bonded wafer structure and an acoustic sensor 120 for sensing sound emitted from the bonded wafer structure during cleaving.

[0032] Bonded wafer structures that can be processed by the cleaving device 110 include any semiconductor structure in which it is desirable to separate the structure into two different structures. In some embodiments, the structure being processed can be a bonded wafer structure for fabricating a silicon-on-insulator structure. Such bonded structures can include a handle wafer, a donor wafer, and a dielectric layer disposed between the handle wafer and the donor wafer. The following describes only one example of a method and system for processing a bonded wafer structure.

[0033] An example of a donor structure 30 that can be bonded to a handle structure to form a bonded wafer structure is shown in Figure 2 . The donor structure 30 can be formed with a dielectric layer 15 deposited on a front surface of a donor wafer 12. It should be understood that alternatively, the dielectric layer can be grown or deposited on the handle wafer or the dielectric layer can be grown on both the donor wafer and the handle wafer and these structures can be bonded in any of a variety of arrangements without limitation. Suitable donor wafers 12 can be composed of silicon, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, indium gallium arsenide, and any combination thereof. In some embodiments, the donor wafer is composed of single crystal silicon.

[0034] The dielectric layer 15 can be any electrically insulating material suitable for use in an SOI structure, including materials such as Si02, Si3N4, aluminum oxide, or magnesium oxide, for example. In some embodiments, the dielectric layer 15 is Si02(i.e., the dielectric layer consists essentially of Si02). In various embodiments, the dielectric layer forms a buried oxide (BOX) layer of the final SOI structure. The dielectric layer 15 can be applied according to any known technique in the art, such as thermal oxidation, wet oxidation, thermal nitridation, or a combination of these techniques. In this regard, it should be understood that although the layered semiconductor structure can be described herein as having a dielectric layer, in some embodiments, the dielectric layer is eliminated (i.e., the dielectric layer is not deposited on either the donor wafer or the handle wafer prior to bonding) and the handle and donor wafers are "direct bonded." Reference herein to such a dielectric layer should not be taken as limiting. Any of several techniques known to those of skill in the art can be used to produce such a direct bonded structure. In such embodiments, the bonding surface of the donor structure is the surface of the donor wafer itself.

[0035] For example, as shown in Figure 3 The ions (e.g., hydrogen atoms, helium atoms, or a combination of hydrogen and helium atoms) can be implanted at a substantially uniform specified depth below the front surface 22 of the donor structure to define the cleave plane 17, for example, as shown in Figure 4 The handle structure 10 can include a dielectric layer deposited on the handle wafer, or as in other embodiments, consist of only the handle wafer (i.e., does not include a dielectric layer). The handle and donor wafers can be single crystal silicon wafers and can be single crystal silicon wafers that have been sliced from a single crystal ingot grown according to conventional Czochralski crystal growth methods.

[0036] As Figure 4The front surface of the dielectric layer 15 of the donor structure is suitably bonded to the front surface of the handle structure 10 to form a bonded wafer structure 20 by a bonding process, as shown in the middle. The dielectric layer 15 and the handle structure 10 can be bonded together when surface activation is performed by exposing the surfaces of the structures to a plasma containing, for example, oxygen or nitrogen. The wafers are then pressed together and a bond at the bonding interface 18 between them is formed. In general, the wafer bonding can be achieved using substantially any technique known in the art for enabling formation of a bonding interface, as long as the energy used to enable formation of the bonding interface is sufficient to ensure that the integrity of the bonding interface is maintained during subsequent processing (i.e., layer transfer by separation along the cleave or separation plane 17 in the donor wafer). Once prepared, the bonded wafer structure 20 is placed in a cleaving apparatus 110 Figure 1 ) to separate (i.e., cleave) a portion of the donor wafer from the bonded structure along the cleave plane to form a layered semiconductor structure. In general, the cleaving apparatus 110 can induce this breakage using techniques known in the art, such as thermal and / or mechanically induced cleaving techniques.

[0037] Referring to Figure 5 After separation, two structures 30, 31 are formed. Because the separation of the bonded wafer structure 20 occurs along the cleave plane 17 in the donor structure 12, Figure 4 ), a portion of the donor structure remains as part of both structures (i.e., a portion of the donor wafer is transferred along with the dielectric layer). The structure 30 includes a portion of the donor wafer. The structure 31 is an SOI structure and includes the handle layer 10, the dielectric layer 15 (sometimes also referred to as a BOX layer), and the device layer 25 (the portion of the donor wafer that remains after cleaving) disposed on top of the dielectric layer 15. The device layer can also be referred to herein at times as an SOI layer. In embodiments where both the donor structure and the handle structure include a dielectric layer, the dielectric layers combine to form the dielectric layer 15 of the SOI structure. The cleaved surface of the layered semiconductor structure (i.e., the thin device layer of the donor wafer) has a rough surface that can be smoothed by additional processing. The structure 31 can be subjected to additional processing to produce a device layer surface thereon having desired characteristics for device fabrication. The cleaving apparatus 110 for separating the bonded wafer structure along the cleave plane can be a mechanical cleaving apparatus, where the separation is induced or achieved by mechanical force alone or in addition to annealing. For example, the bonded structure can be placed in a clamp where a mechanical force is applied perpendicular to opposing sides of the bonded structure to pull a portion of the donor structure away from the bonded structure.

[0038] As Figure 6As shown in the middle, the example cleaving apparatus includes a chuck 60 that applies a mechanical force near the edge of the bonded wafer structure 20 prior to cleaving. Separation of the portion of the donor wafer can be initiated by applying a mechanical wedge or blade 65 at the edge of the bonded wafer at the cleave plane 17 to initiate propagation of a crack along the cleave plane 17. Then, the mechanical force applied by the chuck 60 pulls the portion of the donor structure from the bonded structure, thus forming the SOI structure. Mechanical cleaving apparatuses are commercially available, for example, from Silicon Genesis Corporation (San Jose, CA) as Debond & Cleave Tools.

[0039] In alternative embodiments, the cleaving apparatus 110 is a thermal cleaving apparatus, in which the break is achieved by annealing the bonded structure. For example, the thermal cleaving can be performed at a temperature of about 200 °C to about 800 °C, or from about 250 °C to about 650 °C, for a period of at least about 10 seconds, at least about 1 minute, at least about 15 minutes, at least about 1 hour, or even at least about 3 hours, in an inert (e.g., argon or nitrogen) atmosphere or ambient conditions (where higher temperatures require shorter annealing times, and vice versa). The thermal cleaving apparatus 110 can be a belt furnace, in which the propagation of the cleave is achieved at the leading edge of the bonded structure (i.e., the leading edge in the direction of travel of the structure through the furnace) and travels towards the trailing edge of the bonded wafer structure. Other types of cleaving apparatuses can also be used.

[0040] The cleaving apparatus 110 can generally be configured to process bonded wafer structures of any size, including, for example, 200 mm, 300 mm, greater than 300 mm, or even 450 mm diameter bonded wafer structures. In some embodiments, the cleaving apparatus is configured to process bonded wafer structures that are 200 mm or 300 mm in diameter.

[0041] Referring again to Figure 1 , the cleaving system 100 includes an acoustic sensor 120 for sensing sound emanating from the bonded wafer structure during cleaving and for generating an output in response to the sensed sound. The acoustic sensor 120 can be a microphone, a piezoelectric sensor, a MEMS device, or an acoustic pressure or field transducer.

[0042] The controller 130 is configured to control the cleaving apparatus and generate one or more metrics related to properties of the cleave (e.g., duration of the cleave, quality of the cleave, whether a no layer transfer condition occurred or a pause in the cleave across the wafer) based on the recorded output from the acoustic sensor 120. In some embodiments, the metrics generated by the controller 130 are derived from an audio power curve generated during the cleave. The audio power curve can be derived from the audio amplitude. Examples of metrics that can be calculated include a delay between when the cleave was triggered and the sensed start of the cleave, duration of the cleave, average power during the cleave, maximum power, frequency at which the maximum power occurred, standard deviation of the power, magnitude of the power oscillations, amount of cleave time below a threshold power, maximum single drop time below a threshold power, and number of power drops below a threshold power. In some embodiments, the controller 130 generates 2 or more metrics, or even 3 or more, 5 or more, 7 or more, or 10 or more metrics.

[0043] The controller 130 can be a computer system. A computer system as described herein refers to any known computing device and computer system. As described herein, all such computer systems include a processor and a memory. However, any processor in a computer system referred to herein can also refer to one or more processors, where the processors can be in one computing device or a plurality of computing devices working in parallel. Additionally, any memory in a computer device referred to herein can also refer to one or more memories, where the memories can be in one computing device or a plurality of computing devices working in parallel.

[0044] The term processor as used herein refers to a central processing unit, a microprocessor, a microcontroller, a reduced instruction set circuit (RISC), an application specific integrated circuit (ASIC), a logic circuit, and any other circuit or processor capable of executing the functions described herein. The above are just examples and thus are not intended to limit, in any way, the definition and / or meaning of the term “processor”.

[0045] The term "database" can refer to a body of data, a relational database management system (RDBMS), or both and a database can include any collection of data that is stored in a computer system, including hierarchical databases, relational databases, flat file databases, object-relational databases, object-oriented databases, and any other structured set of records or data stored in a computer system. The above are merely examples, and thus are not intended to limit the definition and / or meaning of the term database in any way. Examples of RDBMS's include, but are not limited to, Oracle® Database, MySQL, IBM® DB2, Microsoft® SQL Server, Sybase®, and PostgreSQL. However, any database can be used in which the systems and methods described herein are implemented.

[0046] In one embodiment, a computer program is provided to enable the controller 130, and this program is embodied on a computer readable medium. In an example embodiment, the computer system executes on a single computer system without being connected to a server computer. In a further embodiment, the computer system runs in a Windows® environment (Windows is a registered trademark of Microsoft Corporation, Redmond, Washington). In yet another embodiment, the computer system runs on a mainframe environment and UNIX® server environment (UNIX is a registered trademark of X / Open Company Limited, Reading, England). Alternatively, the computer system runs on any suitable operating system environment. The computer program is flexible and designed to run on a variety of different environments without compromising any of the primary functionality. In some embodiments, the computer system includes multiple components distributed among a plurality of computing devices. One or more components can be in the form of computer-executable instructions embodied in a computer readable medium.

[0047] The computer system and process are not limited to the specific embodiments described herein. In addition, each component of each computer system and each process can be practiced independent of and separate from other components and processes described herein. Each component and process can also be used in combination with other assembly packages and processes.

[0048] In another embodiment, the memory included in the computer system of controller 130 may include a plurality of modules. Each module may contain instructions configured to be executed using at least one processor. When executed by one or more processors of the computing device, the instructions contained in the plurality of modules may implement at least a portion of the methods described herein.

[0049] One embodiment of the computer system includes a media output component for presenting information to a user. The media output component is any component capable of delivering information to the user (e.g., a metric associated with a split). In some embodiments, the media output component includes an output adapter, such as a video adapter and / or an audio adapter. The output adapter is operatively coupled to a processor and further configured to be operatively coupled to an output device, such as a display device (e.g., a liquid crystal display (LCD), an organic light-emitting diode (OLED) display, a cathode ray tube (CRT), or an "e-ink" display) or an audio output device (e.g., a speaker or headphones).

[0050] Figure 7 An example imaging station 700 (sometimes referred to herein as a thickness measurement station or system) is used to perform reflectance measurement techniques. Imaging station 700 may be part of or separate from the cleaving system 100. Furthermore, imaging station 700 may be used additionally for imaging other than reflectance measurement imaging. In an example embodiment, imaging station 700 is used to image SOI structure 31 after cleaving. In some embodiments, imaging station 700 may be used to bond wafer 20 before cleaving. Alternatively or additionally, imaging station 700 may be used at any point in the manufacturing process for imaging and / or reflectance measurement of the wafer or structure.

[0051] Imaging station 700 includes camera 702, light source 704 and controller 706 to control camera 702 and light source 704 to image SOI structure 31 and generate one or more thickness maps of SOI structure 31.

[0052] In an example embodiment, imaging station 700 is used for RGB reflectance measurement technology, and camera 702 is an RGB camera operable to capture red, green, and blue light, respectively, in a separate channel. In other embodiments, the camera is an n-color camera. For example, a monochrome camera can be used in combination with a set of n filters. Each filter is used with the camera to capture one of n different color images.

[0053] Camera 702 is positioned above the center of structure 31 (or the structure is moved to a position where its center is directly below camera 702). Camera 702 has a sufficiently wide field of view to capture an image of the entire SOI structure 31 without moving.

[0054] Although two lamps are shown in the figure, any suitable number of lamps 704 may be included. In an exemplary embodiment, the light source 704 comprises individually controllable red, green, and blue light-emitting diodes (LEDs), each emitting light of a known wavelength. In other embodiments, the light source is a full-spectrum LED, any other color or combination of colored LEDs, or any other suitable light source for reflectance measurement techniques. In an exemplary embodiment, the light source 704 is an incoherent light source. That is, the light source produces incoherent light and contains more than one wavelength, frequency, and / or phase.

[0055] Controller 706 may be controller 130, or a separate controller containing similar components. Controller 706 controls light source 704 to illuminate SOI structure 31 and controls camera 702 to capture light reflected from SOI structure 31. At least some of the light impacting SOI structure 31 will travel through one or more of the layers of structure 31 before being reflected back to camera 702. The thickness of the layers of SOI structure 31 across the entire structure can be determined by controller 706 based on the wavelength of light, how the material of each layer affects the speed of light, reflection and absorption, and the intensity of the light captured by camera 702.

[0056] Next, the controller 706 can modify one or more parameters of the splitting process performed by the splitting device based on the generated thickness map to correct errors or generally improve the splitting process of the next wafer.

[0057] In an example embodiment, controller 706 controls lamp 704 to illuminate SOI structure 31 and uses camera 702 to capture images of SOI structure. The images include red, green, and blue images captured by different channels of each of the RGB cameras 702.

[0058] The accuracy of the described method can be improved by capturing and stacking multiple images, but at the cost of the additional time required to capture multiple images. Furthermore, the improvement can depend on the amount of noise in each image. For example, in cases where gain and exposure produce images with single-digit noise factors, 100 images would result in a 10-fold increase in accuracy (or a 10-fold reduction in error). Additionally, the resolution of camera 702 is a factor determining the accuracy of the thickness map produced by this method. If camera 702 has an 8-bit resolution, the relative error of some of the ratios discussed below will be less than 0.02, while if camera 702 has a 10-bit resolution, the error will be less than 0.005.

[0059] The illumination provided by light source 704 can also affect the accuracy of the thickness map to be generated. For example, by... Figures 8 to 14 The graph shows that diffuse, broadband white light will produce less accurate results than individual narrowband light of red, green, and blue wavelengths. Figure 8 This is a graph of the spectrum of the filter in an example RGB camera.Figure 9 This is a graph of the white spectrum of an example LED. Figure 10 Is from Figure 8 Example RGB camera and from Figure 9 The curve of the channel spectrum obtained when used with an example white LED. Figure 11 This is a graph of the spectrum of an example RGB LED. Figure 12 Is from Figure 8 Example RGB camera and from Figure 11 The curve of the channel spectrum obtained when RGB LEDs are used together. Figure 13 It comes from Figure 12 The obtained channel spectrum and wavelength-dependent SOI and BOX bias sensitivity curves are shown. Figure 14 It comes from Figure 11 The obtained channel spectrum and wavelength-dependent SOI and BOX bias sensitivity curves are shown.

[0060] Figure 15 This section describes example methods for reducing lighting defects and generating uncalibrated layer thickness maps.

[0061] As part of the image generation process, in step 1, the controller 706 captures or extracts red, green, and blue intensity images (I0, I ... R I G and I B One of them, and also captures red, green, and blue intensity images (Ir) of a reference bare silicon wafer taken by the same or similar camera 702 under the same or similar conditions (e.g., illumination, temperature, etc.). R Ir G and Ir B Images of the sample SOI structure and the bare silicon reference wafer illustrate two types of illumination defects. The first type is caused by uncalibrated illumination of the structure (both the bare silicon and SOI structures) when imaging the structure. These defects are visible as intensity hotspots located in the northeast and southwest of the wafer. The second type is wavelength-dependent illumination defects. These defects are displayed as checkerboard intensity patterns in the images.

[0062] In step 2, the controller 706 corrects the uncalibrated illumination of the structure by using the image intensity ratio of two different color images to a third color image. For example, the controller 706 calculates the ratio of the intensity of the green image to the intensity of the red image of the SOI structure and the reference bare silicon wafer. Therefore, the ratio of the SOI structure is... The ratio of the reference chip is The controller 706 also calculates the ratio of the intensity of the blue image to the intensity of the red image for the SOI structure. and Any of the three colors can be the denominator in the ratio, but the same color must be used for all ratios in any given image calculation. As can be seen from the image in step 2, using these ratios reduces or eliminates the intensity hotspots visible in step 1. Additionally, in other embodiments, more than three colors can be used, and the techniques described herein can be extended to include additional ratios using additional colors. Furthermore, it should be understood that when, for example, a ratio of a green image to a red image is used, the intensity value of each pixel in the green image is divided by the intensity value of the corresponding pixel in the red image. Therefore, the result is a new image in which the intensity value of each pixel is equal to the ratio of the intensity value of the corresponding pixel from the green image to the intensity value of the corresponding pixel from the red image. The result may be referred to herein as an image or a ratio.

[0063] In step 3, to reduce wavelength-dependent illumination defects, the ratio determined above for the SOI structure is divided by the corresponding intensity ratio of the reference bare silicon wafer. That is, the controller calculates... and As seen in the image in step 3, this reduces or removes the checkerboard pattern visible in the image in step 2.

[0064] After completing step 3, image correction is performed to compensate for uncalibrated illumination, and then the resulting intensity image is further processed (e.g., r). GR and r BR The resulting intensity image r is used to calculate the layer thickness map. GR and r BR This can be done using any known technique for generating thickness maps from such images. An example process will be described below.

[0065] First, from the obtained image r GR and r BR Calculate the average thickness of each layer of the structure across the entire structure. This can be achieved by using r GR and r BR Both are input into the model of the layer to determine. For example, Figure 17 The measurement ratio r of a given measurement pair GR and r BR Compared to modeling ratio r GR and r BR The graph shows the weight function. The weight of each pixel / position is determined by Equation 1 below.

[0066] (1)

[0067] Figure 17 The peak value in the measurement ratio r is GR and r BR Very close to modeling ratio r GR With rBR The location. This is used to measure r. GR and r BR In the nonlinear search of the wafer average value for the wafer average dSOI / dBOX value.

[0068] Once the SOI layer is determined ( ) and BOX layer ( The total average thickness is calculated using a linear approximation formula to determine the thickness of the map. (r) GR and r BR It is a nonlinear function over a wide range of dSOI / dBOX, such as Figure 16 As shown in the figure, it is a modeling ratio r GR and r BR A graph as a function of dSOI and dBOX. However, when observing within a smaller dSOI / dBOX range (e.g. Figure 18 (as shown in the image), r GR and r BR It is closer to a linear function and can be linearly approximated within a narrow range of dSOI / dBOX. It is a typical case of target variation of dSOI and dBOX on SOI structure.

[0069] A thickness map is generated by calculating the thickness of all points in the SOI structure as a first-order deviation map from the average thickness. Specifically, the controller 706 determines how much (positive or negative) each point of the layers in the SOI structure 31 differs from the calculated average thickness. This linear approximation can be performed, for example, as follows:

[0070] (2)

[0071] It equals

[0072] (3)

[0073] in

[0074] (4)

[0075] Finally, the determined thickness is corrected for errors caused by angular distortion resulting from the camera being relatively close to the surface of SOI structure 31 without the use of any collimating optics. That is, for example, light does not enter the camera perfectly perpendicular to the surface of the SOI structure and parallel to each other. Instead, some light near the center typically enters the camera 702 perpendicular to the surface of SOI structure 31, and some (particularly reflected from the edge of the wafer) enter at significantly different angles and are not parallel to the light reflected from the center. Correction can be achieved as follows:

[0076] (4)

[0077] Figure 19 It is suitable for use as a controller 130 ( Figure 1 ) and / or controller 706 ( Figure 7 A block diagram of an example embodiment of the computing device 400. For example, the computing device 400 represents the above-described reference. Figure 2 The computing device 106 is shown and described. The wafer measurement device 102, wafer processing device 104, and removal map configuration library 110 may include all or a subset of the components of the computing device 400. The computing device 400 includes a processor 405 for executing instructions. In some embodiments, the executable instructions are stored in a memory region 410. The processor 405 may include one or more processing units (e.g., in a multi-core configuration). The memory region 410 is any means that allows storage and retrieval of information such as executable instructions and / or data. The memory region 410 may include one or more computer-readable storage devices or other computer-readable media, including transient and non-transitory computer-readable media.

[0078] In at least some embodiments, computing device 400 also includes at least one media output component 415 for presenting information to user 401. Media output component 415 is any component capable of delivering information to user 401. In some embodiments, media output component 415 includes an output adapter, such as a video adapter and / or an audio adapter. The output adapter is operatively connected to processor 405 and operatively connected to an output device, such as a display device (e.g., a liquid crystal display (LCD), organic light-emitting diode (OLED) display, cathode ray tube (CRT), or "e-ink" display) or an audio output device (e.g., a speaker or headphones). In some embodiments, at least one of these display devices and / or audio devices is included in media output component 415.

[0079] In some embodiments, computing device 400 includes an input device 420 for receiving input from user 401. Input device 420 may include, for example, a keyboard, pointing device, mouse, stylus, touch-sensitive panel (e.g., touchpad or touchscreen), gyroscope, accelerometer, position detector, or audio input device. A single component (e.g., touchscreen) may serve as both an output device of media output component 415 and an input device 420.

[0080] The computing device 400 may also include a communication interface 425 communicatively connected to one or more remote devices, such as the wafer measurement device 102, the wafer processing device 104, and / or the removal graph configuration file library 110. The communication interface 425 may include, for example, a wired or wireless network adapter or wireless data transceiver for use with mobile phone networks (e.g., GSM, 3G, 4G, or Bluetooth) or other mobile data networks (e.g., WiMAX).

[0081] For example, stored in memory region 410 are processor-executable instructions for providing a user interface to user 401 via media output component 415 and optionally receiving and processing input from input device 420. Memory region 410 may include (but is not limited to) any computer operating hardware suitable for storing and / or retrieving processor-executable instructions and / or data. Memory region 410 may include random access memory (RAM) (e.g., dynamic RAM (DRAM) or static RAM (SRAM)), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and non-volatile RAM (NVRAM). Furthermore, memory region 410 may include multiple storage cells, such as hard disks or solid-state drives in a fault-tolerant disk array (RAID) configuration. Memory region 410 may include a storage local area network (SAN) and / or network attached storage (NAS) system. In some embodiments, memory region 410 includes memory integrated into computing device 400. For example, computing device 400 may include one or more hard disk drives as memory region 410. Memory region 410 may also include memory located outside computing device 400 and accessible by a plurality of computing devices. The memory types described above are merely exemplary and are therefore not limited to the types of memory that can be used to store processor-executable instructions and / or data.

[0082] As used herein, when used in conjunction with ranges of size, concentration, temperature or other physical or chemical properties or characteristics, the terms “about,” “substantially,” “essentially,” and “approximately” mean to cover variations that may exist within the upper and / or lower limits of the range of properties or characteristics, including variations, for example, those arising from rounding, measurement methods, or other statistical variations.

[0083] When elements of this disclosure or embodiments thereof are introduced, the articles “a” and “described” are intended to mean the presence of one or more of the elements. The terms “comprising,” “including,” “containing,” and “having” are intended to be inclusive and mean that additional elements may be present in addition to the listed elements. Terms indicating a particular orientation (e.g., “top,” “bottom,” “side,” etc.) are used for ease of description and do not require any particular orientation of the described item.

[0084] Since various changes can be made to the above construction and method without departing from the scope of this disclosure, all matters contained in the above description and shown in the accompanying drawings are intended to be illustrative rather than limiting.

Claims

1. A thickness measurement system, comprising: A camera is positioned above the center of a semiconductor structure to capture light reflected by the semiconductor structure; At least one light source that provides incoherent, non-collimated light; and A controller, comprising a processor and a memory, is operatively coupled to the RGB camera and the at least one light source, the memory containing instructions that, when executed by the processor, cause the controller to: The semiconductor structure is illuminated using incoherent, non-collimated light from the at least one light source; The camera captures at least one image of the semiconductor structure illuminated by light from the light source, the at least one image comprising a first color, a second color, and a third color image, wherein the first, second, and third colors are different from each other; and A thickness map of at least two layers of the semiconductor structure is generated based on the first color, second color, and third color images and reference first color, second color, and third color images of a reference silicon wafer.

2. The thickness measurement system of claim 1, wherein the instruction causes the controller to generate the thickness map in part based on the light intensity ratio of the first, second, and third color images of the semiconductor structure to the reference first, second, and third color images of the reference silicon wafer.

3. The thickness measurement system of claim 2, wherein the instruction causes the controller to generate the thickness map in part by: A first semiconductor structure ratio is determined by comparing the light intensity of the first color image of the semiconductor structure with the light intensity of the third color image of the semiconductor structure. A second semiconductor structure ratio is determined by comparing the light intensity of the second color image of the semiconductor structure with the light intensity of the third color image of the semiconductor structure. A first reference ratio is determined between the light intensity of the first color image of the reference silicon wafer and the light intensity of the third color image of the reference silicon wafer; and A second reference ratio is determined between the light intensity of the second color image of the reference silicon wafer and the light intensity of the third color image of the reference silicon wafer.

4. The thickness measurement system of claim 3, wherein the instruction causes the controller to generate the thickness map in part by: The first result ratio is determined by dividing the first semiconductor structure ratio by the first reference ratio; and The second result ratio is determined by dividing the second semiconductor structure ratio by the second reference ratio.

5. The thickness measurement system according to any one of claims 1 to 4, wherein the instruction causes the controller to calculate the average thickness of each layer and calculate a final layer thickness map of each layer as a first-order deviation map from the average thickness of the layer.

6. The thickness measurement system according to any one of claims 1 to 4, wherein the instruction causes the controller to correct the thickness map for angular distortion caused by the camera being positioned relatively close to the semiconductor structure without the use of collimating optics.

7. The thickness measurement system according to any one of claims 1 to 4, wherein the semiconductor structure comprises a silicon-on-insulator (SOI) structure, and the at least two layers comprise an SOI layer and a buried oxide (BOX) layer.

8. The thickness measurement system according to any one of claims 1 to 4, wherein the first color is red, the second color is green, and the third color is blue.

9. The thickness measurement system according to claim 8, wherein the camera includes red, green and blue (RGB) cameras.

10. The thickness measurement system according to claim 8, wherein the at least one light source comprises red, green and blue (RGB) light-emitting diodes (LEDs).

11. A method for measuring the thickness of a semiconductor structure, comprising: The semiconductor structure is illuminated with incoherent, non-collimated light from at least one light source; A camera is used to capture at least one image of the semiconductor structure illuminated by light from the light source, the at least one image comprising individual first color, second color, and third color images, the first, second, and third colors being different from each other; and A thickness map of at least two layers of the semiconductor structure is generated based on the first color, second color, and third color images and reference first color, second color, and third color images of a reference silicon wafer.

12. The method of claim 11, wherein generating the thickness map comprises generating the thickness map in part based on the light intensity ratio of the first, second, and third color images of the semiconductor structure to a reference first, second, and third color image of the reference silicon wafer.

13. The method of claim 12, wherein generating the thickness map comprises: A first semiconductor structure ratio is determined by comparing the light intensity of the first color image of the semiconductor structure with the light intensity of the third color image of the semiconductor structure. A second semiconductor structure ratio is determined by comparing the light intensity of the second color image of the semiconductor structure with the light intensity of the third color image of the semiconductor structure. A first reference ratio is determined between the light intensity of the first color image of the reference silicon wafer and the light intensity of the third color image of the reference silicon wafer; and A second reference ratio is determined between the light intensity of the second color image of the reference silicon wafer and the light intensity of the third color image of the reference silicon wafer.

14. The method of claim 13, wherein generating the thickness map comprises: The first result ratio is determined by dividing the first semiconductor structure ratio by the first reference ratio; The second result ratio is determined by dividing the second semiconductor structure ratio by the second reference ratio; and The thickness map is generated based on the first result ratio and the second result ratio.

15. The method according to any one of claims 11 to 14, wherein generating the thickness map comprises calculating the average thickness of each layer and calculating a final thickness map of each layer as a first-order deviation map from the average thickness of the layers.

16. The method of claim 15, wherein the method uses To perform the calculation of the final thickness map of each layer as a first-order deviation map from the average thickness of the layer.

17. The method of claim 15, wherein in 。 18. The method according to any one of claims 11 to 14, further comprising correcting the thickness map for angular distortion caused by the camera being positioned relatively close to the semiconductor structure without the use of collimating optics.

19. The method of claim 18, wherein the thickness map is corrected using the following method. 。 20. The method according to any one of claims 11 to 14, wherein the semiconductor structure comprises a silicon-on-insulator (SOI) structure, and the at least two layers comprise an SOI layer and a buried oxide (BOX) layer.

21. The method according to any one of claims 11 to 14, wherein the first color is red, the second color is green, and the third color is blue.

22. The method of claim 18, wherein capturing at least one image of the semiconductor structure using a camera comprises capturing the at least one image using a red, green, and blue (RGB) camera.

23. The method of claim 18, wherein illuminating the semiconductor structure comprises illuminating the semiconductor structure using red, green, and blue (RGB) light-emitting diodes (LEDs).

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