Digital RF reconstruction circuits, modules, and radar transceiver systems for suppressing antenna leakage

Abstract

This invention relates to the field of wireless sensing, and in particular to a digital radio frequency reconstruction circuit, module, and radar transceiver system for suppressing antenna leakage. The digital radio frequency reconstruction circuit consists of a polyphase filter, a phase interpolator, and a multi-stage attenuator. The polyphase filter orthogonally decomposes the leakage signal into multiple orthogonal signals. Then, the gating circuit in the phase interpolator performs weighted synthesis of two orthogonal signals based on the principle of orthogonal vector synthesis, and adjusts the weights of the two orthogonal signals with the help of multiple signal interpolation circuits, thereby achieving precise phase adjustment. Finally, through cascaded and matched multi-stage attenuators with different attenuation amplitudes, the phase-adjusted circuit undergoes fine amplitude adjustment, thus reconstructing a corrected signal that accurately matches the leakage signal. This invention solves the problems of insufficient correction accuracy and narrow operating frequency band of existing circuits for leakage signals under high-frequency conditions.

Description

Technical Field

[0001] This invention relates to the field of wireless sensing, and in particular to a digital radio frequency reconstruction circuit for suppressing antenna leakage, and a corresponding reconstruction module for the corrected signal and a radar transceiver system. Background Technology

[0002] In millimeter-wave radar systems, antenna leakage is one of the key factors affecting system performance. Antenna leakage can interfere with the received signal, degrading signal quality and consequently affecting the radar's accuracy in detecting and identifying targets. For example, carrier leakage can generate spurious signals, which may mask weak target echo signals, leading to target loss or misjudgment.

[0003] Antenna leakage is primarily caused by imperfections in the transceiver architecture of radar systems. In traditional transceiver architectures, there is a certain degree of coupling between the transmitting and receiving antennas, allowing the transmitted signal to leak to the receiver through various pathways. Furthermore, parasitic parameters in the circuitry and non-ideal characteristics of components exacerbate antenna leakage. To address this issue, existing technical solutions mainly focus on the following aspects: 1. Physical isolation: Reducing coupling by increasing the physical distance between the transmitting and receiving antennas, or by configuring a fixed transmitting antenna at the center of a slide rail and two movable receiving antennas within the rail at each communication node, allowing self-interference signals to cancel each other out after passing through a combiner. However, this method is difficult to implement in applications with high miniaturization and integration requirements. 2. Digital signal processing: Using digital signal processing techniques for interference cancellation in the baseband. While this method can effectively eliminate some interference, it requires additional computational resources and power consumption, and its effectiveness for high-frequency signals is limited. 3. RF domain circuit design: Designing RF circuits, including quadrature signal generators, quadrature selectors, C-DACs, and output transconductance units, to reconstruct self-interference signals. However, this method operates at a very low frequency and has a complex circuit structure, making it an undesirable option for highly integrated chip designs. Summary of the Invention

[0004] To address the issues of insufficient reconstruction accuracy and narrow operating frequency band of the correction signal for leakage signals under high-frequency operating conditions, this invention provides a digital radio frequency reconstruction circuit for suppressing antenna leakage, as well as a corresponding reconstruction module for the correction signal and a radar transceiver system.

[0005] The technical solution provided by this invention is as follows:

[0006] The present invention also includes a digital radio frequency reconstruction circuit for suppressing antenna leakage, comprising: a polyphase filter, a phase interpolator, and a multi-stage attenuator. The polyphase filter receives a set of original differential signals characterizing the leakage signal in the antenna system and decomposes them into four orthogonal signals according to their phase.

[0007] The phase interpolator includes a gating circuit, multiple signal interpolation circuits, capacitor C0, and a buffer. The gating circuit selects two mutually orthogonal signals from four quadrature signals based on a control signal and outputs them synchronously to all signal interpolation circuits. Each activated signal interpolation circuit performs interpolation on the two input signals to obtain the corresponding output signal. The output of each signal interpolation circuit is connected to the upper plate of C0 and the input of the buffer; the lower plate of C0 is grounded. The output of the buffer outputs the phase-modulated output signal PIout.

[0008] A multi-stage attenuator is composed of multiple attenuation circuits with different attenuation amplitudes cascaded in a preset order, and is used to amplitude modulate the input PIout signal to generate the required correction signal.

[0009] By coordinating the operation modes of the phase interpolator and multi-stage attenuator through multiple phase control codes and amplitude control codes, the corresponding correction signal can be generated based on the input leakage signal. Among them, two bits of the phase control code serve as control signals for switching the gating logic of the two gating units, and the remaining bits control the start-up state of each signal interpolation circuit. The bits of the amplitude control code from high to low sequentially control the start-up state of each attenuator with attenuation amplitude from low to high.

[0010] As a further improvement of this invention, the multiphase filter consists of four capacitors C1-C4 and four resistors R1-R4. The positive-phase signal of the original differential signal is connected to the upper plates of C1 and C2 and one end of R1 and R2; the inverted signal of the original differential signal is connected to the upper plates of C3 and C4 and one end of R3 and R4; the lower plate of C4 is connected to the other end of R1 and outputs a quadrature signal Q. P The lower-level board of C1 is connected to the other end of R2 and outputs an orthogonal signal I. P The lower-level board of C2 is connected to the other end of R3 and outputs a quadrature signal Q. N The lower-level board of C3 is connected to the other end of R4 and outputs a quadrature signal I. N Among them, Q P and Q N This constitutes a set of differential numerator signals; I P and I N This constitutes another set of differential molecular signals.

[0011] As a further improvement of the present invention, the gating circuit in the phase interpolator includes two 2-to-1 gating units, which take the two sets of difference numerator signals contained in the four orthogonal signals as the inputs of the two gating units respectively.

[0012] As a further improvement of the present invention, the gating unit in the phase interpolator consists of two transmission gates TG1 and TG2 and one inverter INV1. The input terminals of TG1 and TG2 serve as the input ports of the two inverted signals in the numerator signal, respectively; the output terminals of TG1 and TG2 are connected and serve as the output ports of the gating signal; the inverting control terminal of TG1 is connected to the non-inverting control terminal of TG2; the non-inverting control terminal of TG1 is connected to the inverting control terminal of TG2 and the output terminal of INV1; the input terminal of INV1 is the control signal of the gating logic.

[0013] As a further improvement of the present invention, the signal interpolation circuit adopts any one of the current-type interpolation circuit, voltage-type interpolation circuit, and integral interpolation circuit.

[0014] As a further improvement of this invention, the integral interpolation circuit consists of four PMOS transistors P1~P4, four NMOS transistors N1~N4, and one inverter INV2. The sources of P1 and P2 are connected to VDD, and the drain of P1 is connected to the source of P3; the drain of P2 is connected to the source of P4; the source of N1 is connected to the drain of N3; and the source of N2 is connected to the drain of N4. The sources of N3 and N4 are grounded; P1 and N3 are connected and serve as one of the input ports IN. Q P2 and N4 are connected and used as another input port IN. I The gates of P3 and N2 are connected to the output terminal of INV2; the gates of P4 and N1 are connected to the input terminal of INV2 and serve as control port S. The drains of P3, P4, N1, and N2 are connected and serve as output port OUT.

[0015] As a further improvement of the present invention, in the multi-stage attenuator, each attenuation circuit is selected from any one of the Π-type structure, T-type structure and simple T-type structure according to the difference in attenuation amplitude; the number of attenuation circuits is adaptively set according to the preset attenuation accuracy requirements.

[0016] As a further improvement of the present invention, in the multi-stage attenuator, by reasonably selecting attenuation circuits with different attenuation amplitudes and optimizing the cascading sequence, the attenuation accuracy and amplitude linearity of the circuit output signal meet the requirements.

[0017] As a further improvement of this invention, a multi-stage attenuator with an attenuation accuracy of 0.25dB is implemented through a seven-stage attenuator. The seven-stage attenuator is composed of cascaded attenuation circuits with attenuation accuracies of 0.5dB, 16dB, 2dB, 4dB, 8dB, 1dB, and 0.25dB. Specifically, the attenuation circuits for 0.25dB, 0.5dB, 1dB, and 2dB employ a simple T-type attenuation circuit consisting of one NMOS transistor and one resistor. The attenuation circuits for 4dB and 8dB employ a T-type attenuation circuit consisting of two NMOS transistors and three resistors; and the attenuation circuit for 16dB employs a Π-type attenuation circuit consisting of three NMOS transistors and three resistors.

[0018] As a further improvement of the present invention, the simplified T-type attenuation circuit consists of one NMOS transistor N5 and one resistor R5. The drain of N5 serves as the signal input and signal output terminal; the gate of N5 is connected to the start signal SW; the source of N5 is connected to one end of R5, and the other end of R5 is grounded.

[0019] The T-type attenuation circuit consists of two NMOS transistors N6 and N7 and three resistors R6, R7, and R8. The drain of N6 is connected to one end of R6 and serves as the signal input port. The other end of R6 is connected to one end of R7 and the drain of N7. The other end of R7 is connected to the source of N6 and serves as the signal output port. The source of N7 is connected to one end of R8. The other end of R8 is grounded. The gate of N7 is connected to the start signal SW, and the gate of N6 is connected to the inverted signal of SW.

[0020] The Π-type attenuation circuit consists of three NMOS transistors N8, N9, and N10 and three resistors R9, R10, and R11. The drains of N8 and N9 are connected to one end of R9 and serve as signal input ports. The source of N8 is connected to the drain of N9 and the other end of R9 and serves as a signal output port. The source of N9 is grounded through R10. The source of N10 is grounded through R11. The gates of N9 and N10 are connected to the start signal SW. The gate of N8 is connected to the inverted signal of SW.

[0021] As a further improvement of this invention, for the leakage signal under each operating condition, the digital radio frequency reconstruction circuit uses a set of corresponding phase control codes and amplitude control codes to generate a correction signal with opposite phase and equal amplitude that meets the accuracy requirements based on the leakage signal. Specifically, under a specified leakage signal condition, the values ​​of each bit in the phase control code and amplitude control code are generated using a binary search strategy.

[0022] The present invention also includes a reconstruction module for a corrected signal, which includes the aforementioned digital radio frequency reconstruction circuit for suppressing antenna leakage, and further includes a control code selection circuit or a control code search circuit.

[0023] The control code selection circuit has a preset mapping relationship between leakage signals and appropriate control codes under various specified operating conditions. It is used to select the appropriate control code according to the current operating condition and to adjust the working mode of the phase interpolator and multi-stage attenuator in the digital radio frequency reconstruction circuit to generate an appropriate correction signal.

[0024] The control code search circuit is used to obtain the leakage signal input to the digital RF reconstruction circuit and the correction signal output. It then uses a binary search strategy to adjust the control code until the generated correction signal matches the leakage signal under the current operating conditions.

[0025] The present invention also includes a radar transceiver system comprising a signal transmitter, a signal receiver, an oscillator, and a phase-locked loop; it further includes a digital radio frequency reconstruction circuit for suppressing antenna leakage as described above. The digital radio frequency reconstruction circuit for suppressing antenna leakage generates a correction signal with opposite phase and equal amplitude based on the leakage signal acquired from the signal transmitter side; and outputs it to the oscillator to be superimposed with the received signal from the signal receiver side, thereby eliminating leakage noise in the radio frequency transceiver.

[0026] The present invention has the following beneficial effects:

[0027] This invention provides a reconstruction circuit composed of a multiphase filter, a phase interpolator, and a multi-stage attenuator. The circuit mainly consists of basic components such as capacitors, MOSFETs, and resistors. It can be designed and manufactured using 22nm digital RF circuit technology, and in actual layout design, it can be optimized for RF designs more suitable for high-frequency applications. Thanks to the optimized circuit structure, parameters, and smaller process dimensions, the reconstruction circuit of this invention can achieve the same function on a smaller chip area. It reduces unnecessary components and complex wiring, thereby further reducing chip area and power consumption.

[0028] The reconstruction circuit of this invention employs a novel architecture based on digital radio frequency circuit design. It achieves finer phase modulation by orthogonally decomposing and vector synthesizing the original signal, combined with phase interpolation, and further reduces phase modulation accuracy through cascaded matched multi-stage attenuators. Unlike traditional analog devices, this circuit is specifically designed for the 19-21 GHz frequency band. Its internal components' frequency response and circuit structure are optimized to maintain good performance across this wide frequency range. This circuit overcomes the frequency band limitations of existing solutions and can adapt to a wider range of radio frequency and microwave applications, such as wireless communication systems with wide frequency band requirements and specific radar systems, greatly expanding its application scope.

[0029] The circuit design of this invention is a demand-oriented design, which can adaptively adjust the phase modulation accuracy and amplitude modulation accuracy of the circuit according to the design objectives. For example, using a 7-bit attenuator and a 7-bit phase interpolator, a phase modulation accuracy of up to 2.81° and an attenuation accuracy of 0.25dB can be achieved. Furthermore, the circuit can utilize multi-dimensional control codes for phase and amplitude modulation, making operation more convenient. Through this high-precision adjustment, leakage signals can be eliminated more accurately.

[0030] The reconstruction circuit of this invention can be directly integrated into the antenna system. The reconstruction circuit processes the received leakage signal and then synthesizes the processed corrected signal with the useful signal received by the receiver. In this process, the circuit minimizes the impact on the receiver's noise figure and input matching performance; it ensures stable receiver operation, maintains the receiver's low-noise performance, and improves the quality and sensitivity of the received signal. Attached Figure Description

[0031] Figure 1 This is an architecture diagram of the radar transceiver system described in Embodiment 1 of the present invention.

[0032] Figure 2 This is an architecture diagram of a radar transceiver system designed to overcome antenna leakage problems by introducing a signal correction module.

[0033] Figure 3 This is a circuit diagram of the digital radio frequency reconstruction circuit for suppressing antenna leakage provided in Embodiment 1 of the present invention.

[0034] Figure 4 This is a circuit diagram of the gating unit in the phase interpolator of Embodiment 1 of the present invention.

[0035] Figure 5 This is a circuit diagram of the integral interpolation circuit used in the phase interpolator of Embodiment 1 of the present invention.

[0036] Figure 6 This is a circuit diagram of the multi-stage attenuator in Embodiment 1 of the present invention.

[0037] Figure 7 The circuit diagrams are for three typical attenuator structures in Embodiment 1 of the present invention.

[0038] Figure 8 This is a schematic diagram of the reconstruction module for the corrected signal provided in Embodiment 2 of the present invention.

[0039] Figure 9 This is a schematic diagram of the radar transceiver system provided in Embodiment 3 of the present invention.

[0040] Figure 10 This is a diagram showing the phase modulation effect of the phase interpolator section in the reconstruction circuit of this invention during performance testing.

[0041] Figure 11 This is a diagram showing the amplitude modulation effect of the attenuator section in the reconstruction circuit of this invention during performance testing.

[0042] Figure 12 The antenna leakage suppression effect of the radar transceiver system using the reconstruction circuit of this invention in the performance test is shown in the figure. Detailed Implementation

[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0045] Example 1

[0046] Figure 1 The diagram shows the architecture of a traditional injection-locked radar transceiver system. The signal from the oscillator is transmitted through a power amplifier (PA) and antenna on the transmitter side. The reflected signal from a distant target is received by an antenna and a low-noise amplifier (LNA) on the receiver side and then injected back into the oscillator. The direct injection of the transmitted signal into the oscillator through the receiving loop introduces antenna leakage. To address antenna leakage, such as... Figure 2 As shown, technicians added a signal correction module to the antenna transceiver system. This module generates a correction signal based on the acquired leakage signal and is used to eliminate leakage harmonics in the RF transceiver. However, as mentioned earlier, signal correction modules suitable for injection-locked radar transceiver systems are often not integrated into the chip system, and generally suffer from insufficient reconstruction accuracy of the correction signal, narrow operating frequency band, and inapplicability to high-frequency bands.

[0047] To address this issue, this embodiment further provides a digital radio frequency reconstruction circuit for suppressing antenna leakage. This circuit employs a novel corrected signal reconstruction strategy, including: first, orthogonally decomposing the leaked signal to obtain multiple orthogonal signals; then, weighted combining two orthogonal signals based on the principle of orthogonal vector synthesis, and precisely adjusting the weights of the two orthogonal signals using multiple signal interpolation circuits to achieve precise phase adjustment; finally, finely adjusting the amplitude of the phase-adjusted circuit using cascaded and matched multi-stage attenuators with different attenuation amplitudes; thereby reconstructing a corrected signal that precisely matches the leaked signal.

[0048] Specifically, such as Figure 3 As shown, the digital radio frequency reconstruction circuit for suppressing antenna leakage provided in this embodiment includes: a polyphase filter (PPF), a phase interpolator (PI), and a multi-stage attenuator. The polyphase filter receives a set of original differential signals characterizing the leakage signal in the antenna system and decomposes them into four orthogonal signals according to their phase. For example, assuming the original differential signal of the leakage signal is represented as OUT... P and OUT N The two signals are out of phase. Therefore, the polyphase filter in this embodiment can further decompose the differential signal into four orthogonal signals located in the four quadrants, which are denoted as Q in this embodiment. P Q N I P I N Among them, Q P and Q N This constitutes a set of differential numerator signals; I P and I N This constitutes another set of differential molecule signals; I P With Q P Q N Orthogonal to each other; I N With Q P Q N They are also intersecting each other.

[0049] In this embodiment, the circuit structure of the polyphase filter is not limited, as long as it can achieve orthogonal decomposition of multiple original differential signals. For example, in a typical solution of this embodiment, such as... Figure 3 As shown, a polyphase filter can be constructed from four capacitors C1~C4 and four resistors R1~R4. The positive phase signal OUT of the original differential signal... P The signals are connected to the upper plates of C1 and C2, and one end of R1 and R2, respectively; the inverted signal OUT of the original differential signal. N It is then connected to the upper plates of C3 and C4, as well as one end of R3 and R4. The lower plate of C4 is connected to the other end of R1 and outputs a quadrature signal Q. PThe lower-level board of C1 is connected to the other end of R2 and outputs an orthogonal signal I. P The lower-level board of C2 is connected to the other end of R3 and outputs a quadrature signal Q. N The lower-level board of C3 is connected to the other end of R4 and outputs a quadrature signal I. N The polyphase filter decomposes the four orthogonal signals Q. P Q N I P I N The output is fed into a phase interpolator to achieve fine phase adjustment.

[0050] In this embodiment, the phase interpolator includes two gating units, multiple signal interpolation circuits, a capacitor C0, and a buffer. The phase interpolator uses the two sets of numerator signals from the four orthogonal signals as inputs to the two gating units. Each gating unit selects one input, resulting in two outputs. In the digital circuit of this embodiment, both gating units are 2-to-1 selectors. Each gating unit can select one of the numerator signals from the two inputs based on a 1-bit binary code for output. Therefore, under the control of a 2-bit control code, the two gating units in this embodiment can generate four different output types. P I P >、 P I N >、 N I P >and N I N In the four modes described above, the two output signals are all orthogonal signals, thus enabling orthogonal vector synthesis. Based on this, the phase interpolator in this embodiment can further expand the accuracy range of phase adjustment in the reconstructed signal to... .

[0051] In this embodiment, the two gating units in the phase interpolator actually constitute a special 4-to-2 selector, which can output two specified orthogonal sub-signals from four orthogonal sub-signals based on a 2-bit binary code. In this embodiment, the selector is implemented by two 2-to-1 selectors; in other embodiments, it can also be implemented by other complex logic circuits.

[0052] Furthermore, in this embodiment, the circuit structure of the two gating units in the phase interpolator is not limited, as long as they are both 2-to-1 selectors and can select one of the two input signals for output based on a single bit of binary code. For example, in a typical scheme of this embodiment, such as Figure 3 ​​​​As shown, the gating unit in the phase interpolator consists of two transmission gates TG1 and TG2 and one inverter INV1. The inputs of TG1 and TG2 serve as the input ports for the two inverted signals in the numerator signal, respectively; the outputs of TG1 and TG2 are connected and serve as the output ports for the gating signal; the inverting control terminal of TG1 is connected to the non-inverting control terminal of TG2; the non-inverting control terminal of TG1 is connected to the inverting control terminal of TG2 and the output terminal of INV1; the input terminal of INV1 is the control signal for the gating logic.

[0053] In practical applications, inverter INV1 and transmission gates TG1 and TG2 can each be constructed using one NMOS transistor and one PMOS transistor. Therefore, as Figure 4 As shown, the gating circuit in the phase interpolator of this embodiment can be composed of at least 12 MOS transistors, namely 6 NMOS transistors and 6 PMOS transistors.

[0054] The two orthogonal sub-signals output from the gating circuit are synchronously input into all signal interpolation circuits. Each signal interpolation circuit is controlled by an independent binary control code to adjust its switching state. Each activated signal interpolation circuit performs interpolation on the two input signals to obtain the corresponding output signal. The outputs of each signal interpolation circuit are connected to the upper plate of C0 and the input of the buffer; the lower plate of C0 is grounded. The output of the buffer is used to output the phase-modulated output signal PIout.

[0055] In practical applications, the signal interpolation circuit in a phase interpolator can employ any of three types: current-type interpolation, voltage-type interpolation, or integral interpolation. Since the former two suffer from sensitivity to PVT and low linearity, integral interpolation is preferred in practical applications. In a phase interpolator, each integral interpolation path is activated according to its corresponding control code, and its output current is used to charge capacitor C0. Therefore, by integrating the phase-shift weighted current source, the phase interpolator can generate a voltage slope with high phase linearity. The buffer then evaluates these waveforms within a constant slope region, producing a linearly interpolated output, ultimately resulting in a precisely phase-modulated signal PIout.

[0056] The reconstruction circuit in this embodiment is essentially a demand-oriented circuit module. It adaptively adjusts the accuracy levels of the phase interpolator and multi-stage attenuator based on the design requirements for the phase and attenuation accuracy of the corrected signal, thus meeting the accuracy requirements. Specifically, in the phase interpolator, the number of signal interpolation circuits can be adaptively adjusted according to the reconstruction circuit's requirements for the phase accuracy of the corrected signal. For example, when the number of integral interpolation circuits is four, the phase accuracy can be improved to [a higher level]. When the number of integral interpolation circuits is 5, the phase accuracy can be improved to [percentage missing]. .

[0057] Based on the control logic of the gating circuit and the signal interpolation circuit, assuming that the number of signal interpolation circuits in the phase interpolator used in this embodiment is n, then the phase interpolator requires a total of n+2 bits of phase control code to achieve the desired result. Phase accuracy at the highest level. For example, the aforementioned 7-bit phase interpolator uses 2-bit control codes to adjust the output logic of the gating circuit, and then uses 5-bit control codes to adjust the activation state of the five signal interpolation circuits, ultimately achieving a phase modulation accuracy of up to 2.812°.

[0058] In practical applications, this embodiment does not limit the circuit structure of the signal interpolation circuit; it can utilize various existing optimized circuit designs. In the typical solutions provided in this embodiment, such as... Figure 5 As shown, the integration interpolation circuit can be composed of four PMOS transistors P1~P4, four NMOS transistors N1~N4, and one inverter INV2. The sources of P1 and P2 are connected to VDD, and the drain of P1 is connected to the source of P3; the drain of P2 is connected to the source of P4; the source of N1 is connected to the drain of N3; and the source of N2 is connected to the drain of N4. The sources of N3 and N4 are grounded; P1 and N3 are connected and serve as one of the input ports IN. Q P2 and N4 are connected and used as another input port IN. I The gates of P3 and N2 are connected to the output terminal of INV2; the gates of P4 and N1 are connected to the input terminal of INV2 and serve as control port S. The drains of P3, P4, N1, and N2 are connected and serve as output port OUT.

[0059] In this embodiment, the multi-stage attenuator is composed of multiple attenuation circuits with different attenuation amplitudes cascaded in a preset order. It is used to amplitude modulate the input PIout signal to generate the required correction signal. In practical applications, a suitable number of attenuation circuits can be selected based on the accuracy requirements of the reconstruction circuit for the correction signal amplitude. Then, by rationally selecting attenuation circuits with different attenuation amplitudes and optimizing the cascading order, the final multi-stage attenuator is obtained, ensuring that the attenuation accuracy and amplitude linearity of the circuit's output signal meet the requirements.

[0060] Specifically, in practical applications, the attenuation circuits in a multi-stage attenuator can be selected from any of the following structures based on the difference in attenuation amplitude: Π-type, T-type, and simplified T-type. The number of attenuation circuits is adaptively set according to the preset attenuation accuracy requirements. For small attenuation amplitudes, simplified T-type and T+-type structures are preferred because they have only one path to ground. For large attenuation amplitudes, Π-type structures are preferred because they have two paths to ground. This embodiment allows selection of the structure of each attenuation module based on engineering requirements, with attenuation accuracy and attenuation linearity as the main indicators. Furthermore, because the attenuator's switching between reference and attenuation states causes changes in port impedance, it affects the preceding and following stages. Therefore, to minimize this impact and ensure system stability, this embodiment places attenuation units with smaller port impedance changes at both ends, while placing attenuation units with more drastic port impedance fluctuations inside. By rationally allocating the cascading order of the attenuation units, the simplicity of the circuit structure is ensured (no additional capacitors or inductors are needed for matching between preceding and following stages), while simultaneously meeting practical engineering requirements and exhibiting good attenuation accuracy and linearity.

[0061] Specifically, in practical applications, a multi-stage attenuator with an attenuation accuracy of 0.25dB can be implemented using a seven-stage attenuator. Considering that each attenuation stage requires an independent binary code for switching state adjustment, the seven-stage attenuator in this embodiment can also be called a 7-bit attenuator. Figure 6 As shown, the seven-stage attenuator designed in this embodiment is composed of cascaded attenuation circuits with attenuation accuracies of 0.5dB, 16dB, 2dB, 4dB, 8dB, 1dB, and 0.25dB. The 0.25dB, 0.5dB, 1dB, and 2dB attenuation circuits use a simple T-type structure consisting of one NMOS transistor and one resistor. The 4dB and 8dB attenuation circuits use a T-type structure consisting of two NMOS transistors and three resistors; and the 16dB attenuation circuit uses a Π-type structure consisting of three NMOS transistors and three resistors.

[0062] In this embodiment, as Figure 7 As shown, the simple T-type attenuation circuit consists of one NMOS transistor N5 and one resistor R5. The drain of N5 serves as both the signal input and output terminal; the gate of N5 is connected to the start signal SW; the source of N5 is connected to one end of R5, and the other end of R5 is grounded.

[0063] The T-type attenuation circuit consists of two NMOS transistors N6 and N7 and three resistors R6, R7, and R8. The drain of N6 is connected to one end of R6 and serves as the signal input port. The other end of R6 is connected to one end of R7 and the drain of N7. The other end of R7 is connected to the source of N6 and serves as the signal output port. The source of N7 is connected to one end of R8. The other end of R8 is grounded. The gate of N7 is connected to the start signal SW, and the gate of N6 is connected to the inverted signal of SW.

[0064] The Π-type attenuation circuit consists of three NMOS transistors N8, N9, and N10 and three resistors R9, R10, and R11. The drains of N8 and N9 are connected to one end of R9 and serve as signal input ports. The source of N8 is connected to the drain of N10 and the other end of R9 and serves as a signal output port. The source of N9 is grounded through R10. The source of N10 is grounded through R11. The gates of N9 and N10 are connected to the start signal SW. The gate of N8 is connected to the inverted signal of SW.

[0065] In the digital radio frequency reconstruction circuit for suppressing antenna leakage provided in this embodiment, the operating modes of the phase interpolator and multi-stage attenuators are adjusted collaboratively through multiple phase control codes (such as S<1:7>) and amplitude control codes (such as SW<1:7>); thereby generating a corresponding correction signal based on the input leakage signal. Two bits of the phase control code serve as control signals to switch the gating logic of the two gating units, while the remaining bits control the activation state of each signal interpolation circuit. From the gating circuit to the signal interpolation circuit, the phase of the correction signal is finely adjusted step by step, thereby improving phase control accuracy. The bits of the amplitude control code, from high to low, sequentially control the activation state of each attenuator with an attenuation amplitude from low to high. The switching of the control signal for each attenuation unit changes the degree of signal attenuation; each cascaded unit can achieve a different attenuation amplitude, thus achieving precise attenuation.

[0066] In practical applications, for each operating condition's leakage signal, the digital radio frequency reconstruction circuit uses a set of corresponding phase control codes and amplitude control codes to generate a correction signal with opposite phase and equal amplitude that meets the accuracy requirements based on the leakage signal. Specifically, under a given leakage signal condition, the values ​​of each bit in the phase control code and amplitude control code can be generated using a binary search strategy. In detail, based on the aforementioned signal phase modulation and amplitude modulation control logic, the process of high-precision reconstruction of the correction signal by the digital radio frequency reconstruction circuit for suppressing antenna leakage provided in this embodiment includes the following steps:

[0067] (1) Initialize the amplitude control code of the multi-stage attenuator to a fixed setting. For example, it can be set to half the maximum binary code value. This ensures that the amplitude of the output corrected signal is precisely controlled within a preset specific value range. This operation ensures that the signal amplitude is in a relatively stable state that is easy for subsequent processing.

[0068] (2) Fine-tuning the phase digital control code of the phase interpolator; the fine-tuning process can adopt a binary search strategy to reduce the number of adjustments and improve search efficiency. During the adjustment process, closely observe the output node of the oscillator. In this way, the phase of the signal used to eliminate interference is precisely adjusted to be opposite to the phase of the antenna leakage signal, that is, the phase difference between the two reaches 180°.

[0069] (3) Fine-tune the attenuator again; the fine-tuning process can use a binary search strategy to reduce the number of adjustments and improve search efficiency. The purpose of this adjustment is to make the signal amplitude on the elimination loop as close as possible to the amplitude of the antenna leakage signal in order to achieve the best amplitude matching effect.

[0070] After the precise adjustment of the signal amplitude and phase described above, the corrected signal reconstructed by the circuit is superimposed on the received signal inside the oscillator. Since the corrected signal is highly matched to the antenna leakage signal in both amplitude and phase, the superposition of the two signals can effectively cancel each other out, thereby eliminating the interference of the antenna leakage signal.

[0071] Example 2

[0072] Based on the digital RF reconstruction circuit for suppressing antenna leakage provided in Embodiment 1, this embodiment further provides a reconstruction module for corrected signals. The circuit module in this embodiment is of two types: one is for antenna systems with a finite number of fixed operating conditions, which incorporates control codes and their mapping relationships for all pre-matched corrected signals, thereby automatically switching to a specified mode based on real-time operating conditions to suppress antenna leakage signals. The other type is for high-performance antenna systems with unlimited operating conditions. It incorporates specific signal detection and search logic, which can match the received leakage signal with the reconstructed corrected signal and actively search for the appropriate control codes for the reconstruction process through feedback adjustment.

[0073] Specifically, such as Figure 8 As shown, the reconstruction module for the corrected signal provided in this embodiment includes a digital radio frequency reconstruction circuit for suppressing antenna leakage as in Embodiment 1, and further includes a control code selection circuit or a control code search circuit.

[0074] The control code selection circuit has a preset mapping relationship between leakage signals and appropriate control codes under various specified operating conditions. It is used to select the appropriate control code according to the current operating condition and to adjust the working mode of the phase interpolator and multi-stage attenuator in the digital radio frequency reconstruction circuit to generate an appropriate correction signal.

[0075] The control code search circuit is used to obtain the leakage signal input to the digital RF reconstruction circuit and the correction signal output. It then uses a binary search strategy to adjust the control code until the generated correction signal matches the leakage signal under the current operating conditions.

[0076] In practical applications, the reconstructed correction signal module in this embodiment is a packaged and plug-and-play circuit module that can be used to optimize and modify existing antenna systems or to improve the leakage resistance of newly manufactured antenna systems.

[0077] Example 3

[0078] Based on the scheme in Example 1, such as Figure 9 As shown, this embodiment further provides a radar transceiver system, which includes a signal transmitter, a signal receiver, an oscillator, a phase-locked loop (PLL), and a digital signal processing module. The PLL is composed of a digital loop filter, a frequency and phase detector, and a frequency divider. Furthermore, it includes a digital radio frequency reconstruction circuit for suppressing antenna leakage, as described in Embodiment 1. This circuit generates a correction signal with opposite phase and equal amplitude based on the leakage signal acquired from the signal transmitter side; and outputs it to the oscillator to superimpose it with the received signal from the signal receiver side, thereby eliminating leakage noise in the radio frequency transceiver.

[0079] Unlike the scheme in Embodiment 2, the antenna system in this embodiment directly integrates the digital radio frequency reconstruction circuit for suppressing antenna leakage from Embodiment 1 into the antenna system itself. Existing antenna systems with antenna leakage suppression capabilities may significantly degrade the receiver's noise figure during operation, leading to a decrease in overall receiver performance. In the integrated scheme of this invention, when the antenna leakage signal enters the circuit, the circuit processes the signal and then combines the processed signal with the useful signal received by the receiver. During this process, the circuit minimizes the impact on the receiver's noise figure and input matching performance; this ensures stable receiver operation, maintains the receiver's low-noise performance, and improves the quality and sensitivity of the received signal.

[0080] Performance testing

[0081] To verify the performance of the digital radio frequency reconstruction circuit for suppressing antenna leakage provided by this invention, technicians conducted simulations and performance tests on the relevant circuit modules and radar transceiver system using a 22nm CMOS process.

[0082] 1. Basic performance

[0083] This experiment uses Virtuoso design software to complete the layout design based on the circuit diagram above. The following figure shows the layout of the multiphase filter, phase interpolator and attenuator respectively. The working performance of each module can be verified by extracting parasitic parameters from the layout.

[0084] Figure 10 The image shows the phase modulation performance of the phase interpolator. The specific verification method involves performing transient simulations on the PI module and capturing the corresponding phase for each CNC code condition. Analysis of the data in the image reveals that the phase interpolator of this invention can cover a phase modulation range of 0-360° and can be adjusted according to the leakage signal under different phases. Simultaneously, it can be seen that the phase modulation accuracy of the phase interpolator reaches [a certain level]. It has relatively superior phase modulation linearity, which has a huge advantage in practical engineering.

[0085] Figure 11 This image shows the amplitude modulation performance of the attenuator section in this invention. The specific verification method involves simulating the transmission characteristics of the attenuator module for each corresponding digital control code, with the specific values ​​representing the attenuation amplitude. Analysis of the data in the image reveals that the attenuator of this invention can cover a dynamic attenuation range of 31.75 dB, capable of handling different leakage signals with a maximum difference of 31.75 dB. In practical applications, it can effectively handle leakage signals of varying amplitudes. Simultaneously, it can be seen that the attenuator's amplitude modulation accuracy reaches 0.25 dB, exhibiting relatively superior amplitude modulation linearity and enabling higher-precision antenna leakage elimination.

[0086] Figure 12 This diagram illustrates the antenna leakage suppression effect of the circuit scheme of this invention in application. The specific verification approach involves sending a -40dB signal from the transmitting end of the radar system to the receiving end, and determining the actual signal amplitude reaching the demodulation module of the radar system by testing the amplitude of the signal at the injection port of the oscillator. Analysis of the data in the diagram reveals that when both phase and amplitude errors are controlled within 2 LSBs, the actual injected signal amplitude can be reduced to -60dB. The best elimination performance is achieved when the corrected signal and the leakage signal have opposite phases and the same amplitude.

[0087] 2. Area and power consumption

[0088] Experiments revealed that the solution of this invention can be manufactured using a 22nm CMOS process, resulting in smaller transistor size and lower power consumption. Compared to traditional processes, it can achieve the same functionality on a smaller chip area. The 7-bit attenuator and 7-bit phase interpolator employ optimized circuit design, reducing unnecessary components and complex wiring, thereby further reducing the chip area. Simultaneously, these components also exhibit low power consumption during operation. Specifically, in the 22nm CMOS process, the attenuator corresponds to an area of ​​227μm. 2 The phase interpolator corresponds to an area of ​​0.01 mm². 2 The attenuator consumes 0.23mW and the phase interpolator consumes 2.97mW, meeting the requirements of modern electronic devices for high integration and low power consumption.

[0089] 3. Frequency band and accuracy

[0090] Experiments have shown that the circuit scheme of this invention can operate at high frequencies of 19-21 GHz in practical applications, covering a wide frequency band. Specifically, by comprehensively utilizing a 7-bit phase interpolator and a 7-bit multi-stage attenuator, the phase modulation accuracy reaches 2.81°, and the amplitude modulation accuracy reaches 0.25 dB; it can cover a range of 31.75 dB and 180°, and can generate correction signals with high precision, thus improving the antenna leakage elimination effect.

[0091] The above-described embodiments are merely one implementation of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A digital radio frequency reconstruction circuit for suppressing antenna leakage, mainly comprising a polyphase filter for receiving a set of original differential signals representing leakage signals in an antenna system and decomposing them into four quadrature signals according to phase; a phase interpolator comprising a gating circuit, a plurality of signal interpolation circuits, a capacitor C0 and a buffer Buffer; the gating circuit is used to gate two quadrature signals from the four quadrature signals according to a control signal and synchronously output them to all signal interpolation circuits; each enabled signal interpolation circuit performs interpolation operation on the input two signals to obtain a corresponding output signal; the output end of each signal interpolation circuit is connected with the upper plate of C0 and the input end of Buffer, and the lower plate of C0 is grounded; the output end of Buffer is used to output the phase-modulated output signal PIout; a multi-stage attenuator, which is formed by cascading a plurality of attenuation circuits with different attenuation amplitudes in a preset order, and is used to amplitude-modulate the input PIout signal to generate a required correction signal; The working modes of the phase interpolator and the multi-stage attenuator are adjusted by the multi-phase control code and the amplitude control code, and then a corresponding correction signal is generated according to the input leakage signal. two bits of the phase control code are used as control signals of the gating logic of the two gating units, and the remaining bits are used to control the enable state of each signal interpolation circuit; the bits of the amplitude control code from high to low are used to control the enable state of each attenuator with attenuation amplitude from low to high in turn.

2. The digital RF reconstruction circuit to suppress antenna leakage of claim 1, wherein: The multi-phase filter is composed of four capacitors C1-C4 and four resistors R1-R4; wherein the positive phase signal of the original differential signal is connected with the upper plate of C1 and C2 and one end of R1 and R2; the negative phase signal of the original differential signal is connected with the upper plate of C3 and C4 and one end of R3 and R4; the lower plate of C4 is connected with the other end of R1 and outputs quadrature signal Q P ; the lower plate of C1 is connected with the other end of R2 and outputs quadrature signal I P ; the lower plate of C2 is connected with the other end of R3 and outputs quadrature signal Q N ; the lower plate of C3 is connected with the other end of R4 and outputs quadrature signal I N ; wherein Q P and Q N constitute a set of differential sub-signals; I P and I N constitute another set of differential sub-signals.

3. The digital radio frequency reconstruction circuit for suppressing antenna leakage according to claim 1, characterized in that: the gating circuit in the phase interpolator comprises two 2-to-1 gating units, and two sets of differential sub-signals contained in the four quadrature signals are respectively used as the inputs of the two gating units; the gating unit is composed of two transmission gates TG1 and TG2 and one inverter INV1; the input ends of TG1 and TG2 are respectively used as the input ports of two quadrature signals in the differential sub-signals; the output ends of TG1 and TG2 are connected and used as the output ports of the gating signal; the inverting control end of TG1 is connected with the non-inverting control end of TG2; the non-inverting control end of TG1 is connected with the inverting control end of TG2 and the output end of INV1; the input end of INV1 is used as the control signal of the gating logic; the signal interpolation circuit adopts any one of a current-mode interpolation circuit, a voltage-mode interpolation circuit and an integral interpolation circuit.

4. The digital RF reconstruction circuit to suppress antenna leakage of claim 3, wherein: The integral interpolation circuit is composed of 4 PMOS tubes P1~P4, 4 NMOS tubes N1~N4 and 1 inverter INV2; the source of P1 and P2 is connected with VDD, the drain of P1 is connected with the source of P3, the drain of P2 is connected with the source of P4; the source of N1 is connected with the drain of N3; the source of N2 is connected with the drain of N4; the source of N3 and N4 is connected with ground; P1 and N3 are connected and serve as one of input ports IN Q ; P2 and N4 are connected and serve as another input port IN I ; the gate of P3 and N2 is connected with the output end of INV2; the gate of P4 and N1 is connected with the input end of INV2 and serves as a control port S; the drain of P3, P4, N1 and N2 is connected and serves as an output port OUT.

5. The digital RF reconstruction circuit to suppress antenna leakage of claim 1, wherein: In the multi-stage attenuator, each attenuation circuit selects any one of Π type structure, T type structure and simple T type structure according to the difference of attenuation amplitudes; the number of attenuation circuits is adaptively set according to the preset attenuation accuracy requirement; and / or, in the multi-stage attenuator, by reasonably selecting the attenuation circuits with different attenuation amplitudes and optimizing the cascade order, the attenuation accuracy and amplitude linearity of the circuit output signal meet the requirements.

6. The digital RF reconstruction circuit to suppress antenna leakage of claim 5, wherein: The multi-stage attenuator with 0.25dB attenuation precision is implemented by a seven-stage attenuator; the seven-stage attenuator is sequentially formed by cascading attenuation circuits with 0.5dB, 16dB, 2dB, 4dB, 8dB, 1dB and 0.25dB attenuation precision; wherein the attenuation circuits with 0.25dB, 0.5dB, 1dB and 2dB attenuation precision are simple T-shaped structure attenuation circuits formed by one NMOS transistor and one resistor; the attenuation circuits with 4dB and 8dB attenuation precision are T-shaped structure attenuation circuits formed by two NMOS transistors and three resistors; and the attenuation circuit with 16dB attenuation precision is a Π-shaped structure attenuation circuit formed by three NMOS transistors and three resistors.

7. The digital RF reconstruction circuit to suppress antenna leakage of claim 6, wherein: The simple T-shaped structure attenuation circuit is formed by one NMOS transistor N5 and one resistor R5; the T-shaped structure attenuation circuit is formed by two NMOS transistors N6, N7 and three resistors R6, R7, R8; and the Π-shaped structure attenuation circuit is formed by three NMOS transistors N8, N9, N10 and three resistors R9, R10, R11.

8. The digital RF reconstruction circuit to suppress antenna leakage of claim 7, wherein: For the leakage signal under each working condition, the digital radio frequency reconstruction circuit generates a correction signal with opposite phase and equal amplitude according to the leakage signal by using a corresponding set of phase control codes and amplitude control codes; Wherein, under the specified leakage signal condition, the values of each bit in the phase control code and the amplitude control code are generated by using a search strategy based on the bisection method.

9. A reconstruction module for correcting a signal, characterized by: It comprises the digital radio frequency reconstruction circuit for suppressing antenna leakage as claimed in any one of claims 1-7, and further comprises a control code selection circuit or a control code search circuit; The control code selection circuit is pre-provided with a mapping relationship between leakage signals under various specified working conditions and adaptive control codes, and is used for selecting a corresponding control code according to a current working condition, and adjusting the working modes of the phase interpolator and the multi-stage attenuator in the digital radio frequency reconstruction circuit to generate an adaptive correction signal; The control code search circuit is used for obtaining the leakage signal input into the digital radio frequency reconstruction circuit and the correction signal output therefrom, and adjusting the control code by using a search strategy based on the bisection method until the generated correction signal is adapted to the leakage signal under the current working condition.

10. A radar transceiver system, characterized by It comprises a signal transmitter, a signal receiver, an oscillator and a phase-locked loop, and further comprises a digital radio frequency reconstruction circuit for suppressing antenna leakage as claimed in any one of claims 1-7; the digital radio frequency reconstruction circuit for suppressing antenna leakage is used for generating a correction signal with opposite phase and equal amplitude according to the leakage signal collected on the side of the signal transmitter; and outputting the correction signal to the oscillator to be superimposed with the received signal on the side of the signal receiver, thereby eliminating the leakage noise in the radio frequency transceiver.

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