Firmware management method and electronic device

Abstract

The application discloses a firmware management method and electronic equipment, and relates to the technical field of server firmware management. Through single-point triggering, dynamic topology construction and multi-link collaborative transmission mechanism, the application realizes full-process automation and parallelization refreshing of processor firmware in a small AI server cluster, improves the firmware file transmission rate, reduces manual intervention and operation and maintenance cost, and ensures efficient and reliable refreshing process without affecting the cluster business load through compatible homogeneous / heterogeneous mixed link environment, thereby improving the overall refreshing efficiency of firmware in the server cluster.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of server firmware management, and particularly relates to a firmware management method and an electronic device. BACKGROUND

[0002] An AI (Artificial Intelligence) server is a core computing platform for artificial intelligence algorithms, and provides super large-scale parallel computing capability by virtue of a heterogeneous hardware architecture and software optimization, and is widely applied to scenarios such as model training, inference services, scientific computing and enterprise AI platforms. A GPU (Graphics Processing Unit) is a core component of the hardware architecture of the AI server, and a GPU firmware is a bottom-layer software embedded in the hardware, and is responsible for key functions such as hardware initialization, power management, error detection, performance optimization and security control. Security vulnerabilities can be repaired, performance can be optimized, functions can be extended and compatibility can be improved through firmware updating. Related GPU firmware refreshing modes include manufacturer tool refreshing, operating system integrated management refreshing or out-of-band remote refreshing through IPMI (Intelligent Platform Management Interface) instructions by means of a baseboard management controller. However, there are obvious problems: first, the degree of automation is low, and most schemes rely on manual operation on a per-device basis, which is inefficient and prone to errors; second, the transmission rate is limited, and especially when a low-speed out-of-band management link is used, the firmware file transmission speed is only at the level of KB / s, which seriously affects the timeliness of large-scale refreshing; third, the adaptability to a heterogeneous mixed link environment is poor, and it is difficult to support different interconnection modes or different manufacturer GPU devices in the same operation; and fourth, centralized management schemes usually need to rely on special large-scale management software, which is not suitable for small cluster scenarios that lack such software support, resulting in high operation and maintenance costs and limited scalability. SUMMARY

[0003] The present application provides a firmware management method and an electronic device to at least solve the problems of strong manual dependence, low transmission efficiency and lack of automated collaborative management in the GPU firmware refreshing process in a small AI server cluster in the related art.

[0004] The present application provides a firmware management method, comprising:

[0005] In response to receiving a processor firmware refreshing request, the processor firmware refreshing request is parsed, and according to the parsing result, a server cluster is determined, and the processor firmware file is included in the processor firmware refreshing request;

[0006] A target processor in the server cluster is selected, the target processor is defined as a master processor, and a firmware refreshing process is performed on the master processor based on the processor firmware file;

[0007] In response to the firmware refreshing procedure being executed completely, the server cluster is processor link addressed based on the master processor to construct a processor topology structure, the processor topology structure including the master processor and the slave processor.

[0008] Based on the processor topology structure, the processor firmware file is transmitted to the slave processor, and the firmware refreshing procedure is executed on the slave processor based on the processor firmware file.

[0009] The application further provides an electronic device, including a memory for storing a computer program, and a processor for executing the computer program to implement the following steps of the firmware management method.

[0010] In response to receiving a processor firmware refreshing request, the processor firmware refreshing request is parsed, and based on the parsing result, a server cluster is determined, the processor firmware refreshing request including a processor firmware file;

[0011] A target processor in the server cluster is selected, the target processor is defined as a master processor, and a firmware refreshing procedure is executed on the master processor based on the processor firmware file;

[0012] In response to the firmware refreshing procedure being executed completely, the server cluster is processor link addressed based on the master processor to construct a processor topology structure, the processor topology structure including the master processor and the slave processor;

[0013] Based on the processor topology structure, the processor firmware file is transmitted to the slave processor, and the firmware refreshing procedure is executed on the slave processor based on the processor firmware file.

[0014] The application further provides a computer readable storage medium, the computer readable storage medium storing a computer program, wherein the computer program is executed by a processor to implement the following steps of the firmware management method.

[0015] In response to receiving a processor firmware refreshing request, the processor firmware refreshing request is parsed, and based on the parsing result, a server cluster is determined, the processor firmware refreshing request including a processor firmware file;

[0016] A target processor in the server cluster is selected, the target processor is defined as a master processor, and a firmware refreshing procedure is executed on the master processor based on the processor firmware file;

[0017] In response to the firmware refreshing procedure being executed completely, the server cluster is processor link addressed based on the master processor to construct a processor topology structure, the processor topology structure including the master processor and the slave processor;

[0018] Based on the processor topology, the processor firmware file is transmitted to the slave processor, and a firmware update process is performed on the slave processor based on the processor firmware file.

[0019] The application also provides a computer program product comprising a computer program which, when executed by a processor, implements the following steps of the firmware management method:

[0020] In response to receiving the processor firmware update request, the processor firmware update request is parsed, and based on the parsing result, a server cluster is determined, and the processor firmware update request includes a processor firmware file;

[0021] A target processor in the server cluster is selected, the target processor is defined as a master processor, and a firmware update process is performed on the master processor based on the processor firmware file;

[0022] In response to the firmware update process being completed, the server cluster is addressed by the master processor based on the processor link to construct a processor topology, and the processor topology includes the master processor and the slave processor;

[0023] Based on the processor topology, the processor firmware file is transmitted to the slave processor, and a firmware update process is performed on the slave processor based on the processor firmware file.

[0024] The application realizes the full-process automation and parallelization of processor firmware in a small AI server cluster through a single-point trigger, dynamic topology construction and multi-link cooperative transmission mechanism, improves the firmware file transmission rate, reduces manual intervention and operation and maintenance costs, and ensures efficient and reliable refresh process without affecting the cluster business load through compatible homogeneous / heterogeneous mixed link environment, and improves the overall refresh efficiency of firmware in the server cluster. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0026] Figure 1 An application environment diagram of a firmware management method is provided for the embodiments of the application;

[0027] Figure 2 An overall flowchart of a firmware management method is provided for the embodiments of the application;

[0028] Figure 3 Another overall flowchart of a firmware management method is provided for the embodiments of the application;

[0029] Figure 4 A topological structure diagram provided for an embodiment of the present application;

[0030] Figure 5 An application scenario diagram provided for an embodiment of the present application;

[0031] Figure 6 An internal structure diagram of an electronic device in an embodiment. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0033] It should be noted that, in the description of the present application, the terms “comprise”, “contain” or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0034] It should be noted that the terms “S1”, “S2” and the like are only used for the purpose of describing the steps, and do not specifically refer to the order or sequence, nor limit the present application. They are only used to facilitate the description of the method of the present application, and cannot be understood as indicating the sequence of the steps. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the realization of those of ordinary skill in the art. When the combination of technical solutions contradicts each other or cannot be realized, it should be considered that the combination of technical solutions does not exist, nor is it within the protection scope of the present application.

[0035] According to the background art, the AI server is a high-performance computing platform specially designed for artificial intelligence algorithms, especially deep learning. Through heterogeneous hardware architecture and software optimization, it provides super-large-scale parallel computing capability to solve the computing power bottleneck of servers in AI tasks. Its core goal is to accelerate model training and inference, support trillion-parameter models, real-time AI services, etc. For example, in model training, super-large-scale language models (GPT-4, PaLM2) require thousands of GPU parallel training, and computer vision models (such as diffusion models, 3D reconstruction) rely on high memory bandwidth. In inference services, autonomous driving real-time perception and natural language processing APIs require low-latency responses. In scientific computing, protein folding prediction (AlphaFold) and climate simulation (EC-Earth) combine AI optimization algorithms. In enterprise AI platforms, financial risk control and medical image analysis require private AI services to ensure data security. The core component of the hardware architecture of the AI server is the GPU. The mainstream choice (such as NVIDIA H100) is good at floating-point operations and supports the CUDA (General Purpose Parallel Computing Platform and Programming Model) ecosystem. There are two modes of GPU interconnection: NVLink mode and PCIE (Peripheral Component Interconnect Express) mode. The main difference between the two modes is the communication method between GPUs. GPU firmware (Firmware, abbreviated as FW) is the underlying software code embedded in the graphics processor hardware, responsible for controlling the initialization of the GPU, hardware operation, function optimization, and interaction with other components of the system (such as drivers and operating systems). Its core functions include the following aspects:

[0036] (1) Hardware initialization and configuration, startup phase: GPU firmware is executed when the system is powered on, initializing core circuits, memory controllers, clock frequencies, and other hardware modules to ensure that the GPU enters a usable state; resource configuration: setting register parameters, allocating memory address space, configuring PCIe / NVLink interfaces, etc., providing a hardware abstraction layer for operating systems and drivers.

[0037] (2) Power management and energy efficiency optimization, dynamic frequency and voltage adjustment: dynamically adjusting the GPU core frequency and voltage according to the load (such as NVIDIA GPUBoost technology), balancing performance and power consumption, and controlling low-power modes (such as standby state) to reduce energy consumption during idle time.

[0038] (3) Error detection and fault tolerance mechanism, hardware self-test (POST): detects memory errors, temperature sensor abnormalities, and other hardware faults during startup; ECC error correction (instruction error correction): real-time correction of single-bit errors in memory (common function in enterprise-level GPUs); fault recovery: triggers a reset or falls back to a safe state when the GPU crashes to prevent system crashes.

[0039] (4) Performance optimization and function expansion, algorithm acceleration: solidify commonly used computing instructions (such as matrix operations in AI reasoning), improve the execution efficiency of specific tasks; overclocking support: open firmware interface allows users to adjust frequency and voltage (requires manufacturer authorization); new function activation: unlock hidden hardware functions (such as ray tracing unit optimization) through firmware updates; security and permission control; Secure Boot: verify firmware signature to prevent malicious code injection; firmware encryption: protect firmware update package from reverse engineering or tampering (such as AMD's PSP security co-processor); hardware-level isolation: divide security partitions (such as NVIDIA's GPUSafe) to protect sensitive computing tasks.

[0040] Therefore, GPU manufacturers can solve the following problems through GPU FW updates:

[0041] (1) Security vulnerability fixes, manufacturers regularly release patches to fix hardware-level vulnerabilities (such as Spectre variants, physical attack protection), for example, NVIDIA has fixed GPU memory access vulnerabilities through firmware updates;

[0042] (2) Performance optimization, update power management strategies, memory bandwidth allocation algorithms, or optimize computing unit scheduling for new frameworks (such as PyTorchLightning);

[0043] (3) Function expansion, support new protocols (such as PCIe5.0), virtualization and multi-instance GPU (MIG) configuration, or enable hardware-level sparsity acceleration functions;

[0044] (4) Compatibility upgrade, adapt to new versions of drivers (such as CUDA12), operating systems (such as Ubuntu22.04) or containerization platforms (such as NVIDIA Triton).

[0045] Among them, the common update methods include:

[0046] (1) Refresh through manufacturer tools: such as NVIDIA's nvflash, AMD's ATIFlash;

[0047] (2) Refresh through integrated management by operating system: Windows pushes firmware updates through Device Manager;

[0048] (3) Update through BMC IPMI out-of-band: server GPUs often use baseboard management controllers for remote upgrades;

[0049] (4) Large-scale refresh through large management software integrated IPMI instructions, generally used in large AI cluster servers.

[0050] There are the following problems:

[0051] (1) Strong dependence on artificial: the device needs to be selected one by one and the upgrade is triggered manually, which is inefficient and prone to errors. For AI server clusters, especially small AI clusters, without the support of large management software, refreshing each device one by one is time-consuming and laborious.

[0052] (2) Low link utilization: when refreshing through IPMI instructions, the FW file is generally refreshed through I2C instructions, which is limited by the I2C link rate, and the rate is usually around 100KB, which is low in file transmission efficiency and affects the overall refresh time.

[0053] To solve the above technical problems, the application provides a firmware management method and an electronic device, which realizes the full-flow automation and parallelization of processor firmware refreshing in a small AI server cluster through single-point triggering, dynamic topology construction and multi-link collaborative transmission mechanism, improves the firmware file transmission rate, reduces the manual intervention and operation and maintenance cost, and ensures the refreshing process to be efficient, reliable and not to affect the cluster business load through compatible homogeneous / heterogeneous mixed link environment, thereby improving the overall refreshing efficiency of the firmware in the server cluster.

[0054] In order to make the person skilled in the art better understand the present application, the application will be further described in detail below in combination with the drawings and specific embodiments.

[0055] The firmware management method provided by the application can be applied to an application environment as shown in Figure 1 . The terminal 102 communicates with the data processing platform set on the server 104 through the network, wherein the terminal 102 can be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers and portable wearable devices, and the server 104 can be realized by an independent server or a server cluster composed of multiple servers.

[0056] As shown in Figure 2 , the embodiment of the application provides a firmware management method. Taking the terminal in Figure 1 as an example, the method comprises the following steps:

[0057] S1: In response to receiving a processor firmware refreshing request, the processor firmware refreshing request is parsed, and according to the parsing result, a server cluster is determined, and the processor firmware refreshing request includes a processor firmware file.

[0058] It should be noted that the processor firmware can refer to the GPU FW, which is the firmware for the GPU, refers to the underlying control software running in the non-volatile memory inside the processor (such as GPU), which is responsible for hardware initialization, power management, performance optimization and security functions, usually in the form of binary image file, which can be updated by flashing to fix vulnerabilities, improve performance or expand functions; The processor firmware flashing request refers to the instruction or data packet initiated by the user or the management system to update the specified processor firmware, usually including target processor identification, firmware file to be flashed, operation parameters (such as version number, flashing range) and optional scheduling strategy information; The server cluster refers to a computing resource pool logically integrated by multiple server nodes through network and high-speed interconnection link (such as InfiniBand, NVLink), in this application, it specifically refers to a set of target servers containing processors to be flashed, supporting unified management and collaborative task execution; The processor firmware file refers to a binary data file used to update the firmware inside the processor, usually containing the underlying control code, configuration parameters and verification information required for the processor to run, which is provided by the processor manufacturer or device manufacturer, and can be flashed into the non-volatile memory of the processor through a special tool or protocol, to achieve the purposes of security repair, performance optimization, function expansion or compatibility upgrade, etc.

[0059] S2: Select a target processor in the server cluster, define the target processor as a master processor, and execute a firmware flashing process on the master processor based on the processor firmware file.

[0060] It should be noted that the master processor refers to the processor selected as the control node in the firmware flashing process, which is responsible for coordinating firmware distribution, topology construction, flashing synchronization and other core tasks within the cluster, and usually needs to complete its own firmware flashing first to activate the control function.

[0061] S3: In response to the completion of the firmware flashing process, the server cluster is addressed based on the master processor to construct a processor topology structure, which includes the master processor and the slave processor.

[0062] It should be noted that processor link addressing refers to the process of actively discovering other processors within the cluster by the master processor through broadcasting, probing and other methods, and obtaining their connection paths, link types and communication quality, which is used to construct a network topology map reflecting the actual connection relationship between processors; The processor topology structure refers to a logical structure diagram constructed based on the link addressing result, describing the interconnection relationship of all processors within the server cluster. It contains processor nodes, connection links, link attributes and other elements, which are used to guide the optimal distribution path selection of the firmware file; The slave processor refers to the processor in a controlled state in the firmware flashing process, which receives firmware files and flashing instructions from the master processor, executes local firmware flashing operations, and feeds back the execution results to the master processor.

[0063] S4: Based on the processor topology, the processor firmware file is transferred to the slave processor, and the firmware flashing process is performed on the slave processor based on the processor firmware file.

[0064] In the above implementation, the fully automated and parallel refresh of processor firmware in a small AI server cluster is achieved through single-point triggering, dynamic topology construction and multi-link collaborative transmission mechanism, which improves the firmware file transmission rate, reduces manual intervention and maintenance costs, and ensures that the refresh process is efficient, reliable and does not affect the cluster business load by being compatible with homogeneous / heterogeneous hybrid link environments, thereby improving the overall firmware refresh efficiency in the server cluster.

[0065] In some specific implementations, selecting a target processor in the server cluster and defining the target processor as the master processor includes:

[0066] At least one evaluation metric is determined, which may include load balancing, topology centrality, hardware performance, and user policy coverage. Specifically, load balancing evaluation: real-time monitoring of the computing load, memory usage, and network I / O status of each processor in the cluster, and selecting the processor with the lowest overall load as the master processor; topology centrality evaluation: based on the pre-built processor interconnection topology, calculating the connectivity and link quality of each processor in the network, and selecting the processor with the highest topology centrality as the master processor; hardware performance evaluation: comparing the model, computing power specifications, firmware version, and stability history of each processor, and selecting the processor with the best overall hardware performance as the master processor; user policy coverage: if the firmware update request explicitly specifies the master processor identifier, then the user-specified identifier is used first, overriding the above automatic evaluation results.

[0067] Based on the evaluation metrics, multiple processors in the server cluster are evaluated to obtain the corresponding evaluation results. Multiple processors can be evaluated using a single evaluation metric or multiple evaluation metrics to obtain the final evaluation result. If multiple evaluation metrics are used, the values ​​corresponding to the multiple metrics are normalized, and then the normalized values ​​are weighted and summed to obtain the final evaluation result.

[0068] The multiple evaluation results are sorted, and the target processor is determined based on the sorting results. The target processor is defined as the master processor. If a single evaluation index is used to evaluate multiple processors, the corresponding processor is selected as the master processor based on the above evaluation results. If multiple evaluation indexes are used, the processor corresponding to the evaluation result with the highest sorting result is selected as the master processor. The firmware of the master processor is the firmware to be flashed.

[0069] In the above embodiments, the master processor is dynamically selected by the multi-dimensional and configurable evaluation index, ensuring the optimality, stability and flexibility of the refresh process control node, which not only improves the cluster resource utilization efficiency and refresh task reliability, but also takes into account the user's autonomous control needs, enhancing the system's adaptability in different hardware environments and operation and maintenance strategies.

[0070] In some embodiments, performing a firmware refresh process on the master processor based on the processor firmware file includes:

[0071] transmitting the processor firmware file to the server node where the master processor is located, determining a user-mode migratable computing task running on the master processor, suspending the user-mode migratable computing task, and backing up the current firmware version of the master processor, wherein the user-mode migratable computing task refers to a process / thread running in the user mode of the operating system and can be migrated to other processors by the scheduler;

[0072] verifying the integrity and accuracy of the processor firmware file, wherein the integrity and accuracy verification can be based on the digital signature, checksum or hash value of the processor firmware file to verify that the source is trustworthy, the content is complete and has not been tampered with, and to ensure that the file meets the compatibility requirements of the target processor;

[0073] in response to successful verification of the integrity and accuracy, writing the processor firmware file to the non-volatile memory of the master processor and triggering a master processor restart process;

[0074] in response to the completion of the restart, verifying whether the master processor firmware version is successfully refreshed, and synchronizing the refresh verification result of the master processor to the cluster state management system of the server cluster, wherein verifying whether the master processor firmware version is successfully refreshed is to compare the information of the backed-up current firmware version with the information of the refreshed firmware version, and if the comparison is unsuccessful, the refresh is successful.

[0075] In the above embodiments, by precisely controlling the load, securely verifying the firmware, reliably refreshing and verifying, the data integrity and process controllability of the master processor firmware refresh are ensured, the high security and low business interference of the update process are achieved, and a stable and reliable control node foundation is laid for subsequent cluster collaborative refresh.

[0076] In some embodiments, as shown in Figure 4 in response to the completion of the firmware refresh process, the processor link addressing of the server cluster based on the master processor is performed to construct the processor topology, including:

[0077] broadcasting a discovery instruction to a server cluster based on an interconnection link supported by the master processor, wherein the interconnection link can include a PCIe configuration space, an NVLink interface, or an IB network port, and the discovery instruction is used to determine GPUs of the same type within the cluster;

[0078] receiving response information of the discovery instruction returned by the slave processor in the same server as the master processor and by the slave processor in a different server from the master processor based on the discovery instruction, wherein the response information at least includes a processor identifier, a serial number, a firmware version, and a supported link type;

[0079] performing unique filtering on the slave processor returning the response information according to the serial number to remove the slave processor with repeated serial numbers, i.e., filtering out repeated GPUs, to avoid repeated delivery of the FW file (firmware file), and the slave processor is used to receive the FW file issued by the master processor;

[0080] constructing a weighted processor topology based on the response information after unique filtering and link quality parameters obtained through bidirectional communication testing, wherein the weighted processor topology includes a root node defined based on the master processor, a leaf node defined based on the slave processor, and a connection relationship between the root node and the leaf node, the link quality parameters can include delay, bandwidth, and network congestion, bidirectional communication testing is to communicate the master processor with the slave processor to determine the corresponding link quality parameters, and the weighted processor topology refers to a network connection relationship graph taking the processor as a node, the link as an edge, and each edge being attached with a weight reflecting the link communication quality (such as delay, bandwidth).

[0081] Specifically, the above steps specifically include extracting the SSID (processor identifier) of the GPU itself, and subsequently matching the GPU to be refreshed through the SSID, the master GPU broadcasts an SSID query request through a PCIe / NVLink configuration space, the slave GPU in the single machine responds to the request and returns the SSID, GPUSN (serial number), and link support information, at the same time, receiving the query request will search the device between machines through an IB (InfiniBand Host Channel Adapter, InfiniBand host channel adapter) card, and generate a cluster topology tree and a link support mode, such as an IB card address BUSID, establish a GPU topology tree according to the address obtained by the GPU broadcast, and filter out repeated GPUs according to the SN information of the GPU to avoid repeated delivery of the FW file, and the single machine supports PCIE link and NVLINK link; the GPU interconnection model supports a GPU (machine 1)-IB card (machine 1)-IB card (machine 2)-GPU (machine 2) FW transmission mode, and constructs a topology tree for all GPU links.

[0082] In the above embodiment, the complete, non-redundant and weighted processor topology structure is automatically constructed through active broadcast discovery and link quality detection, which provides an accurate routing map for subsequent efficient and accurate firmware distribution, effectively avoids resource waste, and ensures the optimal selection of transmission path in a multi-link mixed environment.

[0083] In some embodiments, before distributing the processor firmware file to the slave processors, the method further comprises:

[0084] predicting the estimated time length required for each slave processor to complete the firmware update;

[0085] According to the predicted estimated time length, the slave processors in the server cluster are divided into multiple update batches;

[0086] controlling the master processor to trigger the firmware update process of the slave processors in each batch in turn according to the batch order;

[0087] After all the slave processors in any update batch complete the firmware update, the slave processors in the batch are controlled to resume business load operation, while the master processor continues to trigger the update process of the subsequent batches.

[0088] In the above embodiment, by predicting and scheduling in batches, the firmware update task and the cluster business load are alternately performed in time, reducing the idle window of cluster computing power during the update, improving the overall resource utilization and business continuity of the cluster under the premise of ensuring the reliability of the update.

[0089] In some embodiments, based on the processor topology structure, transmitting the processor firmware file to the slave processors comprises:

[0090] Based on the link type and link quality parameters in the processor topology structure, the file transmission path of the processor firmware file is determined, wherein the path selection comprehensively considers the link type (preferably PCIe / NVLink high-speed link), link quality parameters (delay, bandwidth) and network congestion, and the final transmission path can be determined through multi-objective optimization, which is a commonly used method and the specific process is not described here;

[0091] The processor firmware file is divided into multiple data fragments, such as 8KB, and transmission information is attached to each data fragment, including data fragment serial number, check code and slave processor identifier;

[0092] Based on the file transmission path, the multiple data fragments are distributed to the corresponding slave processors in parallel, i.e., the master processor sends the fragmented data through the corresponding link in parallel according to the planned path;

[0093] The receiving slave processor returns the data fragment receiving confirmation information, and retransmits the unconfirmed data fragment based on the processor topology.

[0094] In some embodiments, the method further comprises:

[0095] In response to the master processor having completed the distribution process of the data fragment, a version query instruction is broadcast to the server cluster;

[0096] According to the version information of the version query instruction returned by the slave processor, the slave processor that fails to refresh is determined, and the comparison process is the same as described above and will not be repeated;

[0097] Based on the processor topology, the slave processor that fails to refresh is reinitiated for the processor firmware file transmission and refresh process, and if the transmission and / or refresh is not successful after reaching the preset retry number, an abnormal alarm information is generated, wherein the preset retry number can be set according to actual needs, such as 3 times.

[0098] Specifically, the GPUFW management file reads the image file in the master control GPUSPI, the firmware image is divided into 8KB fragments, and the FW file check code, fragment number and SSID tag are attached. According to the topology tree, the image fragments with the same SSID address are transmitted according to the address in the topology tree and the link transmission mode supported by the GPU, and each fragment is retransmitted at most 3 times. After exceeding, mark the device upgrade failure. At the same time, after the master GPU completes the FW file transmission, the FW file version query is performed in the form of broadcast to confirm whether the version is refreshed successfully. The GPU that fails to refresh is transmitted and refreshed again according to the address in the topology tree. If it still fails after three times, manual confirmation and refresh are performed by artificial.

[0099] In the above embodiments, the dynamic optimization-based topology path implements the fragment parallel transmission and confirmation retransmission mechanism, improves the distribution efficiency and transmission reliability of the firmware file in the multi-link hybrid cluster, and at the same time, the built-in version verification and automatic retry strategy ensures the controllable recovery of individual refresh failure, realizes the high success rate and full-process automation of large-scale processor firmware refresh, and reduces the cost and operation risk of manual intervention.

[0100] In some embodiments, before performing the firmware refresh process on the slave processor based on the processor firmware file, the method further comprises:

[0101] In response to the slave processor having received the data fragment, the integrity and accuracy of the data fragment are verified based on the check code attached to the data fragment;

[0102] In response to successful verification of integrity and accuracy, the processor firmware file corresponding to the data fragment is written into the non-volatile memory corresponding to the slave processor to perform a firmware refresh process on the slave processor.

[0103] Specifically, the slave GPU receives all fragments, and then performs verification according to the check code for each fragment. After successful verification, the slave GPU performs an overwrite of the FW file in the GPU SPI.

[0104] In the above embodiments, by performing piece-by-piece verification and secure refresh of the received firmware fragments locally on the slave processor, the data integrity and execution reliability of the firmware update at the distribution end are ensured, and damage to the firmware caused by transmission errors or storage abnormalities is effectively prevented, thereby providing a bottom-layer guarantee for secure and consistent firmware refresh in a cluster.

[0105] In some specific embodiments, as shown in Figure 3 In response to receiving a processor firmware refresh request, the processor firmware refresh request is parsed, and based on the parsing result, it is determined that the server cluster includes:

[0106] In response to receiving a processor firmware refresh request, the processor identification information and the firmware file carried in the processor firmware refresh request are parsed.

[0107] Based on the processor identification information, the processor and the server node where the processor is located that match the processor identification information are filtered out from a preset device list, and the plurality of server nodes are determined as the server cluster.

[0108] In some specific embodiments, after selecting a target processor in the server cluster and defining the target processor as a master processor, the method further includes:

[0109] Compatibility verification is performed on the firmware file and the target processor in the server cluster to obtain a compatibility verification result.

[0110] In response to the compatibility verification result meeting a preset standard, i.e., successful verification, the firmware file is sent to the server node corresponding to the master processor in the server cluster and saved.

[0111] In the above embodiments, by accurately parsing the request and matching the preset device list, automatic and accurate demarcation of the target server cluster is achieved, avoiding the inefficiency and errors of manual screening. The compatibility verification in the subsequent operation excludes the risk of firmware and hardware mismatch in advance, thereby guaranteeing the safety and success rate of the refresh process and providing a reliable guarantee for automatic and large-scale firmware deployment.

[0112] For better understanding of the above steps, as shown in Figure 5As shown, the embodiment is based on a specific application scenario, and specifically, the operating environment: 8 XX brand GPUs are interconnected through NVLink, and the SSIDs are all 0X00-0X00-0X00; the process: the user selects a GPU as the master GPU through the refresh tool and completes the FW refresh; the master GPU completes GPU addressing and locates the interconnected GPU devices through the IB link, and establishes a GPU link topology tree within the cluster, as shown in Table 1:

[0113] Table 1: Link topology tree table.

[0114]

[0115] Based on the topology tree, the fragmentation transmission takes 1 minute, and after submission, all devices are synchronized and refreshed, and the effect is 10 times more efficient than related methods.

[0116] Scenario 2: Upgrade in a heterogeneous mixed link environment.

[0117] Environment: The server contains 4 XXA models (PCIe Gen4) and 4 XXB models (only PCIe Gen4); process: the master A model GPU triggers the upgrade, and the firmware SSID list only contains the A model identifier; the master GPU discovers 3 A model GPU devices through link addressing, and the B model devices are automatically filtered; effect: GPU FW upgrade compatibility guarantee, 100% success rate.

[0118] In the above firmware management method, including: in response to receiving a processor firmware refresh request, analyzing the processor firmware refresh request, and determining a server cluster according to the analysis result, the processor firmware refresh request including a processor firmware file; selecting a target processor in the server cluster, defining the target processor as a master processor, and executing a firmware refresh process on the master processor based on the processor firmware file; in response to the firmware refresh process being executed, performing processor link addressing on the server cluster based on the master processor to construct a processor topology structure, the processor topology structure including the master processor and a slave processor; based on the processor topology structure, transmitting the processor firmware file to the slave processor, and executing the firmware refresh process on the slave processor based on the processor firmware file, based on which:

[0119] (1) Significantly improve upgrade efficiency and resource utilization.

[0120] Multi-link dynamic cooperation improves the upload rate of the FW file, and replaces the original I2C link transmission mode with transmission through PCIE or NVLink, so that the transmission rate is improved from the original KB / S level to the G / S level, and the transmission rate of the FW file is improved; through the original single FW refresh, the refresh mode is converted to a multi-link multi-machine refresh mode, the labor cost is reduced, and the refresh efficiency of the GPU FW version is greatly improved in a parallel manner.

[0121] (2) Reducing operation and maintenance cost and complexity.

[0122] Process automation to reduce manual intervention: only human operation is required for the master GPU and the last abnormal result confirmation, and the slave firmware upload, device discovery and state synchronization are automatically completed, and the operation and maintenance personnel only need to monitor the results, and the labor cost is reduced by more than 70%; through the multi-link cooperative refresh mode, the mode of the management software is replaced, and the user's expenditure cost is reduced; heterogeneous environment adaptability, hybrid topology support: compatible with PCIe / NVLink heterogeneous link environment, automatically adapt to the firmware upgrade requirements of GPUs of different manufacturers; resource occupation optimization: the upgrade process occupies less than 5% of the host CPU and memory, and does not affect the operation of business load.

[0123] (3) Promoting green computing and sustainable development.

[0124] Energy efficiency optimization, dynamic power management: during the upgrade process, the GPU power mode is adjusted on demand, idle devices enter a low-power state, and the overall energy consumption is reduced by 15%-20%; heat dissipation efficiency is improved: after firmware upgrade, the heat dissipation strategy (such as fan curve adjustment) is optimized, and the hardware life is prolonged.

[0125] Through the description of the above implementation manners, those skilled in the art can clearly understand that the method according to the above embodiment can be realized by means of software and the necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better implementation manner.

[0126] It should be understood that, although Figures 2-5 The steps in the flowchart are displayed in sequence according to the arrows, but these steps are not necessarily executed in sequence according to the arrows. Unless otherwise stated in this article, the execution of these steps has no strict order limitation, and these steps can be executed in other orders. Moreover, Figures 2-5 At least part of the steps in the above embodiment can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or sub-steps or stages of other steps.

[0127] In one embodiment, an electronic device, which can be a terminal, is provided, and an internal structure diagram of the electronic device can be as shown in FIG. 1. Figure 6 The electronic device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. The processor of the electronic device is configured to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for running the operating system and the computer program in the non-volatile storage medium. The network interface of the electronic device is configured to communicate with external terminals through network connections. The computer program is executed by the processor to implement a firmware management method. The display screen of the electronic device can be a liquid crystal display screen or an electronic ink display screen. The input device of the electronic device can be a touch layer overlaid on the display screen, or a key, trackball or touchpad provided on the housing of the electronic device, or an external keyboard, touchpad or mouse, etc.

[0128] Those skilled in the art can understand that the structure shown in FIG. 1 is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the electronic device to which the scheme of the present application is applied. The specific electronic device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components. Figure 6

[0129] Embodiments of the present application provide an electronic device including a memory and a processor, the memory storing a computer program, and the processor being configured to run the computer program to perform the steps in the firmware management method embodiments, including:

[0130] S1: in response to receiving a processor firmware refresh request, parsing the processor firmware refresh request, and determining a server cluster according to the parsing result, the processor firmware refresh request including a processor firmware file;

[0131] S2: selecting a target processor in the server cluster, defining the target processor as a master processor, and performing a firmware refresh process on the master processor based on the processor firmware file;

[0132] S3: in response to the firmware refresh process being completed, performing processor link addressing on the server cluster based on the master processor to construct a processor topology structure, the processor topology structure including the master processor and a slave processor;

[0133] S4: based on the processor topology structure, transmitting the processor firmware file to the slave processor, and performing a firmware refresh process on the slave processor based on the processor firmware file.

[0134] ​The embodiment of the application further provides a computer readable storage medium, and the computer readable storage medium stores a computer program.

[0135] S1: in response to receiving a processor firmware refreshing request, analyzing the processor firmware refreshing request, and determining a server cluster according to an analysis result, the processor firmware refreshing request comprising a processor firmware file;

[0136] S2: selecting a target processor in the server cluster, defining the target processor as a master processor, and performing a firmware refreshing process on the master processor based on the processor firmware file;

[0137] S3: in response to the firmware refreshing process being completed, performing processor link addressing on the server cluster based on the master processor, so as to construct a processor topology structure, the processor topology structure comprising the master processor and a slave processor;

[0138] S4: based on the processor topology structure, transmitting the processor firmware file to the slave processor, and performing a firmware refreshing process on the slave processor based on the processor firmware file.

[0139] In an example embodiment, the computer readable storage medium can include but is not limited to a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media capable of storing a computer program.

[0140] The embodiment of the application further provides a computer program product, and the computer program product comprises a computer program, and the computer program is executed by a processor to implement the steps in the firmware management method embodiment, comprising:

[0141] S1: in response to receiving a processor firmware refreshing request, analyzing the processor firmware refreshing request, and determining a server cluster according to an analysis result, the processor firmware refreshing request comprising a processor firmware file;

[0142] S2: selecting a target processor in the server cluster, defining the target processor as a master processor, and performing a firmware refreshing process on the master processor based on the processor firmware file;

[0143] S3: in response to the firmware refreshing process being completed, performing processor link addressing on the server cluster based on the master processor, so as to construct a processor topology structure, the processor topology structure comprising the master processor and a slave processor;

[0144] S4: transmitting the processor firmware file to the slave processor based on the processor topology, and performing a firmware flashing process on the slave processor based on the processor firmware file.

[0145] Embodiments of the present application also provide another computer program product, comprising a non-volatile computer readable storage medium, the non-volatile computer readable storage medium storing a computer program, the computer program being executed by a processor to implement the steps in the firmware management method embodiments, comprising:

[0146] S1: in response to receiving a processor firmware flashing request, parsing the processor firmware flashing request, and determining a server cluster according to the parsing result, the processor firmware flashing request comprising a processor firmware file;

[0147] S2: selecting a target processor in the server cluster, defining the target processor as a master processor, and performing a firmware flashing process on the master processor based on the processor firmware file;

[0148] S3: in response to the firmware flashing process being completed, performing processor link addressing on the server cluster based on the master processor to construct a processor topology, the processor topology comprising the master processor and a slave processor;

[0149] S4: transmitting the processor firmware file to the slave processor based on the processor topology, and performing a firmware flashing process on the slave processor based on the processor firmware file.

[0150] Those skilled in the art will further appreciate that the steps of the example methods described in connection with the embodiments disclosed herein can be embodied in electronic hardware, computer software, or combinations of both, and that the various illustrative components, methods, and steps have been described generally to illustrate the principles of the application. The particular method of implementing an example is not intended as an implementation of the application, and will depend on the particular application and design constraints imposed. Those skilled in the art will recognize the interchangeability of various components over many implementations, and the specific methods for carrying out the described functions will depend on the particular application and design choices to implement the application. Those skilled in the art will appreciate that the application can be practiced by other than the described implementations, which are presented for purposes of illustration and not of limitation.

[0151] The above provides a detailed description of the firmware management method, device, electronic equipment and storage medium provided by the present application. The principles and implementation modes of the present application are described by applying specific examples, and the above description of the embodiments is only applicable to help understand the method and core idea of the present application. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, some improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the present application.

Claims

1. A firmware management method, characterized by, The method comprises: In response to receiving a processor firmware update request, parsing the processor firmware update request, and determining a server cluster according to the parsing result, the processor firmware update request including a processor firmware file; Selecting a target processor in the server cluster, defining the target processor as a master processor, and executing a firmware update process on the master processor based on the processor firmware file; In response to the completion of the firmware update process, performing processor link addressing on the server cluster based on the master processor to construct a processor topology structure, the processor topology structure including the master processor and a slave processor; Based on the processor topology structure, transmitting the processor firmware file to the slave processor, and executing a firmware update process on the slave processor based on the processor firmware file; In response to the completion of the firmware update process, performing processor link addressing on the server cluster based on the master processor to construct a processor topology structure, the processor topology structure including: Broadcasting a discovery instruction to the server cluster based on the interconnection link supported by the master processor; Based on the discovery instruction, receiving response information of the discovery instruction returned by the slave processor in the same server as the master processor and the response information of the discovery instruction returned by the slave processor in a different server as the master processor, the response information including at least processor identification, serial number, firmware version and supported link type; According to the serial number, performing unique filtering on the slave processors returning the response information to remove the slave processors with duplicate serial numbers; Based on the response information after unique filtering and the link quality parameters obtained through bidirectional communication testing, constructing a weighted processor topology structure, the weighted processor topology structure including a root node defined based on the master processor, a leaf node defined based on the slave processor, and a connection relationship between the root node and the leaf node.

2. The firmware management method according to claim 1, wherein Selecting a target processor in the server cluster, defining the target processor as a master processor includes: Determining at least one evaluation index; Based on the evaluation index, evaluating a plurality of processors in the server cluster to obtain corresponding evaluation results; Sorting a plurality of evaluation results, and determining the target processor according to the sorting result, and defining the target processor as a master processor.

3. The firmware management method of claim 1, wherein, Executing a firmware update process on the master processor based on the processor firmware file includes: Transmitting the processor firmware file to the server node where the master processor is located, determining a user-mode migratable computing task running on the master processor, pausing the user-mode migratable computing task, and backing up the current firmware version of the master processor; Verifying the integrity and accuracy of the processor firmware file; In response to the successful verification of the integrity and accuracy, writing the processor firmware file into the non-volatile memory of the master processor, and triggering the master processor restart process; In response to completion of the restart, it is verified whether the firmware version of the master processor is successfully refreshed, and the refresh verification result of the master processor is synchronized to a cluster state management system of the server cluster.

4. The firmware management method of claim 1, wherein, Based on the processor topology, the processor firmware file is transmitted to the slave processors, including: Based on the link type and link quality parameters in the processor topology, a file transmission path of the processor firmware file is determined; The processor firmware file is divided into multiple data slices, and transmission information is attached to each data slice, including a data slice serial number, a check code, and a slave processor identifier; Based on the file transmission path, the multiple data slices are distributed to the corresponding slave processors in parallel; Data slice reception confirmation information returned by the slave processors is received, and unconfirmed data slices are retransmitted based on the processor topology.

5. The firmware management method according to claim 4, wherein Before performing a firmware refresh process on the slave processors based on the processor firmware file, the method further includes: In response to the slave processors having received the data slices, integrity and accuracy of the data slices are verified based on the check codes attached to the data slices; In response to both the integrity and accuracy being successfully verified, the processor firmware file corresponding to the data slice is written to the non-volatile memory corresponding to the slave processor to perform a firmware refresh process on the slave processor.

6. The firmware management method of claim 4, wherein, The method further includes: In response to the master processor having completed the distribution process of the data slices, a version query instruction is broadcast to the server cluster; Based on version information of the version query instruction returned by the slave processors, a slave processor that fails to be refreshed is determined; Based on the processor topology, processor firmware file transmission and refresh processes are reinitiated for the slave processor that fails to be refreshed, and if transmission and / or refresh are not successful after a preset number of retries, an abnormal alarm information is generated.

7. The firmware management method of claim 1, wherein, In response to receiving a processor firmware refresh request, the processor firmware refresh request is parsed, and based on the parsing result, a server cluster is determined to include: In response to receiving the processor firmware refresh request, processor identifier information and a firmware file carried in the processor firmware refresh request are parsed; Based on the processor identifier information, a processor matching the processor identifier information and a server node where the processor is located are filtered out from a preset device list, and multiple server nodes are determined as the server cluster.

8. The firmware management method of claim 7, wherein, After selecting a target processor in the server cluster and defining the target processor as a master processor, the method further includes: Compatibility of the firmware file and the target processor in the server cluster is verified, and a compatibility verification result is obtained; In response to the compatibility verification result meeting a preset standard, the firmware file is sent to a server node corresponding to the master processor in the server cluster and saved.

9. An electronic device, comprising: The memory is configured to store a computer program. ​ A processor for implementing the steps of the firmware management method according to any one of claims 1 to 8 when executing the computer program.

Images