WASM processor based on stack structure and working method thereof
By directly running WASM bytecode using a stack-based WASM processor, the problem of WASM runtime overhead in IoT devices is solved, achieving efficient instruction-level parallel processing and significant acceleration.
Patent Information
- Application Number
- CN202511418370.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-30
- Publication Date
- 2026-01-30
AI Technical Summary
Existing technologies incur additional compilation overhead when running WASM bytecode in IoT devices, limiting execution speed and preventing it from reaching its potential near-native speed.
Design a stack-based WASM processor that replaces the traditional register file with an operand stack and a control stack. It can directly run WASM bytecode, including a bytecode fetch module, a control module, a dual-stack module, an arithmetic logic module, and a memory module. It supports 172 instructions in five categories and achieves instruction-level parallel processing through a three-stage pipeline.
It effectively reduces the compilation time and storage overhead of WASM runtime, significantly improves the execution efficiency of IoT devices, and achieves acceleration effects of 5.99x to 34.10x and 16.78x to 107.57x, with a power consumption of 9.59 milliwatts.
Smart Images
Figure CN121433722A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the processor design for the new instruction set WebAssembly (WASM for short), used to accelerate the running of programs coded in WASM binary instruction format (.wasm file), belonging to the field of electronic information technology. BACKGROUND
[0002] WASM is a stack-based binary instruction set format, and the design goal is to provide a high-performance, portable and secure code execution environment for the Web platform. Its core feature is to standardize the bytecode format, so that programs written in C / C++, Rust, JavaScript, etc. can run in the browser at near-native speed, breaking through the performance bottleneck of traditional Web applications. This technology realizes system resource isolation through a memory-safe sandboxed execution environment, while maintaining interoperability with existing Web technologies (such as JavaScript), effectively supporting the deployment of compute-intensive tasks (such as graphics rendering, audio / video processing, scientific computing, etc.) on the Web, while also supporting blockchain computing, serverless computing, edge computing, embedded systems, etc. Application scenarios. The cross-platform nature of WASM and its support for multi-language compilation chains also broaden the application scenarios of the technology.
[0003] WASM adopts a stack-based execution model, which provides two advantages. First, its design is closely integrated with high-level programming languages, simplifying the compilation process through structured control instructions. Second, this architecture eliminates the need for register file addressing, while using the space-saving LEB128 (Little Endian Base 128) encoding format. These features make WASM bytecode particularly advantageous for edge IoT applications with limited storage capacity and data transfer bandwidth.
[0004] In the WASM binary format, the length of a complete instruction (operation code + immediate number) is variable. The operation code part of each instruction is 8 bits, used to specify the operation to be performed. The number of immediate numbers depends on the type of operation code, while the length of the immediate number depends on the encoding result. Unlike traditional machine code, WASM bytecode does not have explicit operands, but implicitly obtains them from the operand stack during execution.
[0005] Regarding the WASM binary format, the following concepts need to be explained:
[0006] Module: The smallest indivisible unit of WASM program compilation, transmission and loading.
[0007] Section: The subject matter of a module is classified into different sections, each of which contains multiple items. WASM defines 12 types of sections, each of which is assigned an ID. For example, the function section lists the signature indices of the functions in the module, the memory section lists all the memories defined in the module, the code section stores the local variable information and bytecode of the functions, and so on. Each section contains a section header and a section content, which is composed of a vector structure.
[0008] Vector: Most sections can contain multiple items, so the number of items needs to be recorded first, and then the content of each item is recorded in turn. This structure, which starts with the number and then follows the corresponding number of items, is called a vector.
[0009] Structured control instructions: WASM uses structured control instructions to manage program flow, strictly following the stack structure and static type principles to avoid arbitrary jumps in traditional assembly language. For example, you can use the “block” instruction and the “end” instruction to define a linear code block with a specified return type, or use the “loop” instruction and the “end” instruction to create a loop structure, and use the jump instructions “br” and “br_if” to jump to the start or end of the code block.
[0010] LEB128 encoding format: To optimize space efficiency, WASM binary format uses LEB128 encoding method to represent indexes and immediate numbers. LEB128 format has two characteristics. First, it uses little-endian encoding, with low-order bytes first and high-order bytes last. Second, it uses base 128, with each 7-bit group placed in the low 7 bits of a byte, and the highest bit is a flag bit (1 indicates that there are subsequent bytes, and 0 indicates the end of the sequence). The 7th bit of the termination byte is the sign bit. This scheme realizes variable-length encoding: 32-bit integers require 1 to 5 bytes, and 64-bit integers occupy 1 to 10 bytes. The smaller the integer, the fewer the number of bytes occupied after encoding.
[0011] Linear memory: A continuous, dynamically expandable storage space for efficient storage and access of data. Traditional virtual machines or interpreters usually rely on complex memory management mechanisms or garbage collection strategies, while WASM's linear memory achieves direct control over memory through simplified address space and explicit load / store instructions, while ensuring safety through strict boundary checks.
[0012] As of now, common instruction set architectures (ISAs), such as x86 and RISC-V, are run in a register file-based format, without the stack-based way of WASM. WASM runtime spends a lot of time on converting WASM bytecode into register file-based machine code, which brings unnecessary power consumption and time overhead for edge devices, forming a "WASM runtime overhead", as shown in Figure 1 For lightweight tasks common in Internet of Things applications, the time required for this additional compilation can even exceed the actual execution time of the code itself. Therefore, the potential of WASM to achieve near-native execution speed is weakened. Therefore, it is urgent to eliminate this WASM runtime overhead and develop a processor that can directly process and run WASM bytecode to better adapt to the needs of Internet of Things application scenarios. SUMMARY
[0013] In view of the problems existing in the prior art, the present application designs a WASM processor based on a stack structure and a working method thereof, which can directly run WASM bytecode. The processor replaces the register file of the traditional processor with two hardware stacks: an operand stack and a control stack; the processor can independently complete bytecode preparation section analysis, process and execute 172 WASM instructions in five categories, and then can run complete WASM bytecode in a bare machine mode without additional runtime overhead. In particular, the processor is the first processor that can independently decode and execute all five categories of WASM bytecode.
[0014] The technical scheme of the present application is as follows:
[0015] A WASM processor based on a stack structure, comprising: a bytecode fetching module, a control module, a double-stack module, an arithmetic logic module, and a memory module;
[0016] 1) The bytecode fetching module comprises a data interface, a bytecode cache, and a bytecode window conversion unit; external WASM instructions obtained by the data interface are stored in the bytecode cache through a bytecode input channel; the bytecode window conversion unit uses a register to store a bytecode pointer (BP), and the BP is used to mark the starting address of the bytecode window; the bytecode window conversion unit converts the reordered bytecode cache output into a bytecode window signal using the BP value, and outputs the bytecode window signal to the control module for further decoding; the BP address is output to the control module for storing the return address when executing function jump or loop start instructions; the bytecode window conversion unit simultaneously receives a BP step and a jump control signal output from the control module, wherein the BP step is used to determine the length of the bytecode processed in this period, so as to calculate the BP of the next period and complete the reading of variable-length instructions by period, and the jump control signal is used to complete the jump;
[0017] 2) The control module includes a bytecode decoder, a finite state machine (FSM), a dual-stack controller, a jump control unit, and a function lookup table. The bytecode decoder includes a LEB128 decoder for decoding variable-length immediate values in the bytecode to obtain its byte length. The bytecode decoder decodes the bytecode window signal into opcodes, immediate values, and control signals output to other modules. While decoding, the bytecode decoder calculates the total length of bytes that can be processed in the current cycle in real time and returns this length as the BP step size to the bytecode fetching module. The finite state machine (FSM) records the current hardware operating state and completes state transitions according to the bytecode, outputting the operating mode signal. The dual-stack controller controls the dual-stack module, obtaining the pop and push signals of the dual stack by parsing the opcode and operating mode signal. The jump control unit receives and analyzes the control stack return value and the operating mode signal from the state machine to obtain the jump control signal, and outputs the jump control signal to the bytecode fetching module. The function lookup table stores function signature information and function address information, assisting in the jump of function call instructions and function return instructions, and the passing of function parameters and control block parameters.
[0018] 3) The dual-stack module includes a push selector, an operand stack, a control stack, and a function control stack pointer register. The operand stack (O-Stack) receives stack control signals from the control module, directly processes the push and pop operations of operands for numerical values, parameters, memory, and variable instructions, and merges the three operands at the top of the stack into an operand window for output to the arithmetic logic module and the memory module. It also stores the local variables of each function (or function control block). The control stack (C-Stack) stores the context information of function call instructions and control block start instructions into the corresponding control frames. It also receives stack control signals from the control module, thereby popping the corresponding control frames when a function returns or a control block exits, assisting in the completion of control instructions.
[0019] 4) The arithmetic logic module receives the arithmetic unit control signal from the control module and the operands from the operand stack; the arithmetic unit is used to perform the arithmetic logic calculation required by the instruction; the arithmetic unit outputs the arithmetic operation result and simultaneously outputs it to the push selector of the dual-stack module and the memory read / write address interface of the memory module.
[0020] 5) The memory module inputs are the memory write enable signal from the control module, the read / write address signal from the arithmetic logic module, the immediate address bias from the control module, and the write value from the top of the operand stack. The output memory read value is connected to the push selector.
[0021] Further, in the bytecode module, the bytecode cache is composed of w 8-bit bandwidth SRAMs, used to store the WASM bytecode input from outside; the bytecode fetching module adopts a sliding window strategy with byte addressing as the instruction extraction mechanism, whose steps include:
[0022] (1) filling the WASM bytecode to be executed into the instruction cache according to the line address;
[0023] (2) obtaining the WASM instruction, calculating the BP address, simultaneously reading w bytes of data after the BP from the w SRAMs, arranging the data in byte sequence to form a w-byte instruction window, and sending the window into the bytecode decoder of the control module;
[0024] (3) the bytecode decoder returns the length of the bytecode parsed in this cycle while parsing the instruction content, and the length is returned to the bytecode fetching module as the BP step length to calculate the BP address of the next cycle under the non-jump condition.
[0025] Further, in the control module, the state machine (FSM) includes a state register, a total number of items register, an item counter, a segment type register and a segment length register, used to record the current hardware working state and to complete state conversion according to the bytecode; the state machine integrates the signals in the state register and the segment type register into a working mode signal, and sends the signal to other components of the control module to complete the conversion and control of the overall working state of the control module; the function lookup table includes a function signature lookup table, a signature index lookup table and a function address lookup table, which work together to process the function jump instruction and assist in the transmission of function parameters and control block parameters.
[0026] Further, in the dual-stack module, the four sources of the in-stack operands of the operand stack are respectively the operation results of the arithmetic logic module, the memory readout values of the memory module, the local variables read out from the operand stack, and the immediate numbers from the control module, and the four sources get the final in-stack operands via the in-stack selector, while the in-stack selector is controlled by the in-stack selection signal; the three operands at the top of the operand stack are connected to the arithmetic logic module and the memory module as the operand stack window; meanwhile, the operand stack also stores the local variables in the code block.
[0027] The operand stack provides three operands at the top of the stack to the arithmetic logic module during code execution, the top pointer records the current top address of the stack, and each operand pointer indicates the starting position of the control block and function in the stack; when the operand stack executes the function call instruction or the control block start instruction, the operand stack pointer address A and the new operand stack top pointer of the new code block are calculated, and the storage between the operand stack pointer address A and the new operand stack top pointer is the newly allocated local variable memory; the operands with addresses greater than the operand stack pointer address A are marked as local operands of the code block, and when the function returns or jumps out of the control block, the operand stack top returns to the operand stack pointer A recorded by the control frame, and the local operands are emptied.
[0028] Further, the control stack in the double-stack module stores the context information of the control instruction through the control frame, and each frame contains four parts:
[0029] 1) Control block type: used to identify the control block type (function, linear block, conditional branch block or loop block);
[0030] 2) Operand stack pointer: used to identify the position where the top of the operand stack should return when the function or block jumps out;
[0031] 3) Return value flag: used to record whether there is a return value in the current frame;
[0032] 4) Return address: used to store the function return address or loop iteration start address;
[0033] The control stack dynamically manages these control frames when calling functions or entering control blocks during code segment instruction execution, pops the top frame when the function returns or the control block terminates, and uses the return address stored in the top frame to send the jump target to the jump control unit and inform the operand stack to discard the operands beyond the operand stack pointer; this design uses the control stack to control the operand stack and the jump control unit through the marking mechanism, and completes the control flow management.
[0034] Further, the above-mentioned WASM processor based on the stack structure uses D flip-flops to divide the five modules into three levels of pipelining on the hardware architecture, so that the processor has the instruction level parallel processing capability of three levels of pipelining. The three levels of pipelining are instruction fetching stage (F-Stage), decoding stage (D-Stage) and execution stage (E-Stage):
[0035] 1) The bytecode decoder in the F-Stage control module parses the LEB128 immediate number and calculates the BP step, and the bytecode module combines the BP step and the jump control signal to obtain the accurate BP address of the next cycle; the F-Stage parses the 8-bit operation code and the decoded immediate number, and the two values are sent to the D-Stage through D flip-flops;
[0036] 2) The bytecode decoder in the D-Stage control module corresponds the 8-bit operation code to 172 WASM instruction types through a large lookup table, and further generates corresponding memory write enable signals, operator control signals, and stack selection signals; the dual-stack controller receives the decoding information, combines the BP address and the working mode signal output by the state machine to generate stack control signals; the memory write enable signals, the operator control signals, the stack selection signals, the stack control signals, and the immediate number value and the operation code parsed by the F-Stage are sent to the E-Stage through D flip-flops;
[0037] 3) The E-Stage, the operand stack and the structured control stack cooperate with each other to realize unified stack management; the top three frames of the operand stack are used as the operand stack window, which is open to the arithmetic logic module and the memory module of the E-Stage; the jump control unit receives information from the control stack and the function lookup table to determine the jump control signal, and once the jump occurs, the jump information will be immediately processed by the bytecode fetching module of the F-Stage, and at the same time, the enable signals of the two D flip-flops will be cleared in the next cycle.
[0038] A method for processing WASM bytecode modules using the above-mentioned WASM processor based on a stack structure, which realizes the entire process of WASM bytecode module decoding and execution, specifically comprising:
[0039] (I) Input stage
[0040] First, the WASM bytecode is written into the bytecode cache through the data interface, and after the writing is completed, the host sends a start signal to the state machine of the WASM processor control module, and the state machine enters the preparation stage;
[0041] (II) Preparation stage
[0042] After each reset to the preparation stage, first, a cycle is used to verify the module header of the WASM bytecode to confirm the correctness of the bytecode transmission; then, the processor decodes the bytecode segment in a just-in-time manner and completes the non-code segment function and code segment function of the bytecode segment, and the parsing of each segment is divided into three states of segment header parsing, vector header parsing and project content parsing, which are specifically:
[0043] 1) Segment header parsing: Each time lasts one cycle, in which the segment type register and segment length register in the state machine are updated. The segment type value determines the decoding method of the subsequent vector, and the segment length value is used to skip the useless segment;
[0044] 2) Vector header parsing: Each time lasts one cycle, in which the total number of items register in the state machine is refreshed, and the item counter in the state machine is set to zero;
[0045] 3) Item content parsing: The bytecode decoder decodes the content of each item in turn, while incrementing the item counter in the state machine. After parsing each item, the number of parsed items is compared with the total number of items. When the number of parsed items (the value of the item counter) reaches the total number of items, if the code segment has not been parsed (all segments have not been parsed), return to the segment header parsing state. If the code segment has been parsed, it means that all necessary segments have been parsed, and enter the execution phase;
[0046] (Three) Instruction execution phase
[0047] At the beginning of the instruction execution phase, the jump control unit obtains the starting function address from the function address lookup table, and the BP jumps to the position of the code segment. The five instructions supported by WASM are executed in order in each cycle during the execution phase. When the starting frame at the bottom of the control stack is popped, the control stack is emptied, the instruction execution phase ends, and the processor enters the output phase;
[0048] (Four) Output phase
[0049] In the output phase, the processor sends an end signal to the host computer, and the host computer actively reads the memory of the processor to read out the running results of the WASM code module, and completes the output of the results.
[0050] Further, the parsing functions of each segment of the bytecode segment are as follows: the type segment parses the function signature type and updates the function signature lookup table; the function segment parses the function signature index corresponding to each function and updates the signature index lookup table; the global segment parses and records the number, type and initial value of the global variable; the starting segment obtains the starting function index; the code segment pre-parses and records the function starting address and local variable information in the function header.
[0051] Further, the instruction execution phase has the following working modes for the five different types of instructions:
[0052] (1) Numerical value instruction and parameter instruction: the operand stack pops the required operands and inputs them into the arithmetic logic module, and the arithmetic logic module outputs the operation result to the stack;
[0053] (2) Control instruction: when the operand stack executes call / block / loop / if instruction, the operand stack pointer address and the operand stack top pointer of the new code block are calculated; the storage between the operand stack pointer address and the new operand stack top pointer is the newly allocated local variable memory; at the same time, the control block type, return address, operand stack pointer address and return value flag of the new control block are wrapped into a frame and pushed into the control stack; when the end instruction is encountered, the top frame of the control stack is popped, and the corresponding jump, operand stack top pointer return and return value stack operation are completed according to the information stored in the top frame;
[0054] (3) Local variable instruction: the immediate number decoded from the LEB128 decoder plus the code block operand stack address stored in the control stack is the address of the local variable in the operand stack, and the address calculation is completed by the arithmetic logic module; the access operation of the local variable can be completed by reading and writing the address in the operand stack;
[0055] (4) Global variable instruction: the immediate number decoded from the LEB128 decoder plus the global variable base address is the global variable address, and the address calculation is completed by the arithmetic logic module; the access operation of the global variable can be completed by reading and writing the address in the memory unit;
[0056] (5) Memory instruction: the address operand popped from the operand stack plus the immediate number (offset) decoded from the LEB128 decoder is the starting byte address of the memory, and the address calculation is completed by the arithmetic logic module; the memory read / write operation can be completed by reading and writing the address in the memory unit.
[0057] The technical effects of the present application are as follows:
[0058] The application provides a WASM processor based on a stack structure, which can complete necessary preliminary section analysis and execution of all five instruction types of WASM, and is the first processor capable of decoding and executing all five types of WASM bytecodes independently. The WASM processor introduces unique micro-architecture innovations: 1) a double-stack mechanism of an operand stack and a control stack cooperating with each other, a function lookup table, etc., which directly implement the WASM stack-based logical operation mechanism and the control block-based jump mechanism at the processor level; 2) a sliding window strategy based on the WASM bytecode format is adopted to fetch bytecodes, so that the WASM instructions with the characteristics of processing variable length, little-end first and byte alignment can be flexibly processed; 3) a bytecode decoder and a state machine conversion mechanism based on the WASM bytecode format are provided; based on the above micro-architecture innovations, the processor executes WASM programs, and the step of compiling WASM bytecodes into bytecodes of other instruction sets is omitted, thereby greatly reducing the compilation time and storage overhead of the runtime of WASM, and effectively reducing the overall running time and required hardware resources of the WASM bytecode program. In the PolyBench benchmark test evaluation, the same WASM program is executed, and compared with Intel Xeon CPU and Jetson TX2, the speed is accelerated by 5.99 times to 34.10 times and 16.78 times to 107.57 times, respectively. The prototype chip of the application adopts a 28-nanometer HPC+ logic process of TSMC, which is the same as the process adopted by the popular Internet of Things microprocessor. The core area is compact, which is 0.306 square millimeters, and the average power consumption is 9.59 milliwatts at 50MHz. BRIEF DESCRIPTION OF DRAWINGS
[0059] Figure 1 A flowchart of the running process of the WASM instruction set from software to hardware;
[0060] Figure 2 A hardware architecture block diagram of the WASM processor based on the stack structure;
[0061] Figure 3 A state transition diagram of the WASM processor based on the stack structure, (a) is a state machine workflow, and (b) is the analysis order and function of each segment;
[0062] Figure 4 A working flow diagram of the double-stack cooperation of the operand stack and the control stack. DETAILED DESCRIPTION
[0063] The application will be further clarified, complete and set forth in detail with reference to the accompanying drawings and specific embodiments.
[0064] The WASM processor based on the stack structure is as follows Figure 2The design of the fetch bytecode module, the control module, the double stack module, the arithmetic logic module and the memory module is described in detail below:
[0065] 1) Fetch bytecode module: including data interface, bytecode cache and bytecode window conversion unit. The data interface obtains the input bytecode from the host and stores it in the bytecode cache through the bytecode input channel. The bytecode window conversion unit uses a register to store the bytecode pointer (BP), which is used to mark the starting address of the bytecode window. The BP is controlled by the jump control signal from the jump control unit of the control module and the BP step from the bytecode decoder of the control module. The BP step is used to determine the length of the bytecode processed in this period, thereby calculating the BP of the next period and completing the reading of the variable-length instruction by period. The jump control signal is used to complete the jump. The bytecode window conversion unit uses the BP value to rearrange the output bytecode cache and then converts it into a bytecode window signal. The bytecode window signal is output to the bytecode decoder of the control module for further decoding; the BP address is output to the double stack controller of the control module for storing the return address when executing function jump or loop start instruction.
[0066] The WASM processor needs to process WASM bytecode with three characteristics: variable length, byte alignment and little-endian first. This requires a special instruction extraction mechanism, so a byte-addressable sliding window strategy is designed. The invention designs an independent bytecode cache composed of w random static memories (SRAM), and the I / O width of each SRAM is 8 bits. The WASM bytecode to be executed is first filled into the instruction cache according to the row address. When the WASM instruction is obtained, the byte address of the BP is first calculated, and then the read addresses of the w SRAMs are calculated respectively (let m=BP / w, n=BP%w, then the read addresses of the 1st-n-1th SRAMs are m+1, and the read addresses of the n-wth SRAMs are m), and then w bytes of data are read from the w SRAMs at the same time, and then arranged in byte order to form a w-byte fetch bytecode window, which is sent to the bytecode decoder. The bytecode decoder returns the length of the bytecode parsed in this period while parsing the instruction content, which is used as the BP step to return to the fetch bytecode module to calculate the next period BP address. At the same time, the fetch bytecode module will also receive the jump control signal from the control stack, and move the BP to the target jump address when executing the structured jump instruction.
[0067] 2) Control module: including bytecode decoder, finite state machine (FSM), dual stack controller, jump control unit and function lookup table (including function signature lookup table, signature index lookup table, function address lookup table). The bytecode decoder contains an LEB128 decoder for decoding the variable-length immediate number encoded by LEB128 format in the bytecode window signal, and its output is a 32-bit or 64-bit integer immediate number and the length of the encoded immediate number; the bytecode decoder receives the bytecode window signal from the bytecode fetch unit, decodes it into an operation code, a 32-bit or 64-bit immediate number, and control signals for other units. Control signals include: stack selection signals output to the stack selector of the dual stack module, memory write enable signals output to the memory module, and operation controller signals output to the arithmetic logic module; the bytecode decoder also calculates the length of the bytecode that can be parsed in this period while decoding, and returns the length as the BP step to the bytecode fetch module; the jump control unit receives and analyzes the control stack return value and the working mode signal from the state machine to obtain the jump control signal, including the jump enable signal and the jump address, and outputs the jump control signal to the bytecode fetch module; In order to adapt to different bytecode formats of different bytecode segments, the application designs a finite state machine for decoding control. The state machine includes a state register, a total number of items register, an item counter, a segment type register and a segment length register, which are used to record the current hardware working state and convert the state according to the bytecode completion state. The state machine integrates the signals in the state register and the segment type register into the working mode signal and sends it to the other components of the control module, so as to complete the conversion and control of the overall working state of the control module. The dual stack controller is used to control the dual stack module, and it obtains the out-stack signal and the in-stack signal of the dual stack by analyzing the operation code and the working mode signal. In addition, the bytecode decoder can parse the operation code and the length of the variable-length immediate number of the current instruction, calculate and output the BP step in combination with the working mode signal, and send it to the bytecode fetch module; the function signature lookup table, the signature index lookup table and the function address lookup table work together to process function jump instructions and assist in completing the transmission of function parameters and control block parameters.
[0068] 3) Dual stack module: WASM executes structured control flow through explicit control flow primitives. In order to be able to directly run such structured control flow, the dual stack module combining the operand stack and the control stack is designed. The dual stack module includes the stack selector, the operand stack, the control stack and the function control stack pointer register.
[0069] The operand stack (O-Stack) is similar to the function of the register file, receiving the stack control signal from the control module, and directly processing the operand push / pop operation of the numerical value, parameter, memory and variable instruction. The four sources of the push operand are the operation result of the arithmetic logic module, the memory read value of the memory module, the local variable read from the operand stack, and the immediate number from the bytecode decoder. The final push operand is obtained through the push selector, which is controlled by the push selection signal. The three operands on the top of the operand stack are connected to the arithmetic logic module and the memory module as the operand stack window; meanwhile, the operand stack also stores the local variables of each function (or function control block). During code execution, it provides the top 3 operands (i.e. the operand window) to the arithmetic logic module. The top pointer records the current stack top address, and each operand pointer indicates the control block and the starting position of the function in the stack. When the operand stack executes the function call instruction or the control block start instruction, it calculates the operand stack pointer address A and the new operand stack top pointer of the new code block, and the storage between the operand stack pointer address A and the new operand stack top pointer is the newly allocated local variable memory. The operands with addresses greater than the operand stack pointer address A can be regarded as local operands of the code block, and when the function returns or the control block jumps out, the operand stack top returns to the operand stack pointer A recorded by the control frame, thereby completing the clearing of the local operands.
[0070] The control stack (C-stack) implements the control instruction through the control operand stack and the jump control unit. The control frame in the control stack stores the context information of the control instruction, and receives the stack control signal from the control module, so as to pop the corresponding control frame when the function returns or the control block jumps out, thereby assisting in completing the control instruction, which is similar to the function call stack in the x86 CPU architecture. Each frame contains four parts:
[0071] a) Control block type: used to identify the control block type (function, linear block, conditional branch block or loop block);
[0072] b) Operand stack pointer: used to identify the position of the top of the operand stack that should be returned when the function or block jumps out;
[0073] c) Return value flag: used to record whether the current frame has a return value;
[0074] d) Return address: used to store the storage function return address or loop iteration start address.
[0075] During the code segment instruction execution, the control stack dynamically manages these control frames when calling functions or entering control blocks. When the function returns or the control block terminates, the top frame of the control stack is popped. The control stack uses the return address stored in the top frame to send the jump target to the jump control unit and informs the operand stack to discard the operands beyond the recorded pointer position. This design controls the local variable address allocation of the operand stack and the marking and emptying of local operands through the marking mechanism, thereby completing the control flow management and improving the storage efficiency.
[0076] 4) Arithmetic logic module: The arithmetic logic module in the application supports INT32 (i32) and INT64 (i64) operations in WASM code. In the design, the arithmetic logic module receives the operator control signal from the bytecode decoder of the control module. For parameter and value instructions, the operands come from the operand stack, and the operation result is connected to the stack selector and then pressed back to the stack. For received variable instructions and memory instructions, the adder in the operator is used to calculate the addresses of the global memory, local memory and linear memory, and output the read-write address signal to the memory read-write address interface of the memory module.
[0077] 5) Memory module: including linear memory and global memory for storing WASM bytecode. The application integrates the global memory and the linear memory into a unified hardware main memory, which inputs the write enable signal from the control module, the read-write address signal from the arithmetic logic module, the immediate number address offset from the bytecode decoder of the control module and the write value from the top of the operand stack, and outputs the memory read value to the stack selector. The application specifically implements a single-port SRAM as the memory storage. When executing the read memory instruction, the write enable signal is closed, and the stack selector selects the memory read value to press the stack; when executing the memory write instruction, the write enable signal is enabled, and the operand popped from the top of the operand stack is written into the corresponding address of the memory. The global variable base address can be flexibly configured through the test access port (such as JTAG or I2C) of the processor. The global variable base address divides the address space into two regions: the part above the base address is the global memory, and the part below the base address is the linear memory. This reconfigurable allocation method can flexibly allocate storage space according to the memory usage, thereby fully utilizing the valuable storage resources on the edge device.
[0078] The application divides the above five modules into three levels of pipelining by appropriately inserting D flip-flops in the hardware architecture, so that the processor has a three-level pipelined instruction-level parallel processing capability. The three levels of pipelining are the instruction fetching stage (F-Stage), the decoding stage (D-Stage) and the execution stage (E-Stage):
[0079] 1) The bytecode decoder in the F-Stage control module parses the LEB128 immediate number and calculates the BP step, and the bytecode module combines the BP step and the jump control signal to obtain the accurate BP address of the next cycle. The F-Stage can parse the 8-bit operation code and the decoded immediate number, and the two values are sent to the D-Stage through a D flip-flop.
[0080] 2) The bytecode decoder in the D-Stage control module corresponds the 8-bit operation code to 172 WASM instruction types through a large lookup table, and further generates corresponding memory write enable signals, operator control signals and stack selection signals. The dual-stack controller receives the decoded information operation code, combines the BP address and the working mode signal output by the state machine to generate the stack control signal. The memory write enable signal, the operator control signal, the stack selection signal, the stack control signal and the immediate number value and the operation code parsed by the F-Stage are sent to the E-Stage through a D flip-flop.
[0081] 3) The E-Stage, the operand stack and the structured control stack cooperate with each other to realize unified stack management. The top three frames of the operand stack are used as the operand stack window, which is open to other execution units (arithmetic logic module, memory module) of the E-Stage. The jump control unit receives information from the control stack and function lookup table information to determine the jump control signal. Once the jump occurs, the jump information will be immediately processed by the bytecode fetching module of the F-Stage. Since the validity of the jump instruction under the structured control needs to be verified in the E-Stage, when the following jump is true, the related enable signals of the D-Stage and the E-Stage need to be all set to zero in the next cycle, and the instruction fetching address of the F-Stage in the next cycle should also be updated to the jump address: a) the function call instruction is true; b) the function return jump is true; c) the loop return jump is true.
[0082] According to the characteristics of the segmented running of the WASM bytecode module, the working process of the WASM processor based on the stack structure of the application for processing the WASM bytecode module is: input stage → preparation stage → instruction execution stage → output stage. The process can decode and execute a complete WASM bytecode module. The WASM bytecode module is composed of segments, and the decoding process of each segment is divided into a segment header parsing state, a vector header parsing state and a project content parsing state. Figure 3 The state transition diagram of the WASM processor based on the stack structure designed by the application is shown.
[0083] (I) Input stage. First, the WASM bytecode is written into the bytecode buffer through the data interface, and after the writing is completed, the host sends a start signal to the state machine of the processor control module, and the state machine enters the preparation stage.
[0084] (ii) Preparation phase. The module header of WASM bytecode is an 8-byte constant, in which the module ID and version number each occupies 4 bytes. After resetting to the preparation phase, the module header is first verified with one cycle to confirm the correctness of the bytecode transmission. Subsequently, the processor decodes the bytecode segment in a just-in-time manner and completes the corresponding function of the bytecode segment, in which the main non-code segment functions are as follows: i) type segment, used to initialize the function signature lookup table, thereby storing the number and type of parameter values and the number and type of return values corresponding to each function signature index; ii) function segment, used to initialize the signature index list, which stores the function signature index corresponding to each function index; iii) global segment, used to update the types and values of global parameters and store these global parameters in the memory; iv) start segment, used to obtain the start function index. The non-code segment is parsed, and then the code segment is parsed. The code segment takes the function as the basic element and contains the local variable information and corresponding instructions of each function. The parsing of each segment can be divided into three states of segment header parsing, vector header parsing and item content parsing, which are as follows:
[0085] 1) Segment header parsing: each time lasts one cycle. In this cycle, the segment type register and segment length register in the state machine are updated. The segment type value determines the decoding method of the subsequent vector, and the segment length value is used to skip the useless segment.
[0086] 2) Vector header parsing: each time lasts one cycle. In this cycle, the total number of items register in the state machine is refreshed, and the item counter in the state machine is set to zero.
[0087] 3) Item content parsing: the bytecode decoder sequentially decodes the content of each item while incrementing the item counter in the state machine. After parsing each item, the parsed item number and the total number of items are compared. When the parsed item number (the value of the item counter) reaches the total number of items, if the code segment has not been parsed (all segments have not been parsed), it returns to the segment header parsing state; if the code segment has been parsed, it means that all necessary segments have been parsed, and it enters the execution phase.
[0088] (iii) Instruction execution phase. At the beginning of the instruction execution phase, the jump control unit obtains the start function address from the function address lookup table, and the BP also jumps to this position. The present application adopts a double-stack control data flow, which effectively supports the five instructions of WASM, and each cycle executes one instruction:
[0089] 1. Numerical value instruction and parameter instruction: the operand stack pops out the required operation numbers and inputs them into the arithmetic logic module, and the arithmetic logic module outputs the operation result and pushes it to the stack.
[0090] 2. Control instruction: When the call / block / loop / if instruction is executed by the operand stack, the operand stack pointer address of the new code block (the calculation method is the current operand stack top pointer address minus the number of parameters of the new code block) and the operand stack top pointer (the calculation method is the current O-Stack top pointer address plus the number of new local variables obtained from the function signature register and the signature index lookup table) are calculated. The storage between the operand stack pointer address and the new operand stack top pointer is the newly allocated local variable memory. At the same time, the control block type, return address, operand stack pointer address and return value flag of the new control block are packaged into a frame and pushed into the control stack. When the end instruction is encountered, the top frame of the control stack is popped, and the corresponding jump, operand stack top pointer return, and return value stack operation are completed according to the information stored in the top frame.
[0091] 3. Local variable instruction: The immediate number decoded from the LEB128 decoder plus the code block operand stack address stored in the control stack is the address of the local variable in the operand stack. The address calculation is completed by the arithmetic logic module, and the access operation of the local variable can be completed by reading and writing the address in the operand stack.
[0092] 4. Global variable instruction: The immediate number decoded from the LEB128 decoder plus the global variable base address is the global variable address. The address calculation is completed by the arithmetic logic module, and the access operation of the global variable can be completed by reading and writing the address in the memory unit.
[0093] 5. Memory instruction: The address operand popped out of the operand stack plus the immediate number (offset) decoded from the LEB128 decoder is the starting byte address of the memory. The address calculation is completed by the arithmetic logic module. The memory read / write operation can be completed by reading and writing the address in the memory unit.
[0094] When the starting frame at the bottom of the control stack is popped, the control stack is emptied, the instruction execution phase ends, and the processor enters the output phase.
[0095] (Four) Output phase. When entering the output phase, the processor sends an end signal to the host computer, and the host computer can actively read the memory of the processor and then read out the running result of the WASM code module, thereby completing the result output.
[0096] More specifically, the working process of the double-stack module in the instruction execution phase is explained below through an example as shown in FIG. 1. Figure 4 Figure 4 (a) and (b) show examples of WASM text format and corresponding bytecode format, respectively. In the initial state of execution, the operand stack is empty, while the control stack bottom has been pushed a start function frame containing information of the start function. As instructions are executed in order, the operand stack records the dynamic changes of push / pop operations by calculating the stack top pointer. In Figure 4 In (c-1), two value instructions have been executed, and the corresponding results have been pushed to the top of the operand stack.
[0097] In WASM bytecode format, the parameters of a function or control block are treated as implicit local variables, and the local variables defined in the function header are called explicit local variables. Both kinds of local variables are controlled by three instructions: local.get (0x20), local.set (0x21) and local.tee (0x22). As shown in Figure 4 As shown in (c-2), after the call (0x10) instruction calls function 1, the jump enable signal is activated, and the function jump address is the start address of the function 1 content obtained from the function address table. At the same time, the BP address of the call instruction, the return value signal and the operand stack pointer are combined to form a new function frame and pushed into the control stack. The space between the operand stack pointer and the stack top pointer of function 1 becomes the local memory space of function 1, and the original operand at the top of the stack is naturally included in the local memory space without the need for copying or moving, avoiding the trouble of allocating a new address. Figure 4 In line 28 of (a), the control stack function frame of function 1 is popped, and the return address in this frame becomes the return jump address.
[0098] The local variable address is the sum of the top function operand stack pointer address and the local variable index. The local variable index comes from the immediate number in the local variable instruction, and the function operand stack pointer address comes from the topmost function frame in the control stack, and the sum is calculated by the arithmetic logic module. The taking and storing of local variables are shown in Figure 4 (c-3) and (c-4), respectively.
[0099] Structured control blocks (including linear blocks, conditional branch blocks, and loop blocks) can be viewed as special functions without explicit local variables. The key to block-based jump control is correctly escaping nested control blocks. To handle this control logic, we introduce two new signals: a 1-bit `block_hold` signal and an 8-bit `block_holding_depth` signal. A `block_hold` signal of 1 indicates that the current BP position is a part of the block that should be skipped; therefore, the memory write enable signal, the operand stack push signal, and the jump enable signal are all forcibly disabled. `block_holding_depth` indicates the level of nesting to escape. When a `br` instruction is encountered and valid, the `block_hold` signal is set to 1, and `block_holding_depth` is reset to the immediate value of the `br` instruction. Each time an `end` instruction is encountered, `block_holding_depth` is decremented by 1. When `block_holding_depth` returns to 0, `block_hold` also returns to 0. At this point, the top frame of the control stack is popped, and the operand stack pointer address it contains becomes the new operand stack pointer for the next cycle. The value at the old operand stack pointer will be pushed onto the new operand stack pointer as the return value. Figure 4 (a) The `br` instruction appears on line 21. Therefore, `block_holding_depth` is set to the immediate value "2", and `block_hold` is set to 1. At this point, the stack looks like this. Figure 4 As shown in (c-5). In lines 22 and 24, `block_holding_depth` is reduced to "1" and "0" respectively, while the instructions in lines 23 and 25 are skipped. In line 26, `block_hold` returns to 0, and the control stack frame for block 2 is popped, as shown... Figure 4 As shown in (c-6). The new operand stack pointer returns to the pointer address of block 2, and the return value "312" is pushed onto the stack, overwriting the new stack frame.
[0100] This dual-stack collaborative design offers three advantages for the execution of control instructions: First, no new memory space needs to be allocated when functions pass parameters. Second, structured control blocks and function return values are passed directly on the operand stack, again without requiring additional memory allocation. Third, expired operands are automatically released, eliminating the need for additional compilation cleanup steps.
[0101] This invention uses the example of running nested WASM code within a control block, but it is not limited to any specific WASM code execution task and is applicable to other code execution tasks. It can be applied to other application scenarios involving WASM code execution.
[0102] Finally, various substitutions and modifications can be made to the application without departing from the spirit and scope thereof as defined in the appended claims. Therefore, the application is not to be limited to the particular embodiments disclosed, but is to cover all adaptations and modifications that are deemed to fall within the scope of the claims.
Claims
1. A WASM processor based on stack structure, characterized in that, Comprise: Bytecode fetch module, control module, double stack module, arithmetic logic module and memory module; 1) The bytecode fetch module includes a data interface, a bytecode cache and a bytecode window conversion unit; the external WASM instruction obtained by the data interface is stored in the bytecode cache through a bytecode input channel; the bytecode window conversion unit uses a register to store a bytecode pointer BP, which is used to mark the starting address of the bytecode window; the bytecode window conversion unit converts the reordered output of the bytecode cache into a bytecode window signal using the BP value, and outputs the bytecode window signal to the control module for further decoding; the BP address is output to the control module for storing the return address when executing function jump or loop start instruction; the bytecode window conversion unit simultaneously receives the BP step and jump control signal output from the control module, wherein the BP step is used to determine the length of the bytecode processed in this period, so as to calculate the BP of the next period, and then complete the reading of variable-length instructions by period; the jump control signal is used to complete the jump; 2) The control module includes a bytecode decoder, a finite state machine FSM, a double stack controller, a jump control unit and a function lookup table; the bytecode decoder includes an LEB128 decoder for decoding the variable-length immediate number in the bytecode to obtain its byte length; the bytecode decoder is used to decode the bytecode window signal into an operation code, an immediate number and a control signal output to other modules; the bytecode decoder calculates the total length of the bytes that can be processed in the current period in real time while decoding, and returns the length as the BP step to the bytecode fetch module; the finite state machine FSM is used to record the current hardware working state and complete state transition according to the bytecode, and output a working mode signal; the double stack controller is used to control the double stack module, which obtains the out-stack signal and the in-stack signal of the double stack by analyzing the operation code and the working mode signal; the jump control unit receives and analyzes the control stack return value and the working mode signal from the state machine to obtain the jump control signal, and outputs the jump control signal to the bytecode fetch module; the function lookup table is used to store function signature information and function address information, which is used to assist the jump of function call instruction and function return instruction, and the transmission of function parameters and control block parameters; 3) The double stack module includes a stack selector, an operand stack, a control stack and a function control stack pointer register; the operand stack receives the stack control signal from the control module, directly processes the in-stack and out-stack of the operation number of value, parameter, memory and variable instruction, and combines the three operation numbers closest to the top of the stack into an operation number window output to the arithmetic logic module and the memory module, while storing the local variables of each function or function control block; the control stack is used to store the context information of the function call instruction and the control block start instruction into the corresponding control frame, and receives the stack control signal from the control module, so as to pop up the corresponding control frame when the function returns or the control block jumps out, and assist in completing the control instruction; 4) the arithmetic logic module receives the operator control signal from the control module and the operand from the operand stack; the operator is used to perform the arithmetic logic calculation required by the instruction; the operator outputs the arithmetic operation result to the stack selector of the double stack module and the address interface of the memory module for memory read and write; 5) the memory module inputs the memory write enable signal from the control module, the read and write address signal from the arithmetic logic module, the immediate number address offset from the control module, and the write value from the top of the operand stack, and outputs the memory read value to the stack selector.
2. The stack structure based WASM processor of claim 1, wherein, In the bytecode module, the bytecode cache is composed of w 8-bit bandwidth SRAMs, used to store the WASM bytecode input from the outside; The bytecode fetching module uses a sliding window strategy with byte addressing as the instruction fetching mechanism, which includes the following steps: (1) fill the WASM bytecode to be executed into the instruction cache according to the row address; (2) get the WASM instruction, calculate the BP address, read w bytes of data after the BP from the w SRAMs at the same time, arrange them in byte order to form a w-byte instruction window, and send them to the bytecode decoder of the control module; (3) the bytecode decoder returns the length of the bytecode parsed in this period while parsing the instruction content, which is returned to the bytecode fetching module as the BP step size to calculate the BP address of the next period under non-jump conditions.
3. The stack structure based WASM processor of claim 1, wherein, In the control module, the state machine FSM includes a state register, a total number of items register, an item counter, a segment type register, and a segment length register, which are used to record the current hardware working state and complete state conversion according to the bytecode; the state machine integrates the signals in the state register and the segment type register into a working mode signal, which is sent to other components of the control module to complete the conversion and control of the overall working state of the control module; the function lookup table includes a function signature lookup table, a signature index lookup table, and a function address lookup table, which work together to handle function jump instructions and assist in the transmission of function parameters and control block parameters.
4. The stack structure based WASM processor of claim 1, wherein, In the double stack module, the four sources of the stack-in operand of the operand stack are the operation result of the arithmetic logic module, the memory read value of the memory module, the local variable read from the operand stack, and the immediate number from the control module; the four sources get the final stack-in operand through the stack-in selector, which is controlled by the stack-in selection signal; the three operands at the top of the operand stack are connected to the arithmetic logic module and the memory module as the operand stack window; at the same time, the operand stack also stores the local variables in the code block; During code execution, the operand stack provides the top 3 operands to the arithmetic logic module, the top pointer records the current top address, and each operand pointer indicates the starting position of the control block and function in the stack. When the operation stack executes the function call instruction or the control block start instruction, the operation stack pointer address A and the new operation stack top pointer of the new code block are calculated, and the storage between the operation stack pointer address A and the new operation stack top pointer is the newly allocated local variable memory; the operation number greater than the operation stack pointer address A is marked as the local operation number of the code block, and when the function returns or jumps out of the control block, the operation stack top returns to the operation stack pointer A recorded by the control frame, and the local operation number is emptied.
5. The stack structure based WASM processor of claim 1, wherein, The control stack in the double stack module stores the context information of the control instruction through the control frame, and each frame includes four parts: 1) Control block type: used for identifying the control block type: function, linear block, conditional branch block or loop block; 2) Operation stack pointer: used for identifying the position of the stack top of the operation stack when the function or the block jumps out; 3) Return value flag: used for recording whether the current frame has a return value; 4) Return address: used for storing the storage function return address or loop iteration start address; The control stack dynamically manages these control frames when calling the function or entering the control block during the execution of the code segment instruction, and pops the top frame when the function returns or the control block terminates, the control stack sends the jump target to the jump control unit using the return address stored in the top frame, and informs the operation stack to discard the operation number exceeding the operation stack pointer; the design uses the control stack to control the operation stack and the jump control unit through the marking mechanism, and completes the control flow management.
6. The stack structure based WASM processor of claim 1, wherein, The five modules are divided into three levels of pipelining using D flip-flops on the hardware architecture, so that the processor has the instruction level parallel processing capability of three levels of pipelining; the three levels of pipelining are the instruction fetching stage F-Stage, the decoding stage D-Stage and the execution stage E-Stage: 1) The bytecode decoder in the F-Stage control module parses the LEB128 immediate number and calculates the BP step length, and the bytecode module obtains the accurate BP address of the next cycle in combination with the BP step length and the jump control signal; the F-Stage parses the 8-bit operation code and the decoded immediate number, and the two values are sent to the D-Stage through the D flip-flop; 2) The bytecode decoder in the D-Stage control module corresponds the 8-bit operation code to 172 WASM instruction types through a large lookup table, and further generates the corresponding memory write enable signal, the operator control signal and the stack selection signal; the double stack controller receives the decoding information, generates the stack control signal in combination with the BP address and the working mode signal output by the state machine; the memory write enable signal, the operator control signal, the stack selection signal, the stack control signal and the immediate number value and the operation code parsed by the F-Stage are sent to the E-Stage through the D flip-flop. 3) E-Stage, the operand stack and the structured control stack cooperate with each other to realize unified stack management; the top three frames of the operand stack are used as the operand stack window, which is open to the arithmetic logic module and the memory module of the E-Stage; the jump control unit receives information from the control stack and the function lookup table to determine the jump control signal, and once the jump occurs, the jump information will be immediately processed by the bytecode fetching module of the F-Stage, and at the same time, the enable signals of the two aforementioned D flip-flops will be cleared in the next period.
7. A method for WASM bytecode module processing using the WASM processor of claim 1, wherein, The method realizes the whole process of WASM bytecode module decoding and execution, and specifically includes: (I) input stage First, the WASM bytecode is written into the bytecode cache through the data interface, and after writing is completed, the host sends a start signal to the state machine of the WASM processor control module, and the state machine enters the preparation stage; (II) preparation stage After resetting to the preparation stage each time, first, a period is used to verify the module header of the WASM bytecode to confirm the correctness of the bytecode transmission; then, the processor decodes the bytecode segment in real time and completes the non-code segment function and code segment function of the bytecode segment, and the parsing of each segment is divided into three states of segment header parsing, vector header parsing and item content parsing, which are specifically: 1) Segment header parsing: each time lasts one period, in which the segment type register and the segment length register in the state machine are updated; the segment type value determines the decoding method of the subsequent vector, and the segment length value is used to skip the useless segment; 2) Vector header parsing: each time lasts one period, in which the item total number register in the state machine is refreshed, and the item counter in the state machine is set to zero; 3) Item content parsing: the bytecode decoder parses the content of each item in turn, and at the same time, the item counter in the state machine is incremented, and the parsed item number and the item total number value are compared after each item is parsed; when the parsed item number reaches the item total number value, if the code segment has not been parsed, return to the segment header parsing state; if the code segment is parsed, it means that all necessary segments have been parsed, and the execution stage is entered; (III) instruction execution stage At the beginning of the instruction execution stage, the jump control unit obtains the starting function address from the function address lookup table, and the BP also jumps to the position of the code segment; the five kinds of instructions supported by WASM are executed in sequence in each period during the execution stage; when the starting frame at the bottom of the control stack is popped, the control stack is emptied, the instruction execution stage ends, and the processor enters the output stage; (IV) output stage In the output stage, the processor sends an end signal to the host, the host actively reads the memory of the processor, and then reads out the running result of the WASM code module to complete the result output.
8. The method of claim 7, wherein, The function of each segment of the bytecode segment is as follows: the type segment parses the function signature type and updates the function signature lookup table; the function segment parses the function signature index corresponding to each function and updates the signature index lookup table; the global segment parses and records the number, type and initial value of the global variable; the start segment acquires the start function index; the code segment pre-parsing parses and records the function start address and local variable information in each function header.
9. The method of claim 7, wherein, The instruction execution stage works in the following manner for five different types of instructions respectively: (1) numerical value instruction and parameter instruction: the operand stack pops out the required operation number and inputs it into the arithmetic logic module, and the arithmetic logic module outputs the operation result to the stack; (2) control instruction: when the call / block / loop / if instruction is executed, the operand stack calculates the operand stack pointer address and the operand stack top pointer of the new code block; the memory between the operand stack pointer address and the new operand stack top pointer is the newly allocated local variable memory; at the same time, the control block type, return address, operand stack pointer address and return value flag of the new control block are packaged into a frame and pushed into the control stack; when the end instruction is encountered, the top frame of the control stack is popped out, and the corresponding jump, operand stack top pointer return and return value stack operation are completed according to the information stored in the top frame; (3) local variable instruction: the immediate number decoded from the LEB128 decoder plus the code block operand stack address stored in the control stack is the address of the local variable in the operand stack, and the address calculation is completed by the arithmetic logic module, and the access operation of the local variable can be completed by reading and writing the address in the operand stack; (4) global variable instruction: the immediate number decoded from the LEB128 decoder plus the global variable base address is the global variable address, and the address calculation is completed by the arithmetic logic module, and the access operation of the global variable can be completed by reading and writing the address in the memory unit; (5) memory instruction: the address operation number popped out from the operand stack plus the immediate number offset decoded from the LEB128 decoder is the memory start byte address, and the address calculation is completed by the arithmetic logic module; the memory read / write operation can be completed by reading and writing the address in the memory unit.