Processor, board card and electronic equipment

Abstract

The invention provides a processor, a board card and electronic equipment, the processor comprises an instruction memory, an instruction decompression module, an instruction execution module and a data memory, the instruction memory is used for storing a compression instruction; the instruction decompression module is used for decompressing the compression instruction and generating a corresponding instruction to be processed; the instruction execution module is used for executing the instruction to be processed; the data memory is used for storing to-be-processed data and corresponding processing results; wherein the compression instruction comprises instruction parameters, and the instruction parameters comprise an operation code, an input data base address, a loop parameter and a step length parameter. According to the processor provided by the embodiment of the invention, the execution efficiency of the processor is improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, specifically to a processor, circuit board, and electronic device. Background Technology

[0002] In the existing computer system architecture, the processor is the core of computer data processing, and the instructions are the set of commands that guide its operation. The processor performs data processing by executing instructions.

[0003] In existing technologies, the host computer typically plays a core role in instruction management and scheduling, writing instructions to be executed in batches to the processor's on-chip memory via specific communication protocols. This design stems from the extremely high access speed between on-chip memory and the processor core, significantly reducing instruction read latency and ensuring efficient operation of the processor's execution unit. When a task needs to be executed, the processor's instruction execution unit can directly and quickly read instructions from the on-chip memory, completing the operation through decoding, computation, and other steps. However, on-chip memory is often severely limited by physical size and hardware cost. In certain scenarios, such as multi-tasking operating systems, high-level algorithm execution, and machine learning training tasks, the size of the instructions can expand rapidly, easily exceeding the on-chip memory's capacity. When the total number of instructions exceeds the on-chip storage capacity, a frequent instruction swapping strategy is adopted, dynamically loading some instructions from external memory to the on-chip memory, and then replacing them with other instructions after the instructions on the on-chip memory have been executed. This introduces a large number of additional read and write operations, significantly increasing processor latency and leading to a decrease in execution efficiency.

[0004] Therefore, how to overcome the limitations of on-chip memory capacity to accommodate more instructions has become an important research direction for processors. Summary of the Invention

[0005] In view of the problems in the prior art, embodiments of the present invention provide a processor, board, and electronic device that can at least partially solve the problems existing in the prior art.

[0006] In a first aspect, the present invention proposes a processor, comprising an instruction memory, an instruction decompression module, an instruction execution module, and a data memory, wherein:

[0007] The instruction memory is used to store compression instructions;

[0008] The instruction decompression module is used to decompress and compress instructions, generating corresponding instructions to be processed.

[0009] The instruction execution module is used to execute the instruction to be processed;

[0010] The data storage device is used to store the data to be processed and the corresponding processing results;

[0011] The compression instruction includes instruction parameters, which include an opcode, an input data base address, a loop parameter, and a step size parameter.

[0012] Further, the compression instruction is a first type of instruction, the loop parameters of the first type of instruction include a first loop count, a second loop count, and a third loop count, and the step size parameters of the first type of instruction include a first step size, a second step size, and a third step size; correspondingly, the instruction decompression module is specifically used for:

[0013] Initialize the first current loop count, the second current loop count, and the third current loop count to 1;

[0014] If it is determined that the first current loop count is less than or equal to the first loop count, the second current loop count is less than or equal to the second loop count, and the third current loop count is less than or equal to the third loop count, then an opcode for the current instruction to be processed is generated according to the opcode of the compression instruction, and a data processing address for the current instruction to be processed is generated according to the input data base address, the step size parameter, and the first, second, and third current loop counts, until the loop termination condition is met; wherein, after each generation of the current instruction to be processed, the first current loop count, the second current loop count, or the third current loop count is accumulated; the loop termination condition is that the number of generated instructions to be processed is equal to the product of the first loop count, the second loop count, and the third loop count.

[0015] Further, the compression instruction is a second type of instruction, and the instruction parameters of the second type of instruction include multiple opcodes arranged in a preset order and an input data base address matching the multiple opcodes; the instruction decompression module is specifically used for:

[0016] Initialize the current loop count to 1;

[0017] If it is determined that the current loop count is less than or equal to the loop parameter, then a current group of instructions to be processed is generated based on multiple opcodes arranged in a preset order, the input data base address matching the multiple opcodes, the step size parameter, and the current loop count, until the current loop count is greater than the loop parameter; wherein, after each generation of the current group of instructions to be processed, the current loop count is incremented.

[0018] Further, the step of generating the current group of instructions to be processed based on multiple opcodes arranged in a preset order, the input data base address matching the multiple opcodes, the step size parameter, and the current loop count includes:

[0019] The instruction parameters include multiple opcodes arranged in a preset order. The opcode of the i-th instruction to be processed in the current group is generated based on the i-th opcode. The data processing address of the i-th instruction to be processed is generated based on the input data base address, step size parameter and current loop count that match the i-th opcode. Wherein, i is greater than or equal to 1 and less than or equal to the total number of the multiple opcodes.

[0020] Furthermore, the compression instruction is a third type of instruction, and the input data base address includes the base address of a non-zero element and the base address of a vector; correspondingly, the instruction decompression module is specifically used for:

[0021] Initialize the current loop count to 1;

[0022] If it is determined that the current loop count is less than or equal to the loop parameter, then the opcode of the current instruction to be processed is generated according to the opcode of the compression instruction; the non-zero element address of the current instruction to be processed is generated according to the non-zero element base address, the current step size, and the current loop count; and the vector component address of the current instruction to be processed is generated according to the vector base address, the current step size, and the current loop count, until the current loop count is greater than the loop parameter; wherein, after each generation of the current instruction to be processed, the current loop count is accumulated.

[0023] Furthermore, the processor provided in this embodiment of the invention also includes an instruction generation module, which is used to generate compressed instructions.

[0024] Furthermore, the compression command also includes auxiliary parameters.

[0025] Furthermore, the auxiliary parameters include at least one of the following: output data base address, data block base address, and vector address.

[0026] Secondly, the present invention provides a board that includes at least one processor as described in any of the above embodiments.

[0027] Thirdly, the present invention provides an electronic device comprising at least one board as described in the above embodiments.

[0028] The processor provided in this embodiment of the invention includes an instruction memory, an instruction decompression module, an instruction execution module, and a data memory. The instruction memory stores compressed instructions; the instruction decompression module decompresses the compressed instructions to generate corresponding instructions to be processed; the instruction execution module executes the instructions to be processed; and the data memory stores data to be processed and corresponding processing results. The compressed instructions include instruction parameters, which include an opcode, an input data base address, a loop parameter, and a step size parameter. Because more instructions can be stored in a compressed manner, the frequency of instruction exchange with external systems is reduced, and instruction read / write operations are decreased, thereby improving the processor's execution efficiency. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0030] Figure 1 This is a schematic diagram of the structure of a processor provided in an embodiment of the present invention.

[0031] Figure 2 This is a schematic diagram of the processor provided in another embodiment of the present invention.

[0032] Figure 3 This is a schematic diagram of the decompression process of the first type of instruction provided in an embodiment of the present invention.

[0033] Figure 4 This is a schematic diagram of the decompression process of the second type of instruction provided in an embodiment of the present invention. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. The acquisition, storage, use, and processing of data in the technical solutions of this application all comply with the relevant provisions of laws and regulations. The user information in the embodiments of this application is obtained through legal and compliant means, and the acquisition, storage, use, and processing of user information have been agreed upon by the customer.

[0035] To facilitate understanding of the technical solution provided in this application, the relevant content of the technical solution in this application will be explained below.

[0036] Processor-executed instructions typically include an opcode and operands. The opcode specifies the operation to be performed, such as addition, subtraction, multiplication, matrix multiplication, convolution, memory access, and jump. Operands specify the objects of the operation, such as registers, memory addresses, or constants.

[0037] Processors have limited storage space, and when there are many instructions, there may not be enough storage space to store them all, especially when processing large-scale data, such as computations in artificial intelligence tasks. Therefore, this invention provides a processor that stores instructions in a compressed format on on-chip memory, effectively reducing on-chip storage space usage and improving on-chip storage utilization efficiency. Furthermore, when fetching instructions, reading compressed instructions is equivalent to reading multiple instructions to be processed, reducing the frequency of instruction fetching and thus reducing power consumption.

[0038] Figure 1 This is a schematic diagram of the processor provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the processor provided in this embodiment of the invention includes an instruction memory 1, an instruction decompression module 2, an instruction execution module 3, and a data memory 4, wherein:

[0039] Instruction memory 1 is used to store compression instructions;

[0040] Command decompression module 2 is used to decompress compressed commands and generate corresponding commands to be processed;

[0041] Instruction execution module 3 is used to execute the instruction to be processed;

[0042] Data storage 4 is used to store the data to be processed and the corresponding processing results;

[0043] The compression instruction includes instruction parameters, which include an opcode, an input data base address, a loop parameter, and a step size parameter.

[0044] Specifically, instruction memory 1 can store compression instructions. Each compression instruction includes instruction parameters, which include an opcode, an input data base address, a loop parameter, and a step parameter. The opcode in the compression instruction is the opcode in the processor instruction, used to specify the operation to be performed, such as addition, subtraction, matrix multiplication, convolution, etc. The input data base address is used to recover the storage address of the operand; the complete address of the operand can be obtained through the input data base address and the step parameter. The loop parameter specifies the number of processor instructions that can be recovered during decompression of the compression instruction. The step parameter specifies the offset address of the operand. The processor provided in this embodiment can receive compression instructions from an external source and store them in instruction memory 1.

[0045] The instruction decompression module 2 can retrieve compression instructions from the instruction memory 1, then decompress the compression instructions to generate corresponding pending instructions. Each compression instruction will decompress into multiple pending instructions. The pending instructions may include opcodes and the data storage address of the data to be processed.

[0046] The instruction execution module 3 obtains the corresponding instruction to be processed from the instruction decompression module 2 and executes each instruction to be processed. The instruction execution module 3 can read the data to be processed from the data storage memory 4 according to the data storage address of the data to be processed included in the instruction to be processed, and perform corresponding processing based on the opcode included in the instruction to be processed.

[0047] The processor provided in this embodiment of the invention includes an instruction memory, an instruction decompression module, an instruction execution module, and a data memory. The instruction memory stores compressed instructions; the instruction decompression module decompresses the compressed instructions to generate corresponding instructions to be processed; the instruction execution module executes the instructions to be processed; and the data memory stores data to be processed and corresponding processing results. The compressed instructions include instruction parameters, including an opcode, an input data base address, a loop parameter, and a step size parameter. Because more instructions can be stored in a compressed manner, the frequency of instruction exchange with external systems is reduced, and instruction read / write operations are decreased, thereby improving the processor's execution efficiency. Furthermore, reading compressed instructions is equivalent to reading multiple instructions to be processed, reducing the instruction reading frequency and thus reducing power consumption.

[0048] Based on the above embodiments, the compression instruction is further defined as a first type of instruction. The loop parameters of the first type of instruction include a first loop count, a second loop count, and a third loop count. The step size parameters of the first type of instruction include a first step size, a second step size, and a third step size. Correspondingly, the instruction decompression module is specifically used for:

[0049] Initialize the first current loop count, the second current loop count, and the third current loop count to 1;

[0050] If it is determined that the first current loop count is less than or equal to the first loop count, the second current loop count is less than or equal to the second loop count, and the third current loop count is less than or equal to the third loop count, then an opcode for the current instruction to be processed is generated according to the opcode of the compression instruction, and a data processing address for the current instruction to be processed is generated according to the input data base address, the step size parameter, and the first, second, and third current loop counts, until the loop termination condition is met; wherein, after each generation of the current instruction to be processed, the first current loop count, the second current loop count, or the third current loop count is accumulated; the loop termination condition is that the number of generated instructions to be processed is equal to the product of the first loop count, the second loop count, and the third loop count.

[0051] Specifically, the compression instruction is a first type of instruction, used to process three-dimensional tensor operations, including but not limited to three-dimensional convolution. The loop parameters of the first type of instruction include a first loop count, a second loop count, and a third loop count, each corresponding to a different dimension. For example, the first loop count corresponds to rows, representing the number of loops in the row dimension; the second loop count corresponds to columns, representing the number of loops in the column dimension; and the third loop count corresponds to depth, representing the number of loops in the depth dimension. The stride parameters of the first instruction include a first step length, a second step length, and a third step length. These three step lengths also correspond to different dimensions. For example, the first step length corresponds to rows, representing the offset in the row dimension; the second step length corresponds to columns, representing the offset in the column dimension; and the third step length corresponds to depth, representing the offset in the depth dimension.

[0052] When decompressing the first type of instruction, decompression needs to be performed in three dimensions. First, the first current loop count, the second current loop count, and the third current loop count are initialized to 1. Then, the first current loop count is compared with the first loop count, the second current loop count with the second loop count, and the third current loop count with the third loop count. If the first current loop count is less than or equal to the first loop count, the second current loop count is less than or equal to the second loop count, and the third current loop count is less than or equal to the third loop count, it indicates that the compression instruction has not been completely decompressed. Based on the opcode of the compression instruction, the opcode of the current instruction to be processed is generated, using the opcode of the compression instruction as the opcode of the current instruction to be processed. Furthermore, based on the input data base address, the step size parameter, and the first, second, and third current loop counts, the data processing address of the current instruction to be processed is generated.

[0053] Accumulate the first current loop count, the second current loop count, or the third current loop count, and then compare the first current loop count with the first loop count, the second current loop count with the second loop count, and the third current loop count with the third loop count. If the first current loop count is less than or equal to the first loop count, the second current loop count is less than or equal to the second loop count, and the third current loop count is less than or equal to the third loop count, it indicates that the compression instruction has not been decompressed. Based on the opcode of the compression instruction, generate the opcode of the current instruction to be processed, using the opcode of the compression instruction as the opcode of the current instruction to be processed. Then, based on the input data base address, the step size parameter, the first current loop count, the second current loop count, and the third current loop count, generate the data processing address of the current instruction to be processed.

[0054] The above process is repeated, continuously generating instructions to be processed, until the number of instructions generated equals the product of the first loop count, the second loop count, and the third loop count, thus satisfying the loop termination condition and ending the decompression of the compression instructions. When the loop termination condition is met, the first current loop count equals the first loop count, the second current loop count equals the second loop count, and the third current loop count equals the third loop count.

[0055] The instruction parameters of the first type of instruction may further include a data block base address and an output data base address. The data block base address includes, but is not limited to, the convolution kernel base address, and is used to address the starting address of the data block. The output data base address is used to determine the data storage address of the output result after the instruction to be processed is executed. The output data base address, together with the first step size, the second step size, and the third step size, can obtain the complete address of the output result.

[0056] Based on the above embodiments, the step of generating the data processing address of the current instruction to be processed according to the input data base address, the step size parameter, and the first current loop count, the second current loop count, and the third current loop count includes:

[0057] Based on the three-dimensional address mapping formula AddrInput = BaseAddrInput + e·StrideX + j·StrideY + k·StrideZ, the data processing address AddrInput of the current instruction to be processed is calculated. BaseAddrInput represents the base address of the input data, StrideX represents the first step length, StrideY represents the second step length, StrideZ represents the third step length, e represents the first current loop count, j represents the second current loop count, and k represents the third current loop count.

[0058] For example, the first type of instruction Q is used to process convolution operations in deep learning. The first type of instruction Q includes: a 3D convolution opcode, input data base address, convolution kernel base address, output data base address, X-axis loop count (i.e., first loop count), Y-axis loop count (i.e., second loop count), Z-axis loop count (i.e., third loop count), X-axis stride (i.e., first step size), Y-axis stride (i.e., second step size), and Z-axis stride (i.e., third step size). Here, the X-axis corresponds to rows, the Y-axis corresponds to columns, and the Z-axis corresponds to depth.

[0059] Assuming the X-axis, Y-axis, and Z-axis loop counts are all 8, without instruction compression, 8 × 8 × 8 = 512 independent instructions would need to be stored. If each instruction is 52 bits, then a total of 26,624 bits would be required. However, using the compressed instruction method described in this application, the first type of instruction Q is a 60-bit instruction, achieving a compression efficiency of 99.77%.

[0060] After decompression, the first type of instruction Q yields 52 instructions to be processed. The decompression process for the first type of instruction Q is as follows: Figure 3 As shown:

[0061] Step 1: Initialize the loop count. Initialize the first current loop count e=1, the second current loop count j=1, and the third current loop count k=1.

[0062] Step 2: Determine if e, j, and k are less than or equal to 8. First, check if the current loop count e is less than or equal to the X-axis loop count (8). Second, check if the current loop count j is less than or equal to the Y-axis loop count (8). Third, check if the current loop count k is less than or equal to the Z-axis loop count (8). If e, j, and k are all less than or equal to 8, proceed to step 3. If e is greater than 8, j is greater than 8, or k is greater than 8, it indicates a problem with data accumulation; in this case, the process ends, and an error message can be displayed.

[0063] The third step is to generate the opcode for the instruction to be processed. The opcode for instruction Q (of type I) is obtained as the opcode for the instruction to be processed.

[0064] Step 4: Generate the data processing address of the current instruction to be processed. Based on the input data base address of the first type of instruction Q, the step size parameter L, the first current loop count e, the second current loop count j, and the third current loop count k, calculate the data processing address of the current instruction to be processed.

[0065] Step 5: Output the currently pending instruction. The currently pending instruction includes the opcode and the data processing address of the currently pending instruction.

[0066] Step 6: Calculate e = e + 1. Add 1 to the value of e.

[0067] Step 7: Determine if e is greater than 8. If e is less than or equal to 8, return to step 2; if e is greater than 8, proceed to step 8.

[0068] Step 8: Calculate j = j + 1 and initialize e. Increment the value of j by 1 and initialize e = 1.

[0069] Step 9: Determine if j is greater than 8. If j is less than or equal to 8, return to step 2; if j is greater than 8, proceed to step 10.

[0070] Step 10: Calculate k = k + 1, and initialize e and j. Increment the value of k by 1, and initialize e = 1 and j = 1.

[0071] Step 11: Determine if k is greater than 8. If k is less than or equal to 8, return to step 2; if k is greater than 8, then 8×8×8=512 instructions to be processed have been generated, and the compression instructions have been decompressed.

[0072] Based on the above embodiments, the compression instruction is further defined as a second type of instruction, wherein the instruction parameters of the second type of instruction include multiple opcodes arranged in a preset order and an input data base address matching the multiple opcodes; the instruction decompression module is specifically used for:

[0073] Initialize the current loop count to 1;

[0074] If it is determined that the current loop count is less than or equal to the loop parameter, then a current group of instructions to be processed is generated based on multiple opcodes arranged in a preset order, the input data base address matching the multiple opcodes, the step size parameter, and the current loop count, until the current loop count is greater than the loop parameter; wherein, after each generation of the current group of instructions to be processed, the current loop count is incremented.

[0075] Specifically, the compression instruction is a second type of instruction. This second type of instruction is used to process combined operations, which include combinations of at least two opcodes. The instruction parameters of the second type of instruction include multiple opcodes arranged in a preset order and input data base addresses matching the multiple opcodes. The preset order of the multiple opcodes is used to determine the execution order of the instructions to be processed corresponding to each opcode. The input data base addresses corresponding to each opcode are different. The instruction parameters of the second type of instruction include multiple input data base addresses, and each input data base address has a corresponding opcode.

[0076] When decompressing the second type of instructions, multiple opcodes arranged in a preset order need to be decompressed. First, the current loop count is initialized to 1. Then, the current loop count is compared with the loop parameter. For the second type of instructions, the loop parameter represents the total number of combined opcodes formed by multiple opcodes arranged in a preset order. If the current loop count is less than or equal to the loop parameter, it indicates that there are undecompressed combined opcodes. The instruction decompression module generates a pending instruction for each opcode based on the multiple opcodes included in the compressed instruction, arranged in a preset order. It also generates a data processing address for the pending instruction corresponding to each opcode based on the input data base address matched by each opcode, the step size parameter, and the current loop count. The resulting pending instructions corresponding to the multiple opcodes are used as the current group of pending instructions, and then the current loop count is incremented by 1. The matching relationship between the opcode and the input data base address is predetermined.

[0077] After incrementing the current loop count by 1, it is compared with the loop parameter. If the current loop count is less than or equal to the loop parameter, it indicates that there are undecompressed combination opcodes. The instruction decompression module will generate a processing instruction for each opcode according to the multiple opcodes included in the compression instruction and arranged in a preset order. It will also generate the data processing address of the processing instruction corresponding to each opcode according to the input data base address matched by each opcode, the step size parameter, and the current loop count. The processing instructions corresponding to the multiple opcodes are used as the current group of processing instructions, and then the current loop count is incremented by 1.

[0078] Similarly, when the current loop count exceeds the loop parameter, the decompression of the second type of instruction is completed.

[0079] Based on the above embodiments, the step of generating the current group of instructions to be processed based on a plurality of opcodes arranged in a preset order, an input data base address matching the plurality of opcodes, the step size parameter, and the current loop count includes:

[0080] The instruction parameters include multiple opcodes arranged in a preset order. The opcode of the i-th instruction to be processed in the current group is generated based on the i-th opcode. The data processing address of the i-th instruction to be processed is generated based on the input data base address, step size parameter and current loop count that match the i-th opcode. Wherein, i is greater than or equal to 1 and less than or equal to the total number of the multiple opcodes.

[0081] Specifically, the first opcode is selected from a plurality of opcodes arranged in the preset order and used as the opcode of the first instruction to be processed in the current group. The data processing address of the first instruction to be processed is generated based on the input data base address, step size parameter and current loop number that match the first opcode.

[0082] According to the preset order, the second opcode is selected from multiple opcodes arranged in the preset order and used as the opcode of the second instruction to be processed in the current group. The data processing address of the second instruction to be processed is generated based on the input data base address, step size parameter and current loop number that match the second opcode.

[0083] According to the preset order, the third opcode is selected from the multiple opcodes arranged in the preset order and used as the opcode of the third instruction to be processed in the current group. The data processing address of the third instruction to be processed is generated according to the input data base address, step size parameter and current loop number that match the third opcode.

[0084] Similarly, when the instruction parameters, including all opcodes, have been traversed, the traversal stops, and the generation of instructions to be processed in the current group ends.

[0085] The data processing address for the i-th instruction to be processed is generated based on the input data base address matching the i-th opcode, the step size parameter, and the current loop count.

[0086] If there is an input data base address that matches the i-th opcode, then the data processing address of the i-th instruction to be processed can be obtained based on the input data base address, the step size parameter, and the current loop count.

[0087] If there are multiple input data base addresses that match the i-th opcode, the data processing address of the i-th instruction to be processed can be obtained based on each input data base address, step size parameter, and current loop count. There will be multiple data processing addresses for the i-th instruction to be processed, and the i-th opcode will process multiple data to be processed.

[0088] The data processing address AddrInput can be calculated using the formula AddrInput = BaseAddrInput + μ·Stride, where BaseAddrInput represents the base address of the input data, Stride represents the step size parameter, and μ represents the current loop count.

[0089] For example, the second type of instruction M is used to process combinatorial operations in deep learning, including multiplication, addition and ReLU activation, to calculate the product of the first and second values, add the product to the third value, and activate the result of the addition.

[0090] The second type of instruction M includes: multiplication opcode, addition opcode, ReLU activation opcode, base address of input data A, base address of input data B, base address of input data C, base address of output data, loop parameter, and step parameter.

[0091] Assuming the loop parameter is 16, the second type of instruction M will decompress into 16 groups of instructions to be processed. Each group of instructions will include one multiplication instruction, one addition instruction, and one ReLU activation instruction. The decompression process of the second type of instruction M is as follows: Figure 4 As shown:

[0092] Step 1: Initialize the current loop count. The current loop count is initialized to 1.

[0093] Step 2: Determine if the current loop count is less than or equal to 16. If it is less than or equal to 16, proceed to step 3; if it is greater than 16, the process ends, and the second type of instruction M is decompressed.

[0094] The third step is to initialize the number of iterations to 1.

[0095] Step 4: Generate multiplication instructions. Obtain the first opcode from the second type of instruction M as the multiplication opcode for the multiplication instruction. Based on the base address of the input data A corresponding to the first opcode and the step parameter, obtain the data storage address of the first value of the multiplication instruction. Based on the base address of the input data B and the step parameter, obtain the data storage address of the second value of the multiplication instruction. Based on the base address of the output data and the step parameter, obtain the data storage address of the multiplication result of the multiplication instruction. The multiplication instruction includes the multiplication opcode, the data storage address of the first value, the data storage address of the second value, and the data storage address of the multiplication result. Increment the traversal count by 1.

[0096] Step 5: Generate the addition instruction. Obtain the second opcode from the second type of instruction M as the multiplication opcode for the addition instruction. Based on the base address of the input data C corresponding to the second opcode and the step parameter, obtain the data storage address of the first value of the addition instruction. Use the data storage address of the multiplication result as the data storage address of the second value of the addition instruction. Then, based on the output data base address, the step parameter, and the number of iterations, obtain the data storage address of the multiplication result of the addition instruction. Increment the iteration count by 1.

[0097] Step 6: Generate ReLU activation processing instructions. Obtain the third opcode in the second type of instruction M as the ReLU activation opcode for the ReLU activation processing instruction, and obtain the data storage address of the multiplication result as the data storage address to be processed by the ReLU activation processing instruction. Increment the traversal count by 1.

[0098] Step 7: Determine if opcode decompression is complete. Continue to retrieve opcodes from the second type of instruction M. If no more opcodes are available, then all opcodes have been decompressed, the current loop count is incremented by 1, and the process returns to step 2.

[0099] Compressing multiplication, addition, and ReLU activation instructions into a single instruction saves storage space. The second type of instruction M, after decompression, generates 48 instructions (16 processing instructions + 16 addition instructions + 16 ReLU activation instructions).

[0100] Based on the above embodiments, further, the compression instruction is a third type of instruction, and the input data base address includes the base address of a non-zero element and the base address of a vector; correspondingly, the instruction decompression module is specifically used for:

[0101] Initialize the current loop count to 1;

[0102] If it is determined that the current loop count is less than or equal to the loop parameter, then the opcode of the current instruction to be processed is generated according to the opcode of the compression instruction; the non-zero element address of the current instruction to be processed is generated according to the non-zero element base address, the current step size, and the current loop count; and the vector component address of the current instruction to be processed is generated according to the vector base address, the current step size, and the current loop count, until the current loop count is greater than the loop parameter; wherein, after each generation of the current instruction to be processed, the current loop count is accumulated.

[0103] Specifically, the compression instruction is a third type of instruction, used to process sparse matrix multiplication. A sparse matrix includes zero and non-zero elements, with the number of zero elements greater than the number of non-zero elements. Sparse matrix multiplication calculates the product of non-zero elements and vector components. The input data base addresses of the third type of instruction include non-zero element base addresses and vector base addresses; the non-zero element base addresses are used to recover the storage addresses of the non-zero elements, and the storage addresses of each non-zero element can be obtained through the non-zero element base addresses and the step size parameter. The vector base addresses are used to recover the storage addresses of the vector components, and the storage addresses of each vector component can be obtained through the vector base addresses and the step size parameter.

[0104] When decompressing the third type of instructions, it is necessary to recover the storage addresses of the non-zero elements of the sparse matrix and the storage addresses of the corresponding vector components. First, the current loop count is initialized to 1. Then, the current loop count is compared with the loop parameter. For the third type of instructions, the loop parameter equals the number of instructions to be processed after decompression. If the current loop count is less than or equal to the loop parameter, it indicates that there are undecompressed instructions to be processed. The instruction decompression module obtains the opcode of the compressed instruction as the opcode of the current instruction to be processed, and generates the non-zero element address of the current instruction to be processed based on the non-zero element base address, the current step size, and the current loop count. It also generates the vector component address of the current instruction to be processed based on the vector base address, the current step size, and the current loop count. Then, the current loop count is incremented by 1.

[0105] After incrementing the current loop count by 1, it is compared with the loop parameter. If the current loop count is less than or equal to the loop parameter, it indicates that there are uncompressed instructions to be processed. The instruction decompression module will obtain the opcode of the compressed instruction as the opcode of the current instruction to be processed, and generate the non-zero element address of the current instruction to be processed based on the non-zero element base address, the current step size, and the current loop count. It will also generate the vector component address of the current instruction to be processed based on the vector base address, the current step size, and the current loop count. Then, the current loop count is incremented by 1.

[0106] Similarly, when the current loop count exceeds the loop parameter, the decompression of the third type of instruction is completed.

[0107] The third type of instruction uses non-contiguous address compression, meaning it only stores the address offsets of non-zero elements, skipping zero elements and reducing redundant storage. Assuming a sparse matrix size of 1000x1000 and a sparsity of 1%, storing all 1,000,000 instructions (52 bits each) would require 52MB. Using the third type of instruction in this application, only 100 non-zero element instructions (60 bits / instruction) are stored, resulting in a total storage size of 6KB and a compression efficiency of 99.88%.

[0108] Figure 2 This is a schematic diagram of the processor provided in another embodiment of the present invention, as shown below. Figure 2 As shown, based on the above embodiments, the processor provided in this embodiment of the invention further includes an instruction generation module 5, which is used to generate compressed instructions.

[0109] Specifically, for multiple data items that need to be processed using the same opcode, the same opcode can be used as the opcode of the compression instruction. The multiple data items are stored in a storage address that can be represented by the input data base address and the step parameter, and the number of multiple data items is obtained as the loop parameter, thereby generating the compression instruction.

[0110] Based on the above embodiments, the compression instruction further includes auxiliary parameters. The auxiliary parameters include at least one of the following: output data base address, data block base address, and vector address.

[0111] The output data base address is used to determine the storage address of the output result obtained after the instruction to be processed is executed. The complete address of the output result can be obtained through the output data base address and the step size parameter.

[0112] The data block base address, such as the convolution kernel base address, is used to indicate the starting address of the convolution kernel, thereby addressing the position of the convolution kernel.

[0113] The vector address can include the vector base address and the vector step size, which are used to determine the vector components multiplied by the non-zero elements.

[0114] This invention provides a board that includes at least one processor as described in any of the above embodiments. The processor may be a SIMD processor, a reconfigurable processor, or an AI processor, etc.

[0115] This invention provides an electronic device including at least one board as described in any of the above embodiments. The electronic device includes, but is not limited to, user equipment (UE), mobile devices, user terminals, personal digital assistants (PDAs), handheld devices, computing devices, in-vehicle devices, and other devices with AI application requirements.

[0116] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0117] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0118] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0119] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0120] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0121] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A processor, comprising: The system comprises an instruction memory, an instruction decompression module, an instruction execution module and a data memory, wherein: The instruction memory is configured to store compressed instructions; The instruction decompression module is configured to decompress the compressed instructions to generate corresponding to-be-processed instructions; The instruction execution module is configured to execute the to-be-processed instructions; The data memory is configured to store to-be-processed data and corresponding processing results; The compressed instructions comprise instruction parameters, and the instruction parameters comprise an operation code, an input data base address, a loop parameter and a step parameter.

2. The processor of claim 1, wherein, The compressed instructions are first-type instructions, the loop parameter of the first-type instructions comprises a first loop count, a second loop count and a third loop count, and the step parameter of the first-type instructions comprises a first step, a second step and a third step; accordingly, the instruction decompression module is specifically configured to: initialize a first current loop count, a second current loop count and a third current loop count to 1; if it is determined that the first current loop count is less than or equal to the first loop count, the second current loop count is less than or equal to the second loop count and the third current loop count is less than or equal to the third loop count, generate an operation code of a current to-be-processed instruction according to the operation code of the compressed instruction, and generate a data processing address of the current to-be-processed instruction according to the input data base address, the step parameter and the first current loop count, the second current loop count and the third current loop count, until a loop end condition is met; wherein the first current loop count, the second current loop count or the third current loop count is incremented each time a current to-be-processed instruction is generated; the loop end condition refers to the number of generated to-be-processed instructions being equal to the product of the first loop count, the second loop count and the third loop count.

3. The processor of claim 1, wherein, The compressed instructions are second-type instructions, the instruction parameters of the second-type instructions comprise a plurality of operation codes arranged in a preset order and input data base addresses matched with the plurality of operation codes; and the instruction decompression module is specifically configured to: initialize a current loop count to 1; if it is determined that the current loop count is less than or equal to the loop parameter, generate a current group of to-be-processed instructions based on the plurality of operation codes arranged in the preset order, the input data base addresses matched with the plurality of operation codes, the step parameter and the current loop count, until the current loop count is greater than the loop parameter; wherein the current loop count is incremented each time a current group of to-be-processed instructions is generated.

4. The processor of claim 3, wherein, The generation of the current group of to-be-processed instructions based on the plurality of operation codes arranged in the preset order, the input data base addresses matched with the plurality of operation codes, the step parameter and the current loop count comprises: According to the preset order, the plurality of operation codes included in the instruction parameter are traversed in the preset order, an operation code of an i-th to-be-processed instruction of a current group of to-be-processed instructions is generated according to an i-th operation code, and a data processing address of the i-th to-be-processed instruction is generated according to an input data base address matched with the i-th operation code, a step parameter, and a current loop number; wherein i is greater than or equal to 1 and less than or equal to a total number of the plurality of operation codes.

5. The processor of claim 1, wherein, The compressed instruction is a third type of instruction, and the input data base address includes a non-zero element base address and a vector base address; correspondingly, the instruction decompression module is specifically used for: initializing the current loop number as 1; if it is judged that the current loop number is less than or equal to the loop parameter, generating an operation code of a current to-be-processed instruction according to the operation code of the compressed instruction, generating a non-zero element address of the current to-be-processed instruction according to the non-zero element base address, a current step, and the current loop number, and generating a vector component address of the current to-be-processed instruction according to the vector base address, the current step, and the current loop number, until the current loop number is greater than the loop parameter; wherein the current loop number is accumulated each time a current to-be-processed instruction is generated.

6. The processor of claim 1, wherein, The instruction generation module is further used for generating a compressed instruction.

7. The processor of any one of claims 1 to 6, wherein, The compressed instruction further includes an auxiliary parameter.

8. The processor of claim 7, wherein, The auxiliary parameter includes at least one of an output data base address, a data block base address, and a vector address.

9. A board card characterized by, The system includes at least one processor as claimed in any one of claims 1 to 8.

10. An electronic device, comprising: The system includes at least one board card as claimed in claim 9.

Images