A method for multiplexing upgrade links and controlling backup activation

Abstract

The application discloses a method for multiplexing upgrade links and controlling backup starting, and the whole system comprises an upper computer and a target board card, and the target board card is provided with two kinds of chips, namely, FPGA and FT-M6678. The FPGA communicates with the upper computer through one interface, and on the basis of realizing the online upgrade function, the FPGA is connected with one new serial port and a serial port controller of the FT-M6678 through the signal transparent transmission operation and the signal sending operation of the serial port, so that the upgrade file transmission is realized; the FPGA receives the backup starting switching instruction sent by the upper computer, switches the level and the reset logic connected with the FT-M6678, and then the FT-M6678 completes the soft restart and reads the level in the bootloader stage, so as to judge whether to jump to the backup program to execute the online upgrade function or to jump to the application program to execute the user function. The application has good stability, independence and universality.

Description

Technical Field

[0001] This invention relates to the field of board firmware upgrade technology, and in particular to a method for reusing upgrade links and controlling backup startup. Background Technology

[0002] The FPGA-based hardware architecture with FT-M6678 is widely used in digital signal processing scenarios, offering advantages such as low latency, high computing power, and multi-task collaboration. The ease and stability of firmware upgrades, as well as the high degree of hardware integration, are the core design features of the system.

[0003] The traditional solution using an independent upgrade link has many drawbacks. From a hardware structure perspective, this solution leads to an increase in the number of interfaces, a larger board size, limited layout and routing, and higher component costs. From a software control perspective, the FT-M6678's boot mode switching is highly coupled with the upgrade service. Its backup program startup requires external hardware DIP switches or internal application logic triggering. The former increases the difficulty and risk of structural disassembly and assembly and cannot be remotely controlled, while the latter deeply binds the upgrade service with user functions, which contradicts the streamlined and modular concept of software development and increases the risk of system malfunction. Once the application fails, the firmware cannot be upgraded and repaired again, seriously affecting the stability and maintenance of the board.

[0004] Therefore, there is an urgent need for an online upgrade method that can reuse the upgrade chain and decouple it from the application, so as to further optimize hardware resources and improve software performance. Summary of the Invention

[0005] The purpose of this invention is to provide a method for reusing upgrade links and controlling backup startup, so as to solve the problems in the background art.

[0006] To address the aforementioned technical problems, this invention provides a method for reusing upgrade links and controlling backup startup, based on a host computer and a target board. The target board is equipped with both FPGA and FT-M6678 chips, both of which enable online upgrade and backup startup functions.

[0007] The FPGA communicates with the host computer through a 1-channel RS422 interface. In addition to realizing its own online upgrade function, it uses the pass-through operation of the serial port received signal and the AND operation operation of the transmitted signal to lead out a 1-channel serial port UART from the FPGA pin and connect it to the serial port controller of the FT-M6678 to realize the serial port upgrade file transfer of the FT-M6678.

[0008] The FPGA internally includes two serial port drivers. The serial port transceiver driver has complete transmit and receive functions and is used in conjunction with the upgrade control logic module to realize the transfer of upgrade files and flash memory of the FPGA itself. The serial port receive driver only has a separate receive function and is used in conjunction with the backup boot switching module to realize the switching control of the GPIO and PORN signals of the FT-M6678. The GPIO signal is used to indicate the boot address of the FT-M6678, and the PORN signal is used to control the soft boot of the FT-M6678.

[0009] The FT-M6678's flash stores three programs: a bootloader, a backup program, and an application program. Only the backup program contains upgrade functionality, while the application program does not contain any upgrade-related operations and consists entirely of user functions.

[0010] When upgrading the FT-M6678, the host computer first issues a backup startup switching command. After the FPGA receives and parses the command, it switches the GPIO level and porz reset logic connected to the FT-M6678. Then the FT-M6678 completes a soft reboot and reads the current GPIO level value in the bootloader stage to determine whether to jump to the backup program to execute the online upgrade function or to jump to the application program to execute normally.

[0011] In one implementation, the host computer integrates the upgrade operations of the FPGA and FT-M6678 to make them have the same upgrade process, specifically including: device type selection, baud rate selection, backup startup switching, device search, file description information distribution, and start upgrade.

[0012] The RS422 communication between the host computer and the target board, and the UART communication between the FPGA inside the target board and the FT-M6678, are all based on a unified upgrade protocol format, as follows:

[0013] The frame header consists of four bytes: 0xaa, 0x99, 0x55, and 0x66.

[0014] The data packet length is 1 byte.

[0015] The ID number is 1 byte.

[0016] Operation type: 1 byte;

[0017] The data segment consists of several bytes. When the operation type is data packet transmission, the data segment is a fixed 64 bytes. If the last packet is less than 64 bytes, it is padded with 0s.

[0018] CRC8 checksum is 1 byte, and the calculation range of CRC8 checksum includes all bytes from the frame header to the data segment.

[0019] In one implementation, when the host computer performs upgrade operations on the FPGA and FT-M6678 respectively, the serial communication baud rates are different and vary significantly. The host computer splits the original upgrade file into multiple packets and then transmits them in packets. Each data packet has a verification feedback mechanism when transmitted via the serial port. When the target chip fails to perform CRC8 verification, the host computer is triggered to retransmit. When the host computer detects that the target chip has not responded within a timeout period, a timeout retransmission is triggered.

[0020] In one implementation, the two serial port drivers of the FPGA and the one serial port controller of the FT-M6678 simultaneously parse the serial port data sent by the host computer. Neither the high-speed baud rate driver parses the low-speed real-time signal nor the low-speed baud rate driver parses the high-speed real-time signal will result in erroneous parsing.

[0021] The specific mechanism consists of two parts. The first part is the driver parsing layer, where the baud rates of the two differ by more than 10 times and the length of a single data packet is limited, thus limiting the number of messy data. The second part is the protocol parsing layer, where the received data packet is determined to be valid only if the frame header is valid, the data packet length is valid, the ID number is valid, the operation type is valid, and the final CRC8 check is valid.

[0022] In one implementation, the method includes an upgrade operation performed by a host computer, the process of which is as follows:

[0023] Step 1: Select the device type, which is either FPGA or FT-M6678. Different device types correspond to different ID numbers in the upgrade protocol format. Proceed to Step 2.

[0024] Step 2: Select the baud rate. The baud rate for FPGA and FT-M6678 is different. The specific value should be consistent with the chip. Proceed to Step 3.

[0025] Step 3: Determine whether to switch to backup startup. This operation is not required for FPGA, proceed directly to step 5; this operation is required for FT-M6678, proceed to step 4.

[0026] Step 4: Switch to backup boot. This operation is only for FT-M6678. Proceed to Step 5.

[0027] Step 5: The target device is located. The host computer issues a device search command and proceeds to step 6.

[0028] Step six: The target device receives a device presence response, the host computer receives a search response for the target device, and proceeds to step seven;

[0029] Step 7: Send file description information. The host computer sends the feature information of the upgrade file to the target device, and then proceeds to step 8.

[0030] Step 8: Upon receiving the request to load the response, it indicates that the target device has completed the erase operation on the application storage area based on the received file description information, and proceeds to step 9.

[0031] Step 9: Upgrade file transfer, send the upgrade file in packets, then proceed to Step 10;

[0032] Step 10: Upon receiving the upgrade status reply, it indicates that the target device has been successfully received. Proceed to Step 11.

[0033] Step 11: Status response judgment and packet transmission completion judgment. If the received status response is abnormal or the current packet is not the last packet sent, proceed to step 9 again; the former is to resend the current packet, and the latter is to send the next packet; if the received status response is normal and the current packet is the last packet sent, then the upgrade process ends.

[0034] In one embodiment, the method comprises two parts: an FPGA control flow and an FT-M6678 backup boot flow, specifically:

[0035] Step 1: The second serial port inside the FPGA continuously detects instructions from the host computer and proceeds to Step 2.

[0036] Step 2: Determine if a switch backup boot command has been received. If not, maintain the existing gpio and porz states and proceed to Step 1. If the command is received, proceed to Step 3.

[0037] Step 3: Pull the GPIO level low to instruct the FT-M6678 to boot from the backup program during the boot phase, and proceed to step 4;

[0038] Step 4: Continuously pull the porz signal level low and then continuously pull it high to control the FT-M6678 to reset and restart, then proceed to step 5;

[0039] Step 5: Power on and restart the FT-M6678 or reset and restart it, then proceed to Step 6;

[0040] Step six: The FT-M6678 stores three programs in its flash memory: a bootloader, a backup program, and an application program. Only the backup program contains upgrade functionality; the application program does not contain any upgrade-related operations and consists entirely of user logic functions. In this step, the FT-M6678 begins executing the bootloader to complete some system initialization work, and then proceeds to step seven.

[0041] Step 7: The bootloader program reads the GPIO level value and proceeds to step 8;

[0042] Step 8: Determine the GPIO level value. If it is high, the program jumps to the application program for execution.

[0043] When the signal is low, the program jumps to the backup program for execution; at this point, the startup process ends.

[0044] The present invention provides a method for reusing upgrade links and controlling backup startup, which has the following beneficial effects:

[0045] (1) By reusing the upgrade link, the number of external upgrade interfaces of the target board is reduced, which helps to reduce the board size, weight and layout routing; at the same time, it also realizes the integration of two chip upgrade functions by a single host computer;

[0046] (2) By controlling the output levels of gpio and porz through FPGA, the backup startup switching of FT-M6678 is realized, and the online upgrade function and application are completely separated, which not only reduces the system operation risk, but also improves the versatility of the online upgrade module. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of the system architecture of the present invention;

[0048] Figure 2 This is a schematic diagram of the process by which the host computer performs the upgrade operation according to the present invention;

[0049] Figure 3 This is a schematic diagram of the process of FPGA controlling FT-M6678 backup startup in this invention. Detailed Implementation

[0050] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a method for reusing upgrade links and controlling backup startup proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0051] This invention provides a method for reusing upgrade links and controlling backup startup, based on the following system architecture: Figure 1 As shown, it includes a host computer and a target board. The target board is equipped with both FPGA and FT-M6678 chips, both of which can realize online upgrade and backup boot functions; it can be further expanded, and the number of FT-M6678 chips is unlimited.

[0052] The FPGA communicates with the host computer through one RS422 interface (including RS422_rx and RS422_tx). In addition to realizing its own online upgrade function, it also connects to the serial port controller of FT-M6678 by passing through the serial port received signal and performing AND operation on the transmitted signal (the idle state of the serial bus is high level, and the low level is a valid signal). This enables the serial port upgrade file transfer of FT-M6678. In other words, the target board as a whole only has one serial port to connect to the host computer.

[0053] The FPGA contains two serial port drivers. The first serial port driver has complete transmit and receive functions, i.e., a serial port transmit / receive driver. It is used in conjunction with the upgrade control logic module to realize the transfer of upgrade files and flash memory of the FPGA itself. The second serial port driver only has a separate receive function, i.e., a serial port receive driver. It is used in conjunction with the backup boot switching module to realize the switching control of the GPIO and PORN signals of the FT-M6678. The GPIO is used to indicate the boot address of the FT-M6678, and the PORN is used to control the soft boot of the FT-M6678.

[0054] The two serial port drivers inside the FPGA have different baud rates. The serial port transmit and receive drivers use the baud rate of the upgraded serial port of the FPGA, while the serial port receive driver uses the same baud rate as the upgraded serial port of the FT-M6678.

[0055] The host computer integrates the upgrade operations for FPGA and FT-M6678, making them have the same upgrade process. The specific upgrade process includes: device type selection, baud rate selection, backup startup switching, device search, file description information distribution, and start upgrade.

[0056] The RS422 communication between the host computer and the target board, and the UART communication between the FPGA inside the target board and the FT-M6678, are all based on a unified upgrade protocol format, as follows: frame header (4 bytes, 0xaa, 0x99, 0x55, 0x66), data packet length (1 byte), ID number (1 byte), operation type (1 byte), data segment (several bytes, which is a fixed 64 bytes when the operation type is data packet transmission, and the last packet is padded with 0 if it is less than 64 bytes) and CRC8 checksum (1 byte). The calculation range of CRC8 checksum includes all bytes from the frame header to the data segment.

[0057] When the host computer performs upgrade operations on the FPGA and FT-M6678 respectively, the serial communication baud rates are different and differ significantly, being above 1M and below 115200bps respectively. The host computer splits the original upgrade file into multiple packets and then transmits them in packets. Each data packet transmitted via the serial port has a verification feedback mechanism. When the CRC8 verification on the target chip fails, the host computer can be triggered to retransmit. When the host computer detects that the target chip has not responded within a timeout period, it can trigger a timeout retransmission.

[0058] The FPGA's two serial port drivers and the FT-M6678's one serial port controller simultaneously parse serial data sent from the host computer. Whether a high-speed baud rate driver is parsing a low-speed real-time signal or a low-speed baud rate driver is parsing a high-speed real-time signal, no parsing errors occur. The specific mechanism consists of two parts: the first part is the driver parsing layer, where the baud rates differ by more than 10 times and the length of a single data packet is limited, thus limiting the amount of non-compulsive data; the second part is the protocol parsing layer, where a received data packet is considered valid only if the frame header, data packet length, ID number, operation type, and finally the CRC8 checksum are all valid.

[0059] The FPGA-controlled online upgrade of the FT-M6678 consists of two main parts: the host computer and the target device. The general process is as follows: Figure 2 , Figure 3 As shown.

[0060] Please see Figure 2 The process for the host computer to perform the upgrade operation is as follows:

[0061] Step 1: Select the device type, which is either FPGA or FT-M6678. Different device types correspond to different ID numbers in the upgrade protocol format. Proceed to Step 2.

[0062] Step 2: Select the baud rate. The upgrade baud rates for FPGA and FT-M6678 are above 1M and below 115200 respectively. The specific values ​​must be consistent with the chip side. Proceed to Step 3.

[0063] Step 3: Determine whether to switch to backup startup. This operation is not required for FPGA, proceed directly to step 5; this operation is required for FT-M6678, proceed to step 4.

[0064] Step 4: Switch to backup boot. This operation is only for FT-M6678. Proceed to Step 5.

[0065] Step 5: The target device is located. The host computer issues a device search command and proceeds to step 6.

[0066] Step six: The target device receives a device presence response, the host computer receives a search response for the target device, and proceeds to step seven;

[0067] Step 7: Send file description information. The host computer sends the characteristic information of the upgrade file (including file size in bytes, number of packets sent in sub-packets, and file CRC8 checksum) to the target device, and then proceeds to step 8.

[0068] Step 8: Upon receiving the request to load the response, it indicates that the target device has completed the erase operation on the application storage area based on the received file description information, and proceeds to step 9.

[0069] Step 9: Upgrade file transfer, send the upgrade file in packets, then proceed to Step 10;

[0070] Step 10: Upon receiving the upgrade status reply, it indicates that the target device has been successfully received. Proceed to Step 11.

[0071] Step 11: Status response judgment and packet transmission completion judgment. If the received status response is abnormal or the current packet is not the last packet sent, the process will return to step 9. The difference is that the former retransmits the current packet, while the latter sends the next packet. If the received status response is normal and the current packet is the last packet sent, the upgrade process ends.

[0072] Please see Figure 3 The FPGA-controlled FT-M6678 backup startup process can be divided into two parts: the FPGA control process and the FT-M6678 backup startup process. The overall process steps here are numbered independently of those described above. Figure 2 The step numbers in the text are not related; specifically:

[0073] Step 1: The second serial port inside the FPGA continuously detects instructions from the host computer and proceeds to Step 2.

[0074] Step 2: Determine if a switch-backup boot command has been received. If not, maintain the existing gpio and porz states (both signals are high in the original state) and proceed to Step 1. If the command is received, proceed to Step 3.

[0075] Step 3: Pull the GPIO level low to instruct the FT-M6678 to boot from the backup program during the boot phase, and proceed to step 4;

[0076] Step 4: Continuously pull the porz signal level low and then continuously pull it high to control the FT-M6678 to reset and restart, then proceed to step 5;

[0077] Step 5: Power on and restart the FT-M6678 or reset and restart it, then proceed to Step 6;

[0078] Step six: The FT-M6678 stores three programs in its flash memory: a bootloader, a backup program, and an application program. Only the backup program contains upgrade functionality; the application program does not contain any upgrade-related operations and consists entirely of user logic functions. In this step, the FT-M6678 begins executing the bootloader to complete some system initialization work, and then proceeds to step seven.

[0079] Step 7: The bootloader program reads the GPIO level value and proceeds to step 8;

[0080] Step 8: Determine the GPIO level value. When it is high, the program jumps to the application execution.

[0081] When the signal is low, the program jumps to the backup program for execution; at this point, the startup process ends.

[0082] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method of multiplexing upgrade links and controlling backup initiation, characterized by, The target board is equipped with two chips of FPGA and FT-M6678, and both the FPGA and the FT-M6678 are implemented with online upgrading and backup starting functions based on the host computer; The FPGA communicates with the host computer through a 1-way rs422 interface, and on the basis of realizing the online upgrading function, the FPGA is connected with the serial port controller of the FT-M6678 through a 1-way serial port uart drawn from the FPGA pin, so as to realize the serial port upgrading file transmission of the FT-M6678 by means of the transparent transmission operation of the serial port receiving signal and the operation of the sending signal; The FPGA internally contains two-way serial port drivers, and the serial port receiving and transmitting driver has complete receiving and transmitting functions, and is used in combination with the upgrading control logic module to realize the upgrading file transmission of the FPGA itself and the solidification of the flash; The serial port receiving driver only has a separate receiving function, and is used in combination with the backup starting switching module to realize the switching control of the gpio and porz signals of the FT-M6678; wherein the gpio signal is used to indicate the starting address of the FT-M6678, and the porz signal is used to control the soft starting of the FT-M6678; The flash of the FT-M6678 stores three programs, namely, bootloader, backup program and application program, and only the backup program contains the upgrading function, and the application program does not contain any upgrading related operation, and is a user function; When the FT-M6678 is upgraded, the host computer first issues a backup starting switching instruction, the FPGA receives and analyzes the instruction, and then switches the gpio level and porz reset logic connected with the FT-M6678, after which the FT-M6678 completes the soft restart, and reads the current gpio level value in the bootloader stage to determine whether to jump to the backup program to execute the online upgrading function or to jump to the application program to execute normally. The host computer integrates the upgrading operations of the FPGA and the FT-M6678 to make them have the same upgrading process, which specifically includes device type selection, baud rate selection, backup starting switching, device searching, file description information issuing and starting upgrading.

2. The method of claim 1, wherein, The rs422 communication between the host computer and the target board and the uart communication between the FPGA and the FT-M6678 in the target board are based on a unified upgrading protocol format, which is as follows: The frame header is 0xaa, 0x99, 0x55 and 0x66, which are four bytes; The data packet length is 1 byte; The id number is 1 byte; The operation type is 1 byte; The data segment is a plurality of bytes, and when the operation type is data packet transmission, the data segment is fixedly 64 bytes, and the last packet is filled with 0 if it is less than 64 bytes; The crc8 check is 1 byte, and the calculation range of the crc8 check includes all bytes from the frame header to the data segment.

3. The method of claim 1, wherein the method further comprises: The host computer is different and has a large difference in serial communication baud rate when upgrading the FPGA and the FT-M6678 respectively; the host computer splits the original upgrade file into multiple packets and then transmits the packets, each data packet has a check feedback mechanism when transmitted through the serial port, when the target chip fails the crc8 check, the host computer triggers the retransmission; when the host computer detects that the target chip does not reply within a timeout, the timeout retransmission is triggered.

4. The method of claim 1, wherein the method further comprises: The 2 serial port drivers of the FPGA and the 1 serial port controller of the FT-M6678 simultaneously analyze the serial port data issued by the host computer, and high-speed baud rate driving analysis of low-speed real-time signals or low-speed baud rate driving analysis of high-speed real-time signals will not appear error analysis; The specific mechanism includes 2 parts, the first part is the driving analysis layer, the baud rate difference is more than 10 times and the single packet data byte length is limited, so that the number of chaotic data is limited; the second part is the protocol analysis layer, and the received data packet is valid only when the frame header is valid, the data packet length is valid, the id number is valid, the operation type is valid, and the final crc8 check is valid.

5. The method of multiplexing upgrade links and controlling backup initiation of claim 1, wherein, The method comprises that the host computer performs the upgrade operation, and the flow is as follows: Step one, select the device type, which is divided into FPGA and FT-M6678, different device types correspond to different id numbers in the upgrade protocol format, and turn to step two; Step two, select the baud rate, the upgrade baud rate of the FPGA and the FT-M6678 is different, the specific value is consistent with the chip end, and turn to step three; Step three, judge whether to switch the backup start, for the FPGA, this operation is not needed, and directly turn to step five; for the FT-M6678, this operation is needed, and turn to step four; Step four, switch the backup start, this operation is only for the FT-M6678, and turn to step five; Step five, the target device performs device searching, the host computer issues a searching device command, and turn to step six; Step six, the target device receives a device existing reply, the host computer receives the searching reply of the target device, and turn to step seven; Step seven, issue the file description information, the host computer sends the feature information of the upgrade file to the target device, and turn to step eight; Step eight, receive the request loading reply, which indicates that the target device has completed the erasing operation on the application storage area based on the file description information, and turn to step nine; Step nine, upgrade file transmission, send the upgrade file in packets, and turn to step ten; Step ten, receive the upgrade status reply, which indicates that the target device receives the upgrade file, and turn to step eleven; Step eleven, state reply judgment and packet sending completion judgment, if the received state reply is abnormal or the current packet sending is not the last packet, turn to step nine again; the former is to resend the current packet, and the latter is to send the next packet; if the received state reply is normal and the current packet sending is the last packet, end the upgrade flow.

6. The method of multiplexing upgrade links and controlling backup initiation of claim 1, wherein, The method comprises the FPGA control flow and the FT-M6678 backup start flow, which are as follows: Step one, the 2nd serial port of the FPGA continuously detects the host computer instruction, and turn to step two; Step two, judge whether to receive the switch backup start instruction, if not received, keep the original gpio, porz state unchanged, turn into step one; If the instruction is received, turn into step three; Step three, pull down the gpio level, used to indicate FT-M6678 to start from the backup program in the boot stage, turn into step four; Step four, pull down the porz signal level continuously and then pull up continuously, control FT-M6678 reset and restart, turn into step five; Step five, FT-M6678 power on restart or reset restart, turn into step six; Step six, FT-M6678 stores three programs in the flash, which are bootloader, backup program and application program respectively, only the backup program contains upgrade function, the application program does not contain any upgrade related operation, which are all user logic functions; This step FT-M6678 starts to execute bootloader, completes part of system initialization work, turn into step seven; Step seven, bootloader program reads gpio level value, turn into step eight; Step eight, judge gpio level value, when it is high level, the program jumps to the application program execution; When it is low level, the program jumps to the backup program execution; Thus, the starting process is completed.

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