DDR memory frequency switching test method and apparatus

Abstract

The application relates to the field of memory management, and provides a DDR memory frequency switching test method and device. The method comprises the following steps: acquiring a plurality of preset frequency gears of DDR memory; constructing a multi-stage test flow of at least two different switching modes; for each test stage, generating target data before performing a frequency switching action, acquiring actual data from the DDR memory in the process of performing the frequency switching action, comparing the target data with the actual data, and detecting whether the frequency switching process causes data jump; based on the comparison result of each test stage, performing reliability determination on the corresponding switching mode of the DDR memory, establishing a fault association relationship between the plurality of test stages, determining a potential frequency switching fault currently existing in the DDR memory when data jump is detected in any test stage; and performing collaborative verification on the actual data in different switching modes in the multi-stage test flow to form a frequency switching test report. The frequency switching test reliability and test efficiency can be improved.

Description

Technical Field

[0001] This application relates to the field of memory management, and more specifically, to a method and apparatus for testing DDR memory frequency switching. Background Technology

[0002] Double Data Rate (DDR) is a critical system-level resource in smart terminals, and its operating frequency directly affects the device's data throughput, application response speed, and overall power consumption. In Android systems, to achieve a balance between performance and power consumption, a dynamic frequency switching mechanism for DDR memory is introduced. This mechanism monitors system load and reduces the DDR operating frequency and voltage under low load conditions to save energy, while increasing the operating frequency in a timely manner to meet performance demands under high load conditions. However, when switching between high and low frequencies, DDR may experience data read / write anomalies, system lag, or even crashes. To prevent problematic chips from entering mass production, specific tests on the frequency switching stability of DDR are typically conducted before shipment.

[0003] In existing technologies, memory verification typically relies on chip-in-chip stability testing tools or basic stress testing methods. However, these methods mostly operate at fixed frequencies or involve unidirectional switching, failing to cover complex switching modes such as multi-frequency random switching and sequential frequency ramping / increase. Furthermore, existing tests primarily focus on high-load stress testing or single-frequency verification, failing to simulate actual frequency jumps and rapid ramping / increases in Android systems, resulting in the failure to detect potential switching anomalies in advance. Some tests only focus on the read / write normality of DDR at the target frequency, ignoring data jumps and bit flips that may be introduced by the switching action itself, thus failing to assess the impact of frequency switching on data integrity. Android's screen-switching function relies heavily on DDR access; if data jumps occur during DDR switching, it can lead to interface abnormalities and system crashes, issues that existing tests cannot effectively reproduce and identify. Moreover, existing tests lack a multi-stage, multi-mode systematic verification process, failing to establish a hierarchical verification mechanism from random switching, sequential downclocking, sequential upclocking to mixed random switching, resulting in an incomplete assessment of DDR chip reliability. Therefore, a memory management scheme is urgently needed to address at least one of these technical problems. Summary of the Invention

[0004] In this context, the embodiments of this application aim to provide a DDR memory frequency switching test method and apparatus to achieve automated switching test of DDR memory frequency, and solve the technical problems of insufficient frequency switching test coverage, inability to detect switching process errors, and inability to identify potential related faults between different switching modes in the prior art.

[0005] In a first aspect of the embodiments of this application, a method for testing DDR memory frequency switching is provided. The method includes: acquiring multiple preset frequency levels of DDR memory; constructing a multi-stage test process including at least two different switching modes, wherein in each test stage, when performing a DDR memory data write operation or read operation, the frequency of the DDR memory is synchronously switched according to the corresponding switching mode; for each test stage, target data is generated before the frequency switching action is performed, and actual data is acquired from the DDR memory during the frequency switching action, and the consistency of the target data and the actual data is compared to detect whether the frequency switching process causes a data jump; based on the comparison results of each test stage, the reliability of the corresponding switching mode of the DDR memory is determined, and a fault correlation relationship is established between multiple test stages; when a data jump is detected in any test stage, a potential frequency switching fault currently existing in the DDR memory is determined based on the reliability determination result and the fault correlation relationship; and the actual data collected under different switching modes in the multi-stage test process are collaboratively verified to form a frequency switching test report containing potential frequency switching faults and collaborative verification results.

[0006] In a second aspect of the embodiments of this application, a DDR memory frequency switching testing device is provided. The device includes the following modules: an acquisition module for acquiring multiple preset frequency levels of DDR memory; a construction module for constructing a multi-stage test process including at least two different switching modes, wherein in each test stage, when performing a DDR memory data write operation or read operation, the DDR memory frequency is synchronously switched according to the corresponding switching mode; a detection module for generating target data before performing the frequency switching action in each test stage, acquiring actual data from the DDR memory during the frequency switching action, comparing the target data with the actual data for consistency, and detecting whether the frequency switching process causes data jumps; a fault location module for performing reliability determination on the corresponding switching mode of the DDR memory based on the comparison results of each test stage, establishing fault correlation relationships between multiple test stages, and determining the potential frequency switching fault currently existing in the DDR memory based on the reliability determination results and the fault correlation relationships when any test stage detects a data jump; and a verification output module for performing collaborative verification on the actual data collected under different switching modes in the multi-stage test process, forming a frequency switching test report including potential frequency switching faults and collaborative verification results.

[0007] This application discloses a method and apparatus for testing DDR memory frequency switching. The method first acquires multiple preset frequency levels of the DDR memory. Then, a multi-stage test process is constructed, including at least two different switching modes. In each test stage, during DDR memory data write or read operations, the DDR memory frequency is synchronously switched according to the corresponding switching mode. For each test stage, target data is generated before the frequency switching action, and actual data is acquired from the DDR memory during the frequency switching action. The target data and the actual data are compared for consistency to detect whether the frequency switching process causes data jumps. Furthermore, based on the comparison results of each test stage, the reliability of the corresponding switching mode of the DDR memory is determined, and a fault correlation is established between multiple test stages. When a data jump is detected in any test stage, a potential frequency switching fault in the DDR memory is determined based on the reliability determination result and the fault correlation. Finally, the actual data collected under different switching modes in the multi-stage test process are collaboratively verified to form a frequency switching test report containing potential frequency switching faults and collaborative verification results. This application's implementation combines a multi-stage, multi-mode testing architecture, a dynamic data monitoring mechanism, cross-stage fault correlation analysis, and collaborative verification reports to achieve full-scenario coverage, real-time error capture, and potential fault root cause localization during DDR memory frequency switching, significantly improving the reliability and efficiency of frequency switching testing. While ensuring the stable operation of basic memory functions, this application's implementation can effectively identify data jump risks during the switching process and extract implicit correlation faults between different switching modes, contributing to hardware stability verification and fault prevention. Attached Figure Description

[0008] Figure 1 This is a flowchart illustrating a DDR memory frequency switching test method as shown in this application.

[0009] Figure 2 This is a schematic diagram of a DDR memory frequency switching test device shown in this application. Detailed Implementation

[0010] To address at least one of the aforementioned technical problems, this application provides a DDR memory frequency switching test method and apparatus, which solves the problems existing in current DDR memory testing, such as insufficient coverage of complex scenarios, lack of data integrity assessment, inability to effectively reproduce faults, and unsystematic verification process.

[0011] To address the technical problem that existing tests mainly rely on fixed frequencies or unidirectional switching and cannot cover complex modes such as random switching at multiple frequency points, the technical solution of this application first obtains multiple preset frequency levels of DDR memory to provide basic support for complex frequency switching. Then, it constructs a multi-stage test process that includes at least two different switching modes, incorporating modes such as random switching, sequential downclocking, sequential upclocking, and mixed random switching into a graded verification mechanism. This completely changes the limitation of the single-mode testing in existing tests and achieves a comprehensive simulation of actual frequency switching scenarios in the Android system.

[0012] To address the issue that existing tests fail to simulate real-world scenarios such as random frequency jumps and rapid frequency increases / decreases, thus failing to expose potential anomalies, this application proposes a testing mechanism that synchronizes read / write operations with frequency switching. During each test phase, when performing DDR memory data write or read operations, a frequency switch is simultaneously performed according to the corresponding switching mode. This accurately reproduces the actual working conditions of high-frequency DDR access and frequency jumps coexisting in Android system operations such as screen switching, effectively triggering and identifying potential faults such as interface anomalies and system freezes. For existing tests that only focus on the normality of read / write operations at the target frequency point and ignore data issues introduced by the switching action, this application establishes a consistency comparison system between target data and actual data. Benchmark target data is generated before frequency switching, and actual data is acquired and compared in real time during the switching process. This directly detects data jumps and bit flips caused by frequency switching, achieving data integrity assessment of the frequency switching process and further improving the accuracy and efficiency of frequency switching testing.

[0013] To address the lack of a systematic verification process and incomplete reliability assessment in existing testing methods, this application's technical solution establishes a complete verification chain through a progressive design of multi-stage testing. This not only performs individual reliability assessments for each switching mode but also establishes fault correlations between multiple testing stages. When a data jump is detected at any stage, the results of the entire process and correlation analysis can be combined to pinpoint the potential root cause of the fault, avoiding misjudgments or omissions caused by isolated testing. Simultaneously, by collaboratively verifying actual data under different switching modes and generating a comprehensive report containing fault information and verification results, it provides a comprehensive and accurate basis for DDR chip reliability assessment, helping to solve the fragmented problem of existing testing and assessment and ensuring the stable operation of DDR memory under various frequency switching scenarios.

[0014] Figure 1 The flowchart of a DDR memory frequency switching test method provided in one embodiment of this application, shown below, includes:

[0015] Step S101: Obtain multiple preset frequency levels for DDR memory;

[0016] Step S102: Construct a multi-stage test process including at least two different switching modes, wherein in each test stage, when performing DDR memory data write or read operations, the frequency of DDR memory is switched synchronously according to the corresponding switching mode.

[0017] Step S103: For each test phase, target data is generated before the frequency switching action is performed, and actual data is obtained from DDR memory during the frequency switching action. The target data and the actual data are compared for consistency to detect whether the frequency switching process causes data jump.

[0018] Step S104: Based on the comparison results of each test stage, the reliability of the corresponding switching mode of the DDR memory is determined, and a fault correlation relationship is established between multiple test stages. When a data jump is detected in any test stage, the potential frequency switching fault of the DDR memory is determined based on the reliability determination results and the fault correlation relationship.

[0019] Step S105: Collaboratively verify the actual data collected under different switching modes in the multi-stage test process to form a frequency switching test report that includes potential frequency switching faults and collaborative verification results.

[0020] In this embodiment, DDR memory can be a high-performance dynamic random access memory (DRAM) used in the Android system. Its core feature is that it can adjust its operating frequency and voltage in real time according to the device's operating load (such as standby, video playback, large-scale games, etc.) to achieve a dynamic balance between performance and power consumption. During the system startup phase, the available frequency levels of the DDR memory are pre-configured using a dedicated tool and stored in the configuration file during the Loader phase. Developers can also monitor its working status in real time through debug nodes.

[0021] The testing method in this application embodiment constructs a multi-stage process comprising four progressive testing phases to comprehensively cover typical frequency switching scenarios of DDR memory. For example, the first stage is a random switching mode, simulating high-frequency, irregular frequency jumps such as screen switching in Android systems. The second stage is a sequential frequency reduction mode, switching from high to low levels according to preset thresholds. The third stage is a sequential frequency increase mode, increasing the frequency in reverse step by step. The fourth stage is a hybrid random switching mode, combining the characteristics of the preceding modes to verify stability under complex switching conditions. Optionally, an interference switching mode can also be added to the above process. Data read / write and frequency switching operations are performed synchronously in each stage. Through a dynamic monitoring mechanism that generates target data before switching, captures actual data during switching, and performs consistency comparison, anomalies such as data jumps and bit flips that may occur during the switching process are identified.

[0022] Understandably, the corresponding switching modes for DDR memory are test modes designed to comprehensively cover different frequency change scenarios in real-world applications, and they include four typical types. The random switching mode jumps randomly between multiple preset frequency levels, primarily simulating high-frequency, irregular frequency jumps such as screen switching in Android systems. For example, when the preset frequency levels are 6400MHz, 5500MHz, 3200MHz, and 2400MHz, the switching process might jump directly from 3200MHz to 6400MHz, and then randomly switch to 800MHz, without a fixed order or interval. The sequential downclocking mode switches gradually from high to low preset frequency levels, for example, from 6400MHz to 5500MHz, 3200MHz, 2400MHz, until the lowest level of 600MHz, simulating frequency adjustment scenarios as system load gradually decreases. The sequential upclocking mode is the opposite of the sequential downclocking mode. It increases the frequency step by step from low to high according to preset frequency levels, for example, from 600MHz to 800MHz, 1200MHz, 2400MHz, and finally to the highest level of 6400MHz, corresponding to the frequency changes as the system load gradually increases. The hybrid random switching mode combines the features of the first three modes. During the test, it flexibly combines random jumps, sequential downclocking, and sequential upclocking actions. For example, it first randomly switches between multiple levels, then performs a period of sequential downclocking, and then enters a random switching state again, thereby verifying the stability of DDR memory under complex and ever-changing frequency switching conditions.

[0023] The reliability assessment result is a clear conclusion drawn from the consistency comparison between the target data and the actual data in each test phase, determining the reliability of DDR memory operating in the corresponding switching mode. Its core function is to determine whether DDR memory will cause data anomalies due to frequency switching in that switching mode. If the two are completely consistent after comparison, it indicates that the DDR memory operates reliably in that switching mode and can normally cope with frequency changes without causing data problems. If there are differences after comparison, it indicates that the reliability of DDR memory in that switching mode is substandard, and frequency switching will cause anomalies such as data jumps and bit flips. For example, in the sequential frequency increase mode test, the target data is a set of continuous binary data. If the actual data obtained during the switching process is completely consistent with the target data, then the reliability of DDR memory in that mode is deemed acceptable; if some bytes in the actual data change, then the reliability in that mode is deemed unacceptable. Fault correlation refers to the fault correlation analysis mechanism established between multiple test phases, used to uncover the inherent connections between faults in different switching modes. Its core function is to help locate the root cause of potential faults, rather than viewing faults in a single phase in isolation. For example, in both sequential frequency reduction mode and hybrid random switching mode, data jumps occur when switching between 5500MHz and 3200MHz. Through fault correlation analysis, it can be determined that the fault may be related to the switching logic or voltage matching problem between these two frequency ranges, rather than an accidental anomaly in a single mode.

[0024] The frequency switching test report, which includes potential frequency switching failures and collaborative verification results, is a comprehensive document formed by integrating and processing all data and analysis results from the multi-stage testing process. Its core function is to provide a comprehensive assessment of the reliability of DDR memory frequency switching, supporting subsequent product selection, troubleshooting, and optimization. The potential frequency switching failure section details anomalies detected in each testing phase, including the switching mode in which the failure occurred, the specific frequency switching range, and the type and manifestation of the data anomaly. For example, it records that in random switching mode, three data bit flips occurred when jumping from 6400MHz to 2400MHz, resulting in data integrity corruption and potentially causing interface anomalies during Android system screen switching. The collaborative verification results section presents conclusions after cross-analysis and comprehensive verification of actual data collected under different switching modes, including the overall reliability rating of each switching mode, a summary of the correlation between failures under different modes, and an assessment of the adaptability of DDR memory in various practical application scenarios. For example, collaborative verification revealed that all modes involving rapid switching between mid-to-high frequency levels had varying degrees of failure, while low-frequency switching was entirely reliable. This led to the conclusion that the DDR memory lacked stability in mid-to-high frequency rapid switching scenarios. It also clarified that it could be used normally in low-frequency application scenarios such as standby and light video playback, but there were risks in mid-to-high frequency scenarios such as large-scale games and multi-tasking switching. This provides a direct reference for the application scenario classification and quality control of DDR memory.

[0025] In step S101, multiple preset frequency levels of the DDR memory are obtained.

[0026] As an optional embodiment, in step S101, obtaining multiple preset frequency levels of DDR memory includes: reading a preset frequency level configuration file based on the hardware characteristics of DDR memory to obtain multiple frequency levels; classifying the multiple frequency levels according to frequency ranges during the reading process, into high frequency level, mid frequency level, and low frequency level; and establishing a set of candidate frequencies based on the classification results of the multiple frequency levels.

[0027] The frequency level is a pre-set, stable operating frequency for DDR memory. It's the core basis for dynamically adjusting performance and power consumption based on system load. Each level corresponds to a set of matching operating voltage parameters to ensure stable data read and write at that frequency. Furthermore, it provides clear switching points for memory frequency switching, allowing the system to accurately switch to the corresponding frequency level based on different load scenarios such as standby, video playback, and demanding games, achieving a balance between performance and power consumption. For example, DDR memory presets such as 6400MHz, 5500MHz, 3200MHz, 2400MHz, 1200MHz, 800MHz, and 600MHz each represent an independent frequency level. When the system is running demanding games, it will switch to a higher level like 6400MHz or 5500MHz to ensure performance, while in standby mode, it will switch to a lower level like 800MHz or 600MHz to reduce power consumption.

[0028] For example, firstly, a preset frequency profile is read based on the hardware characteristics of the DDR memory to obtain multiple frequency profiles. During the reading process, the multiple frequency profiles are classified according to frequency ranges: 6400MHz and 5500MHz are classified as high-frequency profiles, 3200MHz and 2400MHz as mid-frequency profiles, and 1200MHz, 800MHz, and 600MHz as low-frequency profiles. Then, based on the classification results of the multiple frequency profiles, a set of candidate frequencies including high-frequency, mid-frequency, and low-frequency profiles is established.

[0029] Besides categorizing frequencies into high-frequency, mid-frequency, and low-frequency ranges, frequency levels can also be divided based on switching priority and voltage matching. When categorizing by switching priority, the core principle is to classify different frequency ranges according to their usage frequency and importance in actual Android system applications, dividing them into high-priority, mid-priority, and low-priority ranges. High-priority ranges are those switched most frequently during daily system operation, such as 2400MHz and 3200MHz, which are suitable for common scenarios like multitasking and short video playback. Mid-priority ranges are those used occasionally, such as 5500MHz, suitable for medium-sized games and high-definition video playback. Low-priority ranges are those rarely triggered, such as 6400MHz, used only in extreme performance tests or special professional applications. This categorization method optimizes test resource allocation, prioritizing testing of switching modes related to high-priority ranges, thus improving testing efficiency and focus. When classifying by voltage matching relationship, it is based on the difference in operating voltage corresponding to different frequency ranges, categorizing them into near voltage range group, medium voltage range group, and far voltage range group. Within the near voltage range group, the voltage difference between ranges is small; for example, 1200MHz (1.0V), 800MHz (0.9V), and 600MHz (0.8V) all have a difference of around 0.1V. Within the medium voltage range group, the voltage difference between ranges is moderate; for example, 2400MHz (1.2V) and 3200MHz (1.3V). Within the far voltage range group, the voltage difference between ranges is large; for example, 5500MHz (1.5V) and 600MHz (0.8V). This classification method is designed to specifically test the impact of voltage changes on frequency switching stability, especially the switching of the far voltage range group, which is more prone to data jumps and other faults, requiring focused verification.

[0030] In addition to the frequency ranges corresponding to 6400MHz and 5500MHz mentioned in the examples above, more detailed frequency ranges can be defined based on the product positioning and application scenarios of DDR memory, or to accommodate different performance levels. For example, for DDR memory in entry-level Android devices, the range can be divided into ultra-low frequency ranges of 400MHz to 800MHz, low frequency ranges of 1000MHz to 2400MHz, and mid-frequency ranges of 2800MHz to 4800MHz. For DDR memory in high-end flagship devices, the range can be divided into mid-frequency ranges of 3600MHz to 5200MHz, high frequency ranges of 5600MHz to 6400MHz, and ultra-high frequency ranges of 6800MHz to 8000MHz. It's important to understand that this classification method is designed to accommodate DDR memory products of different performance levels, ensuring that testing covers the actual operating frequency range of the corresponding devices. Another example is dividing the frequency range evenly. If the preset frequency range of DDR memory is 600MHz to 6400MHz, it can be evenly divided into six ranges, each spanning about 1000MHz, namely 600MHz to 1600MHz, 1600MHz to 2600MHz, 2600MHz to 3600MHz, 3600MHz to 4600MHz, 4600MHz to 5600MHz, and 5600MHz to 6400MHz. The function of this division method is to ensure the comprehensiveness of the test and avoid some frequency ranges not being fully verified due to uneven division of the ranges.

[0031] In step S102, a multi-stage test process including at least two different switching modes is constructed. Furthermore, in each test stage, when performing DDR memory data write or read operations, the frequency of the DDR memory is synchronously switched according to the corresponding switching mode.

[0032] Specifically, a multi-stage test process with at least two different switching modes is constructed. The core objective is to comprehensively cover typical frequency switching scenarios of DDR memory in the Android system. By synchronizing read and write operations with frequency switching in each test stage, actual usage conditions are simulated to ensure the relevance and effectiveness of the test. This test process includes four progressive test stages, each with its own emphasis on switching modes, operational logic, and functions.

[0033] The first phase is a random switching mode. The test process is designed so that the CPU continuously writes data to the DDR memory until the memory is completely full. Then, during data read operations, the operating frequency of the DDR memory is randomly switched synchronously according to several preset frequency levels. For example, the preset frequency levels are 6400MHz, 5500MHz, 3200MHz, 2400MHz, 1200MHz, 800MHz, and 600MHz. When reading data, it may switch directly from 3200MHz to 6400MHz, and then randomly jump to 800MHz. The switching action is synchronized with the read operation in real time, without a fixed order. The function of this phase is to simulate the real-world scenario of high-frequency, irregular frequency jumps, such as screen switching in the Android system, and to focus on testing whether the data read process is stable during random frequency switching and whether any abnormalities such as data jumps occur.

[0034] The second stage is a sequential frequency reduction mode. During the test, the CPU continuously writes data to the DDR memory. While writing data, the DDR memory frequency is gradually and synchronously switched in descending order of preset frequency levels. For example, starting from the highest level of 6400MHz, it sequentially switches to 5500MHz, 3200MHz, 2400MHz, 1200MHz, 800MHz, and finally to 600MHz. The write operation is uninterrupted, and the frequency switching and data writing are synchronized in real time. The function of this stage is to simulate the frequency adjustment scenario when the Android system load gradually decreases, verifying the impact of the gradual frequency reduction during data writing on data integrity, and detecting whether the frequency reduction action will cause abnormal data writing.

[0035] The third stage is the sequential frequency increase mode, which is the reverse of the sequential frequency decrease mode. The CPU continuously writes data to the DDR memory, gradually and synchronously switching frequencies in a preset frequency range from low to high during the writing process. For example, starting from the lowest level of 600MHz, it sequentially increases to 800MHz, 1200MHz, 2400MHz, 3200MHz, 5500MHz, and finally to 6400MHz. The writing rhythm is consistent with the frequency increase action, ensuring that each segment of written data corresponds to a specific frequency state. The function of this stage is to simulate the frequency increase scenario when the Android system load gradually increases, focusing on verifying the stability of the frequency increase during the data writing process and troubleshooting data failures that may be caused by the frequency increase action.

[0036] The fourth stage is a hybrid random switching mode. The test process combines the switching characteristics of the first three stages. The CPU performs data write operations to the DDR memory, and during the write process, a hybrid frequency switching is performed simultaneously. The switching actions are not fixed and may include combinations such as random jumps, a series of sequential frequency reductions, another random jump, and a series of sequential frequency increases. For example, when writing data, it first randomly jumps from 3200MHz to 5500MHz, then sequentially reduces the frequency to 2400MHz, then randomly jumps to 6400MHz, and then sequentially increases the frequency to 5500MHz. The write operation and these complex switching actions proceed synchronously in real time. This stage simulates complex and variable real-world scenarios such as multi-task switching and frequent load fluctuations in the Android system, comprehensively verifying the operational stability of DDR memory under various switching mode combinations, ensuring comprehensive coverage of potential failure scenarios.

[0037] As an optional embodiment, step S102 involves constructing a multi-stage test process including at least two different switching modes, including: combining candidate frequencies in the candidate frequency set in pairs to form candidate frequency sets for different switching modes; generating frequency switching sequences matching random switching mode, ascending switching mode, descending switching mode, and interference switching mode based on the candidate frequency sets; and assigning a corresponding switching mode and a frequency switching sequence matching the switching mode to each test stage when constructing each test stage, and generating stage configuration information describing the execution logic of each test stage. The stage configuration information includes a target frequency set, access method, frequency switching trigger strategy, and execution order of the multi-stage test process, so that frequency switching under different switching modes covers different frequency ranges of DDR memory.

[0038] In the above embodiments, firstly, based on the candidate frequency set established in step S101, all candidate frequencies are combined in pairs to form a candidate frequency set. For example, the candidate frequency set includes 6400MHz, 5500MHz, 3200MHz, 2400MHz, 1200MHz, 800MHz, and 600MHz. After pairing, all possible dual-frequency combinations such as 6400MHz and 5500MHz, 6400MHz and 3200MHz, 5500MHz and 2400MHz, and 1200MHz and 600MHz are obtained. The function of this candidate frequency set is to provide a comprehensive frequency switching basis for various subsequent switching modes, ensuring that no switching possibility between any two frequencies is missed, thereby improving the comprehensiveness of the test from the root.

[0039] Next, matching frequency switching sequences are generated for each of the four switching modes based on the candidate frequency set. For the random switching mode, different frequency combinations are randomly selected from the candidate frequency set and arranged in a random order to form a sequence, such as 6400MHz-3200MHz-5500MHz-2400MHz-800MHz-

[0040] The 6400MHz-600MHz sequence has no preset logic for switching between adjacent frequencies, simulating irregular frequency jumps such as screen switching in the Android system. The ascending-order switching mode selects candidate frequency combinations in ascending order of frequency, for example, 600MHz-800MHz-1200MHz-2400MHz-3200MHz-

[0041] The 5500MHz-6400MHz range, where each adjacent combination has a higher frequency than the previous one, simulates the frequency increase process as the system load gradually increases. The descending sequence switching mode is the reverse of the ascending sequence, selecting candidate frequency combinations in descending order of frequency, for example, 6400MHz-5500MHz-3200MHz-

[0042] The 2400MHz-1200MHz-800MHz-600MHz sequence simulates the frequency drop process when the system load decreases. The interference switching mode sequence inserts discontinuous interference frequency combinations into the normal switching combinations, such as 3200MHz-5500MHz-1200MHz-6400MHz-800MHz-2400MHz-600MHz. The sequence suddenly inserts frequency switching combinations with large spans, which simulates the frequency change scenario caused by drastic load fluctuations during multitasking switching in the Android system, increasing the rigor of the test.

[0043] Finally, a corresponding switching mode and matching frequency switching sequence are assigned to each test phase, and detailed phase configuration information is generated. The target frequency set in the phase configuration information is a subset of candidate frequency combinations used in that phase. For example, the target frequency set for the ascending switching mode is a combination of low to high frequencies such as 600MHz, 800MHz, and 1200MHz. The access method is set to data writing or reading according to the test scenario. Referring to the actual application scenarios of the Android system, most phases use continuous CPU data writing, while some phases use data reading to ensure coverage of both core operations. The frequency switching trigger strategy clearly defines the triggering conditions for switching, such as triggering a frequency switch every 500 sets of data written, or triggering a switch at fixed intervals. The execution order clearly defines the logical sequence of multi-stage tests. For example, the tests are executed in the order of random switching mode, ascending switching mode, descending switching mode, and interference switching mode. This ensures that the frequency switching under different switching modes can cover the high-frequency, mid-frequency, and low-frequency ranges of DDR memory. For instance, random mode covers all range combinations, ascending mode focuses on the transition from low-mid-frequency to high-frequency, descending mode focuses on the transition from high-frequency to low-mid-frequency, and interference mode covers cross-range abrupt changes. Ultimately, this achieves multi-scenario coverage of all key frequency switching scenarios for DDR memory, ensuring the accuracy of subsequent tests.

[0044] Further optionally, in the above embodiments, when constructing each test phase, a corresponding switching mode and a frequency switching sequence matching the switching mode are assigned to each test phase, including: constructing a scenario model based on the operating load characteristics of the Android system; selecting a target frequency set matching the scenario model from the candidate frequency set according to the access density, access cycle and expected frequency jump behavior corresponding to the scenario model; selecting a switching mode adapted to the corresponding scenario model for each test phase, and selecting a frequency switching sequence matching the switching mode from the frequency switching sequence.

[0045] In this embodiment, the runtime load characteristics of the Android system are the core attributes related to hardware resource consumption and memory access exhibited by the Android system under different usage scenarios. These encompass key indicators such as CPU utilization, memory access demand, and frequency adjustment frequency, and their function is to provide realistic data for scenario model construction. For example, when a device is in standby mode, CPU utilization is below 5% and memory access is minimal; when a large game is running, CPU utilization is above 80%, memory access is frequent, and frequency adjustments are frequent. These different behaviors all fall under runtime load characteristics. The scenario model is a test simulation model with clearly defined parameterized characteristics, abstracted and refined based on the runtime load characteristics of the Android system in actual usage scenarios. It can be used to recreate the DDR memory working environment under different usage scenarios, making the test more closely resemble actual application conditions. The scenario model includes, but is not limited to, at least one of standby scenarios, video playback scenarios, and high-load application scenarios. For example, the standby scenario model will extract the core characteristics of low access volume and stable frequency, while the high-load application scenario model will highlight the characteristics of frequent access and frequent frequency jumps. Access density is the number of times DDR memory is accessed by the CPU per unit time, used to quantify the level of memory access busyness, and its function is to provide a basis for frequency level selection. For example, in standby scenarios, the number of memory accesses per unit time is only a few dozen, resulting in low access density. In high-load application scenarios, the number of accesses per unit time can reach tens of thousands, resulting in high access density.

[0046] The core of constructing the scenario model in the above embodiments is to collect operational data of the Android system in actual use, extract key load characteristics under different scenarios, and then abstract them into a standardized model that can be used for testing. In the specific execution process, common core usage scenarios of Android devices are first selected, such as standby, video playback, and large-scale games. Operational data for each scenario is collected in real time using testing tools, including CPU utilization, DDR memory access frequency, access interval, frequency adjustment frequency, and frequency change range. Subsequently, the collected data is analyzed and refined to extract the core load characteristics of each scenario. For example, in the standby scenario, the CPU utilization is consistently below 5%, the DDR memory access frequency is extremely low (no more than 10 accesses per minute), and the frequency remains stable below 800MHz with almost no fluctuations. In the video playback scenario, the CPU utilization is maintained at 20%-30%, memory access is regular (accessing once every 10 milliseconds), and the frequency is stable between 2400MHz-3200MHz with occasional small fluctuations. In high-load application scenarios (such as large-scale 3D games), CPU utilization exceeds 80%, memory access is frequent, occurring every 1-5 milliseconds, and the frequency fluctuates frequently between 3200MHz and 6400MHz with a significant range. Finally, these core characteristics are parameterized to form corresponding scenario models. Each model clearly defines the load range, memory access characteristics, and frequency variation patterns under that scenario, providing a basis for subsequent test configurations.

[0047] Furthermore, based on the access density, access cycle, and expected frequency jump behavior corresponding to the scenario model, a target frequency set matching the scenario model is selected from the candidate frequency set. The access cycle is the time interval between two consecutive accesses of DDR memory, reflecting the temporal pattern of access and assisting in determining a reasonable interval for frequency switching. For example, in a video playback scenario, memory access is relatively regular, with the time interval between two accesses remaining stable at around 10 milliseconds, resulting in a fixed access cycle; in high-load application scenarios, the access interval may fluctuate between 1 and 5 milliseconds, and the access cycle is not fixed. Frequency jump behavior refers to the regularity and characteristics of DDR memory frequency changes in specific scenarios, including jump frequency, jump span, and jump order, guiding the selection of switching modes. For example, in a standby scenario, the frequency jump frequency is extremely low, almost maintaining a fixed low frequency, with a small jump span; in a multi-task switching scenario, the frequency jump frequency is high, with a large span and no fixed order. The frequency switching sequence is an ordered combination of frequency switching based on a candidate frequency set, generated for different switching modes (random, ascending, descending, interference). Its function is to simulate the frequency change process under a specific switching mode and provide a specific switching path for testing.

[0048] The candidate frequency set is a collection of all possible frequency pairs formed by combining multiple preset frequency levels of DDR memory in pairs. Its function is to provide a comprehensive foundation for selecting the target frequency set. For example, if the preset frequency levels are 6400MHz, 5500MHz, 3200MHz, 2400MHz, 1200MHz, 800MHz, and 600MHz, the candidate frequency set would include all dual-frequency combinations such as 6400MHz and 5500MHz, 5500MHz and 3200MHz, and 1200MHz and 600MHz. The target frequency set is a subset of frequency combinations from the candidate frequency set that match a specific scenario model. Its function is to provide a basis for frequency switching that fits the actual scenario in the corresponding testing phase, ensuring the test's relevance. For example, the target frequency set for the standby scenario model might only include low-frequency combinations such as 800MHz and 600MHz, and 1200MHz and 800MHz.

[0049] Understandably, the core of the above steps in selecting the target frequency set is to ensure that the frequency combinations accurately match the actual operating characteristics of the scenario model, thus ensuring that the test scenario closely reflects real-world usage conditions. First, the three key parameters corresponding to the scenario model are clarified: access density reflects the frequency of memory access per unit time, access cycle reflects the regularity of the time interval between two accesses, and frequency jump behavior reflects the frequency, span, and order of frequency changes. Then, based on these parameters, suitable frequency combinations are selected from the candidate frequency set. For example, for the standby scenario model, its access density is extremely low, the access cycle is long (over 1 minute), and the frequency jump behavior is almost non-existent and stable in the low-frequency range. Therefore, combinations of all low-frequency levels are selected from the candidate frequency set, such as 600MHz and 800MHz, 800MHz and 1200MHz, forming the target frequency set for this scenario model, ensuring that the frequency combinations conform to the low-frequency stability characteristics of standby. For the video playback scenario model, with moderate access density and a fixed access period (around 10 milliseconds), the frequency jump behavior is characterized by small jumps within the mid-frequency range. Frequency combinations between 2400MHz and 3200MHz are selected from the candidate frequency set, such as 2400MHz and 3200MHz, 3200MHz and 5500MHz (occasionally jumping slightly to the upper limit of the mid-frequency range), forming the target frequency set. For the high-load application scenario model, with extremely high access density and a short access period (1-5 milliseconds), the frequency jump behavior is characterized by frequent, large-span jumps within the high-frequency range. High-frequency combinations between 3200MHz and 6400MHz are selected from the candidate frequency set, such as 3200MHz and 5500MHz, 5500MHz and 6400MHz, 3200MHz and 6400MHz, forming the target frequency set, ensuring that the frequency combinations can simulate the high-frequency jump characteristics under high load.

[0050] Furthermore, a switching mode adapted to the scenario model is selected for each testing phase. The core of selecting a switching mode is to ensure that the frequency change logic of the switching mode is consistent with the frequency jump behavior of the scenario model, simulating the frequency switching process in real-world scenarios. First, the frequency jump behavior characteristics of each scenario model are analyzed, and then a suitable switching mode is matched accordingly. For example, the frequency jump behavior of the standby scenario model is low-frequency and stable with almost no jumps, making it suitable for sequential frequency reduction mode or stable low-frequency mode. These switching modes have smooth frequency changes and very few jumps, consistent with the frequency characteristics of standby. The frequency jump behavior of the video playback scenario model is regular small jumps within the mid-frequency range, making it suitable for sequential frequency increase mode or fixed mid-frequency switching mode. These switching modes have stable frequency changes and small spans, consistent with the frequency adjustment logic during video playback. The frequency jump behavior of the high-load application scenario model is frequent, large-span, and irregular jumps within the high-frequency range, making it suitable for random switching mode or interference switching mode. These switching modes have no fixed order of frequency changes and large spans, accurately simulating the frequency jump characteristics of scenarios such as large-scale games. If the scenario model is a multi-task switching scenario (combining multiple load characteristics), its frequency jump behavior is a sudden jump across intervals and without regularity. It is adapted to the interference switching mode, which can simulate the frequency mutation when switching between different loads, ensuring that the test covers complex scenarios.

[0051] Next, a sequence matching the switching mode is selected from the frequency switching sequences. Specifically, the core of selecting the frequency switching sequence is to ensure that the frequency change path of the sequence perfectly matches the characteristics of the switching mode and the scene model, providing a specific frequency switching path for testing. First, based on the previously generated frequency switching sequence library, each switching mode corresponds to multiple preset frequency switching sequences. The differences between the sequences are reflected in the order, span, and interval of frequency changes. Then, based on the scene model and switching mode in the testing phase, the most suitable sequence is selected. For example, for the sequential frequency reduction mode corresponding to the standby scene model, a smooth frequency reduction sequence in the low-frequency range is selected from the sequential frequency reduction frequency switching sequences, such as 1200MHz-800MHz-600MHz. This sequence has a small frequency span and smooth changes, which conforms to the frequency stability characteristics during standby. For the sequential frequency increase mode corresponding to the video playback scene model, a stable frequency increase sequence in the mid-frequency range is selected from the sequential frequency increase sequences, such as 2400MHz-3200MHz-5500MHz. This sequence changes frequency within the mid-frequency range with a moderate span, which conforms to the frequency adjustment rules during video playback. For the random switching mode corresponding to the high-load application scenario model, frequent large-span sequences within the high-frequency range are selected from the random sequence class, such as 3200MHz-

[0052] The frequency sequence 6400MHz-5500MHz-3200MHz-6400MHz exhibits a wide frequency range with no fixed order, accurately simulating frequency jumps during large-scale games. For the interference switching mode corresponding to the multi-task switching scenario model, sequences with sudden jumps across intervals are selected from the interference sequences, such as 2400MHz-6400MHz-

[0053] The 1200MHz-5500MHz frequency range includes sudden transitions from intermediate frequency to high frequency and from high frequency to low frequency, which conforms to the frequency change characteristics during multi-task switching, ensuring that the test can effectively cover potential faults in this scenario.

[0054] Further optionally, in the above embodiments, generating stage configuration information for describing the execution logic of each test stage includes: determining the access method of the current test stage based on the scenario model, wherein the access method includes sequential access, random access, or mixed access; determining a frequency switching triggering strategy based on the switching mode and the target frequency set, wherein the frequency switching triggering strategy includes triggering by access count, triggering by time slice, or triggering by scenario feature event; determining the frequency disturbance intensity of the current test stage based on the load change characteristics of the scenario model, so as to simulate the actual DDR frequency switching behavior under the corresponding scenario in each test stage; and constructing the stage configuration information by combining the target frequency set, the access method, the frequency switching triggering strategy, the frequency disturbance intensity, and the execution order of the multi-stage test process.

[0055] It's worth noting that the access methods refer to the specific data read / write path patterns of CPU-memory interaction in DDR memory testing. The core function is to simulate memory access logic under different Android system scenarios, ensuring that the tested read / write behavior closely resembles real-world applications. Sequential access means the CPU performs read / write operations sequentially according to consecutive memory addresses, resulting in a fixed and predictable access path, suitable for simulating scenarios with continuous data transmission. Random access means the CPU selects memory addresses randomly without a fixed address order, exhibiting no predictable pattern, used to simulate complex access scenarios such as multitasking. Hybrid access combines the characteristics of the first two methods, accessing consecutive addresses during some periods and randomly selecting addresses during others, adapting to access scenarios with both regularity and sudden changes. For example, during video playback, the CPU reads frame data sequentially, which is sequential access. During multitasking, the CPU randomly reads cached data from different applications, which is random access. Large games simultaneously load maps (sequential) and player input commands (random), which is hybrid access.

[0056] Frequency switching triggering strategies are rules that control the timing of DDR memory frequency switching. Their core function is to accurately match the temporal patterns of frequency changes in the scenario model, ensuring that frequency switching is consistent with the timing characteristics of the actual scenario. **Frequency-based triggering:** Frequency switching is triggered after a preset number of memory read / write operations, suitable for scenarios with fixed access frequencies. **Time-slice triggering:** Frequency switching is triggered at preset fixed intervals, suitable for scenarios with stable access rhythms. **Scenario-specific event triggering:** Frequency switching is triggered when a specific scenario event occurs, suitable for scenarios with clearly event-driven frequency changes. For example, switching the frequency after every 1000 read / write operations is frequency-based triggering. Switching the frequency every 50 milliseconds is time-slice triggering; triggering a frequency switch when a background download task starts is scenario-specific event triggering.

[0057] The target frequency set is a subset of frequency combinations selected from the candidate frequency set that are suitable for the current scenario model. Its core function is to provide a basis for frequency switching that fits the scenario during the testing phase, ensuring that the frequency range meets actual usage requirements. For example, the target frequency set for the standby scenario model is a pairwise combination between 600MHz, 800MHz, and 1200MHz, while the target frequency set for the high-load application scenario is a pairwise combination between 3200MHz, 5500MHz, and 6400MHz.

[0058] Frequency disturbance intensity is a parameter describing the severity of frequency switching. Its core function is to simulate the fluctuation amplitude and frequency of frequency changes under different scenarios. Its quantitative indicators include frequency jump span (the difference between adjacent switching frequencies) and jump frequency (the number of switching times per unit time). Disturbance intensity is divided into three levels: low, medium, and high. Low intensity corresponds to small jump span and low frequency; medium intensity corresponds to moderate span and medium frequency; and high intensity corresponds to large span and high frequency. For example, the disturbance intensity in a standby scenario is low, while the disturbance intensity in a high-load multi-tasking scenario is high.

[0059] The multi-stage testing process is a progressive test chain consisting of at least two test phases with different switching modes. Its core function is to comprehensively cover various frequency switching scenarios in the Android system, verifying the stability of DDR memory step by step from simple to complex. The process typically includes stages such as random switching, sequential downclocking, sequential upclocking, and mixed random switching, executed in order of increasing scenario complexity.

[0060] The stage configuration information is a standardized document that integrates the target frequency set, access method, frequency switching trigger strategy, frequency disturbance intensity, and multi-stage execution order. Its core function is to provide clear execution basis for each test stage, ensuring that the test process is repeatable and quantifiable, and enabling testers to accurately reproduce the test conditions corresponding to the scenario model according to the configuration.

[0061] In the above embodiments, the purpose of determining the access method is to match the memory access path patterns in the scenario model, so that the tested read / write behavior is consistent with the actual Android system scenario. First, the load characteristics of the scenario model are analyzed to determine whether the CPU's memory access path in this scenario has a regularity. If the access behavior of the scenario model has a fixed order, such as the video playback scenario model, its core feature is the continuous reading of consecutive video frame data. The access path proceeds sequentially according to memory addresses without skipping or random selection. In this case, the sequential access method is selected. The CPU will read and write data from low to high consecutive memory addresses. For example, starting from address 0x00000000, it will read and write sequentially to 0x00010000, and then continue to subsequent addresses, simulating the continuous transmission logic of video frame data. If the access behavior of the scenario model is irregular, such as in a multi-task switching scenario model, where the CPU frequently switches between accessing cached data from different applications with random and unpredictable address selection, then a random access method is chosen. The CPU can first access address 0x00008000, then jump to 0x00020000, and then return to 0x00005000, simulating random access to data from multiple applications. If the access behavior of the scenario model has both regularity and randomness, such as in a large game scenario model, where sequential access to consecutive addresses occurs when loading map resources, and random access to instruction cache addresses occurs when responding to player operation commands, then a hybrid access method is chosen. The CPU accesses a series of consecutive addresses, then inserts random address access, and then resumes sequential access, simulating both the regular read / write of resource loading and the random read / write of operation responses.

[0062] Furthermore, the frequency switching trigger strategy is determined based on the switching mode and the target frequency set. Specifically, the core of determining the trigger strategy is to ensure that the timing of frequency switching matches the logic of the switching mode and the range of the target frequency set, ensuring that the switching rhythm conforms to the actual scenario. If the switching mode is sequential frequency reduction or sequential frequency increase, and the target frequency set has a stepped frequency distribution (e.g., 6400MHz, 5500MHz, 3200MHz), it needs to switch gradually at a fixed rhythm. In this case, triggering based on the number of accesses is chosen, for example, triggering a frequency switch once every 2000 memory read / write operations, ensuring that there is enough read / write data to verify the stability at that frequency after each switch, and avoiding excessively frequent switching that could lead to data anomalies that cannot be located. If the switching mode is random switching, and the target frequency set contains frequency combinations in different ranges (e.g., 600MHz, 3200MHz, 6400MHz), it needs to simulate irregular switching timing. In this case, triggering based on time slices is chosen, for example, triggering a frequency switch every 50 milliseconds, regardless of the number of read / write operations during that period, switching at a fixed time interval, conforming to the timing logic of the Android system's background automatic frequency adjustment. If the switching mode is interference switching and the target frequency set contains a large-span combination across intervals (such as 1200MHz, 6400MHz), it is necessary to simulate event-driven sudden switching. In this case, select to trigger according to scene characteristic events, such as setting virtual events such as "background download task start", "application switching", "screen brightness adjustment" etc. When the event is triggered, frequency switching is executed immediately to simulate the frequency change caused by sudden behavior in actual use.

[0063] Next, the frequency perturbation intensity for the current testing phase is determined based on the load change characteristics of the scenario model. The purpose of this step is to reproduce the drastic load changes in the scenario model, ensuring that the fluctuation amplitude and frequency of frequency switching closely match the actual scenario. First, the load change characteristics of the scenario model are analyzed to determine whether the load is stable, fluctuating gently, or fluctuating drastically. If the load of the scenario model is consistently stable with no significant fluctuations, such as in a standby scenario model where CPU utilization is below 5%, memory access is minimal, and the frequency remains consistently low, then a low-frequency perturbation intensity is set. The frequency jump range is controlled between 200MHz and 400MHz (e.g., switching from 600MHz to 800MHz, or from 800MHz to 1200MHz), and the jump frequency is no more than 5 times per minute, simulating a nearly stable frequency state during standby. If the load of the scenario model fluctuates smoothly, such as a video playback scenario model, the CPU utilization rate remains at 20%-30%, the access rhythm is fixed, and the frequency is slightly adjusted in the mid-frequency range. In this case, set the mid-frequency perturbation intensity, and control the jump span between 800MHz-1500MHz (e.g., switching from 2400MHz to 3200MHz, or from 3200MHz to 5500MHz), with a jump frequency of 10-20 times per minute, to simulate small frequency fluctuations when the load changes smoothly. If the load of the scenario model fluctuates drastically, such as a high-load multitasking scenario model, the CPU utilization rate frequently switches between 30%-90%, memory access is frequent and chaotic, and the frequency needs to jump rapidly between high and low frequency ranges. In this case, set the high-frequency perturbation intensity, and control the jump span above 2000MHz (e.g., switching from 3200MHz to 6400MHz, or from 5500MHz to 1200MHz), with a jump frequency of more than 30 times per minute, to simulate a sudden frequency change scenario when the load fluctuates drastically.

[0064] Finally, the configuration information for the test phase is built. The purpose of this step is to systematically integrate the previously determined parameters, forming a standardized basis for test execution and ensuring that the execution logic of each test phase is clear and implementable. First, the target frequency set corresponding to the current test phase is defined. For example, the target frequency set for high-load application scenarios is a combination of 3200MHz and 5500MHz, 5500MHz and 6400MHz, or 3200MHz and 6400MHz. Next, the determined access method is entered, such as the random access method corresponding to this scenario. Then, the frequency switching trigger strategy is recorded, such as triggering by the number of accesses, triggering a switch once every 1000 reads and writes. Next, the frequency disturbance intensity level is defined, such as high disturbance intensity, jump span ≥2000MHz, frequency ≥30 times / minute. Finally, the execution order of this test phase in the multi-phase process is determined, for example, arranged in the order of random switching mode (first phase), sequential frequency reduction mode (second phase), high-load interference mode (third phase), and mixed random mode (fourth phase). These parameters are organized into a standardized file containing the target frequency range, read / write path rules, switching trigger conditions, disturbance intensity standards, and execution order. This file is the stage configuration information. For example, the stage configuration information for a high-load application scenario can be clearly defined as follows: the target frequency set is a pairwise combination within the 3200MHz-6400MHz range; the access method is random access; the frequency switching trigger strategy is triggered once every 1000 reads / writes; the frequency disturbance intensity is high; and the execution order is the third stage. This configuration information can directly guide testers to accurately execute tests for the corresponding scenario, ensuring that the testing process is highly consistent with the actual application scenario.

[0065] Step S103: For each test phase, target data is generated before the frequency switching action is performed, and actual data is obtained from DDR memory during the frequency switching action. The target data and the actual data are compared for consistency to detect whether the frequency switching process causes data jump.

[0066] In this embodiment, the generation of target data focuses on supporting data consistency comparison during frequency switching, relying on the CPU in the testing system, and must meet the basic requirements of accurate verification and unambiguous comparison. The target data generation logic is closely integrated with the DDR memory testing process. Specifically, the CPU autonomously generates data according to testing requirements. There are no special restrictions on the data type; it can be any information with comparable characteristics, such as continuous binary data, ordered character sequences, or fixed-format numerical sets. The core is to ensure that the data can be clearly determined whether it has changed during subsequent reading or verification.

[0067] The timing of data generation must match the operational scenarios of different testing phases. In the first phase of testing, the CPU continuously writes data to the DDR memory until it is completely full. The data written at this point constitutes the target data for this phase, providing a complete benchmark for subsequent random frequency switching comparisons. In the second, third, and fourth phases of testing, the CPU generates the target data synchronously during the data writing operation. The data is gradually stored in the DDR memory as the writing action progresses. This generation process is synchronized with the frequency switching action, ensuring that each segment of written data can serve as a benchmark to detect whether any jumps occur during the switching process. For example, the CPU can generate a set of continuous hexadecimal data from 0000 to FFFF, or generate a repeating sequence of characters "ABCDEFG". After these data are written to the DDR memory, they become the target data. This data does not require complex encryption or formatting; it only needs to ensure its continuity and stability. This allows the actual data subsequently obtained from the DDR memory to be clearly identified through byte-by-byte and bit-by-bit comparisons, clearly identifying anomalies such as bit flips, missing data, and disordered sequences, providing a reliable benchmark for frequency switching fault detection.

[0068] It's important to understand that in practical applications, the target data generation scenario in the random frequency switching test phase assumes that memory is filled before frequency switching begins, providing complete benchmark data for read comparisons under irregular frequency jumps. In the test system, the CPU initiates data writing operations according to preset rules, continuously transferring data to DDR memory. The data type can be a continuous binary sequence, an ordered set of values, or a fixed string—information with clear comparison characteristics—until the DDR memory is completely full. When the memory storage capacity reaches saturation, target data generation is complete, and all generated data will serve as the benchmark for subsequent random frequency switching. For example, the CPU generates continuous hexadecimal data from 0000 0000 to FFFF FFFF, writing it byte-by-byte to DDR memory. Once all memory addresses are filled with this data, the target data generation process ends, followed by the random frequency switching and data read comparison phase. This simulates the data benchmark construction requirements under high-frequency, irregular frequency jump scenarios such as screen switching in the Android system.

[0069] The target data generation scenario in the sequential downclocking test phase assumes that the write operation and frequency downclocking proceed simultaneously, with the generation process and frequency switching action linked in real time. Specifically, the CPU initiates a data write operation, and the data is gradually stored in the DDR memory as the write operation proceeds. Simultaneously, the DDR memory performs downclocking operations in stages from high to low according to preset frequency levels. The generation, writing, and downclocking of target data are performed synchronously. The generated target data is segmented according to the writing order, corresponding to different frequency ranges, ensuring that each segment can serve as a comparison benchmark during the corresponding frequency switching process. For example, with preset frequency levels of 6400MHz, 5500MHz, 3200MHz, and 2400MHz, the CPU generates an ordered decimal numerical sequence 1, 2, 3, 4… When writing data “1-1000”, the DDR memory is at 6400MHz. When writing “1001-2000”, the frequency is simultaneously downclocked to 5500MHz. Target data is continuously generated according to the writing rhythm, with each segment corresponding to a specific frequency state, used to detect whether the written data undergoes a jump during the sequential downclocking process.

[0070] The target data generation scenario in the sequential frequency increase mode test phase assumes that the write operation and frequency increase proceed synchronously, which is the reverse of the sequential frequency decrease mode. The generation logic focuses on building benchmark data under the scenario of gradually increasing frequency. Specifically, the CPU begins writing data to DDR memory, and the data is stored gradually in a continuous or segmented form. During this process, the DDR memory performs frequency increase operations step by step from low to high according to the preset frequency levels. The generation progress of the target data is consistent with the write operation and the frequency increase rhythm. The generated target data also corresponds one-to-one with the frequency increase interval according to the write order, ensuring that there is corresponding benchmark data for comparison when switching frequency levels. For example, the preset frequency levels are 600MHz, 800MHz, 1200MHz, and 2400MHz. The CPU generates a repeating "ABCDEFG" character sequence. When writing the first 500 sets of sequences, the DDR memory is at 600MHz. When writing the 501st to 1000th sets of sequences, the frequency is simultaneously increased to 800MHz. The target data is continuously generated during the frequency increase process to detect whether the integrity of the written data is affected by the frequency change during sequential frequency increase.

[0071] The target data generation scenario in the hybrid random switching mode test phase assumes dynamic synchronization between write operations and hybrid frequency switching, comprehensively adapting to the baseline data requirements under complex switching actions. Specifically, the CPU initiates a data write operation, with data being gradually stored in DDR memory in a continuous or segmented manner. Simultaneously, the DDR memory performs hybrid switching actions, which may include combinations such as random jumps, a period of sequential frequency reduction, another random jump, and a period of sequential frequency increase. The generation of target data is synchronized in real time with these complex switching actions. The generated target data is segmented according to time sequence and switching actions, with each segment corresponding to a set of hybrid switching behaviors, ensuring that there is a clear benchmark for comparison under different switching combination scenarios. For example, the CPU generates alternating binary data "010101..." and "101010...". During the write process, the DDR memory first randomly jumps from 3200MHz to 5500MHz, then sequentially reduces the frequency to 2400MHz, and then randomly jumps to 6400MHz. Target data is continuously generated with the write and hybrid switching actions, with each segment corresponding to a specific switching combination scenario, used to verify the stability of data generation and storage under complex and variable frequency switching conditions.

[0072] As an optional embodiment, in step S103, data generation rules are configured, and target data with preset bit characteristics is generated using a pseudo-random sequence generator or a fixed pattern generator. The target data is then mapped to a specific test address space of the DDR memory. The operation type of the current test phase is identified. If the current test phase is a read operation verification phase, the target data is pre-written into the specific test address space, and a read operation is performed on the specific test address space to collect actual data during the effective window period of the DDR memory frequency switching instruction. If the current test phase is a write operation verification phase, the target data is written into the specific test address space during the effective window period of the DDR memory frequency switching instruction, and a readback operation is performed on the specific test address space to collect actual data after the writing is completed. The XOR check value of the target data and the actual data is calculated. If the XOR check value indicates that there are inconsistent bits, it is determined that a data jump has been detected, and the frequency switching action, logical address, and corresponding error bits that caused the data jump are recorded.

[0073] In the above embodiments, firstly, clear data generation rules need to be configured. Based on testing requirements, a pseudo-random sequence generator or a fixed pattern generator is selected to generate target data. The data generation rules are preset standards used to regulate the generation method of target data. Their core function is to ensure that the generated target data possesses characteristics that can be accurately verified, facilitating subsequent comparison with actual data to identify anomalies. These rules include parameters such as data bit width, bit distribution pattern, and repetition period. For example, the data may be set to have a 32-bit width, with each 8 bits forming a repetition unit, or the data may be set to contain a specific number of 0 and 1 bits to improve anomaly detection sensitivity.

[0074] In this embodiment, the pseudo-random sequence generator is a tool that generates irregular but reproducible data sequences following a specific algorithm. Its core function is to generate target data with random distribution characteristics, simulating the complex and ever-changing data forms in real-world applications. For example, using a linear feedback shift register algorithm, it generates continuously changing binary data without obvious repeating patterns, such as 00101101, 01101010, 11010101, etc. This type of data can comprehensively detect the stability of different bits in memory. The fixed pattern generator is a tool that generates fixed repeating or specific regular data sequences. Its core function is to generate target data with clearly defined characteristics, facilitating the rapid location of specific bits in abnormal data. For example, it generates a fixed repeating binary sequence of 01010101, or generates continuously increasing sequences of 00000001, 00000010, 00000011. Abnormal changes in this type of data can intuitively reflect the fault location.

[0075] To simulate complex and varied data scenarios in real-world applications, a pseudo-random sequence generator can be used. This generator produces random but reproducible target data according to a preset bit width (e.g., 32 bits) and bit distribution ratio (e.g., 50% 0 and 50% 1). For example, it can continuously generate 32-bit binary data such as 00110010, 10101100, and 01100101. To quickly locate abnormal bits, a fixed pattern generator can be used to generate target data with a fixed pattern, such as a repeating 16-bit binary sequence 0000111100001111, or continuously increasing 8-bit data such as 00000001, 00000010, up to 11111111. After generating the target data, it is mapped to a specific test address space in DDR memory. This address space needs to be pre-defined and independent of the system and application data storage areas, for example, mapped to a continuous address range from 0x00010000 to 0x00020000. This ensures that the test data is not interfered with by other operations and facilitates precise location of data storage. The preset bit features are pre-defined bit-level characteristics of the target data. Their core function is to provide a clear basis for data consistency verification, including bit distribution ratios, fixed bit values ​​at specific positions, and bit flip cycles. For example, the ratio of 0 to 1 bits in the data is set to 1:1, or the 16th bit of each 32-bit data is fixed as 1. Whether these features are retained is checked to determine if the data is abnormal. The target data is standard data generated according to data generation rules and used as a comparison benchmark. Its core function is to provide a reference for data integrity detection during frequency switching. Its form is determined by the data generation rules and the generator type. For example, irregular 32-bit data generated by a pseudo-random sequence generator or repeating binary sequences generated by a fixed pattern generator can both be used as target data.

[0076] Next, the operation type of the current testing phase is identified to determine whether it is a read operation verification phase or a write operation verification phase. If it is a read operation verification phase, the core is to check the integrity of the data read during frequency switching. The operation process involves pre-writing the generated target data completely into a specific test address space, for example, writing the aforementioned pseudo-random sequence data sequentially into each address from 0x00010000 to 0x00020000. Then, a frequency switching command is sent to the DDR memory. Within the command's effective window (e.g., 10 to 20 milliseconds after the command is issued), a continuous read operation is performed on the specific test address space, collecting actual data address by address to ensure that the collected data is real data under dynamic adjustment during the frequency switching process. If it is a write operation verification phase, the core is to check the integrity of the data written during frequency switching. The operation process involves immediately entering the effective window after sending the frequency switching command to the DDR memory, and writing the target data address by address into the specific test address space within the window. After the write operation is completed, a readback operation is immediately performed on that address space to collect the actually stored data, avoiding data distortion due to subsequent operations overwriting or interference. For example, during the write operation verification phase, the frequency switching instruction is to switch from 3200MHz to 5500MHz. Within the effective window period, fixed pattern data is written into the test address space, and after the writing is completed, the data of each address is immediately read back as the actual data.

[0077] The specific test address space is a dedicated address range within DDR memory specifically designed for frequency switching tests. Its core function is to isolate test data from system or application data, preventing mutual interference and ensuring the accuracy of test results. This address space is typically a contiguous physical address range, such as 0x00010000 to 0x00020000 in DDR memory. It is used only for storing target data and collecting actual data, and does not participate in data read / write operations during normal device operation. The operation type refers to the core operation category performed on the DDR memory in the current test phase, divided into read operation verification and write operation verification phases. Their core function is to clarify the test focus, verifying the impact of frequency switching on the integrity of memory read and write operations. The read operation verification phase focuses on detecting whether data read during frequency switching is abnormal, while the write operation verification phase focuses on detecting whether data written during frequency switching is abnormal. The effective window of a frequency switching command refers to the time period from when the DDR memory receives the command until the frequency stabilizes completely at the target level. Its core function is to identify the critical period during frequency switching where data anomalies are most likely to occur, ensuring that the collected data accurately reflects the impact of the switching action. This window is typically in the millisecond range, for example, within 10 to 20 milliseconds after the command is issued. During this time, the memory frequency is dynamically adjusted, and data read / write operations are most susceptible to interference.

[0078] Finally, a bit-by-bit XOR operation is performed on the collected target data and the actual data to calculate the XOR checksum. This checksum is used to determine if the data is consistent. The actual data is the real data collected from a specific test address space during the effective window of the frequency switching instruction, obtained through read or readback operations. Its core function is to compare it with the target data, reflecting the actual state of the data during the frequency switching process. Its format is consistent with the target data (e.g., both are 32-bit binary data), but bit changes may occur due to frequency switching interference. The XOR checksum is obtained by performing an XOR operation on the corresponding bits of the target data and the actual data. Its core function is to quickly detect whether the two sets of data are consistent. The rule for the XOR operation is that the result is 0 for the same bit and 1 for different bits. If the checksum is all 0, the data is consistent. If there are non-zero bits, it indicates a data anomaly; the position of the non-zero bit is the error position. Data jumps refer to inconsistent bit changes between the actual data and the target data during the frequency switching process. Their core function is to identify data integrity failures in DDR memory during frequency switching, manifested as bit flips, missing data, or disordered sequence. For example, if a bit in the target data is 1, but the corresponding bit in the actual data is 0, this constitutes a data jump, which may lead to issues such as abnormal screen switching or system crashes on Android. For instance, if the target data is 32-bit binary 0011010100111000, and the actual data is 0011010100011000, an XOR operation yields a checksum of 0000000000100000. If the 10th bit (counting from 0) of this checksum is 1, it indicates a mismatch, thus confirming a data jump. If the checksum is all 0s, it means the target data and actual data are completely identical, and no data jump has occurred. After determining that a data jump has occurred, key information must be recorded in detail, including the frequency switching action that caused the jump (e.g., switching from 3200MHz to 5500MHz), the logical address of the data storage (e.g., 0x00010008), and the corresponding error bit (e.g., the 10th bit). The information recorded here can accurately pinpoint the specific scenario and location of DDR memory frequency switching failure, providing a clear basis for subsequent fault analysis and chip optimization, preventing DDR memory with such failures from entering the market, and ensuring the stable operation of Android system functions such as screen switching.

[0079] Further optionally, in one embodiment of step S103, the detection of whether the frequency switching process causes data jump can also be based on the Logistic chaotic mapping algorithm to construct a data generation model, configure initial iteration values ​​and bifurcation parameters, iteratively generate a chaotic sequence with nonlinear ergodic characteristics, and quantize the chaotic sequence into the target data in binary format; write the target data into a test address segment of DDR memory, wherein the test address segment is mapped to the physical address space of DDR memory through a Hilbert curve trajectory to maximize the spatial locality interference of the test data; after the frequency switching action is completed, read the actual data in the test address segment through direct memory access, and calculate the Hamming distance between the actual data and the target data segment by segment using a sliding window mechanism; construct a spatiotemporal distribution map based on the Hamming distance, and statistically analyze the peak and mean Hamming distances within a unit sliding window. When a non-zero Hamming distance is detected and it shows clustering characteristics on the spatiotemporal distribution map, it is determined that a sudden data jump fault is caused by the frequency switching process.

[0080] Specifically, in the above embodiments, firstly, a data generation model is built based on the Logistic chaotic mapping algorithm. The core purpose is to generate target data with high detection sensitivity to meet the needs of DDR memory frequency switching tests. The Logistic chaotic mapping algorithm is a numerical iterative method designed based on the principle of nonlinear dynamics. Its core function is to generate disordered and comprehensive data sequences. Its core logic is to allow values ​​to evolve continuously through specific iterative relationships. During the iteration process, the next value is determined by the current value and the bifurcation parameter, which can produce complex and non-repeating results, suitable for constructing highly sensitive test data. The data generation model is a standardized data production framework built on the Logistic chaotic mapping algorithm. Its core function is to transform the algorithm iteration process into target data that can be directly used for DDR memory testing. The framework includes modules such as parameter configuration, iterative calculation, and format conversion to ensure that the generated data meets the test verification requirements and can accurately reflect the impact of frequency switching on the data.

[0081] In the above steps, the initial iteration value and bifurcation parameter of the algorithm are configured. The initial iteration value is selected as a value between zero and one, for example, 0.45. The bifurcation parameter is set in the chaotic interval of 3.5 to 4.0, for example, 3.9. This parameter range ensures that the generated sequence has strong nonlinear ergodic characteristics and covers a wider variety of numerical combinations. The initial iteration value is the starting value for starting the Logistic chaotic mapping algorithm. Its core function is to determine the initial state of the chaotic sequence. The value is usually between zero and one, for example, 0.35 or 0.75. Different initial values ​​will generate different sequences, but all maintain the characteristics of disorder and ergodicity, providing a diverse data foundation for testing. The bifurcation parameter is a key parameter for adjusting the iterative behavior of the Logistic chaotic mapping algorithm. Its core function is to control the degree of disorder and coverage of the chaotic sequence. The value is generally between zero and four. When the parameter is between 3.5 and 4.0, the sequence will exhibit a completely chaotic state. For example, setting the parameter to 3.85 can generate a sequence with strong disorder and covering a wider range of numerical values, improving the comprehensiveness of data jump detection.

[0082] Subsequently, iterative calculations are initiated. According to the algorithm's logic, the next value is obtained by multiplying the current value by the bifurcation parameter, then multiplying by one and subtracting the current value. This iterative process continues to generate chaotic sequences. A chaotic sequence is a continuous set of values ​​generated by the Logistic chaotic mapping algorithm after iteration. Its core function is to serve as the original source of the target data. Its characteristic is non-linear traversal, meaning the values ​​fluctuate irregularly but can uniformly cover a specific interval. For example, the iteratively generated values ​​such as 0.3, 0.806, 0.599, and 0.958 have no fixed distribution but cover the interval from 0 to 1. For instance, with an initial iteration value of 0.45 and a bifurcation parameter of 3.9, the value obtained in the first iteration is 3.9 multiplied by 0.45, then multiplied by one and subtracted from 0.45, approximately 0.965. The second iteration uses 0.965 as a base to calculate, obtaining a value of approximately 0.126. Subsequent iterations continue to generate irregular sequence data. Nonlinear traversal characteristics are the core properties of chaotic sequences. They are characterized by irregular numerical values ​​that can fully cover a preset range. The core function is to make the target data contain more diverse bit combinations, avoid anomaly omissions caused by monotonous data patterns, and ensure that various potential data jump problems can be detected in DDR memory frequency switching tests.

[0083] Next, the chaotic sequence is quantized and converted using a unified conversion rule. For example, values ​​greater than 0.5 are mapped to binary 1, and values ​​less than or equal to 0.5 are mapped to binary 0. The sequences 0.965, 0.126, 0.48, and 0.97 generated in the iterations are converted into the binary sequence 1, 0, 0, 1, ultimately forming the target data in binary format. This data, due to its non-linear traversal characteristics, can comprehensively cover different bit combinations, improving the detection probability of data jumps. Quantization is a process of converting continuous values ​​in a chaotic sequence into binary data. Its core function is to adapt to the binary storage format of DDR memory, facilitating subsequent data reading, writing, and comparison. For example, setting the conversion rule that values ​​greater than 0.5 correspond to binary 1 and values ​​less than or equal to 0.5 correspond to binary 0, the chaotic sequences 0.3, 0.806, and 0.599 are converted into binary 0, 1, 1.

[0084] Furthermore, a dedicated test address segment is allocated within the DDR memory. This segment is a continuous logical address range, such as 0x00030000 to 0x00040000, specifically for storing test data. This avoids conflicts with system runtime data or application data, ensuring that test results are not interfered with. Subsequently, this test address segment is mapped to the physical address space of the DDR memory using a Hilbert curve trajectory. The Hilbert curve transforms continuous logical addresses into dispersed physical addresses according to specific recursive rules. For example, logical address 0x00030000 is mapped to physical address 0x80012345, logical address 0x00030001 is mapped to physical address 0x80056789, and subsequent addresses are mapped to different physical regions sequentially according to the curve trajectory. This mapping method maximizes the spatial locality of interference of test data, simulating the actual scenario of random data distribution during multi-tasking operation in the Android system, making the test closer to real-world usage conditions. The Hilbert curve trajectory is a curve that can continuously fill space. Its core function is to map continuous test address segments (logical addresses) to the dispersed physical address space of DDR memory. During the mapping, it extends according to specific recursive rules, so that logically continuous addresses are distributed in a dispersed manner at the physical level. For example, the continuous interval of logical address from 0x00030000 to 0x00040000 can be mapped to dispersed physical addresses such as 0x80012345, 0x80056789, and 0x80024680 through the curve trajectory.

[0085] After mapping, the previously generated binary target data is written byte by byte into the mapped physical address space to ensure that the target data is completely stored in the test area, laying the foundation for subsequent comparison with actual data. The physical address space is the actual hardware address range used to store data in DDR memory. Its core function is to provide the physical carrier for data storage, corresponding to the test address segment corresponding to the logical address. For example, the physical address range of DDR memory is 0x80000000 to 0xFFFFFFFF, with each address corresponding to an independent storage unit used to store test data. Spatial locality interference refers to the dispersed distribution of test data in the physical address space after mapping using a Hilbert curve. Its core function is to break the conventional pattern of centralized data storage, simulating the actual scenario of random data distribution during multi-tasking operation in the Android system, increasing the testing difficulty of the impact of frequency switching on data, and more comprehensively exposing potential faults in DDR memory.

[0086] Next, after the DDR memory completes its frequency switching, the actual data within the test address range is immediately read using Direct Memory Access (DMI). This method eliminates the need for CPU processing, interacting directly with the DDR memory through a dedicated hardware controller. This allows for fast and interference-free data acquisition, avoiding delays or data distortion caused by CPU intervention, and ensuring that the acquired data accurately reflects the memory state after the frequency switch. DMI is a data stream transmission method that interacts directly with the DDR memory via hardware without CPU intervention. Its core function is to quickly and interference-free acquire the actual data in memory, avoiding delays or data distortion caused by CPU intervention, and ensuring that the acquired data accurately reflects the memory state after the frequency switch. For example, data in the physical address range can be read directly through a dedicated controller without CPU involvement in data transfer. For instance, after the DDR memory completes its frequency switch from 3200MHz to 5500MHz, all data in the physical address range from 0x80012345 to 0x80056789 can be read using DMI. Then, a sliding window mechanism is employed, setting the window length and step size. For example, the window length is 64 bytes and the step size is 32 bytes. The target data and actual data are segmented according to the window, and the Hamming distance between the two sets of data is calculated segment by segment. For example, if the target data in a certain window is 0101010100111000 and the actual data is 0101010100011000, there are two different bits in the two sets of data, and the Hamming distance of this window is 2. By calculating the Hamming distance of all windows segment by segment, the complete difference data is obtained. The sliding window mechanism is a method for segmenting continuous data. Its core function is to divide the target data and actual data into multiple fixed-length segments and perform precise comparisons segment by segment. For example, setting the window length to 64 bytes and moving 32 bytes each time forms continuous overlapping segments, making the data comparison more detailed and avoiding the omission of local anomalies due to overall comparison.

[0087] Finally, the Hamming distance data from all sliding windows are integrated to construct a spatiotemporal distribution map based on Hamming distance. The horizontal axis of the map represents the physical address of the test address segment, and the vertical axis represents the time series after frequency switching. Each coordinate point is indicated by its Hamming distance to the corresponding address and time window through color intensity. For example, points with a Hamming distance of 3 are marked in dark red, and points with a Hamming distance of 0 are marked in light blue, visually presenting the distribution of data anomalies. Hamming distance is an indicator that measures the degree of difference between two sets of binary data. Its core function is to quantify the severity of data jumps. Its value is equal to the number of corresponding bits that differ between the two sets of data. For example, if the target data is 01010101 and the actual data is 01100101, the two sets of data differ by two bits, and the Hamming distance is 2, which can intuitively reflect the degree of data anomaly. The spatiotemporal distribution map is a visualization chart formed by integrating Hamming distance data in the address and time dimensions. Its core function is to intuitively present the distribution pattern of data jumps. The horizontal axis of the chart is the physical address of DDR memory, and the vertical axis is the time series after frequency switching. The size of the Hamming distance is indicated by the color intensity. For example, the location with a larger Hamming distance is marked with a darker color, which makes it easier to observe the concentrated areas of data anomalies.

[0088] Next, the peak and mean Hamming distances within each sliding window are calculated. For example, if the Hamming distance data in a window are 0, 2, 3, and 1, the peak value is 3, and the mean value is 1.5. These indicators quantify the intensity and overall level of data jumps within that window. The peak and mean Hamming distances are statistical indicators of the Hamming distance data within a single sliding window. The peak value refers to the maximum Hamming distance within the window, and the mean value refers to the average value of all Hamming distances within the window. The core function is to quantify the anomaly intensity and overall level of a single data segment. For example, if the Hamming distances in a window are 1, 3, 2, and 0, the peak value is 3, and the mean value is 1.5, it clearly reflects the data jump situation of that segment.

[0089] Finally, observe the characteristics of the spatiotemporal distribution map. If a non-zero Hamming distance is detected, and these non-zero values ​​show a clustering characteristic on the map—that is, multiple consecutive windows within a specific physical address range or time range show non-zero Hamming distances (for example, after a frequency switch, within the physical address range of 0x80012345 to 0x80012445, the Hamming distances for four consecutive time windows are two, three, two, and four respectively, showing a clear concentrated distribution)—then it is determined that a sudden data jump fault caused by a frequency switch has been detected. Simultaneously, record the corresponding frequency switch action, the involved physical address range, and the peak and average Hamming distances. This provides accurate data support for subsequent fault analysis and DDR memory quality screening, preventing DDR memory with such serious faults from entering the market and ensuring the stable operation of the Android system. Clustering features refer to the concentrated distribution of non-zero Hamming distances in the spatiotemporal distribution map. This manifests as multiple consecutive sliding windows exhibiting non-zero Hamming distances within a specific physical address range or time period. Its core function is to distinguish between sudden faults and random errors. For example, if the Hamming distance of five consecutive windows is greater than zero after a frequency switch in a certain physical address segment, this qualifies as a clustering feature. Sudden data jump faults refer to instantaneous, concentrated bit changes caused by DDR memory frequency switching. Their core function is to identify fault types that severely impact data integrity. These faults can lead to issues such as abnormal screen switching and system crashes in Android systems, making them a key area to investigate during DDR memory testing.

[0090] Step S104: Based on the comparison results of each test stage, the reliability of the corresponding switching mode of the DDR memory is determined, and a fault correlation relationship is established between multiple test stages. When a data jump is detected in any test stage, the potential frequency switching fault of the DDR memory is determined based on the reliability determination results and the fault correlation relationship.

[0091] As an optional embodiment, in step S104, for each test phase, the number of frequency switching times, error bit density, and frequency switching paths of data jumps detected in each test phase are statistically analyzed, and the statistical results are compared with a preset reliability threshold to output the phase reliability index of the corresponding switching mode; a fault diagnosis matrix is ​​constructed, where the rows of the fault diagnosis matrix correspond to different switching modes, and the columns correspond to the frequency range classification of DDR memory; when any switching mode is determined to be of low reliability level in a certain frequency range, a fault indicator is marked at the corresponding position in the fault diagnosis matrix to establish the correlation between the switching mode and the fault frequency range; the fault diagnosis matrix is ​​cross-compared. The system includes switching modes and frequency ranges with fault indicators. If a data jump occurs only in ascending or descending switching modes, it is determined to be a fault of insufficient timing constraints for frequency switching in a specific direction. If a data jump occurs during the read operation verification phase but not during the write operation verification phase, it is determined to be a fault of insufficient data retention capability during frequency switching. If a data jump occurs in all test phases and involves all high, medium, and low frequency levels, it is determined to be a fault of insufficient systemic stability of the DDR memory frequency switching control unit. Based on the correlation analysis of the stage reliability indicators and the fault diagnosis matrix, combined with preset location rules, the type and scope of potential frequency switching faults currently existing in the DDR memory are determined.

[0092] First, for each test phase, three core parameters are statistically analyzed to quantify fault-related characteristics. The frequency switching count refers to the total number of frequency switching actions that trigger data jumps within that phase, reflecting the frequency of fault occurrence. For example, in a random switching mode test, if 10 frequency switches are performed and 3 trigger data jumps, this parameter is 3. The error bit density is the ratio of the number of error bits when a data jump occurs to the total number of bits in the target data, reflecting the severity of the data jump. For example, if 5 error bits appear in 1000 bits of target data, the density is 0.005. The frequency switching path is the specific sequence of frequency changes that trigger data jumps, used to locate specific fault scenarios. For example, if an anomaly occurs when switching from 3200MHz to 5500MHz, the path is from 3200MHz to 5500MHz. Subsequently, these statistical results are compared with preset reliability thresholds, which are benchmark parameters for measuring the reliability of the handover mode. These thresholds include frequency handover number thresholds and error bit density thresholds. For example, the handover number threshold is set to 2 and the density threshold is set to 0.003. If the actual statistical value exceeds the threshold, the corresponding handover mode's stage reliability index is output as low level. This index reflects the stability of the mode (divided into high, medium, and low levels). If the threshold is not exceeded, a high level is output, providing an intuitive basis for subsequent reliability judgment.

[0093] Next, a fault diagnosis matrix is ​​constructed. The fault diagnosis matrix is ​​a two-dimensional table structure used to systematically analyze the fault distribution of DDR memory frequency switching tests. Its core function is to establish a clear correlation between switching modes and fault frequency ranges, allowing testers to intuitively grasp the fault distribution patterns under different scenarios and providing clear data support for subsequent cross-analysis and fault localization. The role of the fault diagnosis matrix is ​​to analyze the fault distribution of different switching modes in each frequency range. Its row dimension corresponds to all switching modes involved in the tests, such as random switching, ascending order switching, descending order switching, and mixed random switching. The column dimension corresponds to the frequency range classification of DDR memory, namely, the high-frequency range (5500MHz-6400MHz), mid-frequency range (2400MHz-3200MHz), and low-frequency range (600MHz-1200MHz) divided according to preset frequency levels. The elements of the fault diagnosis matrix consist of three parts: first, the switching mode identifier at the beginning of each row, used to distinguish different frequency switching test scenarios; for example, the "ascending order switching mode" identifier corresponds to all data in that row being the test results for that mode. Second, the frequency range identifier at the top of the column is used to distinguish different frequency ranges. For example, the identifier "Medium Frequency Range 2400MHz-3200MHz" corresponds to all data in this column being test results within that frequency range. Third, the fault indicator in the cross cells of the table is a simplified identifier used to mark the presence or absence of a fault. It is usually represented by a specific value. For example, 1 indicates that a certain switching mode is judged to have a low reliability level in the corresponding frequency range, with faults such as data jumps. 0 indicates that the mode meets the reliability standard in the corresponding range and there is no fault. For example, when any switching mode is judged to have a low reliability level in a certain frequency range, a fault indicator is marked in the corresponding cell of the matrix. This indicator is used to clarify whether a fault exists, with 1 indicating the presence of a fault and 0 indicating no fault. For example, if the ascending switching mode has low reliability in the high frequency range, then 1 is marked in the cross cell of the "Ascending Switching" row and the "High Frequency Range" column, thus establishing a clear association between the switching mode and the faulty frequency range. For example, if the ascending-order switching mode exhibits data jumps during testing in the high-frequency range (5500MHz-6400MHz), indicating low reliability, a 1 is marked in the cell at the intersection of the "ascending-order switching mode" row and the "high-frequency range 5500MHz-6400MHz" column. Conversely, if the random switching mode shows no faults during testing in the low-frequency range (600MHz-1200MHz), meeting reliability standards, a 0 is marked in the corresponding cell. Through this combination of elements, the fault diagnosis matrix integrates scattered test results into a systematic fault distribution map, clearly showing which switching modes have problems in which frequency ranges, providing crucial support for accurately locating the fault type and its impact range.

[0094] Subsequently, all cells marked with fault indicators in the fault diagnosis matrix were cross-checked to identify the types of switching modes and frequency ranges involved in the faults, thus determining the distribution characteristics of data jumps. For example, the comparison revealed that fault indicators only appeared in the high-frequency and mid-frequency cells of the "ascending order switching" row, with no markings for other modes, indicating that data jumps only occurred in the ascending order switching mode. If fault indicators only existed in the switching mode cells corresponding to the read operation verification phase, and were not marked in the write operation phase, it indicated that data jumps only occurred during the read operation. If fault indicators were present in cells for all switching modes and all frequency ranges, it indicated that data jumps existed in all scenarios.

[0095] Based on the cross-comparison results and preset location rules, the specific fault type is determined. These preset location rules are pre-defined logic that matches the jump scenario with the fault type. If the data jump only occurs in ascending or descending switching modes, it indicates the fault is related to the timing of the frequency switching direction, and is determined to be a fault due to insufficient timing constraints in a specific direction of frequency switching. For example, if the anomaly only occurs in ascending switching, it may be due to a defect in the memory's timing adaptation to increasing frequency. If the data jump only occurs during the read operation verification phase and not during the write operation verification phase, it indicates the memory can write data normally, but cannot stably retain the stored data after frequency switching, leading to read anomalies, and is determined to be a fault due to insufficient data retention during frequency switching. If the data jump occurs in all test phases and all frequency ranges, involving all high, medium, and low frequency levels, it indicates the fault originates from an underlying design or hardware problem in the memory frequency switching control unit, and is determined to be a fault due to insufficient systemic stability of the DDR memory frequency switching control unit.

[0096] Finally, by combining the correlation analysis results of the stage reliability indicators and fault diagnosis matrix of each testing phase, the scope of the fault's impact is further clarified. This scope is the set of switching modes, frequency ranges, and operation types involved in the fault, used to quantify the degree to which the fault covers the usage scenario. For example, after determining that the fault is due to insufficient timing constraints in ascending sequence switching mode, the matrix shows that the fault involves high-frequency and mid-frequency ranges. The stage reliability indicators show that the high-frequency range has more fault switching times and a higher error bit density. Therefore, the potential fault type is finally determined to be insufficient timing constraints in ascending sequence switching mode, with an impact range of mid-frequency to high-frequency range (2400MHz-6400MHz). Ascending sequence switching actions in this range are prone to causing data jumps. If the fault is determined to be due to insufficient system stability, the matrix shows that the fault covers all switching modes and frequency ranges, and the stage reliability indicators are all at a low level. Therefore, the scope of the fault's impact is determined to be all frequency switching scenarios of DDR memory. A comprehensive investigation and optimization of the memory control unit is required to provide a clear basis for subsequent fault handling and DDR memory quality screening.

[0097] Step S105: Collaboratively verify the actual data collected under different switching modes in the multi-stage test process to form a frequency switching test report that includes potential frequency switching faults and collaborative verification results.

[0098] As an optional embodiment, in step S105, error timestamps detected in the actual data collected under random switching mode, descending order switching mode, ascending order switching mode, and interference switching mode are extracted and time-aligned to verify whether there is overlap of error timestamps across modes and operations within a short time interval. If overlap occurs, it is collaboratively confirmed as a transient timing synchronization fault. Furthermore, the physical addresses of memory cells that experience data jumps in different switching modes are extracted and address set cross-analysis is performed. If data jumps are detected in at least two switching modes in any address or address block set, it is collaboratively confirmed as a frequency dependence defect of the DDR memory cell corresponding to the current address or address block. Next, sensitivity analysis is performed on the data jump results collected under ascending and descending order switching modes. If the error density of a specific frequency switching path is higher than the error density of the reverse path, it is collaboratively confirmed that the frequency switching direction is sensitive. Finally, the potential frequency switching faults, timing collaborative verification results, address collaborative verification results, and parameter sensitivity verification results are integrated, and a fault diagnosis matrix and stage reliability indicators for each stage are added to form a frequency switching test report containing qualitative conclusions and quantitative data on DDR memory frequency switching reliability.

[0099] Firstly, timing-based collaborative verification primarily identifies transient synchronization faults across modes through time alignment analysis of error timestamps. An error timestamp refers to the specific time point recorded when a data jump is detected in random switching, descending order switching, ascending order switching, and interference switching modes. Its function is to accurately mark the timing location of the fault. For example, if a data jump is detected at 10.0 milliseconds in random switching mode, this time point is the error timestamp. During operation, all error timestamps in each mode are extracted, and then these timestamps are uniformly mapped to the same time axis for time alignment processing. The purpose is to verify whether there is overlap of error timestamps across modes or operations within a short time interval. For example, if data jumps occur at 10.0 milliseconds in random switching mode and at 10.2 milliseconds in interference switching mode, with a time interval of only 0.2 milliseconds, this constitutes a short-term overlap. In this case, collaborative verification confirms a transient timing synchronization fault. This fault refers to data jumps occurring simultaneously in different switching modes within a similar time period, rooted in timing synchronization abnormalities, which may cause sudden freezing of the Android system when switching screens.

[0100] Next, address-based cross-verification can be used to locate hardware defects through cross-analysis of physical memory addresses. Physical memory addresses are the actual hardware addresses where data is stored in DDR memory, such as 0x80012345 and 0x80012346. Their function is to identify the specific hardware location where data jumps occur. During operation, all physical memory addresses where data jumps occur in each switching mode are extracted, forming address sets corresponding to different modes. Then, cross-analysis of these address sets is performed. The core objective is to determine whether the same address or address block is detected as having data jumps by multiple modes. For example, if the ascending-order switching mode detects a data jump in the address range 0x80012345-0x80012350, and the mixed random switching mode also finds data anomalies in this address range, meaning at least two modes are experiencing failures in the same address block, this is confirmed as a frequency-dependent defect in the DDR memory cell corresponding to the current address or address block. This defect refers to the inherent sensitivity of a specific memory cell to frequency switching actions; regardless of which switching mode involves this cell, it is prone to triggering data jumps, representing a hardware-level stability vulnerability.

[0101] Then, parameter sensitivity verification was performed to perform path sensitivity analysis for ascending and descending switching modes. Sensitivity analysis compares the data jump results in the forward and reverse directions of the same frequency switching path to quantify the fault differences in different directions. Its function is to identify the impact of frequency switching direction on stability. During operation, corresponding frequency switching paths in ascending and descending modes are selected, such as the ascending path 3200MHz→5500MHz and the descending path 5500MHz→3200MHz. The data jump error density of the two paths is calculated separately. The error density is the ratio of the number of erroneous bits to the total number of target data bits. If the error density of a specific frequency switching path is higher than that of the reverse path, for example, the error density of 3200MHz→5500MHz is 0.008, while that of the reverse path is 0.002, then the frequency switching direction is confirmed to be sensitive, indicating that the stability performance of DDR memory differs under different switching directions, and there is a deficiency in timing adaptation or voltage matching in the specific direction.

[0102] Finally, all verification results are integrated to form a complete test report. During operation, previously identified potential frequency switching faults (such as transient timing synchronization faults, frequency-dependent defects, etc.), timing coordination verification results (cross-mode time overlap and statistical data), address coordination verification results (a list of addresses or address blocks with frequency-dependent defects), and parameter sensitivity verification results (comparative data on sensitive frequency switching paths and error density) are systematically integrated. A fault diagnosis matrix (visually presenting the fault distribution of each switching mode in different frequency ranges) and stage reliability indicators for each phase (high, medium, and low levels and corresponding quantitative parameters) are also added, ultimately forming a frequency switching test report. This report includes qualitative conclusions and quantitative data. Qualitative conclusions include whether DDR memory frequency switching reliability is acceptable or whether there are specific directional sensitive defects. Quantitative data includes the number of error timestamp overlaps, the number of frequency-dependent defect addresses, and the error density of each path. Its core function is to provide a comprehensive basis for DDR memory quality screening, preventing faulty memory from entering the market, and providing precise data analysis support for subsequent fault optimization, ensuring the stable operation of Android system functions that rely on DDR access, such as screen switching and multitasking.

[0103] This application's embodiments, through the combination of a multi-stage, multi-mode testing architecture, a dynamic data monitoring mechanism, cross-stage fault correlation analysis, and collaborative verification reports, achieve full-scenario coverage of the DDR memory frequency switching process, real-time error capture, and potential fault root cause localization, significantly improving the reliability and efficiency of frequency switching testing. While ensuring the stable operation of basic memory functions, this application's implementation can effectively identify data jump risks during the switching process and extract implicit correlation faults between different switching modes, contributing to hardware stability verification and fault prevention.

[0104] After introducing the methods of exemplary embodiments of this application, the following references are made. Figure 2 This application describes an exemplary embodiment of a DDR memory frequency switching test apparatus. Specifically, Figure 2The DDR memory frequency switching test device shown is applied to memory frequency testing scenarios. The device includes the following modules: an acquisition module for acquiring multiple preset frequency levels of DDR memory; a construction module for constructing a multi-stage test process including at least two different switching modes, wherein in each test stage, when performing DDR memory data write or read operations, the frequency of the DDR memory is synchronously switched according to the corresponding switching mode; a detection module for generating target data before performing the frequency switching action in each test stage, and acquiring actual data from the DDR memory during the frequency switching action, comparing the target data with the actual data for consistency, and detecting whether the frequency switching process causes data jumps; a fault location module for determining the reliability of the corresponding switching mode of the DDR memory based on the comparison results of each test stage, establishing fault correlations between multiple test stages, and determining the potential frequency switching fault of the DDR memory based on the reliability determination results and fault correlations when a data jump is detected in any test stage; and a verification output module for co-verifying the actual data collected in different switching modes in the multi-stage test process, and generating a frequency switching test report including potential frequency switching faults and co-verification results. The above-described apparatus can implement the steps described in the above-described method embodiments, and the specific implementation methods of each step will not be repeated here.

[0105] After introducing the methods and apparatus of the exemplary embodiments of this application, a terminal device of the exemplary embodiments of this application will be described next. The terminal device can implement the steps described in the above method embodiments, and the specific implementation of each step will not be repeated here.

[0106] It should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Therefore, the protection scope of this application should be determined by the scope of the claims.

Claims

1. A method for testing DDR memory frequency switching, characterized in that, The method includes: Get multiple preset frequency levels for DDR memory; A multi-stage test process with at least two different switching modes is constructed, wherein in each test stage, when performing DDR memory data write or read operations, the frequency of the DDR memory is synchronously switched according to the corresponding switching mode. For each test phase, target data is generated before the frequency switching action is performed, and actual data is obtained from DDR memory during the frequency switching action. The target data and the actual data are compared for consistency to detect whether the frequency switching process causes data jump. Based on the comparison results of each test phase, the reliability of the corresponding switching mode of DDR memory is determined, and a fault correlation is established between multiple test phases. When a data jump is detected in any test phase, the potential frequency switching fault of DDR memory is determined based on the reliability determination results and the fault correlation. Collaboratively verify the actual data collected under different switching modes in the multi-stage testing process to generate a frequency switching test report that includes potential frequency switching faults and collaborative verification results. The construction process includes a multi-stage testing procedure with at least two different switching modes, including: The candidate frequencies in the candidate frequency set are combined in pairs to form candidate frequency sets for different switching modes. Based on the candidate frequency set, frequency switching sequences matching the random switching mode, ascending order switching mode, descending order switching mode, and interference switching mode are generated respectively. When constructing each test phase, a corresponding switching mode and a frequency switching sequence matching the switching mode are assigned to each test phase, and phase configuration information describing the execution logic of each test phase is generated. The phase configuration information includes a target frequency set, access method, and frequency switching trigger strategy. The phase configuration information also includes the execution order of the multi-stage test process so that the frequency switching under different switching modes covers different frequency ranges of DDR memory.

2. The DDR memory frequency switching test method according to claim 1, characterized in that, The process of obtaining multiple preset frequency levels for DDR memory includes: Based on the hardware characteristics of DDR memory, the preset frequency level configuration file is read to obtain multiple frequency levels; During the reading process, multiple frequency levels are categorized according to frequency range, into high-frequency levels, mid-frequency levels, and low-frequency levels; The candidate frequency set is established based on the classification results of multiple frequency ranges.

3. The DDR memory frequency switching test method according to claim 1, characterized in that, The process of assigning a corresponding switching mode and a frequency switching sequence matching the switching mode to each test phase during the construction of each test phase includes: A scenario model is constructed based on the runtime load characteristics of the Android system, wherein the scenario model includes at least one of the following: standby scenario, video playback scenario, and high-load application scenario. Based on the access density, access cycle, and expected frequency jump behavior corresponding to the scene model, a target frequency set matching the scene model is selected from the candidate frequency set; For each test phase, a switching mode adapted to the corresponding scenario model is selected, and a frequency switching sequence matching the switching mode is selected from the frequency switching sequence.

4. The DDR memory frequency switching test method according to claim 3, characterized in that, The generation of phase configuration information describing the execution logic of each test phase includes: The access method for the current testing phase is determined based on the scenario model. The access method includes sequential access, random access, or a mixed access method. A frequency switching triggering strategy is determined based on the switching mode and the target frequency set. The frequency switching triggering strategy includes triggering by access count, triggering by time slice, or triggering by scene feature event. The frequency disturbance intensity of the current test phase is determined based on the load change characteristics of the scenario model, so as to simulate the actual DDR frequency switching behavior under the corresponding scenario in each test phase. The stage configuration information is constructed by combining the target frequency set, the access method, the frequency switching trigger strategy, the frequency disturbance intensity, and the execution order of the multi-stage test process.

5. The DDR memory frequency switching test method according to claim 1, characterized in that, For each test phase, target data is generated before the frequency switching action is performed, and actual data is obtained from DDR memory during the frequency switching action. A consistency comparison is performed between the target data and the actual data to detect whether the frequency switching process causes data jumps, including: Configure data generation rules, use a pseudo-random sequence generator or a fixed pattern generator to generate target data with preset bit features, and map the target data to a specific test address space of DDR memory; Identify the operation type of the current test phase. If the current test phase is the read operation verification phase, then write the target data into the specific test address space in advance, and perform a read operation on the specific test address space to collect actual data during the effective window period of the DDR memory execution frequency switching instruction. If the current test phase is the write operation verification phase, then within the effective window of the DDR memory execution frequency switching instruction, the target data is written into the specific test address space, and after the writing is completed, a readback operation is performed on the specific test address space to collect actual data. Calculate the XOR check value between the target data and the actual data. If the XOR check value indicates that there are inconsistent bits, it is determined that a data jump has been detected, and the frequency switching action, logical address and corresponding error bits that caused the data jump are recorded.

6. The DDR memory frequency switching test method according to claim 5, characterized in that, Whether the detection frequency switching process causes data jumps also includes: A data generation model is constructed based on the Logistic chaotic mapping algorithm. Initial iteration values ​​and bifurcation parameters are configured to iteratively generate a chaotic sequence with nonlinear ergodic characteristics. The chaotic sequence is then quantized and converted into the target data in binary format. The target data is written into the test address segment of DDR memory, wherein the test address segment is mapped to the physical address space of DDR memory through a Hilbert curve trajectory in order to maximize the spatial locality interference of the test data. After the frequency switching action is completed, the actual data in the test address segment is read through direct memory access, and the Hamming distance between the actual data and the target data is calculated segment by segment using a sliding window mechanism. Construct a spatiotemporal distribution map based on Hamming distance, and statistically analyze the peak and mean Hamming distances within a unit sliding window. When a non-zero Hamming distance is detected and it exhibits clustering characteristics on the spatiotemporal distribution map, it is determined that a sudden data jump fault is caused by a frequency switching process.

7. The DDR memory frequency switching test method according to claim 1, characterized in that, The reliability of the corresponding switching mode of DDR memory is determined based on the comparison results of each test phase. Fault correlation is established between multiple test phases. When a data jump is detected in any test phase, the potential frequency switching fault of the DDR memory is determined based on the reliability determination results and the fault correlation, including: For each test phase, the number of frequency switching times, error bit density, and frequency switching path of the data jump detected in each test phase are counted, and the statistical results are compared with the preset reliability threshold to output the phase reliability index of the corresponding switching mode. A fault diagnosis matrix is ​​constructed, wherein the rows of the fault diagnosis matrix correspond to different switching modes and the columns correspond to the frequency range classification of DDR memory; when any switching mode is determined to be of low reliability level in a certain frequency range, a fault indicator is marked at the corresponding position in the fault diagnosis matrix to establish the association between the switching mode and the fault frequency range. Cross-compare the switching modes and frequency ranges with fault indicators in the fault diagnosis matrix; if the data jump only occurs in the ascending or descending switching mode, it is determined to be a fault of insufficient frequency switching timing constraints in a specific direction; if the data jump occurs in the read operation verification phase but not in the write operation verification phase, it is determined to be a fault of insufficient data retention capability during the frequency switching process; if the data jump occurs in all test phases and involves all high, medium and low frequency levels, it is determined to be a fault of insufficient system stability of the DDR memory frequency switching control unit. Based on the correlation analysis of the stage reliability indicators and the fault diagnosis matrix, and combined with the preset location rules, the type and scope of impact of the potential frequency switching faults currently existing in the DDR memory are determined.

8. The DDR memory frequency switching test method according to claim 7, characterized in that, The process involves collaboratively verifying actual data collected under different switching modes during the multi-stage testing process to generate a frequency switching test report that includes potential frequency switching faults and collaborative verification results. Extract the erroneous timestamps detected in the actual data collected under random switching mode, descending switching mode, ascending switching mode and interference switching mode respectively, and perform time alignment to verify whether there is an overlap of erroneous time points across modes and operations within a short time interval. If an overlap occurs, it is collaboratively confirmed as a transient timing synchronization failure. Extract the physical memory addresses where data jumps occur in different switching modes, perform cross-analysis of address sets, and if it is found that data jumps are detected in at least two switching modes in any address or address block set, then it is jointly confirmed as a frequency dependence defect of the DDR memory unit corresponding to the current address or address block. Sensitivity analysis was performed on the data jump results collected in ascending and descending switching modes. If the error density of a specific frequency switching path is higher than the error density of the reverse path, the frequency switching direction is confirmed to be sensitive. The potential frequency switching faults, timing co-verification results, address co-verification results, and parameter sensitivity verification results are integrated, and a fault diagnosis matrix and stage reliability indicators for each stage are added to form a frequency switching test report containing qualitative conclusions and quantitative data on the reliability of DDR memory frequency switching.

9. A DDR memory frequency switching testing device, characterized in that, The device includes the following modules: The acquisition module is used to acquire multiple preset frequency levels of DDR memory; A building module is used to build a multi-stage test process including at least two different switching modes, wherein in each test stage, when performing DDR memory data write or read operations, the frequency of the DDR memory is synchronously switched according to the corresponding switching mode. The construction process includes a multi-stage testing procedure with at least two different switching modes, including: The candidate frequencies in the candidate frequency set are combined in pairs to form candidate frequency sets for different switching modes. Based on the candidate frequency set, frequency switching sequences matching the random switching mode, ascending order switching mode, descending order switching mode, and interference switching mode are generated respectively. When constructing each test phase, a corresponding switching mode and a frequency switching sequence matching the switching mode are assigned to each test phase, and phase configuration information describing the execution logic of each test phase is generated. The phase configuration information includes the target frequency set, access method and frequency switching trigger strategy. The phase configuration information also includes the execution order of the multi-stage test process so that the frequency switching under different switching modes covers different frequency ranges of DDR memory. The detection module is used to generate target data before performing the frequency switching action for each test stage, and to obtain actual data from DDR memory during the frequency switching action, and to compare the target data with the actual data to detect whether the frequency switching process causes data jumps. The fault location module is used to determine the reliability of the corresponding switching mode of DDR memory based on the comparison results of each test stage, establish fault correlation between multiple test stages, and determine the potential frequency switching fault of DDR memory based on the reliability determination results and fault correlation when a data jump is detected in any test stage. The verification output module is used to collaboratively verify the actual data collected under different switching modes in the multi-stage test process, and generate a frequency switching test report that includes potential frequency switching faults and collaborative verification results.

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