Integrator resetting method and device under flexible direct current partition co-frequency control and medium
By acquiring the output value of the integrator in the synchronous frequency control module, determining the reset condition, and reducing the output value at the target rate, the integrator saturation problem under synchronous grid partitioning is solved, automatic reset of flexible DC power is realized, and the regulation efficiency and flexibility of the power system are improved.
Patent Information
- Application Number
- CN202511542182.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-27
- Publication Date
- 2026-01-30
AI Technical Summary
Under synchronous grid partitioning, in-frequency control leads to integrator saturation, which prevents automatic reset and affects the dynamic adjustment of flexible DC power and the controller's response capability.
By obtaining the output value of the integrator in the same frequency control module, it is determined whether the regression start condition is met, and the output value is reduced at the target rate within the target delay time until the regression end condition is met. The regression parameters are optimized using the particle swarm optimization algorithm, and a fault set is constructed to achieve smooth regression.
It enables automatic clearing of the integrator output value after the disturbance subsides, releasing flexible DC transmission capacity and improving the efficiency of power system regulation resource utilization and operational flexibility.
Smart Images
Figure CN121440607A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of frequency control technology, and in particular to an integrator reset method, apparatus and medium under flexible DC zone frequency control. Background Technology
[0002] "Flexible DC zoning" refers to dividing a traditional synchronous power grid into multiple asynchronous or weakly connected regions using flexible DC back-to-back asynchronous interconnection technology. This technology can effectively suppress the problem of excessive short-circuit current, but it lacks rapid power exchange capability between regions. In order to improve the power exchange capability between regions, existing technologies have proposed adding synchronous frequency control to back-to-back flexible DC projects to achieve "quasi-synchronous frequency operation" between asynchronous power grids.
[0003] However, existing research focuses on the main strategy design of frequency-controlled operation, neglecting the design of its exit and reset mechanisms. In asynchronous power grids, both theory and engineering practice have proven that frequency-controlled operation does not suffer from controller saturation. However, if such frequency-bias-based flexible DC power modulation strategies are applied to synchronous power grid partitions (such as synchronous regions interconnected by flexible DC), the situation is significantly different: because the systems on both sides operate synchronously, after the flexible DC power changes, the power flow quickly shifts to the parallel AC channel, and the frequency deviation is almost zero. As a result, after the frequency-controlled operation, the flexible DC power remains at the power level after the operation and cannot automatically reset, leading to the long-term occupation of DC transmission capacity and affecting the controller's subsequent response capability. Summary of the Invention
[0004] The purpose of this invention is to provide a method, apparatus, and medium for integrator resetting under flexible DC zoned synchronous frequency control, which can solve the integrator saturation problem under synchronous grid zoned synchronous frequency control, thereby achieving flexible DC power resetting.
[0005] To achieve the above objectives, embodiments of the present invention provide an integrator regression method under flexible DC partitioned frequency control, comprising: Obtain the output value of the integrator in the frequency synchronization control module; When the output value is saturated, determine whether the target parameter satisfies the regression start condition within the target delay duration; If so, decrease the output value of the integrator at the target rate until the regression termination condition is met.
[0006] As an improvement to the above scheme, the target parameters include the receiving-end frequency difference, the sending-end frequency difference, and the positive sequence voltage of the buses on both sides of the same-frequency control module. Therefore, the reset start condition includes: The difference between the receiving end frequency difference and the sending end frequency difference is located in the dead zone; The positive sequence voltages of both buses on the same frequency control module are greater than the first preset threshold.
[0007] As an improvement to the above scheme, the target delay duration and the target rate are obtained in the following way: Initialize the fault set and the reversion parameter set, wherein the reversion parameter set includes several sets of reversion parameters, each set of reversion parameters consisting of a delay duration and a rate, and the fault set is used to trigger the action of the synchronous control module; The simulation platform was called to perform simulations and obtain the regression effect of each set of regression parameters under each fault. Based on the regression effect, the scoring function is called to calculate the score for each set of regression parameters; With the goal of optimizing the score, the regression parameters are iteratively optimized to obtain the target delay duration and the target rate.
[0008] As an improvement to the above scheme, the regression effect includes the number of stabilization actions, the number of regression actions, and the instability state term, then: The scoring function is obtained by weighted summation of the number of stabilization actions, the number of regression actions, and the instability penalty term. The optimization of the score refers to minimizing the score.
[0009] As an improvement to the above scheme, the iterative optimization of the regression parameters includes: Using the regression parameters of each group as particles and the score as the fitness of each particle, the particle swarm optimization algorithm is used to iteratively optimize the regression parameters.
[0010] As an improvement to the above scheme, the fault set is obtained in the following way: Using the substation busbar as nodes and the impedance value between two adjacent nodes as the edge weight, an undirected weighted graph is constructed. Starting from the node configured with the same frequency control module, search the undirected weighted graph to obtain the first preset number of target nodes with the minimum impedance; Faults are set on the target node to construct a fault set.
[0011] As an improvement to the above solution, setting a fault on the target node includes: Based on the node type of each target node, a fault is set for each target node; wherein, the node type includes at least one of generator node, transmission node and DC converter node.
[0012] As an improvement to the above scheme, the regression termination condition is that the output value of the integrator is within a preset range.
[0013] To achieve the above objectives, embodiments of the present invention also provide an integrator reset device under flexible DC partitioned frequency control, comprising: The data acquisition module is used to acquire the output value of the integrator in the synchronous frequency control module; The regression condition judgment module is used to determine whether the target parameter satisfies the regression start condition within the target delay duration when the output value is saturated. The regression module is used to decrease the output value of the integrator at a target rate until the regression termination condition is met when the target parameter meets the regression start condition within the target delay duration.
[0014] To achieve the above objectives, embodiments of the present invention also provide a computer-readable storage medium, the computer-readable storage medium including a stored computer program, wherein, when the computer program is executed, it controls the device where the computer-readable storage medium is located to perform the integrator regression method under flexible DC partitioned frequency control as described in any of the above embodiments.
[0015] Compared with existing technologies, the integrator reset method, apparatus, and medium provided in this invention under flexible DC zone co-frequency control obtain the output value of the integrator in the co-frequency control module; when the output value is saturated, it is determined whether the target parameter meets the reset start condition within the target delay time; if so, the output value of the integrator is reduced at the target rate until the reset end condition is met. This invention can automatically and smoothly clear the integrator output value to zero after the disturbance subsides, thereby releasing the transmission capacity of flexible DC and enabling it to respond to subsequent disturbances at any time, thus improving the utilization efficiency and operational flexibility of power system control resources. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of a synchronous frequency control module in the prior art; Figure 2 This is a schematic diagram of an improved synchronous frequency control module provided in an embodiment of the present invention; Figure 3 This is a flowchart of an integrator regression method under flexible DC partitioned synchronous control according to an embodiment of the present invention; Figure 4 This is a schematic diagram of optimizing latency and rate based on the PSO algorithm according to an embodiment of the present invention; Figure 5 This is an undirected weighted graph provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the simulation results of the experiment of this invention; Figure 7 This is a schematic diagram of the structure of an integrator resetting device under flexible DC partitioned frequency control according to an embodiment of the present invention. Detailed Implementation
[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0018] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0019] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0020] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0021] Understandably, the frequency-matching control module is a power modulation module whose function is to dynamically modulate the DC transmission power according to the frequency deviation of the AC systems on both sides in order to provide power support for the AC systems on both sides. Furthermore, after the disturbance subsides, the frequency-matching control module needs to safely and reliably shut down to avoid power blockage.
[0022] Specifically, see Figure 1 This is a schematic diagram of a synchronous frequency control module in existing technology. Figure 1 It can be seen that the frequency difference at the sending end Frequency difference between receiving and receiving ends After passing through a filtering stage and a frequency limiting stage, the signal enters the frequency controller. and Indicates the filtering stage. Represents a complex variable. and The time constant is represented by P, and the limiting frequency is ±1 Hz (Hertz). Furthermore, the diagram shows that the frequency controller is a PI (Proportional-Integral) controller, where P represents the proportional element and I represents the integral element. This represents the active power modulation command. For example, the output of the PI controller is shown in the following formula: (1) in, This indicates an active power modulation command; Indicates the proportionality coefficient; Indicates the integral coefficient; This indicates the frequency difference between the sending and receiving ends, and , Indicates rated power. Indicates the measured power at the sending end; This indicates the frequency difference at the receiving end, and , Indicates rated power. Indicates the measured power at the receiving end; Indicates time.
[0023] It is worth noting that existing synchronous frequency control modules do not consider the DC power frequency fluctuation problem caused by measurement errors. Therefore, in some embodiments of the present invention, dead-time control is also introduced to isolate the controller input after disturbance. For example, the mathematical description of dead-time control is as follows: (2) in, This indicates the input quantity of the frequency controller after the dead time is introduced; Indicates the frequency difference between the sending and receiving ends; Indicates the frequency difference at the receiving end; The dead zone threshold can be determined based on measurement error statistics and RTDS (Real Time Digital Simulator) simulation.
[0024] Furthermore, although introducing dead-time control can prevent malfunctions of the proportional element after disturbances, the integral element, characterized by the integration of the input error signal, will still exhibit a saturated state and fail to reach zero. This results in the continuous input of power modulation commands to the main control loop, causing the frequency-synchronized control to remain in a saturated state for an extended period, thus failing to perform its intended function. Therefore, see... Figure 2 This invention introduces a regression strategy based on existing strategies to eliminate DC integral power error after disturbance.
[0025] To achieve the above objectives, embodiments of the present invention provide an integrator regression method under flexible DC partitioned frequency control, comprising: S1. Obtain the output value of the integrator in the synchronous frequency control module; S2. When the output value is saturated, determine whether the target parameter satisfies the regression start condition within the target delay time. S3. If so, decrease the output value of the integrator at the target rate until the regression termination condition is met.
[0026] For example, see Figure 3 This is a flowchart of an integrator reset method under flexible DC zoned frequency control according to an embodiment of the present invention. Specifically, after obtaining the output value of the integrator, saturation detection and reset start condition judgment are required. It is worth noting that saturation detection can be understood as determining whether the integrator needs to be reset, while reset start condition judgment can be understood as determining whether the current power system state is suitable for integrator reset. For example, when the system is unstable or a fault occurs, integrator reset is not suitable.
[0027] For example, during saturation detection, if the output value of the detection integrator reaches the limit value ±Pmax, the output value is determined to be saturated, and a reset condition judgment is performed; if the output value of the detection integrator does not reach the limit value ±Pmax, the output value is determined to be unsaturated, and the following steps are not executed.
[0028] Furthermore, the reset start condition determination refers to determining whether the target parameter continuously meets the reset start condition within the target delay duration. If the target parameter continuously meets the reset start condition within the target delay duration, the integrator is cleared; otherwise, the following steps are not executed. For example, the reset start condition could be that the receiving and sending ends are frequency synchronized and the AC system is fault-free.
[0029] Furthermore, when the integrator is cleared, the integrator output value is decreased at a fixed rate (target rate), as follows: (3) in, Indicates the output value of the integrator Regarding time The derivative of the integrator, which is the rate at which the integrator output value decreases; Represents a symbolic function; Indicates the target rate.
[0030] It is worth noting that the target rate should be less than the maximum power change rate that the system can withstand in order to avoid secondary impacts. For example, the target rate can be 10 MW / s (Megawatt per second).
[0031] Furthermore, when the reset termination condition is met, the integrator's output value is stopped decreasing, i.e., the zeroing process is stopped. For example, the reset termination condition could be that the integrator's output value is within a preset range, where the preset range could be [-2, 2], and the unit is MW (Megawatt). Furthermore, after stopping the zeroing process, the integrator state is also reset.
[0032] As one optional implementation, the target parameters include the receiving-end frequency difference, the sending-end frequency difference, and the positive sequence voltage of the buses on both sides of the same-frequency control module. Therefore, the reset start condition includes: The difference between the receiving end frequency difference and the sending end frequency difference is located in the dead zone; The positive sequence voltages of both buses on the same frequency control module are greater than the first preset threshold.
[0033] For example, in this embodiment of the invention, the regression start condition includes two aspects: first, the difference between the receiving end frequency difference and the sending end frequency difference is located in the dead zone, as shown in the following formula: (4) in, Indicates the frequency difference at the receiving end; Indicates the frequency difference between the sending and receiving ends; This represents the dead zone threshold.
[0034] Furthermore, the reset start condition also includes that the positive sequence voltage of both buses on both sides of the same frequency control module is greater than the first preset threshold. For example, the first preset threshold can be 0.8 pu (per unit).
[0035] It is worth noting that the target parameter must continuously meet the regression start condition within the target delay duration in order to be considered as meeting the regression start condition.
[0036] As one optional implementation, the regression termination condition is that the output value of the integrator is within a preset range.
[0037] Compared to stopping the clearing process only when the integrator reaches zero, this embodiment of the invention stops clearing when the output value falls into a preset range. This avoids the integrator output value from frequently moving around the zero value or even entering a loop and being unable to exit, thus ensuring the normal execution and efficiency of the clearing process.
[0038] Furthermore, in this invention, the values of the regression parameters (target delay duration and target rate) affect the integrator's zeroing effect. Specifically, a rate that is too slow may result in the global modulation output not being zeroed before the near-field stabilization strategy is activated. Conversely, if the global activation direction is opposite to the stabilization strategy activation direction, the cost of the near-field stabilization strategy activation may increase. Therefore, the coordination with the stabilization strategy must be considered when selecting the target rate. Furthermore, a rate that is too fast may cause the frequency difference between the two sides to fluctuate near the dead zone during the zeroing process, resulting in the global modulation repeatedly entering and exiting the zeroing logic.
[0039] Furthermore, if the delay is too short, the system may not have recovered to stability yet. If a rapid reset is performed at this time, it may cause the system to become transiently unstable again. Therefore, the delay duration needs to be set in conjunction with the speed.
[0040] For example, in some implementations, the target delay duration and target rate are determined by offline simulation to ensure the rationality of the regression parameters.
[0041] As one optional implementation, the target delay duration and the target rate are obtained in the following manner: Initialize the fault set and the reversion parameter set, wherein the reversion parameter set includes several sets of reversion parameters, each set of reversion parameters consisting of a delay duration and a rate, and the fault set is used to trigger the action of the synchronous control module; The simulation platform was called to perform simulations and obtain the regression effect of each set of regression parameters under each fault. Based on the regression effect, the scoring function is called to calculate the score for each set of regression parameters; With the goal of optimizing the score, the regression parameters are iteratively optimized to obtain the target delay duration and the target rate.
[0042] For example, a power grid simulation model is built, a time-domain simulator is used, fault-triggered synchronous control actions are set, and the synchronous control actions and the regression effect are evaluated to iteratively optimize the regression parameters.
[0043] As one optional implementation, the regression effect includes the number of stabilization actions, the number of regression actions, and an instability state term, then: The scoring function is obtained by weighted summation of the number of stabilization actions, the number of regression actions, and the instability penalty term. The optimization of the score refers to minimizing the score.
[0044] For example, the scoring function is shown in the following formula: (5) in, Represents the scoring function; This indicates a fault under the current regression parameters. The number of stabilization actions after an event can be calculated based on the stabilization strategy table and simulation curves. This indicates a fault under the current regression parameters. The number of regression actions within the simulation window after the event (also known as the number of times the zeroing strategy exits) can be obtained through time-domain simulation. Indicates a fault The instability penalty term is, for example, determined by the instability state term. The instability state term is used to indicate whether the system experiences transient instability after a fault occurs. If so, the instability penalty term is assigned a positive value; otherwise, the instability penalty term is set to 0. The weight of the number of stabilization actions; The weight representing the number of recursive actions; Indicates the weight of the instability penalty term; This indicates the number of faults in the fault set.
[0045] As one optional implementation, the iterative optimization of the regression parameters includes: Using the regression parameters of each group as particles and the score as the fitness of each particle, the particle swarm optimization algorithm is used to iteratively optimize the regression parameters.
[0046] For a better understanding of the optimization method for regression parameters described in this invention, please refer to [link to relevant documentation]. Figure 4 The following is an explanation through an example. In this example, the optimization algorithm adopts the Particle Swarm Optimization Algorithm (PSO). Specifically, a set of regression parameters is used as the position of a particle to initialize the fault set (combined) and the position and velocity of the particles; further, the faults in the fault set are traversed, the regression strategy is configured according to the regression parameters, and the DSP (Digital Signal Processor) time-domain simulation calculation is performed to obtain the regression effect; further, the above formula (5) is used as the fitness function, and the fitness of each particle is calculated according to the regression effect and the fitness function; then, the particles are selected, crossovered and mutated, and the swarm optimum and individual optimum are updated; then, the position and velocity of the particles are updated, where the velocity is the direction and distance of change in the next iteration; further, it is determined whether the termination condition is met. If yes, the optimal configuration result is output as the target delay time and target rate. If no, the time-domain simulation calculation step is returned to continue iterating on the regression parameters.
[0047] Furthermore, research has revealed that the selection of the fault set affects the optimization results of the regression parameters. For example, if the fault set is too large, faults that are more sensitive to changes in the regression parameters will be overwhelmed by a large number of insensitive faults, resulting in insignificant optimization effects and increased time consumption. Conversely, if the fault set is too small, the generalization ability of the obtained target regression parameters may be poor, leading to poor performance in other faults. Therefore, in some embodiments of this invention, a fault set construction method based on graph search is also proposed.
[0048] As one optional implementation, the fault set is obtained in the following way: Using the substation busbar as nodes and the impedance value between two adjacent nodes as the edge weight, an undirected weighted graph is constructed. Starting from the node configured with the same frequency control module, search the undirected weighted graph to obtain the first preset number of target nodes with the minimum impedance; Faults are set on the target node to construct a fault set.
[0049] For example, see Figure 5 This is an undirected weighted graph provided in an embodiment of the present invention, wherein each substation bus in the power system is a node, and the impedance value between two adjacent nodes is the weight of the edge. Figure 5 In the diagram, red dots represent mother nodes (the flexible DC back-to-back nodes where the same-frequency control module is located), pink dots represent generator nodes, cyan dots represent transmission nodes, and yellow dots represent DC converter nodes. Furthermore, Dijkstra's algorithm can be used to search for the node with the smallest sum of the first n impedances, which is then used as the target node. The target node is then divided into subgraphs, such as... Figure 5 The blue area in the graph. Further, faults are set on the target nodes in the subgraph to construct a fault set.
[0050] As one optional implementation, setting a fault on the target node includes: Based on the node type of each target node, a fault is set for each target node; wherein, the node type includes at least one of generator node, transmission node and DC converter node.
[0051] For example, a trip fault can be set for the generator node, a DC blocking fault can be set for the DC converter node, and a three-phase short-circuit ground fault can be set for the transmission node. Furthermore, if the transmission node is connected to a double-circuit line, a three-phase simultaneous trip fault of the double-circuit line can be set, and a DC blocking fault can be set for the DC converter node.
[0052] Furthermore, to verify the effectiveness of the present invention, simulation verification was conducted based on a real inter-provincial power grid. This power grid structure includes an outer ring AC channel, two back-to-back flexible DC systems, and one point-to-point conventional DC system. In this experiment, the total number of target nodes, n (the first preset number), was set to 30, the fault set contained 31 faults, the dead zone threshold in the regression termination condition was set to 2MW, the dead zone in the same-frequency control module was set to 0.005Hz, and the optimization algorithm used was particle swarm optimization. After 20 iterations, the particle swarm optimization algorithm converged, resulting in a target delay of 25ms (milliseconds) and a target rate of 20MW / s. Further, to verify the rationality of the target rate obtained in this experiment, simulations were also conducted on the DC power changes under different rates during a trip fault. (See [link to relevant documentation]). Figure 6 The figure shows the simulation results of this experiment. As can be seen from the figure, when the target delay time is set to 25ms and the target speed is 20MW / s, the DC power can recover quickly, the oscillation is small, and the system returns to stability.
[0053] See Figure 7 This invention also provides an integrator resetting device 10 under flexible DC partitioned frequency control, comprising: Data acquisition module 11 is used to acquire the output value of the integrator in the synchronous frequency control module; The regression condition judgment module 12 is used to determine whether the target parameter satisfies the regression start condition within the target delay duration when the output value is saturated. The regression module 13 is used to decrease the output value of the integrator at a target rate until the regression termination condition is met when the target parameter meets the regression start condition within the target delay duration.
[0054] The integrator reset device under flexible DC partitioned frequency control provided in this embodiment of the invention can realize all the process steps of the integrator reset method under flexible DC partitioned frequency control described in the above embodiment. The functions and technical effects of each module and unit in the device are the same as the functions and technical effects of the integrator reset method under flexible DC partitioned frequency control described in the above embodiment. The specific implementation method is not described here.
[0055] To achieve the above objectives, embodiments of the present invention also provide a computer-readable storage medium, the computer-readable storage medium including a stored computer program, wherein, when the computer program is executed, it controls the device where the computer-readable storage medium is located to perform the integrator regression method under flexible DC partitioned frequency control as described in any of the above embodiments.
[0056] Compared with existing technologies, the integrator reset method, apparatus, and medium provided in this invention under flexible DC zone co-frequency control obtain the output value of the integrator in the co-frequency control module; when the output value is saturated, it is determined whether the target parameter meets the reset start condition within the target delay time; if so, the output value of the integrator is reduced at the target rate until the reset end condition is met. This invention can automatically and smoothly clear the integrator output value to zero after the disturbance subsides, thereby releasing the transmission capacity of flexible DC and enabling it to respond to subsequent disturbances at any time, thus improving the utilization efficiency and operational flexibility of power system control resources.
[0057] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.
Claims
1. An integrator reset method under flexible DC zoned same frequency control, characterized in that, The method comprises: acquiring an output value of an integrator in a same-frequency control module; when the output value is saturated, determining whether a target parameter meets a reset start condition within a target delay duration; if yes, reducing the output value of the integrator at a target rate until a reset end condition is met.
2. The integrator reset method for flexible DC zoning same-frequency control according to claim 1, characterized in that, The target parameter comprises a receiving-end frequency difference, a sending-end frequency difference, and positive sequence voltages of busbars on both sides of the same-frequency control module, and the reset start condition comprises: a difference between the receiving-end frequency difference and the sending-end frequency difference is within a dead zone; the positive sequence voltages of the busbars on both sides of the same-frequency control module are both greater than a first preset threshold.
3. The integrator reset method for flexible DC zoning same-frequency control according to claim 1, characterized in that, The target delay duration and the target rate are obtained by: initializing a fault set and a reset parameter set, wherein the reset parameter set comprises a plurality of groups of reset parameters, each group of reset parameters comprises a delay duration and a rate, and the fault set is used to trigger the same-frequency control module to act; calling a simulation platform to perform simulation to obtain a reset effect of each group of reset parameters under each fault; based on the reset effect, calling a scoring function to calculate a score of each group of reset parameters; iteratively optimizing the reset parameters to obtain the target delay duration and the target rate, with the optimization of the score as a target.
4. The integrator reset method for flexible DC zoning same-frequency control according to claim 3, characterized in that, The reset effect comprises a number of steady control actions, a number of reset actions, and an instability state item, and the scoring function is obtained by weighted summation of the number of steady control actions, the number of reset actions, and an instability penalty item. The optimization of the score refers to minimization of the score. The iteratively optimizing the reset parameters comprises:
5. The integrator reset method for flexible DC zoning same frequency control of claim 3, wherein, taking each group of reset parameters as a particle, taking the score as a fitness of each particle, and using a particle swarm optimization algorithm to iteratively optimize the reset parameters. The fault set is obtained by:
6. The integrator reset method for flexible DC zoning same-frequency control according to claim 3, characterized in that, constructing an undirected weighted graph with busbars of a substation as nodes and impedance values between adjacent two nodes as weights of edges; starting from a node where the same-frequency control module is configured, searching the undirected weighted graph to obtain target nodes with minimum impedance and a first preset number; setting a fault on the target nodes to construct the fault set. The setting a fault on the target nodes comprises:
7. The integrator reset method for flexible DC zoning same-frequency control according to claim 6, characterized in that, setting a fault for each target node based on a node type of the target node, wherein the node type comprises at least one of a generator node, a transmission node, and a DC conversion node. The reset end condition is that the output value of the integrator is within a preset interval.
8. The integrator reset method for flexible DC zoning same-frequency control according to claim 1, wherein, The method comprises:
9. An integrator reset device under flexible DC zoned co-frequency control, characterized by, a data acquisition module configured to acquire an output value of an integrator in a same-frequency control module; a reset condition determination module configured to determine whether a target parameter meets a reset start condition within a target delay duration when the output value is saturated; a reset module configured to reduce the output value of the integrator at a target rate when the target parameter meets the reset start condition within the target delay duration until a reset end condition is met. The computer readable storage medium comprises a stored computer program, wherein the computer program controls a device where the computer readable storage medium is located to execute the flexible DC partition same-frequency control integrator reset method in any one of claims 1-8 when the computer program runs.
10. A computer-readable storage medium, characterized in that,