P-gate gallium nitride transistor with gate self-protection function

Abstract

The application relates to the technical field of semiconductor transistors, and relates to a P-type gate gallium nitride transistor with a gate self-protection function, which is sequentially provided with a substrate, a buffer layer, a channel layer, a potential barrier layer, a P-type material layer and a dielectric layer from bottom to top; a source electrode and a drain electrode are arranged above the potential barrier layer, and the source electrode and the drain electrode are respectively located on the two sides of the P-type material layer; a two-terminal passive switching device is electrically connected with the dielectric layer, and the two-terminal passive switching device comprises a first metal layer, a special dielectric layer and a second metal layer which are sequentially arranged from bottom to top; the two-terminal passive switching device is arranged above the dielectric layer and jointly forms a gate of the P-type gate gallium nitride transistor together with the dielectric layer, the P-type material layer and the potential barrier layer; or the gate is arranged above the dielectric layer, the first metal layer is electrically connected with the source electrode, and the second metal layer is electrically connected with the gate. The application realizes rapid gate overvoltage self-protection, and effectively prevents irreversible breakdown or degradation of the gate structure due to overvoltage stress.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor transistors, and more specifically, to a P-type gate gallium nitride transistor with gate self-protection function. Background Technology

[0002] Gallium nitride (GaN) materials have shown great potential in the field of power devices due to their excellent properties such as wide bandgap, high critical breakdown electric field and high electron saturation velocity, and can effectively meet the urgent needs of modern electronic systems for high efficiency and high power density.

[0003] However, despite the widespread application of P-type gate gallium nitride transistors (GaN transistors), their maximum gate operating voltage is typically limited to 7-8 V, severely restricting their reliability in higher voltage or high-noise environments. This voltage bottleneck mainly stems from the degradation of the gate / P-GaN interface under high electric field stress and the bombardment effect of hot electrons. To address this issue, recent research has focused on optimizing the gate structure. For example, reducing the Mg doping concentration within the P-GaN layer to lower the peak electric field in the Schottky junction, or performing high-temperature annealing on the P-GaN surface to form a GaON surface enhancement layer to improve resistance to hot electron bombardment, or optimizing the AlGaN barrier layer to reduce the number of hot electrons and thus reduce bombardment of the P-GaN surface. However, while these methods can enhance the gate's breakdown voltage, they still cannot fundamentally overcome the limitations imposed by the hot electron effect and cannot provide stable and reliable protection for the gate structure in the transistor. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of existing technologies in providing stable and reliable protection for the gate structure in transistors, and to provide a P-type gate gallium nitride transistor with gate self-protection function, which realizes fast gate overvoltage self-protection, actively clamps the gate voltage within a safe range, thereby effectively preventing irreversible breakdown or degradation of the gate structure.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0006] A P-type gate gallium nitride transistor with gate self-protection function is provided, comprising:

[0007] The following layers are arranged sequentially from bottom to top: a substrate, a buffer layer, a channel layer, a barrier layer, a P-type material layer, and a dielectric layer; a source and a drain are disposed above the barrier layer, and the source and the drain are respectively located on both sides of the P-type material layer.

[0008] It also includes a passive switching device at both ends, which includes a first metal layer, a special dielectric layer and a second metal layer arranged sequentially from bottom to top. When the voltage applied between the first metal layer and the second metal layer does not reach the turn-on voltage, the passive switching device at both ends maintains a high-resistance state; when the voltage applied between the first metal layer and the second metal layer reaches the turn-on voltage, the conductivity of the special dielectric layer increases nonlinearly, and the passive switching device at both ends switches to a low-resistance state.

[0009] The passive switching devices at both ends are disposed above the dielectric layer and together with the dielectric layer, the P-type material layer and the barrier layer, constitute the gate of the P-type gate gallium nitride transistor; or, the gate is disposed above the dielectric layer, the first metal layer is electrically connected to the source, and the second metal layer is electrically connected to the gate.

[0010] The P-type gate gallium nitride transistor with gate self-protection function of the present invention, during operation, forms a basic structure based on a substrate, buffer layer, channel layer, barrier layer, P-type material layer and dielectric layer arranged sequentially from bottom to top. The source and drain, located above the barrier layer and on both sides of the P-type material layer, are used for current transport. The passive switching device at both ends maintains a high-resistance state under normal gate voltage below its turn-on voltage, without affecting the normal operation of the transistor. Once an abnormal overvoltage occurs at the gate and reaches the turn-on voltage of the switching device, the conductivity of its special dielectric layer increases nonlinearly, causing the device to instantly switch to a low-resistance state. At this time, the overvoltage signal is quickly clamped or discharged. The passive switching device at both ends of the present invention has two design forms: it can be directly placed above the dielectric layer, in which case the gate of the transistor is composed of the dielectric layer, P-type material layer and barrier layer; or it can be designed as an independent component, with its two ends connected to the drain and the gate disposed above the dielectric layer, respectively. This invention integrates a passive switching device with voltage-sensitive switching characteristics into the device, achieving rapid gate overvoltage self-protection. It actively clamps the gate voltage within a safe range, thereby effectively preventing irreversible breakdown or degradation of the gate structure due to overvoltage stress and significantly improving the reliability of the device.

[0011] Furthermore, the special dielectric layer achieves a nonlinear surge in conductivity through abrupt changes in the carrier transport mechanism. This abrupt change manifests as a shift from localized hopping transport to global extended transport of carriers. By causing this abrupt shift in the carrier transport mechanism within the special dielectric layer, from localized hopping to global extension, the resistance decreases dramatically. This provides the core physical basis for achieving a nonlinear surge in conductivity in passive switching devices at both ends, ensuring a rapid transition of the device to the conduction state when the turn-on voltage is reached. This is crucial for achieving reliable and sharp switching functionality and lays a solid physical foundation for rapid gate voltage clamping protection.

[0012] Furthermore, the carrier transport mechanism abruptly changes to an electronic excitation abruptly triggered by the tunneling pure electronic excitation effect. Limiting the carrier transport mechanism to an electronic excitation abruptly triggered by the tunneling pure electronic excitation effect provides a fast and low-energy-consumption switching triggering method. This mechanism mainly relies on quantum tunneling and electronic excitation under the influence of an electric field. Through the quantum tunneling effect, carriers escape from their localized states, independent of thermal accumulation processes, thus resulting in faster switching action, lower response delay, and improved device performance stability and reversibility during repeated switching processes.

[0013] Furthermore, the carrier transport mechanism abruptly transforms into a thermally induced structural abrupt change caused by local structural alterations or the formation of metastable crystalline filaments. Specifying the carrier transport mechanism as a thermally induced structural abrupt change caused by local structural alterations or the formation of metastable crystalline filaments provides a stable and powerful switching triggering path. This mechanism induces reversible changes in the local microstructure of the medium through Joule heating, forming transient conductive filaments. This ensures that the device exhibits a significantly low-resistance state after power-on, thereby enabling more effective and thorough clamping against overvoltage.

[0014] Furthermore, the turn-on voltage of the passive switching device at both ends is higher than the threshold voltage of the P-type gate gallium nitride transistor and lower than the maximum breakdown voltage of the gate. The higher turn-on voltage of the passive switching device prevents accidental triggering of the switching device within the normal gate voltage operating range, thus avoiding interference with the normal gate control function of the transistor. The lower turn-on voltage of the passive switching device ensures that, in the event of abnormal overvoltage, the switching device can be triggered before irreversible breakdown damage occurs in the gate dielectric, and quickly clamp the gate voltage to a safe level, thereby providing active and timely overvoltage protection for the P-GaN gate structure.

[0015] Furthermore, the special dielectric layer is prepared using atomic layer deposition (ALD) or magnetron sputtering. ALD achieves atomic-level precision control and extreme uniformity of the thin film by alternately introducing gaseous precursors; magnetron sputtering achieves efficient film deposition by selecting alloy or ceramic targets and applying appropriate sputtering atmospheres. Both processes can be performed at low temperatures, effectively avoiding thermal damage to the underlying P-type material layer, barrier layer, and other heat-sensitive structures, thus ensuring the overall performance and reliability of the device.

[0016] Furthermore, an ohmic contact is formed between the dielectric layer and the P-type material layer. This ohmic contact minimizes contact resistance and voltage loss at the metal-semiconductor interface, thereby improving the trigger response speed of the passive switching devices at both ends and ensuring the reliability of the gate voltage clamping function.

[0017] Furthermore, the material of the special dielectric layer is one or more combinations of amorphous silicon, oxides, and chalcogenides. The oxides include hafnium dioxide, tantalum oxide, and zinc oxide, while the chalcogenides include germanium selenide compounds, germanium telluride compounds, antimony telluride compounds, arsenic selenide compounds, arsenic sulfide compounds, and germanium antimony telluride compounds. The special dielectric layer must possess the characteristic of undergoing a drastic conductivity state transition under a specific threshold electric field. The aforementioned materials, due to their unique amorphous structure and electron transport behavior, are ideal choices for achieving this steep nonlinear transition.

[0018] Furthermore, the materials of the first metal layer and the second metal layer are one or more combinations of titanium, aluminum, nickel, gold, copper, osmium, palladium, platinum, iridium, and tungsten. Both the first metal layer and the second metal layer are made of metal materials with low resistivity, thereby reducing internal resistance and improving the conductivity of the transistor. At the same time, these materials are commonly used metal materials in semiconductor processing, reducing production costs.

[0019] Furthermore, the thickness of the special dielectric layer is between 10 nm and 30 nm. Limiting the thickness of the special dielectric layer to the range of 10 nm to 30 nm allows for a precise balance between the switching characteristics and reliability of the device. At this thickness, the dielectric layer can accumulate a sufficient electric field to reliably trigger abrupt changes in the carrier transport mechanism, ensuring the realization of the switching function; it also avoids problems such as premature breakdown or excessive leakage current due to excessive thickness, as well as the problem of excessively high turn-on voltage required due to excessive thickness.

[0020] Compared with the prior art, the beneficial effects of the present invention are:

[0021] 1. By using a passive switching device with bidirectional threshold switching characteristics, fast gate overvoltage self-protection is achieved, actively clamping the gate voltage within a safe range, thereby effectively preventing irreversible breakdown or degradation of the gate structure due to overvoltage stress, and significantly improving the reliability of the device.

[0022] 2. The device structure has been optimized, achieving efficient integration of functions and saving area. The vertical stacking method enables the protection function and the transistor body to be integrated on a single chip, rather than simply adding external circuitry. This avoids complex external wiring and additional discrete protection components, significantly saving chip area.

[0023] 3. The feasibility and compatibility of the process are ensured. The substrate, p-type nitride material, dielectric layer, and metal electrode material used are all commonly used materials in GaN device fabrication processes. The fabrication process is also compatible with existing mainstream production lines, eliminating the need to develop entirely new and complex processes, thus lowering the barrier to entry and production costs. Attached Figure Description

[0024] Figure 1This is a schematic diagram of a P-type gate gallium nitride transistor with gate self-protection function.

[0025] Figure 2 A front view of a P-type gate gallium nitride transistor with gate self-protection function;

[0026] Figure 3 This is a schematic diagram of the structure of a P-type gate gallium nitride transistor with gate self-protection function in Example 2.

[0027] In the attached figure: 1. Substrate; 2. Buffer layer; 3. Channel layer; 4. Barrier layer; 5. P-type material layer; 6. Dielectric layer; 7. First metal layer; 8. Special dielectric layer; 9. Second metal layer; 10. Source; 11. Drain; 12. Gate. Detailed Implementation

[0028] The present invention will be further described below with reference to specific embodiments. The accompanying drawings are for illustrative purposes only, representing schematic diagrams rather than actual physical objects, and should not be construed as limiting the scope of this patent. To better illustrate the embodiments of the present invention, some components in the drawings may be omitted, enlarged, or reduced, and do not represent the actual dimensions of the product. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0029] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present patent. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0030] Example 1

[0031] This embodiment is a first embodiment of a P-type gate gallium nitride transistor with gate 12 self-protection function, including a substrate 1, a buffer layer 2, a channel layer 3, a barrier layer 4, a P-type material layer 5 and a dielectric layer 6 arranged sequentially from bottom to top; a source 10 and a drain 11 are arranged above the barrier layer 4, and the source 10 and the drain 11 are respectively located on both sides of the P-type material layer 5.

[0032] It also includes a passive switching device at both ends, which includes a first metal layer 7, a special dielectric layer 8 and a second metal layer 9 arranged sequentially from bottom to top. When the voltage applied between the first metal layer 7 and the second metal layer 9 does not reach the turn-on voltage, the passive switching device at both ends remains in a high-resistance state; when the voltage applied between the first metal layer 7 and the second metal layer 9 reaches the turn-on voltage, the conductivity of the special dielectric layer 8 increases nonlinearly, and the passive switching device at both ends switches to a low-resistance state.

[0033] The passive switching devices at both ends are disposed above the dielectric layer 6, and together with the dielectric layer 6, the P-type material layer 5 and the barrier layer 4, they constitute the gate 12 of the P-type gate gallium nitride transistor.

[0034] like Figure 1 , Figure 2 As shown, the P-type gate gallium nitride transistor with gate 12 self-protection function in this embodiment has a basic structure formed by a substrate 1, a buffer layer 2, a channel layer 3, a barrier layer 4, a P-type material layer 5, and a dielectric layer 6 arranged sequentially from bottom to top. The source 10 and drain 11, located above the barrier layer 4 and on both sides of the P-type material layer 5, are used for current transport. The passive switching devices at both ends maintain a high-resistance state under normal gate voltage conditions that do not reach their turn-on voltage, without affecting the normal operation of the transistor. Once an abnormal overvoltage occurs at the gate 12 and reaches the turn-on voltage of the switching device, the special dielectric layer 8 experiences a nonlinear sharp increase in conductivity, causing the device to instantly switch to a low-resistance state. At this time, the overvoltage signal is quickly clamped or discharged. By integrating the passive switching devices with voltage-sensitive switching characteristics at both ends into the device, this invention achieves rapid gate 12 overvoltage self-protection, actively clamping the gate 12 voltage within a safe range, thereby effectively preventing irreversible breakdown or degradation of the gate 12 structure due to overvoltage stress, and significantly improving the reliability of the device.

[0035] In this embodiment, the special dielectric layer 8 achieves a nonlinear surge in conductivity through abrupt changes in the carrier transport mechanism. This abrupt change manifests as a shift from localized, hopping carrier transport to global, extended transport. By causing this abrupt shift in the carrier transport mechanism within the special dielectric layer 8, from localized to global extension, the resistance decreases dramatically. This provides the core physical basis for achieving a nonlinear surge in conductivity in passive switching devices at both ends, ensuring a rapid transition to the conductive state when the device reaches the turn-on voltage. This is crucial for achieving reliable and sharp switching functionality and lays a solid physical foundation for rapid gate voltage clamping protection.

[0036] In this embodiment, the carrier transport mechanism mutation is an electronic excitation mutation triggered by the tunneling pure electronic excitation effect. Limiting the carrier transport mechanism to an electronic excitation mutation triggered by the tunneling pure electronic excitation effect provides a fast and low-energy-consumption switching triggering method. This mechanism mainly relies on quantum tunneling and electronic excitation under the influence of an electric field. Through the quantum tunneling effect, carriers escape from their local states, independent of thermal accumulation processes, thus resulting in faster switching action, lower response delay, and improved device performance stability and reversibility during repeated switching processes.

[0037] The turn-on voltage of the passive switching device at both ends is higher than the threshold voltage of the P-type gate gallium nitride transistor and lower than the maximum breakdown voltage of the gate 12. The higher turn-on voltage prevents accidental triggering of the switching device within the normal gate voltage operating range, thus avoiding interference with the normal gate control function of the transistor. The lower turn-on voltage ensures that, in the event of abnormal overvoltage, the switching device can be triggered before irreversible breakdown damage occurs in the gate 12 dielectric, quickly clamping the gate voltage to a safe level, thereby providing active and timely overvoltage protection for the P-GaN gate structure.

[0038] The special dielectric layer 8 is prepared using either atomic layer deposition (ALD) or magnetron sputtering. ALD achieves atomic-level precision control and extreme uniformity of the thin film by alternately introducing gaseous precursors; magnetron sputtering achieves efficient film deposition by using alloy or ceramic targets under appropriate sputtering atmospheres. Both processes can be performed at low temperatures, effectively avoiding thermal damage to heat-sensitive structures such as the underlying P-type material layer 5 and barrier layer 4, thus ensuring the overall performance and reliability of the device. When the special dielectric layer 8 is prepared using atomic layer deposition (ALD), the specific preparation process includes: S1, selecting a suitable gaseous precursor according to the design material, placing the substrate 1 structure, which has already undergone the preparation of the P-type material layer 5 and the first metal layer 7, into the reaction chamber of the ALD equipment, and evacuating the chamber to a preset high vacuum; S2, heating the substrate 1 structure and stabilizing it at a preset low-temperature process temperature to avoid damaging the underlying heat-sensitive structure; S3, introducing one or more selected precursors through cyclic alternating pulses, and purging with inert gas after each pulse, causing the precursors to undergo a self-limiting surface chemical reaction on the surface of the first metal layer 7, and depositing layer by layer. By precisely controlling the number of reaction cycles, atomic-level thickness control of the special dielectric layer 8 is achieved. After deposition, if it is necessary to optimize the film composition or charge carrier characteristics, a low-temperature annealing process can be performed to ensure that the special dielectric layer 8 maintains its amorphous state and obtains the required steep conductivity transition function.

[0039] An ohmic contact is formed between dielectric layer 6 and P-type material layer 5. This ohmic contact minimizes contact resistance and voltage loss at the metal-semiconductor interface, thereby improving the trigger response speed of the passive switching devices at both ends and ensuring the reliability of the gate 12 voltage clamping function.

[0040] Example 2

[0041] This embodiment is a second embodiment of a P-type gate gallium nitride transistor with gate 12 self-protection function. This embodiment is similar to the first embodiment, except that, as Figure 3 As shown, the gate 12 is disposed above the dielectric layer 6, the first metal layer 7 is electrically connected to the source 10, and the second metal layer 9 is electrically connected to the gate 12. In this embodiment, the bidirectional threshold switch is used as an independent, monolithically integrated protection element, directly connected in parallel between the gate 12 and the source 10, thereby constructing an intelligent overvoltage clamping unit inside the chip to replace the Zener diode that needs to be externally connected in traditional circuits.

[0042] Under normal operating conditions, i.e., when the gate-source voltage is less than the turn-on voltage of the passive switching devices at both ends, the passive switching devices at both ends are in a high-resistance off state, which is equivalent to a very large resistor connected in parallel between the gate and the source, having almost no effect on the gate 12 circuit. Under overvoltage operating conditions, i.e., when the gate-source voltage is greater than the turn-on voltage of the passive switching devices at both ends, the passive switching devices at both ends are in a low-resistance on state, forming a current discharge path connected in parallel between the gate and the source, thereby preventing the Schottky junction from being subjected to high voltage and thus protecting the gate 12.

[0043] The carrier transport mechanism abruptly transforms into a thermally induced structural abrupt change caused by local structural alterations or the formation of metastable crystalline filaments. This constraint provides a stable and powerful switching triggering path. This mechanism induces reversible changes in the local microstructure of the dielectric through Joule heating, forming transient conductive filaments. This ensures the device exhibits a significantly low-resistance state after power-on, thereby enabling more effective and thorough clamping against overvoltage.

[0044] Example 3

[0045] This embodiment is the third embodiment of a P-type gate gallium nitride transistor with gate 12 self-protection function. This embodiment is similar to Embodiment 1, except that the material of the special dielectric layer 8 is one or more combinations of amorphous silicon, oxides, and chalcogenides. The oxides include hafnium dioxide, tantalum oxide, and zinc oxide, while the chalcogenides include germanium selenide compounds, germanium telluride compounds, antimony telluride compounds, arsenic selenide compounds, arsenic sulfide compounds, and germanium antimony telluride compounds. The special dielectric layer 8 needs to possess the characteristic of undergoing a sharp conduction state transition under a specific threshold electric field. The aforementioned materials, due to their unique amorphous structure and electron transport behavior, are ideal choices for achieving this steep nonlinear transition.

[0046] The first metal layer 7 and the second metal layer 9 are made of one or more of the following materials: titanium, aluminum, nickel, gold, copper, osmium, palladium, platinum, iridium, and tungsten. Both the first metal layer 7 and the second metal layer 9 are made of metal materials with low resistivity, thereby reducing internal resistance and improving the conductivity of the transistor. At the same time, these materials are commonly used metal materials in semiconductor processing, which reduces production costs.

[0047] The thickness of the special dielectric layer 8 is between 10 nm and 30 nm. Limiting the thickness of the special dielectric layer 8 to the range of 10 nm to 30 nm allows for a precise balance between the switching characteristics and reliability of the device. At this thickness, the dielectric layer 6 can accumulate a sufficient electric field to reliably trigger abrupt changes in the carrier transport mechanism, ensuring the realization of the switching function; while avoiding premature breakdown or excessive leakage current due to excessive thickness, as well as the problem of excessively high turn-on voltage required due to excessive thickness.

[0048] The P-type material layer 5 is made of one or more of gallium nitride, aluminum nitride, aluminum gallium nitride, and indium gallium nitride. By limiting the P-type material layer 5 to gallium nitride, aluminum nitride, aluminum gallium nitride, or indium gallium nitride, on the one hand, these P-type materials can form a reliable ohmic contact with the dielectric layer 6, ensuring that when the passive switching devices at both ends are triggered to a low-resistance state, the overvoltage signal can be efficiently coupled to the P-type material layer 5, achieving effective clamping protection for the gate structure. On the other hand, these materials are all common channel materials for P-type gallium nitride devices.

[0049] Substrate 1 can be any one of silicon substrate 1, silicon carbide substrate 1, or sapphire substrate 1. Choosing silicon, silicon carbide, or sapphire substrate 1 takes into account lattice matching, cost advantages, and process compatibility, making it suitable for growing gallium nitride epitaxy.

[0050] The dielectric layer 6 is made of one or more of the following materials: aluminum oxide, silicon oxide, silicon nitride, aluminum nitride, gallium oxynitride, aluminum oxynitride, silicon oxynitride, hafnium oxide, and yttrium oxide. The oxides, nitrides, and oxynitrides used in the dielectric layer 6 all have the insulating properties of hindering diffusion and preventing current flow, so that no leakage current will occur when the gate 12 modulates the electric field.

[0051] In the specific implementation of the above embodiments, the technical features can be combined in any non-contradictory way. For the sake of brevity, not all possible combinations of the above technical features are described. However, as long as the combination of these technical features is not contradictory, it should be considered to be within the scope of this specification.

[0052] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A P-type gate gallium nitride transistor with gate self-protection function, characterized in that, include: The following layers are arranged sequentially from bottom to top: substrate (1), buffer layer (2), channel layer (3), barrier layer (4), P-type material layer (5), and dielectric layer (6); a source electrode (10) and a drain electrode (11) are disposed above the barrier layer (4), and the source electrode (10) and the drain electrode (11) are located on both sides of the P-type material layer (5); It also includes a passive switching device at both ends, which includes a first metal layer (7), a special dielectric layer (8) and a second metal layer (9) arranged sequentially from bottom to top. When the voltage applied between the first metal layer (7) and the second metal layer (9) does not reach the turn-on voltage, the passive switching device at both ends maintains a high resistance state. When the voltage applied between the first metal layer (7) and the second metal layer (9) reaches the turn-on voltage, the conductivity of the special dielectric layer (8) increases nonlinearly, and the passive switching device at both ends switches to a low resistance state. The passive switching devices at both ends are disposed above the dielectric layer (6) and together with the dielectric layer (6), the P-type material layer (5) and the barrier layer (4) constitute the gate (12) of the P-type gate gallium nitride transistor; or, the gate (12) is disposed above the dielectric layer (6), the first metal layer (7) is electrically connected to the source (10), and the second metal layer (9) is electrically connected to the gate (12); the special dielectric layer (8) achieves a nonlinear sharp increase in conductivity through a sudden change in the carrier transport mechanism, the sudden change in the carrier transport mechanism is manifested as a sudden change in the jump transport of carriers from local to global extended transport; the sudden change in the carrier transport mechanism is an electronic excitation sudden change caused by the tunneling pure electron excitation effect or a thermal structural sudden change caused by local structural changes or the formation of metastable crystalline filaments; the turn-on voltage of the passive switching devices at both ends is higher than the threshold voltage of the P-type gate gallium nitride transistor and lower than the maximum breakdown voltage of the gate (12).

2. The P-type gate gallium nitride transistor with gate self-protection function according to claim 1, characterized in that, The special dielectric layer (8) is prepared by atomic layer deposition or magnetron sputtering.

3. The P-type gate gallium nitride transistor with gate self-protection function according to claim 1, characterized in that, An ohmic contact is formed between the dielectric layer (6) and the P-type material layer (5).

4. The P-type gate gallium nitride transistor with gate self-protection function according to any one of claims 1 to 3, characterized in that, The material of the special dielectric layer (8) is one or more of amorphous silicon, oxides, and chalcogenides. The oxides include hafnium dioxide, tantalum oxide, and zinc oxide. The chalcogenides include germanium selenide compounds, germanium telluride compounds, antimony telluride compounds, arsenic selenide compounds, arsenic sulfide compounds, and germanium antimony telluride compounds.

5. The P-type gate gallium nitride transistor with gate self-protection function according to any one of claims 1 to 3, characterized in that, The materials of the first metal layer (7) and the second metal layer (9) are one or more combinations of titanium, aluminum, nickel, gold, copper, osmium, palladium, platinum, iridium and tungsten.

6. The P-type gate gallium nitride transistor with gate self-protection function according to any one of claims 1 to 3, characterized in that, The thickness of the special dielectric layer (8) is 10 nm to 30 nm.

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