Display device

Abstract

[Problem] To provide a display device capable of flexibly adjusting the resolution and display position of display information. [Solution] A display device according to the present disclosure comprises: a pixel array unit in which a plurality of pixels are arranged in a two-dimensional array; a memory that receives an input of image data and temporarily stores the data; an image processing unit that inserts black data into the image data output from the memory and generates output data; a vertical logic circuit that controls a vertical driver that determines a display position of the output data in a vertical direction; and a horizontal logic circuit that controls a horizontal driver that supplies a gradation voltage corresponding to gradation information of the output data to each pixel of the output data in a horizontal direction. An insertion position of black data and a display position in a vertical direction are determined based on a display start position specified by a user.

Description

Technical Field

[0001] This disclosure relates to display devices. Background Technology

[0002] In existing display devices, users can change the display resolution to various types, and for example, after changing the display resolution, display the image at the changed display resolution with a fixed position (such as the center of the image) as the center.

[0003] Reference List

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application No. 2017-97306 Summary of the Invention

[0006] The problem to be solved by the present invention

[0007] As a technology related to display devices, there exists a head-mounted display (HMD) system equipped with an information processing terminal. In this system, when the information processing terminal detects movement of the user's head, it changes the display position of the information on the head-mounted display in a direction that reduces the deviation between the display position and the user's line of sight.

[0008] While there are technologies that allow changing the display position via information processing terminals, there are no technologies that allow flexibly adjusting the display position or resolution of information via display devices.

[0009] Therefore, in response to these problems, this disclosure provides a display device that can flexibly adjust the resolution and display position of the displayed information.

[0010] Solution to the problem

[0011] The display device according to a first aspect of this disclosure includes: a pixel array section, wherein a plurality of pixels are arranged in a two-dimensional array; a memory for receiving and temporarily storing image data as input; an image processing unit for inserting black data into image data output from the memory and generating output data; a vertical logic circuit for controlling a vertical driver, the vertical driver determining the display position of the output data in the vertical direction; and a horizontal logic circuit for controlling a horizontal driver, the horizontal driver providing a grayscale voltage corresponding to the grayscale information of the output data to each pixel of the output data in the horizontal direction, wherein the insertion position of the black data and the display position in the vertical direction are determined based on a display start position specified by a user. Therefore, the display device can flexibly adjust the resolution and display position of the input image data based on the display start position specified by the user.

[0012] Furthermore, in the first aspect, image data is input synchronously with a first clock, which serves as the input clock, and black data is inserted into the image data synchronously with a second clock generated internally by the display device. Therefore, since the black data is inserted synchronously with the clock generated internally by the display device, the display device can set the input clock to a low clock frequency based on the amount of image data, and thus achieve low power consumption.

[0013] Furthermore, in the first aspect, the clock frequency in the second clock is higher than the clock frequency in the first clock. Therefore, since the insertion of black data is synchronized with the clock generated internally by the display device, the display device can set the input clock to a low clock frequency according to the amount of image data, and thus achieve low power consumption.

[0014] Furthermore, in the first aspect, the display device also includes an oscillator or PLL circuit, wherein the second clock is generated by the oscillator or PLL circuit. Therefore, since the insertion of black data is synchronized with the clock generated internally by the display device, the display device can set the input clock to a low clock frequency based on the amount of image data, and thus achieve low power consumption.

[0015] Furthermore, in the first aspect, the vertical driver includes: one or more flip-flops that perform a shift operation; one or more selection switches connected to the one or more flip-flops and providing a selection pulse to the pixel array; and a selector that provides a vertical start pulse to the one or more flip-flops, and the selector includes an nth set of shift registers (n is a natural number) connected to the leading flip-flops among the one or more flip-flops. Therefore, because each set of shift registers in the display device has a configuration where multiple flip-flops share a selector, the increase in circuit size can be suppressed compared to a configuration where each flip-flop has its own selector.

[0016] Furthermore, in the first aspect, the selector to which the vertical start pulse is input and the shift register to which the selection pulse is started are determined based on the display start position. Therefore, since each set of shift registers in the display device has a configuration where multiple flip-flops share the selector, the increase in circuit size can be suppressed compared to a configuration where each flip-flop has its own selector.

[0017] Furthermore, in the first aspect, the vertical driver performs a scanning operation (hereinafter, empty transmission) by transmitting a vertical start pulse relative to the output data in advance, and determines the display start position in the vertical direction. Therefore, the display device can flexibly adjust the resolution and display position of the input image data based on the user-specified display start position.

[0018] Furthermore, in the first aspect, the line segment performing empty transmission becomes a black area. Therefore, the display device can flexibly adjust the resolution and display position of the input image data based on the user-specified display start position.

[0019] Furthermore, in the first aspect, the memory is either a row memory or a frame memory. Therefore, the display device can suppress the increase in circuit size by including a row memory. Moreover, by including a frame memory or the like instead of a row memory, image data input from an external device can be received simultaneously, and subsequent processing can be performed. When outputting from the frame memory, the image processing unit can eliminate the need for partial scanning processing in the vertical direction by inserting black data into the image data. Although a display device equipped with a frame memory has a large circuit size, it increases the freedom of input data format and suppresses power consumption when receiving image data input from an external device.

[0020] Furthermore, in the first aspect, the memory is located on the output side of the data input interface that receives image data as input. Therefore, the display device can flexibly adjust the resolution and display position of the input image data based on a user-specified display start position.

[0021] Furthermore, in the first aspect, the display device receives input from an external device in a specific input data format that includes image data and synchronization signals. Therefore, the display device can set the input clock to a low clock frequency based on the amount of image data, and thus achieve low power consumption.

[0022] Furthermore, in the first aspect, the light-emitting element included in the pixel is an organic EL element or a liquid crystal element. Therefore, the light-emitting element included in the pixel can be a variety of light-emitting elements such as organic EL elements or liquid crystal elements, and in addition, a display device including various pixels can be realized.

[0023] Furthermore, in the first aspect, the vertical driver includes one or more address decoders that receive an address signal indicating the start position of the display in the vertical direction as input to determine the start position of the display. Therefore, compared to the shift register method, by employing an address decoder, the display device can simplify the control of the vertical driver.

[0024] Furthermore, in the first aspect, the horizontal driver fixes the potential state of the signal lines of the pixels in the black area. Therefore, since the processing of the pixel's transistors for the black area is fixed, the display device can eliminate the need for scanning processing by the vertical driver. Moreover, since the input format of the pixel's signal format is not limited to a specific signal format, the degrees of freedom are increased, and furthermore, the speed can be reduced.

[0025] The display device according to a second aspect of this disclosure includes: a pixel array section, wherein a plurality of pixels are arranged in a two-dimensional array; a first horizontal logic circuit for receiving and temporarily storing image data as input; an image processing unit for inserting black data into the image data output from the first horizontal logic circuit and generating output data; a vertical logic circuit for controlling a vertical driver, the vertical driver determining the display position of the output data in the vertical direction; and a second horizontal logic circuit for controlling a horizontal driver, the horizontal driver providing a grayscale voltage corresponding to the grayscale information of the output data to each pixel of the output data in the horizontal direction, wherein the insertion position of the black data and the display position in the vertical direction are determined based on a display start position specified by a user. Therefore, the display device can flexibly adjust the resolution and display position of the input image data based on the user-specified display start position. Furthermore, the display device can insert black data into the image data at a timing other than when outputting from the line memory, and can improve the design freedom of the display device.

[0026] Furthermore, in the second aspect, the insertion of black data into the image data is performed after the output of a timing controller that controls the operation timing of the display controller, which includes vertical and horizontal logic circuits. Therefore, the display device can insert black data into the image data at a timing other than when the line memory is output, thus increasing the design freedom of the display device.

[0027] Furthermore, in the second aspect, the display device receives input from an external device in a specific input data format that includes image data and synchronization signals. Therefore, the display device can set the input clock to a low clock frequency based on the amount of image data, and thus achieve low power consumption.

[0028] Furthermore, in the second aspect, image data is input synchronously with a first clock, which serves as the input clock, and black data is inserted into the image data synchronously with a second clock generated internally by the display device. Therefore, since the black data is inserted synchronously with the clock generated internally by the display device, the display device can set the input clock to a low clock frequency based on the amount of image data, and thus achieve low power consumption.

[0029] Furthermore, in the first aspect, the display device is part of a wearable electronic device. Therefore, the display device can flexibly adjust the resolution and display position of the input image data based on the user-specified display starting position.

[0030] Furthermore, in the first aspect, the electronic device is a head-mounted display including a display device, and the display start position is determined based on the eye position of the user wearing the head-mounted display. Therefore, the display device can flexibly adjust the resolution and display position of the input image data based on the user-specified display start position. Attached Figure Description

[0031] Figure 1 This is a block diagram illustrating an example configuration of a display device according to a first embodiment.

[0032] Figure 2 This is a diagram illustrating a configuration example of a data input interface according to the first embodiment.

[0033] Figure 3 This is a diagram illustrating a configuration example of a timing controller according to the first embodiment.

[0034] Figure 4 This is a diagram illustrating a configuration example of a display controller according to the first embodiment.

[0035] Figure 5 This is a diagram illustrating an example configuration of the display unit according to the first embodiment.

[0036] Figure 6 This is a diagram illustrating an example of pixel configuration according to the first embodiment.

[0037] Figure 7 This is a specified example of the display start position in the display device according to the first embodiment.

[0038] Figure 8 This is an explanatory diagram concerning the horizontal system control in the display device according to the first embodiment.

[0039] Figure 9 This is an explanatory diagram concerning the vertical system control in a display device according to the first embodiment.

[0040] Figure 10 This is an example of a timing diagram in the effective area and black area of ​​a pixel according to the first embodiment.

[0041] Figure 11 This is a first variation of the pixel according to the first embodiment.

[0042] Figure 12 This is a second variation of the pixel according to the first embodiment.

[0043] Figure 13 This is a third modification of the pixels according to the first embodiment.

[0044] Figure 14This is a fourth variation of the pixel according to the first embodiment.

[0045] Figure 15 This is a fifth variation of the pixel according to the first embodiment.

[0046] Figure 16 This is a sixth variation of the pixel according to the first embodiment.

[0047] Figure 17 This is a seventh variation of the pixel according to the first embodiment.

[0048] Figure 18 This is the eighth modification of the pixels according to the first embodiment.

[0049] Figure 19 This is the ninth variation of the pixel according to the first embodiment.

[0050] Figure 20 This is an explanatory diagram regarding the vertical system control in a variation of the display device according to the first embodiment.

[0051] Figure 21 This is a block diagram of a timing controller according to the second embodiment.

[0052] Figure 22 This is an explanatory diagram of the operation in the display device according to the second embodiment.

[0053] Figure 23 This is an explanatory diagram of the operation in a modified example of the display device according to the second embodiment.

[0054] Figure 24 This is a diagram showing the appearance of a head-mounted display, which is an example of an electronic device that applies a display device according to the first embodiment, the second embodiment, and variations thereof.

[0055] Figure 25 This is a diagram showing the appearance of a head-mounted display, which is another example of an electronic device that applies a display device according to the first embodiment, the second embodiment, and variations thereof.

[0056] Figure 26 This is a diagram showing the appearance of a digital camera as an example of an electronic device that applies a display device according to the first embodiment, the second embodiment, and variations thereof.

[0057] Figure 27 This is a diagram showing the appearance of a television device, which is an example of an electronic device that applies a display device according to the first embodiment, the second embodiment, and variations thereof.

[0058] Figure 28This is a diagram showing the appearance of a smartphone, which is an example of an electronic device that uses a display device according to the first embodiment, the second embodiment, and variations thereof.

[0059] Figure 29 This is a diagram showing an example configuration of a vehicle that uses a display device according to the first embodiment, the second embodiment, and variations thereof.

[0060] Figure 30 This is a diagram showing the appearance of a liquid crystal projector, which is an example of an electronic device that applies a display device according to the first embodiment, the second embodiment, and variations thereof. Detailed Implementation

[0061] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0062] (First Implementation)

[0063] Figure 1 This is a block diagram illustrating an example configuration of a display device according to a first embodiment.

[0064] Display device 1 is a device for displaying images and includes a data input interface 11, a timing controller 12, a display controller 13, a display unit 14, an oscillator 15, a serial interface 16, a register 17, and an electronic fuse 18. Furthermore, display device 1 is connected to an external device 2 via a MIPI display serial interface (DSI) 20”.

[0065] Display unit 14 includes a plurality of pixels arranged in a two-dimensional array. Hereinafter, a group of pixels arranged in the horizontal direction is referred to as a "row", and a group of pixels arranged in the direction perpendicular to the rows is referred to as a "column".

[0066] The data input interface 11 receives serially transmitted image data, etc., as input from the external device 2 of the display device 1, under the timing of an external clock. This image data is data intended for display on the display unit 14, and for example, the input includes still image data or moving image data consisting of multiple images in chronological order. The display device 1 receives the input from the external device in a predetermined input data format that includes image data and synchronization signals, and the data input interface 11 converts the serial display data into parallel data.

[0067] Furthermore, the data input interface 11 generates vertical and horizontal synchronization signals, and provides these signals, along with parallel data, to the timing controller 12. Here, the vertical synchronization signal indicates the timing for displaying image data, and the horizontal synchronization signal indicates the timing for displaying lines. The MIPI DSI interface 20, clock control unit 21, synchronization signal generation unit 22, serial-to-parallel conversion unit 23, command interface 24, and line memory 25 constituting the data input interface 11 will be described later.

[0068] The timing controller 12 controls the timing of the operation of the display controller 13. The timing controller 12 generates pixel data from parallel data and provides the pixel data along with a start signal to the display controller 13. Hereinafter, the start signal in the horizontal direction is referred to as the horizontal start pulse HST, and the start signal in the vertical direction is referred to as the vertical start pulse VST. The clock generation unit 31, timing generation unit 32, image processing unit 33, and brightness control unit 34 constituting the timing controller 12 will be described later.

[0069] The display control unit 13 controls each drive circuit of the display unit 14. The display controller 13 synchronizes with the horizontal start pulse HST and provides pixel data to the horizontal driver 53. The pixel data includes grayscale information representing the grayscale of each color, such as red (R), green (G), and blue (B).

[0070] Furthermore, the display controller 13 synchronizes with the vertical start pulse VST to control the vertical driver 52. The vertical driver 52 sequentially drives pixel rows under the control of the display controller 13. The vertical logic circuit 41 and horizontal logic circuit 42 constituting the display controller 13 will be described later.

[0071] The display unit 14 drives the vertical driver 52 and the horizontal driver 53 to display pixel data based on the control of the display controller 13. The pixel array 51, the vertical driver 52, the horizontal driver 53, and the gamma correction circuit 54 constituting the display unit 14 will be described later.

[0072] Oscillator 15 generates a clock internally in display device 1. Display device 1 synchronizes with the internally generated clock to perform processing on image data. For example, oscillator 15 can be a ring oscillator.

[0073] Serial interface 16 performs serial communication with register 17 and various function blocks. Serial interface 16 can perform, for example, three-wire serial communication with register 17.

[0074] The electronic fuse 18 is an electronic fuse capable of storing characteristic value information specific to the display of the display device 1, and has one-time programmable (OTP) function.

[0075] Figure 2 This is a diagram illustrating a configuration example of a data input interface according to the first embodiment.

[0076] The data input interface 11 includes a MIPI display serial interface (DSI) interface 20, a clock control unit 21, a synchronization signal generation unit 22, a serial-to-parallel conversion unit 23, a command interface 24, and a line memory 25.

[0077] The MIPI DSI interface 20 receives image data and synchronization signals that have been serially transmitted via MIPI DSI communication from an external device 2 connected via another MIPI DSI interface 20' in a predetermined input data format. This example shows communication via MIPI DSI communication, but other communication methods can also be used to receive input such as image data. In this embodiment, the display device 1 can receive image data and the like as input in a predetermined input data format, regardless of the initial display position. The clock control unit 21 controls the timing control unit 12 to cause the clock generation unit 31 (described later) to generate clock signals during the display of image data. The synchronization signal generation unit 22 generates horizontal and vertical synchronization signals based on the image data. Furthermore, the serial-to-parallel conversion unit 23 converts serial image data into parallel data. The command interface 24 receives data as input from the register 17, for example, via serial communication. A row memory 25 is provided on the output side of the data input interface 11, receives a row of image data as input, and temporarily stores the image data. The row memory 25 is an example of a memory. When the stored image data is output from the line memory 25, black data is inserted, thus enabling flexible display positioning in the horizontal direction. Details of the line memory 25 will be described later.

[0078] Figure 3 This is a diagram illustrating a configuration example of a timing controller according to the first embodiment.

[0079] The timing controller 12 includes a clock generation unit 31, a timing generation unit 32, an image processing unit 33, and a brightness control unit 34.

[0080] The clock generation unit 31 generates horizontal and vertical clock signals with predetermined frequencies under the control of the clock control unit 21. The frequencies of these clock signals are higher than the frequency of the horizontal synchronization signal. The clock generation unit 31 provides these clock signals to the display controller 13.

[0081] The timing generation unit 32 generates a vertical start pulse VST and a horizontal start pulse HST based on the vertical synchronization signal and the horizontal synchronization signal provided by the synchronization signal generation unit 22, and provides the vertical start pulse VST and the horizontal start pulse HST to the display controller 13.

[0082] The image processing unit 33 performs various image processing operations on the parallel data provided from the serial-to-parallel conversion unit 23 via the row memory 25. For example, the image processing unit 33 performs resolution conversion processing, interpolation of color information (W, etc.) for each pixel, and so on. The image processing unit 33 generates pixel data for each pixel through image processing and outputs the pixel data as output data.

[0083] Furthermore, in this embodiment, an example will be described whereby the image processing unit 33 performs the insertion of black data, which will be described later, when data is output from the line memory 25. For example, a function block for a black data insertion unit in the data input interface 11 can be provided, through which the insertion of black data can be implemented.

[0084] The brightness control unit 34 performs operations and controls the brightness modulation speed to steplessly adjust the brightness, and controls the gamma correction circuit 54.

[0085] Figure 4 This is a diagram illustrating a configuration example of a display controller according to the first embodiment.

[0086] The display controller 13 includes a vertical logic circuit 41 and a horizontal logic circuit 42.

[0087] The vertical logic circuit 41 is synchronized with the vertical start pulse VST and controls the vertical driver 52. The horizontal logic circuit 42 is synchronized with the horizontal start pulse HST and controls the horizontal driver 53.

[0088] Figure 5 This is a diagram illustrating an example configuration of the display unit according to the first embodiment.

[0089] The display unit 14 includes a pixel array 51, a vertical driver 52, a horizontal driver 53, and a gamma correction circuit 54.

[0090] Pixel array 51 includes a plurality of pixels arranged in a two-dimensional array. Display unit 14 can perform color display, and a pixel used as a unit for forming a color image includes a plurality of sub-pixels. For example, a pixel includes three sub-pixels: a sub-pixel that emits red light, a sub-pixel that emits green light, and a sub-pixel that emits blue light. By appropriately controlling the emission of each pixel, the desired image is displayed in pixel array 51. The detailed circuit configuration of the pixels will be described later.

[0091] The combination of subpixels constituting a pixel is not limited to three colors. For example, to expand the color reproduction range, a pixel can be configured by adding at least one subpixel that emits complementary light. Furthermore, the display device 1 can also be configured such that there are no subpixels and one pixel array 51 corresponds to one pixel. Moreover, the display device 1 does not necessarily need to perform color display and can be configured to perform monochrome display.

[0092] Each pixel is connected to signal lines WSL and SGL. Each signal line SGL is connected to the horizontal driver 53, and each signal line WSL is connected to the vertical driver 52. Furthermore, pixel signals are provided to the pixel via signal line SGL, and selection pulses SEL are provided to the pixel via signal line WSL. The selection pulse SEL is a signal used to drive a predetermined row.

[0093] The gamma correction circuit 54 adjusts the grayscale voltage and performs gamma correction according to the characteristics of the display device 1. Controlled by the brightness control unit 34, the gamma correction circuit 54 reads the setting value for adjusting the brightness level stored in the register 17 and generates grayscale voltages representing the grayscale. For example, in the case of controlling grayscale at 256 levels, 256 grayscale voltages with different values ​​are generated. The gamma correction circuit 54 provides these grayscale voltages to the level driver 53.

[0094] The horizontal driver 53 selects a grayscale voltage corresponding to the grayscale information of the pixel data for each pixel in the selected row and provides the grayscale voltage as a pixel signal. The vertical driver 52 sequentially drives the rows of the pixel array 51 under the control of the display controller 13. As the horizontal driver 53, various configurations of the horizontal driver 53, such as voltage follower type or RAMP DAC type, can be adopted.

[0095] Figure 6 This is a diagram illustrating an example of pixel configuration according to the first embodiment.

[0096] Each of the above sub-pixels corresponds to Figure 6 The pixel PIX in the image. Figure 6 This is a circuit diagram illustrating an example of the circuit configuration of a pixel PIX in an organic EL display device 1, such as the pixel PIX according to this embodiment. For example, a light-emitting element EL is used as the light-emitting part of the pixel PIX. The light-emitting element EL is an example of a current-driven electro-optic element whose luminous brightness changes according to the value of the current flowing through the device.

[0097] like Figure 6 As shown, a pixel PIX includes a light-emitting element (EL) and a driving circuit that drives the EL by applying current to it. The cathode electrode of the EL is connected to a cathode potential Vcath node shared by all pixel PIXs.

[0098] The driving circuit for driving the light-emitting element EL includes transistors T1 to T4 and capacitors C1 and C2. Here, transistors T1 to T4 are configured as P-channel transistors.

[0099] Transistors T1 through T4 are also referred to as the driving transistor, sampling transistor, light-emitting control transistor, and reset transistor, respectively. Furthermore, capacitors C1 and C2 are also referred to as the storage capacitor and auxiliary capacitor, respectively.

[0100] Transistor T2's gate is connected to signal line WSL, its source to signal line SGL, and its drain to the gate of transistor T1 and capacitor C1. One end of capacitor C1 is connected to the drain of transistor T2 and the gate of transistor T1, and the other end is connected to capacitor C2, the drain of transistor T3, and the source of transistor T1. Transistor T3's gate is connected to signal line DSL, its source to power line VCCP, and its drain to the drain of transistor T1. Transistor T1's gate is connected to the drain of transistor T2 and one end of capacitor C1, its source to the drain of transistor T3, the other end of capacitor C1, and capacitor C2, and its drain to the anode of light-emitting element EL and the source of transistor T4. Transistor T4's gate is connected to signal line AZSL, its source to the source of transistor T1 and the anode of light-emitting element EL, and its drain to power line VSS.

[0101] The signal line DSL is a signal line that receives a light emission control signal as input to control the light emission element EL to emit light or not emit light, and the signal line AZSL is a signal line that receives a drive signal as input to control the light emission element EL so that it does not emit light during the non-light emission period of the light emission element EL.

[0102] Since transistors T1 to T4 are switching transistors used as switching elements, they are not limited to P-channel transistors. For example, transistors T1 to T4 can be N-channel transistors, or they can be configured to have a mixture of P-channel and N-channel transistors.

[0103] In the pixel PIX with the above circuit configuration, transistor T1 is connected in series with the light-emitting element EL. Transistor T2 samples the grayscale voltage supplied from the horizontal driver 53 and writes the grayscale voltage into capacitor C1. Transistor T3 controls the light-emitting element EL to emit light or not. Transistor T4 is connected to the power supply line VSS on the low-potential side and initializes the voltage of the anode of the light-emitting element EL.

[0104] Capacitor C1 holds the written grayscale voltage through the sampling operation of transistor T2. Transistor T1 drives the light-emitting element EL by causing a drive current corresponding to the holding voltage of capacitor C1 to flow through the light-emitting element EL.

[0105] Capacitor C2 suppresses the change in the source potential of driving transistor T1 when writing grayscale voltage, and sets the voltage between the gate and drain of driving transistor T1 to the threshold voltage of driving transistor T1.

[0106] In the following text, an example will be described of how the display device 1 adjusts the resolution of the image data as input data, and how the user flexibly adjusts the display position of the image data.

[0107] Figure 7 This is a specified example of the display start position in the display device according to the first embodiment.

[0108] In the following text, X and Y coordinates will be used to describe the positions on the pixel array 51. In this example, the horizontal direction of the display device 1 is defined as the X direction, and its vertical direction is defined as the Y direction. Furthermore, the upper left corner of the pixel array 51 is set as the origin.

[0109] This figure illustrates an example where display device 1 is implemented as a head-mounted display, and the user specifies the display position of image data. Besides being implemented as a head-mounted display, display device 1 can also be implemented as part of various electronic devices, such as other wearable electronic devices using technologies such as AR or VR, television devices, or smartphones. The user specifies the starting coordinates for display on the head-mounted display. Figure 7 A to Figure 7 In the example of C, in the display starting coordinates, with the coordinates (X, Y) = (0, 0) at the top left of pixel array 51, and the rightward direction in the diagram being the +X direction, and the downward direction being the +Y direction, the display starting position is represented as (X, Y) = (H_SHIFT, V_SHIFT). The values ​​of H_SHIFT and V_SHIFT are stored, for example, in register 17 and communicated using serial interface 16. These values ​​can also be stored in a memory area other than register 17 (not shown).

[0110] In addition, for example, when a user wearing a head-mounted display moves their gaze, the starting coordinates of the display can be specified by automatically assigning the starting position of the head-mounted display based on the amount of change in the gaze position.

[0111] Figure 7 A shows an example where the upper left corner of the user-specified pixel array 51 is used as the starting position for display. Furthermore, Figure 7 B shows an example of a position near the center of a user-specified pixel array as the starting position for display. Furthermore, Figure 7 C shows an example of a user-specified location outside pixel array 51 (in this example, corresponding to coordinates (-X, -Y)) as the starting position for display. Figure 7 B and Figure 7 In case of truncation in the image data to be displayed in C, the display device 1 displays a portion of the image data that can be displayed within the pixel array 51, based on the display start position. If the user specifies a position outside the pixel array 51 as the display start position and a portion of the image data cannot be displayed on the pixel array 51, the display device 1 may not display the image data. In the following text, "user-specified display start position" includes cases where the user specifies the display start position through an input interface (not shown) and cases where the display device 1 automatically specifies the display start position from the user's line of sight.

[0112] In addition, users can specify the display resolution. The dimensions of the user-specified display resolution will be described as H_ACTIVE in the X direction and V_ACTIVE in the Y direction.

[0113] Figure 8 This is an explanatory diagram concerning the horizontal system control in the display device according to the first embodiment.

[0114] In this figure, the horizontal system control of the display device 1, which displays image data starting from a user-specified display start position, is described. Furthermore, for this description, the size of the pixel array 51 is set to (X, Y) = (X_MAX, Y_MAX), and the resolution of the image data is set to (X, Y) = (H_ACTIVE, V_ACTIVE). Additionally, H_ACTIVE and V_ACTIVE are also used, for example, as values ​​representing the effective period of data in the vertical and horizontal directions of the display device 1. For example, H_ACTIVE and V_ACTIVE are stored in register 17.

[0115] Display device 1 receives image data as input data in MIPI DSI interface 20 at timings of the input clock. Furthermore, display device 1 converts the serial data into parallel data in serial-to-parallel conversion unit 23. The image data converted to parallel data is stored in row memory 25 at timings of the input clock. Row memory 25 stores one row of image data at a time.

[0116] The display device 1 uses an oscillator 15 to generate a clock, and the timing of the internally generated clock provides data stored in the row memory 25 to the timing controller 12. The input clock may have a low clock frequency corresponding to the amount of image data. Furthermore, when the image processing unit 33 inserts black data as described below and generates output data, the internally generated clock uses a higher clock frequency than the input clock to improve image resolution. The insertion of black data is performed at the timing of the internally generated clock. For example, the internally generated clock may be set to the minimum necessary clock frequency for performing scanning processing on the output data using the vertical driver 52 and the horizontal driver 53. The input clock is an example of a first clock, and the internally generated clock is an example of a second clock. The first clock may be generated not only by the oscillator 15 but also by another oscillation circuit (such as a PLL circuit).

[0117] When outputting a line of image data from the line memory 25, the image processing unit 33 inserts black data between X=0 and X=H_SHIFT. Furthermore, when outputting image data, the image processing unit 33 also inserts black data between X=H_SHIFT+H_ACTIVE and X=H_MAX. Moreover, the image processing unit 33 inserts black data for each line of image data in a similar manner. Therefore, the display device 1 can insert black data at positions other than the display position of each line of image data, thereby enabling flexible adjustment of the display position in the horizontal direction.

[0118] Here, as a reference Figure 8 In the description of horizontal system control, display device 1 receives image data as input from external device 2 at a low-speed input clock corresponding to the amount of image data. Furthermore, when outputting from line memory 25, image processing unit 33 inserts black data at predetermined positions and outputs image data at an internally generated clock that is faster than the input clock. Figure 8 In example A, image processing unit 33 inserts black data up to the position H_SHIFT as one line of output data. Furthermore, after inserting black data, image processing unit 33 inserts image data as valid data. Then, after inserting valid data (at the position H_SHIFT+H_ACTIVE), image processing unit 33 again inserts black data up to the position H_MAX. Image processing unit 33 repeats this operation in the horizontal direction corresponding to the number of lines V_ACTIVE. In this way, the insertion position of black data is determined based on the display start position specified by the user.

[0119] Next, we will refer to Figure 8 B describes the level of system control. Figure 8 Figure B illustrates the image data at the truncation position of pixel array 51. In this figure, H_SHFT relative to... Figure 8 In the example where position A is on the +X direction side, the image data cannot be fully contained in the horizontal direction. In this case, compared to... Figure 8 Similarly, in case A, when outputting from row memory 25, image processing unit 33 inserts black data up to the H_SHFT position. Furthermore, after inserting the black data, image processing unit 33 inserts image data as valid data. In this case, image processing unit 33 inserts image data from the H_SHIFT position to the H_MAX position. Image processing unit 33 repeats this operation in the horizontal direction corresponding to the row number of V_ACTIVE. The insertion of black data is performed based on the data enable signals generated from H_SHFT and H_ACTIVE.

[0120] Figure 9 This is an explanatory diagram regarding the vertical system control in the display device according to the first embodiment.

[0121] Figure 9 A portion of the vertical driver 52 of the display device 1 is shown. In this figure, vertical system control for allowing the display device 1 to display image data starting from a user-specified display start position will be described.

[0122] In this embodiment, the vertical driver 52 is a shift register type comprising a shift register 43 with multiple flip-flops 45 cascaded together, and includes one or more selectors 44 on the input side of the pilot flip-flop 45 for providing a vertical start pulse to the multiple flip-flops. In this embodiment, the vertical driver 52 is configured such that four flip-flops 45 share a single selector 44. Furthermore, the flip-flops 45 are set in a number corresponding to the number of pixels in the vertical direction, and for example, in the case where the pixel array 51 includes 100 pixels in the vertical direction, the same number of flip-flops 45 are included.

[0123] In this embodiment, the vertical driver 52 performs a shift operation by synchronizing the vertical start pulse VST with the vertical clock signal. At this time, the vertical driver 52 performs a blank transfer of the scan operation by advancing the transmission of the vertical start pulse VST relative to the output data. Furthermore, the display start position in the vertical direction is determined by the blank transfer, which is called a partial scan in the vertical direction. A blank transfer is performed for the rows from Y=0 to V_SHIFT. For rows where the vertical start pulse VST is advanced relative to the output data, a blank transfer is performed, and therefore, the selection pulse SEL, which is the output from the trigger 45, is not provided to the pixel array 51 via the selection switch 46, and the output data is not displayed on the pixel array 51. Therefore, these rows become black areas.

[0124] On the other hand, the vertical start pulse VST is sequentially transmitted to each trigger 45 through a shift operation. The display device 1 outputs output data starting from the row whose timing of the data output from the vertical driver 52 matches the vertical start pulse VST. The horizontal driver 53 selects a grayscale voltage corresponding to the grayscale information for each pixel PIX in the selected row and provides the grayscale voltage as a pixel signal to the pixel array 51, and the display device 1 displays the output data on the pixel array 51. In this way, the vertical driver 52 determines the display position in the vertical direction.

[0125] Therefore, under the control of the vertical logic circuit 41, the vertical driver 52 can shift the display position of the output data to the row (V_SHIFT position) ahead of the vertical start pulse VST relative to the image data, thereby enabling flexible adjustment of the display position in the vertical direction.

[0126] exist Figure 9 In this embodiment, the vertical driver 52 is configured during blanking such that four flip-flops 45 share a single selector 44, rather than connecting the selector 44 to all flip-flops 45. In the following, the configuration in which one or more flip-flops 45 are cascaded, the selector 44 is connected to the pilot flip-flop 45, one or more flip-flops 45 share the selector 44, and a selection switch 46 is connected to each of the one or more flip-flops 45 is referred to as a shift register set. In this embodiment, the vertical driver 52 includes an nth set of shift registers (n is a natural number) and performs adjustments to the display position for each set of shift registers. Figure 9 The top view shows all of the first set of shift registers and a portion of the second set of shift registers.

[0127] exist Figure 9 In this circuit, the vertical driver 52 receives the V_SHIFT[i:j] signal as input from the vertical logic circuit 41 (where i and j are natural numbers). The V_SHIFT[i:j] signal is used to determine the display position in the vertical direction. For example, in the case where the V_SHIFT[i:j] signal contains an 11-bit binary number, the high 9 bits determine the position of the vertical start pulse VST input selector 44, while the low 2 bits determine the position of the selector switch 46 within the starting and ending group.

[0128] The vertical start pulse VST input to the selector 44 of a specific group is sequentially transmitted to the subsequent trigger 45 via a shift operation. In this way, the selector 44 for the vertical start pulse input is determined based on the display start position specified by the user, and in addition, the shift register 43 within the group that begins to provide the selection pulse to the pixel array 51 is determined.

[0129] exist Figure 9In this example, the vertical driver 52 receives the V_SHIFT[i:j] signals from the 11-bit binary number of the vertical logic circuit 41 as input, and determines the set of shift registers 43 to which the vertical start pulse VST is input via V_SHIFT[10:2] (corresponding to the high nine bits). Furthermore, the vertical driver 52 also determines the position of the selector switch 46 within the starting and ending groups via V_SHIFT[1:0] (corresponding to the low two bits). For example, if the V_SHIFT[i:j] signals are represented as “000_0000_0010”, V_SHIFT[10:2] corresponds to “000_0000_00”, and V_SHIFT[2:0] corresponds to “10”. In this example, “000_0000_00” represents the shift register 43 of the topmost group of the vertical driver 52, and “10” represents the third switch in that group starting from the top. In this configuration, the vertical driver 52 determines to perform an empty transfer from the top to the first row (out[0]) and the second row (out[1]) in the row direction, and outputs data from the third row (out[3]) starting from the top. In this way, the display position in the vertical direction is determined based on the display start position specified by the user.

[0130] The number of flip-flops 45 included in a group is not limited to four. For example, a group of shift registers 43 may include two or eight flip-flops 45, and a group may include any number of flip-flops 45.

[0131] Display device 1 can be provided with a frame memory for storing screen image data instead of line memory 25. By replacing line memory 25 with a frame memory, display device 1 can receive image data as input from external device 2 at once and perform subsequent processing. When outputting from frame memory, image processing unit 33 can eliminate the need for partial scanning processing in the vertical direction by inserting black data into the image data. Although display device 1 with frame memory has a large circuit scale, it can increase the freedom of input data format and suppress power consumption when receiving image data input from external device 2. Furthermore, display device 1 can be provided with a partial frame memory for storing multiple lines of image data instead of line memory 25.

[0132] Figure 10 This is an example of a timing diagram of the effective area and black area of ​​a pixel according to the first embodiment.

[0133] Figure 10 A is an example of a timing diagram showing the effective area of ​​pixels (PIX). Specifically, Figure 10A is a timing diagram showing the potential changes of signal line WSL, signal line DSL, and signal line AZSL. The valid area is the area where valid data is output.

[0134] It should be noted that because transistors T1 to T4 are P-channel type, when signal lines WSL, DSL, and AZSL are at a low potential, these transistors are in the ON state, i.e., in the conducting state, and when signal lines WSL, DSL, and AZSL are at a high potential, these transistors are in the OFF state, i.e., in the non-conducting state.

[0135] use Figure 10 In configuration A, before the emission period, the pixel PIX initializes the voltage of the anode of the light-emitting element EL by setting the signal line AZSL to the ON state, thus turning on transistor T4. After initializing the voltage of the anode of the light-emitting element EL, the pixel PIX sets transistor T4 to the OFF state. During emission, the pixel PIX turns on transistor T2 (signal line WSL is ON), and therefore the voltage across capacitor C2 is set based on the pixel signal supplied from signal line SGL. When signal line DSL is ON, transistor T3 is ON. During the period when transistor T3 is ON, transistor T1 generates a current corresponding to the voltage across capacitor C2 flowing to the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor T1.

[0136] Next, during the lighting period, the pixel PIX sets the signal line DSL to the off state and the signal line AZSL to the on state, thereby cutting off the current to the light-emitting element EL and initializing the voltage of the anode of the light-emitting element EL.

[0137] Figure 10 B is an example of a timing diagram showing the pixel PIX that displays the black area. (Compared to...) Figure 10 A is similar. Figure 10 B is a timing diagram showing the changes in the potential of signal line WSL, signal line DSL, and signal line AZSL.

[0138] In the black area, the potential states are fixed, wherein signal line WSL is set to the off state, signal line DSL is set to the off state, and signal line AZSL is set to the on state (i.e., connected to the on state). Figure 10 (Similar processing during the lighting period in A). Therefore, the display device 1 eliminates the need for scanning processing of the vertical logic circuit 41, and the signal format input to the pixel PIX is not limited to a specific format, thereby increasing the degree of freedom and further reducing the speed.

[0139] Figure 11 This is a first variation of the pixel according to the first embodiment.

[0140] Apart from Figure 6 In addition to the pixel PIX described herein, display device 1 may also employ Figure 11 The pixel PIX in the image. Figure 11 In this design, the pixel PIX includes a capacitor C01, transistors MN02 and MN03, and a light-emitting element EL. Transistors MN02 and MN03 are N-type MOSFETs. The gate of transistor MN02 is connected to signal line WSL, its drain is connected to signal line SGL, and its source is connected to the gate of transistor MN03 and capacitor C01. One end of capacitor C01 is connected to the source of transistor MN02 and the gate of transistor MN03, and the other end is connected to the source of transistor MN03 and the anode of the light-emitting element EL. The gate of transistor MN03 is connected to the source of transistor MN02 and one end of capacitor C01, its drain is connected to power line VCCP, and its source is connected to the other end of capacitor C01 and the anode of the light-emitting element EL. The light-emitting element EL is, for example, an organic EL element, with its anode connected to the source of transistor MN03 and the other end of capacitor C01, and its cathode connected to power line Vcath. The voltage of power line VCCP is appropriately switched between a first voltage and a second voltage lower than the first voltage.

[0141] Using this configuration, in the pixel PIX, transistor MN02 is set to the ON state, thereby setting the voltage across capacitor C01 based on the pixel signal supplied from signal line SGL. During the period when the voltage on power line VCCP is a first voltage, transistor MN03 causes current to flow to the light-emitting element EL according to the voltage across capacitor C01. The light-emitting element EL emits light based on the current supplied from transistor MN03. In this way, the pixel PIX emits light with a brightness according to the pixel signal. Note that during the period when the voltage on power line VCCP is a second voltage, the light-emitting element EL is turned off.

[0142] Figure 12 This is a second variation of the pixel according to the first embodiment.

[0143] Apart from Figure 6 In addition to the pixel PIX described herein, display device 1 may also employ Figure 12 The pixel PIX in the image. Figure 12In this configuration, the pixel PIX includes capacitors C11 and C12, transistors MP12 to MP15, and a light-emitting element EL. Transistors MP12 to MP15 are P-type MOSFETs. The gate of transistor MP12 is connected to signal line WSL, the source is connected to signal line SGL, and the drain is connected to the gate of transistor MP14 and capacitor C12. One end of capacitor C11 is connected to power line VCCP, and the other end is connected to capacitor C12, the drain of transistor MP13, and the source of transistor MP14. One end of capacitor C12 is connected to the other end of capacitor C11, the drain of transistor MP13, and the source of transistor MP14, and the other end is connected to the drain of transistor MP12 and the gate of transistor MP14. The gate of transistor MP13 is connected to signal line DSL, the source is connected to power line VCCP, and the drain is connected to the source of transistor MP14, the other end of capacitor C11, and one end of capacitor C12. The gate of transistor MP14 is connected to the drain of transistor MP12 and the other end of capacitor C12. Its source is connected to the drain of transistor MP13, the other end of capacitor C11, and one end of capacitor C12. The drain of MP14 is also connected to the anode of the light-emitting element EL and the source of transistor MP15. The gate of transistor MP15 is connected to signal line AZSL. Its source is connected to the drain of transistor MP14 and the anode of the light-emitting element EL. The drain of MP15 is also connected to power line VSS.

[0144] Using this configuration, in the pixel PIX, transistor MP12 is set to the ON state, whereby the voltage across capacitor C12 is set based on the pixel signal supplied from signal line SGL. Transistor MP13 is switched on and off based on the signal from signal line DSL. During the ON state of transistor MP13, transistor MP14 causes current to flow to the light-emitting element EL based on the voltage across capacitor C12. The light-emitting element EL emits light based on the current supplied from transistor MP14. In this way, the pixel PIX emits light with a brightness based on the pixel signal. Transistor MP15 is switched on and off based on the signal from signal line AZSL. During the ON state of transistor MP15, the voltage of the anode of the light-emitting element EL is initialized by setting it to the voltage of power line VSS.

[0145] Figure 13 This is a third modification of the pixels according to the first embodiment.

[0146] Apart from Figure 6 In addition to the pixel PIX described herein, display device 1 may also employ Figure 13The pixel PIX consists of capacitor C21, transistors MN22 to MN25, and a light-emitting element EL. Transistors MN22 to MN25 are N-type MOSFETs. The gate of transistor MN22 is connected to the gate of signal line WSL, the drain is connected to signal line SGL, and the source is connected to the gate of transistor MN24 and capacitor C21. One end of capacitor C21 is connected to the source of transistor MN22 and the gate of transistor MN24, and the other end is connected to the source of transistor MN24, the drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN23 is connected to signal line DSL, the drain is connected to power line VCCP, and the source is connected to the drain of transistor MN24. The gate of transistor MN24 is connected to the source of transistor MN22 and one end of capacitor C21, the drain is connected to the source of transistor MN23, and the source is connected to the other end of capacitor C21, the drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN25 is connected to signal line AZSL, the drain is connected to the source of transistor MN24, the other end of capacitor C21 and the anode of light-emitting element EL, and the source is connected to power line VSS.

[0147] Using this configuration, in the pixel PIX, transistor MN22 is set to the ON state, thereby setting the voltage across capacitor C21 based on the pixel signal supplied from signal line SGL. Transistor MN23 is switched on and off based on the signal from signal line DSL. During the ON state of transistor MN23, transistor MN24 causes current to flow to the light-emitting element EL according to the voltage across capacitor C21. The light-emitting element EL emits light based on the current supplied from transistor MN24. In this way, the pixel PIX emits light with a brightness based on the pixel signal. Transistor MN25 is switched on and off based on the signal from signal line AZSL. During the ON state of transistor MN25, the voltage of the anode of the light-emitting element EL is initialized by setting it to the voltage of power line VSS.

[0148] Figure 14 This is a fourth variation of the pixel according to the first embodiment.

[0149] Apart from Figure 6 In addition to the pixel PIX described herein, display device 1 may also employ Figure 14The pixel PIX comprises capacitor C31, transistors MP32 to MP36, and a light-emitting element EL. Transistors MP32 to MP36 are P-type MOSFETs. The gate of transistor MP32 is connected to signal line WSL, the source to signal line SGL, and the drain to the gate of transistor MP33, the drain of transistor MP34, and capacitor C31. One end of capacitor C31 is connected to power line VCCP, and the other end is connected to the drain of transistor MP32, the gate of transistor MP33, and the drain of transistor MP34. The gate of transistor MP34 is connected to signal line AZSL1, the source to the drain of transistor MP33 and the source of transistor MP35, and the drain to the drain of transistor MP32, the gate of transistor MP33, and the other end of capacitor C31. The gate of transistor MP35 is connected to signal line DSL, the source to the drain of transistor MP33 and the source of transistor MP34, and the drain to the source of transistor MP36 and the anode of the light-emitting element EL. The gate of transistor MP36 is connected to signal line AZSL2, the source is connected to the drain of transistor MP35 and the anode of light-emitting element EL, and the drain is connected to power line VSS.

[0150] Using this configuration, in the pixel PIX, transistor MP32 is set to the ON state, thereby setting the voltage across capacitor C31 based on the pixel signal supplied from signal line SGL. Transistor MP35 is switched on and off based on the signal from signal line DSL. During the period when transistor MP35 is ON, transistor MP33 causes current to flow to the light-emitting element EL based on the voltage across capacitor C31. The light-emitting element EL emits light based on the current supplied from transistor MP33. In this way, the pixel PIX emits light with a brightness based on the pixel signal. Transistor MP34 is switched on and off based on the signal from signal line AZSL1. During the period when transistor MP34 is ON, the drain and gate of transistor MP33 are connected to each other. Transistor MP36 is switched on and off based on the signal from signal line AZSL2. During the period when transistor MP36 is ON, the voltage of the anode of the light-emitting element EL is initialized by setting it to the voltage of power line VSS.

[0151] Figure 15 This is a fifth variation of the pixel according to the first embodiment.

[0152] Apart from Figure 6 In addition to the pixel PIX described herein, display device 1 may also employ Figure 15The pixel is shown in the image. One end of capacitor C48 is connected to signal line SGL1, and the other end is connected to power line VSS. One end of capacitor C49 is connected to signal line SGL1, and the other end is connected to signal line SGL2. Transistor MP49 is a P-type MOSFET, with its gate connected to signal line WSL2, its source connected to signal line SGL1, and its drain connected to signal line SGL2.

[0153] The pixel PIX includes capacitor C41, transistors MP42 to MP46, and a light-emitting element EL. Transistors MP42 to MP46 are P-type MOSFETs. The gate of transistor MP42 is connected to signal line WSL1, the source is connected to signal line SGL2, and the drain is connected to the gate of transistor MP43 and capacitor C41. One end of capacitor C41 is connected to power line VCCP, and the other end is connected to the drain of transistor MP42 and the gate of transistor MP43. The gate of transistor MP43 is connected to the drain of transistor MP42 and the other end of capacitor C41, the source is connected to power line VCCP, and the drain is connected to the source of transistors MP44 and MP45. The gate of transistor MP44 is connected to signal line AZSL1, the source is connected to the drain of transistor MP43 and the source of transistor MP45, and the drain is connected to signal line SGL2. The gate of transistor MP45 is connected to signal line DSL, the source is connected to the drain of transistor MP43 and the source of transistor MP44, and the drain is connected to the source of transistor MP46 and the anode of the light-emitting element EL. The gate of transistor MP46 is connected to signal line AZSL2, the source is connected to the drain of transistor MP45 and the anode of light-emitting element EL, and the drain is connected to power line VSS.

[0154] Using this configuration, in the pixel PIX, transistor MP42 is set to the ON state, whereby the voltage across capacitor C41 is set based on the pixel signal supplied from signal line SGL1 via capacitor C49. Transistor MP45 is switched on and off based on the signal from signal line DSL. During the ON state of transistor MP45, transistor MP43 causes current to flow to the light-emitting element EL based on the voltage across capacitor C41. The light-emitting element EL emits light based on the current supplied from transistor MP43. In this way, the pixel PIX emits light with brightness according to the pixel signal. Transistor MP44 is switched on and off based on the signal from signal line AZSL1. During the ON state of transistor MP44, the drain of transistor MP43 and signal line SGL2 are connected to each other. Transistor MP46 is switched on and off based on the signal from signal line AZSL2. During the ON state of transistor MP46, the voltage of the anode of the light-emitting element EL is initialized by setting it to the voltage of power line VSS.

[0155] Figure 16 This is a sixth variation of the pixel according to the first embodiment.

[0156] Apart from Figure 6 In addition to the pixel PIX described herein, display device 1 may also employ Figure 16 The pixel PIX is arranged in a matrix in the display area 100, and the display area 100 is located between the first control unit 40 and the second control unit 70.

[0157] The first control unit 40 includes transmission gates TG45 and TG46, transistors MP56 and MP57, and capacitor C61. Transistors MP56 and MP57 are P-type MOSFETs. Pixel signals are provided to the input of transmission gate TG45, and the output of transmission gate TG45 is connected to one end of signal line 14a. The input of transmission gate TG46 is connected to signal line 14b, and the output of transmission gate TG46 is connected to power line Vorst. One end of capacitor C61 is connected to signal line 14a, and the other end is connected to power line VSS1. The gate of transistor MP56 is connected to signal line INIL, the source is connected to power line Vini, and the drain is connected to signal line 14b. The gate of transistor MP57 is connected to signal line ELL, the source is connected to power line Vel, and the drain is connected to signal line 14b.

[0158] The second control unit 70 includes a transmission gate TG72, a transistor MP73, and a capacitor C82. The transistor MP73 is a P-type MOSFET. The input terminal of the transmission gate TG72 is connected to the other end of signal line 14a, and its output terminal is connected to the drain of the transistor MP73 and one end of the capacitor C82. The gate of the transistor MP73 is connected to signal line REFL, its source is connected to power line Vref, and its drain is connected to the output terminal of the transmission gate TG72 and one end of the capacitor C82. One end of the capacitor C82 is connected to the output terminal of the transmission gate TG72 and the drain of the transistor MP73, and the other end is connected to one end of signal line 14b.

[0159] The pixel PIX includes capacitor C132, transistors MP121 to MP125, and a light-emitting element EL. Transistors MP121 to MP125 are P-type MOSFETs. The gate of transistor MP122 is connected to signal line WSL, its source is connected to signal line 14b, and its drain is connected to the gate of transistor MP121 and capacitor C132. One end of capacitor C132 is connected to power line Vel, and the other end is connected to the drain of transistor MP122 and the gate of transistor MP121. The gate of transistor MP121 is connected to the drain of transistor MP122 and the other end of capacitor C132, its source is connected to power line Vel, and its drain is connected to the sources of transistors MP123 and MP124. The gate of transistor MP123 is connected to signal line AZSL, its source is connected to the drain of transistor MP121 and the source of transistor MP124, and its drain is connected to signal line 14b. The gate of transistor MP124 is connected to signal line DSL, its source is connected to the drain of transistor MP121 and the source of transistor MP123, and its drain is connected to the drain of transistor MP125 and the anode of light-emitting element 130. The gate of transistor MP125 is connected to signal line AZSL, its source is connected to power line Vorst, and its drain is connected to the drain of transistor MP124 and the anode of light-emitting element 130.

[0160] Using this configuration, in the pixel PIX, transistor MP122 is set to the ON state, whereby the voltage across capacitor C132 is set based on the pixel signal supplied via transmission gate TG45, signal line 14a, transmission gate TG72, capacitor C82, and signal line 14b. Transistor MP124 is switched on and off based on the signal of signal line DSL. During the ON state of transistor MP124, transistor MP121 causes current to flow to the light-emitting element EL based on the voltage across capacitor C132. The light-emitting element EL emits light based on the current supplied from transistor MP121. In this way, the pixel PIX emits light with a brightness based on the pixel signal. Transistors MP123 and MP125 are switched on and off based on the signal of signal line AZSL. During the ON state of transistor MP123, the drain of transistor MP121 and the source of transistor MP124 are connected to signal line 14b. During the ON state of transistor MP125, the voltage of the anode of the light-emitting element EL is initialized by setting the voltage Vorst of the power supply line. Furthermore, transistor MP56 is turned on and off based on the signal line INIL, transistor MP57 is turned on and off based on the signal line ELL, and transistor MP73 is turned on and off based on the signal line REFL. When transistor MP56 is on, signal line 14b is set to the voltage of power line Vini, and when transistor MP57 is on, signal line 14b is set to the voltage of power line Vel. When transistor MP73 is on, one end of capacitor C82 is initialized by being set to the voltage of power line Vref.

[0161] Figure 17 This is a seventh variation of the pixel according to the first embodiment.

[0162] Apart from Figure 6 In addition to the pixel PIX described herein, display device 1 may also employ Figure 17The pixel PIX comprises capacitor C51, transistors MP52 to MP60, and a light-emitting element EL. Transistors MP52 to MP60 are P-type MOSFETs. The gate of transistor MP52 is connected to signal line WSL, the source is connected to signal line SGL, and the drain is connected to the drain of transistor MP53 and the source of transistor MP54. The gate of transistor MP53 is connected to signal line DSL, the source is connected to power line VCCP, and the drain is connected to the drain of transistor MP52 and the source of transistor MP54. The gate of transistor MP54 is connected to the source of transistor MP55, the drain of transistor MP57, and capacitor C51. The source of transistor MP54 is connected to the drains of transistors MP52 and MP53, and the drain of transistor MP54 is connected to the sources of transistors MP58 and MP59. One end of capacitor C51 is connected to power line VCCP, and the other end of capacitor C51 is connected to the gate of transistor MP54, the source of transistor MP55, and the drain of transistor MP57. Capacitor C51 may include two capacitors connected in parallel with each other. The gate of transistor MP55 is connected to signal line AZSL1, its source is connected to the gate of transistor MP54, the drain of transistor MP57, and the other end of capacitor C51, and its drain is connected to the source of transistor MP56. The gate of transistor MP56 is connected to signal line AZSL1, its source is connected to the drain of transistor MP55, and its drain is connected to power line VSS. The gate of transistor MP57 is connected to signal line WSL, its drain is connected to the gate of transistor MP54, the source of transistor MP55, and the other end of capacitor C51, and its source is connected to the drain of transistor MP58. The gate of transistor MP58 is connected to signal line WSL, its drain is connected to the source of transistor MP57, and its source is connected to the drain of transistor MP54 and the source of transistor MP59. The source of transistor MP59 has a gate connected to signal line DSL, its source is connected to the drain of transistor MP54 and transistor MP58, and its drain is connected to the source of transistor MP60 and the anode of light-emitting element EL. The gate of transistor MP60 is connected to signal line AZSL2, the source is connected to the drain of transistor MP59 and the anode of light-emitting element EL, and the drain is connected to power line VSS.

[0163] Using this configuration, in the pixel PIX, transistors MP52, MP54, MP58, and MP57 are in the ON state, thereby setting the voltage across capacitor C51 based on the pixel signal supplied from signal line SGL. Transistors MP53 and MP59 are ON and OFF based on the signal from signal line DSL. During the ON state of transistors MP53 and MP59, transistor MP54 causes current to flow to the light-emitting element EL based on the voltage across capacitor C51. The light-emitting element EL emits light based on the current supplied from transistor MP54. In this way, the pixel PIX emits light with brightness based on the pixel signal. Transistors MP55 and MP56 are ON and OFF based on the signal from signal line AZSL1. During the ON state of transistors MP55 and MP56, the gate voltage of transistor MP54 is initialized by setting the gate voltage of transistor MP54 to the voltage of power supply line VSS. Transistor MP60 is ON and OFF based on the signal from signal line AZSL2. During the period when transistor MP60 is in the on state, the voltage of the anode of the light-emitting element EL is initialized by setting the voltage of the power supply line VSS.

[0164] Figure 18 This is the eighth modification of the pixels according to the first embodiment.

[0165] Apart from Figure 6 In addition to the pixel PIX described herein, display device 1 may also employ Figure 18 The pixel PIX in the signal line WSNL and the signal line WSPL are out of phase with each other.

[0166] The pixel PIX includes capacitors C61 and C62, transistors MN63, MP64, and MN65 through MN67, and a light-emitting element EL. Transistors MN63 and MN65 through MN67 are N-type MOSFETs, and transistor MP64 is a P-type MOSFET. The gate of transistor MN63 is connected to signal line WSNL, and its drain is connected to signal line SGL and the source of transistor MP64, while its source is connected to the drain of transistor MP64, capacitors C61 and C62, and the gate of transistor MN65. The gate of transistor MP64 is connected to signal line WSPL, and its source is connected to signal line SGL and the drain of transistor MN63, while its drain is connected to the source of transistor MN63, capacitors C61 and C62, and the gate of transistor MN65. For example, capacitor C61 is a metal-oxide-semiconductor (MOM) capacitor, with one end connected to the source of transistor MN63, the drain of transistor MP64, capacitor C62, and the gate of transistor MN65, and the other end connected to power line VSS2. Note that capacitor C61 may include, for example, a MOS capacitor or a metal-insulator-metal (MIM) capacitor. Capacitor C62 includes, for example, a MOS capacitor, with one end connected to the source of transistor MN63, the drain of transistor MP64, one end of capacitor C61, and the gate of transistor MN65, and its other end connected to power line VSS2. Note that capacitor C62 may include, for example, a MOM capacitor or a MIM capacitor. Furthermore, the other end of capacitor C62 may be connected to power line VSS3 (not shown). The gate of transistor MN65 is connected to the source of transistor MN63, the drain of transistor MP64, and one end of each of capacitors C61 and C62. The drain of transistor MN65 is connected to power line VCCP, and the source of transistor MN65 is connected to the drains of transistors MN66 and MN67. The gate of transistor MN66 is connected to signal line AZL, its drain is connected to the source of transistor MN65 and the drain of transistor MN67, and its source is connected to power line VSS1. The gate of transistor MN67 is connected to signal line DSL, and its drain is connected to the source of transistor MN65 and the drain of transistor MN66. The source is connected to the anode of light-emitting element EL.

[0167] Using this configuration, in the pixel PIX, at least one of transistors MN63 and MP64 is set to the ON state, thereby setting the voltage across capacitors C61 and C62 based on the pixel signal supplied from signal line SGL. Transistor MN67 is switched on and off based on the signal from signal line DSL. During the period when transistor MN67 is ON, transistor MN65 causes a current corresponding to the voltage across capacitors C61 and C62 to flow to the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP65. In this way, the pixel PIX emits light with a brightness according to the pixel signal. Transistor MN66 can be switched on and off based on the signal from signal line AZL. Furthermore, transistor MN66 can be used as a resistive element with a resistance value according to the signal from signal line AZL. In this case, transistors MN65 and MN66 constitute a so-called source follower circuit.

[0168] Figure 19 This is the ninth variation of the pixel according to the first embodiment.

[0169] Apart from Figure 6 In addition to the pixel PIX described herein, display device 1 may also employ Figure 19 The pixel PIX in the image. Figure 19 This shows the configuration of pixels in a liquid crystal display device. Note that... Figure 19 The area corresponding to four pixels (PIX) is shown. As shown, each pixel (PIX) includes a liquid crystal element (LC), a storage capacitor (Cp), and a FET (FET) 110. Each pixel (PIX) is connected to a scan line (GL) and a signal line (DL). The scan line (GL) is connected, for example, to the gate of the FET 110 and is wiring for providing a scan signal to the FET 110 from a scan line driving circuit (not shown) at a predetermined timing. The signal line (DL) is wiring for providing a signal based on an externally input video signal from the signal line driving circuit to each pixel (P). Note that the scan line driving circuit and the signal line driving circuit are formed in or connected to the peripheral region of the effective pixel region A. The pixels are formed in multiple layers on the driving substrate 10.

[0170] Figure 20 This is an explanatory diagram regarding the vertical system control in a variation of the display device according to the first embodiment.

[0171] In this variation, the vertical driver 52 is configured not using a shift register method, but rather an address decoding method. Because, besides... Figure 9Configurations other than those shown are similar to those in the first embodiment, so their description is omitted. The vertical driver 52 includes one or more address decoders 47 and receives a signal (address signal) indicating the display start position in the vertical direction from the vertical logic circuit 41 as input. Furthermore, the address decoders 47 are configured in the same number as the number of pixels in the vertical direction, and for example, if the pixel array 51 includes 100 pixels in the vertical direction, the address decoders 47 are also configured in the same number. The vertical driver 52 selects a target address decoder 47 from the address signal and determines the display position of the output data in the vertical direction.

[0172] For example, the vertical logic circuit 41 decodes signals related to the display start position in the vertical direction specified by the user and generates an address signal containing the decoded value. The vertical logic circuit 41 selects a specific row based on the decoded value and outputs a selection pulse SEL. The horizontal driver 53 outputs the output data for that row based on the output of the selection pulse SEL. The vertical logic circuit 41 uses an address decoding method, which simplifies the control of the vertical driver 52 compared to a shift register method.

[0173] exist Figure 20 In the example, the vertical driver 52 receives the value "234" as input, which is the decoded value contained in the decoded signal from the vertical logic circuit 41. This value represents the third row from the top in the row direction, and the vertical driver 52 outputs a selection pulse SEL from the address decoder 47 of that row. The horizontal driver 53 outputs output data in the horizontal direction based on the selection pulse SEL. On the other hand, the first and second rows from the top become black areas.

[0174] According to this embodiment, the display device 1 can flexibly adjust the resolution and display position of the input image data based on the user-specified display start position.

[0175] Furthermore, according to this embodiment, the display device 1 receives input data in a specific format, including image data and synchronization signals, from an external device. Therefore, the input clock can be set to a low clock frequency based on the amount of image data, thus achieving low power consumption.

[0176] Furthermore, according to this embodiment, since black data is inserted into the internally generated clock, the display device 1 can set the input clock to a low clock frequency according to the amount of image data, and thus achieve low power consumption.

[0177] Furthermore, according to this embodiment, since each group of shift registers 43 in the display device 1 has a configuration where multiple flip-flops 45 share a selector 44, the increase in circuit size can be suppressed compared to a configuration where each flip-flop 45 is provided with a selector 44. Additionally, the display device 1 can similarly suppress the increase in circuit size by including a row memory 25.

[0178] Furthermore, according to this embodiment, in the event of a truncation in the image data to be displayed, the display device 1 can display image data that can be displayed within the pixel array 51 from a user-specified display start position.

[0179] Furthermore, according to this embodiment, since the processing of black areas by the transistors of the pixel PIX is fixed, the display device 1 can eliminate the need for scanning processing of the vertical driver 52. Moreover, since the input format of the signal format to the pixel PIX is not limited to a specific signal format, the degree of freedom is increased, and furthermore, the speed can be reduced.

[0180] Furthermore, according to this embodiment, the light-emitting elements included in the pixels can be various light-emitting elements such as organic EL elements or liquid crystal elements, and in addition, a display device 1 including various pixel PIXs can also be realized.

[0181] Furthermore, according to this embodiment, the display device 1 can employ an address decoding method as the vertical logic circuit 41. By employing an address decoder 47, the display device 1 can facilitate the control of the vertical driver 52 compared to the shift register method.

[0182] (Second Implementation)

[0183] Figure 21 This is a block diagram of a timing controller according to the second embodiment.

[0184] In this embodiment, unlike the first embodiment, the display device 1 includes a first horizontal logic circuit 43 and a second horizontal logic circuit 44 instead of the horizontal logic circuit 42. Other configurations are the same as in the first embodiment, and therefore their description is omitted. In this embodiment, the display device 1 inserts black data into the pixel data when the first horizontal logic circuit 43 outputs.

[0185] Figure 22 This is an explanatory diagram of the operation in the display device according to the second embodiment.

[0186] In this example, the image processing unit 33 inserts black data before and after the valid data in a row, and compares the first and second embodiments. In the first embodiment, the image processing unit 33 inserts black data when the row memory 25 outputs. The black data is inserted at the H_SHIFT position, and then valid data corresponding to the display resolution (H_ACTIVE) is inserted. After the valid data is inserted, black data is inserted again, and output data is created. By inserting black data, valid data is stored in the storage area of ​​the second horizontal logic circuit 44 with a correspondence offset relative to the first horizontal logic circuit 43. In the second embodiment, the timing controller 12 synchronizes with the horizontal start pulse HST to provide pixel data to the first horizontal logic circuit 43. This pixel data contains grayscale information representing the grayscale of each color such as R, G, and B. The first horizontal logic circuit 43 temporarily stores the pixel data. Furthermore, the image processing unit 33 provides pixel data with grayscale information containing inserted black data to the second horizontal logic circuit 44 when the first horizontal logic circuit 43 outputs. The insertion of black data is based on a data enable signal. In this embodiment, the display device 1 may not include the row memory 25. Furthermore, a black data insertion unit can be installed in the display controller 13, and the insertion of black data can be implemented by a function block.

[0187] Figure 23 This is an explanatory diagram of the operation in a modified example of the display device according to the second embodiment.

[0188] In this variation, the image processing unit 33 inserts black data into the image data when the timing controller 12 outputs, instead of inserting black data into the image data when the row memory 25 outputs. The insertion of black data is based on a data enable signal. Furthermore, a black data insertion unit can be provided in the timing controller 12, and the insertion of black data can be implemented through a function block. Additionally, in this variation, the first horizontal logic circuit 43 and the second horizontal logic circuit 44 can be configured as a horizontal logic circuit 42 similar to the horizontal logic circuit in the first embodiment.

[0189] According to this embodiment, the display device 1 can insert black data into the image data at times other than when the row memory 25 is output, and can improve the design freedom of the display device 1.

[0190] (First application example)

[0191] Next, application examples of the display system described in the above embodiments and variations will be described.

[0192] (First application example)

[0193] Figure 24This is an illustration showing an example of the appearance of a head-mounted display 110. For example, the head-mounted display 110 includes ear loops 112 on both sides of the eyeglass-shaped display unit 111 for wearing on the user's head. The technology according to the above-described embodiments, etc., can be applied to this head-mounted display 110.

[0194] (Second application example)

[0195] Figure 25 This is an illustration showing an example of the appearance of another head-mounted display 120. The head-mounted display 120 is a see-through type head-mounted display including a main body 121, an arm 122, and a lens barrel 123. The head-mounted display 120 is mounted on glasses 128. The main body 121 includes a control panel and a display unit for controlling the operation of the head-mounted display 120. The display unit emits image light to display an image. The arm 122 connects the main body 121 and the lens barrel 123 and supports the lens barrel 123. The lens barrel 123 projects the image light provided from the main body 121 through the arm 122 towards the user's eyes via the lenses 129 of the glasses 128. The technology according to the above-described embodiments, etc., can be applied to this head-mounted display 120.

[0196] Note that the head-mounted display 120 is a so-called light guide plate type head-mounted display, but is not limited to this, and can also be, for example, a so-called bird bus type head-mounted display. For example, a bird bus type head-mounted display includes a beam splitter and a partially transparent reflector. The beam splitter directs light encoded with image information toward the reflector, and the reflector reflects the light toward the user's eyes. Both the beam splitter and the partially transparent reflector are partially transparent. Therefore, light from the surrounding environment reaches the user's eyes.

[0197] (Third application example)

[0198] Figure 26 A and Figure 26 B represents an example of the appearance of the digital camera 130. Figure 26 A shows a front view. Figure 26B shows a rear view. The digital camera 130 is an interchangeable-lens single-lens reflex camera and includes a camera body (camera frame) 131, an imaging lens unit 132, a grip 133, a monitor 134, and an electronic viewfinder 135. The imaging lens unit 132 is an interchangeable lens unit and is located approximately near the center of the front surface of the camera body 131. The grip 133 is located on the left side of the front surface of the camera body 131, and is held by the camera operator. The monitor 134 is located approximately to the left of the center of the rear surface of the camera body 131. The electronic viewfinder 135 is located above the monitor 14 on the rear surface of the camera body 131. By observing the electronic viewfinder 135, the camera operator can visually identify the optical image of the subject guided by the imaging lens unit 132 and determine the composition. The technology described in the above example can be applied to the electronic viewfinder 135.

[0199] (Fourth application example)

[0200] Figure 27 This is an illustration showing an example of the appearance of a television device 140. The television device 140 includes an image display screen 141 having a front panel 142 and a filter glass 143. The technology described in the above examples can be applied to the image display screen 141.

[0201] (Fifth application example)

[0202] Figure 28 This is an illustration showing an example of the appearance of a smartphone 150. The smartphone 150 includes a display unit 151 that displays various information and an operation unit 152 that receives user input, including buttons, etc. The technology described in the above embodiments can be applied to the display unit 151.

[0203] (Sixth Application Example)

[0204] Figure 29 A and Figure 29 B represents a configuration example of a vehicle that applies the technology disclosed herein. Figure 29 A shows an example of the vehicle interior viewed from the rear of vehicle 200, and Figure 29 B shows an example of the interior of the vehicle as viewed from the left rear of vehicle 200.

[0205] Figure 29 A and Figure 29 Vehicle B includes a central display 201, a console display 202, a head-up display 203, a digital rearview mirror 204, a steering wheel display 205, and a rear-seat entertainment display 206.

[0206] The central display 201 is positioned on the dashboard 261 facing the driver's seat 262 and the passenger seat 263. Figure 29 Example A shows a central display 201 with a horizontally elongated shape extending from the driver's seat 262 side to the passenger seat 263 side; however, the screen size and placement of the central display 201 are not limited thereto. The central display 201 can display information detected by various sensors. As specific examples, the central display 201 can display captured images by an image sensor, distance images to obstacles in front of or to the sides of the vehicle measured by a ToF sensor, passenger body temperature detected by an infrared sensor, etc. The central display 201 can be used to display at least one of, for example, safety-related information, operational-related information, lifestyle logs, health-related information, authentication / identification-related information, or entertainment-related information.

[0207] Safety-related information includes information based on sensor detection results such as drowsiness detection, distraction detection, child passenger misbehavior detection, seatbelt fastening status, and passenger-related actions. Operation-related information concerns gesture information about passenger actions detected by sensors. Gestures may include operations of various facilities within the vehicle, such as air conditioning, navigation systems, audiovisual (AV) systems, lighting, etc. A life log includes a life log for all passengers. For example, the life log includes a record of each passenger's actions. By acquiring and storing life logs, passenger status can be checked in the event of an accident. Health-related information includes passenger body temperature detected by temperature sensors and information on passenger health status estimated based on the detected body temperature. Optionally, information about passenger health status can be estimated based on passenger faces imaged by image sensors. Furthermore, information about passenger health status can be estimated based on passenger responses obtained through conversations conducted with passengers using automated voice systems. Authentication / recognition-related information includes information such as keyless entry functions for performing facial authentication using sensors and automatic seat height and position adjustment functions in facial recognition. Entertainment-related information includes operational information of the AV devices for passengers detected by sensors, and information on the content to be displayed for passengers detected and identified by sensors.

[0208] For example, the console display 202 can be used to display life log information. The console display 202 is located near the gear shift lever 265 in the center console 264 between the driver's seat 262 and the passenger seat 263. The console display 202 can also display information detected by various sensors. Furthermore, the console display 202 can display images of the vehicle's surroundings captured by image sensors, or it can display images of the distances to obstacles around the vehicle.

[0209] The head-up display 203 is virtually displayed behind the windshield 266 in front of the driver's seat 262. The head-up display 203 can be used to display at least one of the following: safety-related information, operational-related information, lifestyle logs, health-related information, authentication / identification-related information, or entertainment-related information. Because the head-up display 203 is typically virtually positioned in front of the driver's seat 262, it is suitable for displaying information directly related to vehicle operation, such as vehicle speed, remaining fuel, and remaining battery level.

[0210] The digital rearview mirror 204 can not only display the rear of the vehicle, but also the status of the rear passengers, and therefore can be used to display, for example, the life log information of the rear passengers.

[0211] The steering wheel display 205 is positioned near the center of the vehicle's steering wheel 267. The steering wheel display 205 can be used to display at least one of the following: safety-related information, operational information, life logs, health-related information, authentication / identification-related information, or entertainment-related information. Specifically, the steering wheel display 205 is close to the driver's hands and is therefore suitable for displaying life log information such as the driver's body temperature, or for displaying information regarding the operation of AV devices, air conditioning systems, etc.

[0212] The rear-seat entertainment display 206 is attached to the rear surface of the driver's seat 262 and the passenger seat 263, and is intended for viewing by passengers in the rear seats. The rear-seat entertainment display 206 can display at least one of the following: safety-related information, operational-related information, daily logs, health-related information, authentication / identification-related information, or entertainment-related information. Specifically, since the rear-seat entertainment display 206 is located directly in front of the rear-seat passengers, it displays information relevant to them. The rear-seat entertainment display 206 can display, for example, information about the operation of AV devices or the air conditioning system, or it can display the results of body temperature measurements of the rear-seat passengers taken by the temperature sensor 5.

[0213] The technology described above can be applied to the central display 201, console display 202, head-up display 203, digital rearview mirror 204, steering wheel display 205, and rear-seat entertainment display 206.

[0214] (Seventh Application Example)

[0215] Figure 30The liquid crystal projector 300 shown is a so-called three-panel projector, which splits light from a light source into three primary colors: red, blue, and green, and displays a color image for each color using a liquid crystal display panel. For ease of explanation, the liquid crystal display panel 10 incident with red light will be referred to as liquid crystal display device 325R, the liquid crystal display panel 10 incident with green light as liquid crystal display device 325G, and the liquid crystal display panel 10 incident with blue light as liquid crystal display device 325B. Liquid crystal display devices 325R, 325G, and 325B are liquid crystal display panels, and all three have substantially the same structure. These liquid crystal display devices 325R, 325G, and 325B are controlled by control circuit 20.

[0216] Figure 30 The liquid crystal projector 300 includes a light source 311 that emits light, a first lens array 312 disposed on the light-emitting side of the light source 311, a mirror 314 that reflects the emitted light from the first lens array 312 and changes the optical path (optical axis 310) of the emitted light by 90°, and a second lens array 313 into which the reflected light from the mirror 314 is incident.

[0217] Mirror 314 is preferably a total reflection mirror.

[0218] The first lens array 312 and the second lens array 313 each have a plurality of microlenses 312M and 313M arranged in a two-dimensional manner. The first lens array 312 and the second lens array 313 are used to homogenize the illuminance distribution of light and have the function of splitting the incident light into multiple small beams.

[0219] Note that an ultraviolet (UV) / infrared (IR) cutoff filter (not shown) may be disposed between the light source 311 and the first lens array 312.

[0220] Light source 311 emits white light, including red, blue, and green light required for color image display. Light source 311 includes a light emitter (not shown) that emits white light and a reflector that reflects and focuses the light emitted from the light emitter.

[0221] As a light emitter, for example, a lamp such as an ultra-high pressure mercury lamp, a halogen lamp, a metal halide lamp, or a xenon lamp is used. The reflector preferably has a shape with high light-gathering efficiency and, for example, has a rotationally symmetric concave shape, such as a rotating ellipsoidal mirror or a rotating parabolic mirror. Furthermore, the light-emitting point of the light emitter is located at the focal position of the concave reflector.

[0222] The white light emitted from the light emitter of the light source 311 is transformed into approximately parallel light by the reflector, passes through the first lens array 312, and enters the total reflection mirror 314. The white light, whose optical axis 310 is deflected by 90° by the total reflection mirror 314, enters the second lens array 313.

[0223] Figure 30 The liquid crystal projector 300 shown includes a PS combining element 315, a condenser lens 316, and a dichroic mirror 317 on the light-emitting side of the second lens array 313.

[0224] The PS synthesizing element 315 has multiple phase retardation plates 315A positioned at locations corresponding to the spaces between adjacent microlenses in the second lens array 313. A half-wave plate is an example of a phase retardation plate 315A.

[0225] The PS combining element 315 splits the incident light into P-polarized and S-polarized components. Furthermore, the PS combining element 315 causes one of the two polarized light components (e.g., the P-polarized component) to maintain its polarization direction before being emitted from the polarization conversion element 315, and the other polarized light component (e.g., the S-polarized component) is converted into another polarized light component (e.g., the P-polarized component) by the action of the half-wave plate 315A before being emitted.

[0226] The light emitted from the PS synthesizer 315 is converged by the condenser lens 316 and incident on the dichroic mirror 317.

[0227] The dichroic mirror 317 reflects, for example, red light LR in the incident light and transmits other colors of light, thereby decomposing the incident light into red light LR and other colors.

[0228] In addition, the liquid crystal projector 300 has a mirror 318, a field lens 324R, an incident-side polarizing plate 330I, a liquid crystal display device 325R, and an emitting-side polarizing plate 330S along the optical path of the red light LR separated by the dichroic mirror 317.

[0229] As the mirror 318, a total internal reflection mirror is preferably used. The total internal reflection mirror 318 reflects the red light LR, which is decomposed by the dichroic mirror 317, toward the incident-side polarizing plate 330I and the liquid crystal display device 325R.

[0230] As described above, the incident-side polarizer 330I allows light from the red light LR incident from the total reflection mirror 318 to pass through in the same direction as the polarization axis 330a.

[0231] The liquid crystal display device 325R spatially modulates the red light LR incident via the incident-side polarizer 330I according to the input image data. The emitting-side polarizer 330S allows light in the red light LR modulated by the liquid crystal display panel 325R that is aligned with the polarization axis 330b to pass through.

[0232] The LCD projector 300 has a dichroic mirror 319 that follows the light path of other colors of light separated by the dichroic mirror 317. The dichroic mirror 319 separates the incident light into green light LG and blue light LB, for example, by reflecting green light LG in the incident light and transmitting blue light LB.

[0233] In the optical path of the green light LG, which is decomposed by the dichroic mirror 319, a field lens 324G, an incident-side polarizing plate 330I, a liquid crystal display panel 325G, and an emitting-side polarizing plate 330S are provided.

[0234] The incident-side polarizer 330I allows light from the green light LG incident from the dichroic mirror 319, which is aligned with the polarization axis 330a, to pass through.

[0235] The liquid crystal display device 325G spatially modulates the green light LG incident through the incident side polarizer 330I based on the input image data.

[0236] The emitting-side polarizer 330S allows light in the green light LG modulated by the liquid crystal display panel 325G to pass through in the same direction as the polarization axis 330b.

[0237] In addition, along the light path of the blue light LB decomposed by the dichroic mirror 319, a relay lens 320, a mirror 321, a relay lens 322, a mirror 323, a field lens 324B, an incident-side polarizing plate 330I, a liquid crystal display device 325B, and an emitting-side polarizing plate 330S are provided.

[0238] Reflectors 321 and 323 are preferably total internal reflection mirrors. Total internal reflection mirror 321 reflects the blue light LB incident via relay lens 320 toward total internal reflection mirror 323. Total internal reflection mirror 323 reflects the blue light LB reflected by total internal reflection mirror 321 and incident via relay lens 322 toward incident-side polarizing plate 330I and liquid crystal display panel 325B.

[0239] The incident-side polarizer 330I allows light from the green light LG incident from the total reflection mirror 323, which is aligned with the polarization axis 330a, to pass through.

[0240] The liquid crystal display device 325B spatially modulates the blue light LB reflected by the total reflection mirror 323 and incident through the field lens 324B and the incident-side polarizing plate 330I according to the input image data.

[0241] The emitting-side polarizer 330S allows light from the blue light LB modulated by the liquid crystal display panel 325B, which is aligned with the polarization axis 330b, to pass through. At the intersection of the light paths of the red light LR, green light LG, and blue light LB, a cross prism 326 is provided, which has the function of synthesizing the three colors of light.

[0242] As an example, the cross prism 326 is configured with four right-angle prisms, which have incident surfaces 326R, 326G and 326B on which red light LR, green light LG and blue light LB are incident respectively, and an emitting surface 326T on which light obtained by synthesizing red light LR, green light LG and blue light LB is emitted.

[0243] In the liquid crystal projector 300, a dichroic film is coated on the joint surface of each right-angle prism, such that the green light LG incident in the cross prism 326 is transmitted toward the emitting surface 326T side, and the red light LR and blue light LB incident in the cross prism 326 are reflected toward the emitting surface 326T side.

[0244] As described above, the cross prism 326 combines the three colors of light incident on the incident surfaces 326R, 326G and 326B, and emits the combined light from the emitting surface 326T.

[0245] Furthermore, the LCD projector 300 includes a projection lens 327 for projecting the composite light emitted from the cross prism 326 toward the screen 328. The projection lens 327 preferably includes multiple lenses and has scaling and focusing functions for adjusting the size of the image projected onto the screen 328.

[0246] Although this disclosure has been described with reference to the above-described embodiments, modifications, application examples, and examples of their applications, this disclosure is not limited to the embodiments, etc., and various modifications can be made. Note that the effects described in this specification are merely illustrative. The effects of this disclosure are not limited to those described in this specification. This disclosure may have effects other than those described in this specification.

[0247] In addition, for example, this disclosure may have the following configuration. (1)

[0249] A display device, comprising: A pixel array section, wherein multiple pixels are arranged in a two-dimensional array. The memory receives image data as input and temporarily stores the image data. The image processing unit inserts black data into the image data output from the memory and generates output data; Vertical logic circuitry controls a vertical driver that determines the display position of the output data in the vertical direction; and The horizontal logic circuit controls the horizontal driver, which provides a grayscale voltage corresponding to the grayscale information of the output data to each pixel of the output data in the horizontal direction. The insertion position of the black data and its display position in the vertical direction are determined based on the display start position specified by the user. (2)

[0251] According to the display device of (1), image data is input synchronously with a first clock as an input clock, and black data is inserted into the image data synchronously with a second clock generated inside the display device. (3)

[0253] According to the display device of (2), the clock frequency in the second clock is higher than the clock frequency in the first clock. (4)

[0255] According to the display device of (2), it also includes: Oscillator or PLL circuit, The second clock is generated by an oscillator or a PLL circuit. (5)

[0257] According to the display device in (1), The vertical driver includes: One or more triggers perform a shift operation. One or more selection switches are connected to one or more triggers and provide selection pulses to the pixel array section, and The selector provides a vertical start pulse to one or more triggers, and The selector includes the nth shift register (where n is a natural number) connected to the pilot flip-flop in one or more flip-flops. (6)

[0259] According to the display device of (5), the selector to which the vertical start pulse is input and the shift register that begins to provide the selection pulse to the pixel array are both determined based on the display start position. (7)

[0261] According to the display device of (5), the vertical driver performs a no-transmission and determines the display start position in the vertical direction. In the no-transmission, the scanning operation is performed by transmitting a vertical start pulse in advance relative to the output data. (8)

[0263] The display device according to claim 7, wherein the line performing the empty transmission becomes a black area. (9)

[0265] According to the display device of (1), the memory is a row memory or a frame memory. (10)

[0267] According to the display device of (1), the memory is provided on the output side of the data input interface that receives image data as input. (11)

[0269] According to the display device of (1), the display device receives input from an external device in a specific format of input data containing image data and synchronization signals. (12)

[0271] According to the display device of (1), the light-emitting element included in the pixel is an organic EL element or a liquid crystal element. (13)

[0273] According to the display device of (1), the vertical driver includes one or more address decoders, which receive an address signal indicating the display start position in the vertical direction as input to determine the display start position. (14)

[0275] According to the display device of (8), the horizontal driver fixes the potential state of the signal line of the pixel in the black area. (15)

[0277] A display device, comprising: A pixel array section, wherein multiple pixels are arranged in a two-dimensional array. The first level logic circuit receives image data as input and temporarily stores the image data; The image processing unit inserts black data into the image data output from the first level logic circuit and generates output data; Vertical logic circuitry controls a vertical driver that determines the display position of the output data in the vertical direction; and The second horizontal logic circuit controls the horizontal driver, which provides a grayscale voltage corresponding to the grayscale information of the output data to each pixel of the output data in the horizontal direction. Specifically, the insertion position of the black data and its display position in the vertical direction are determined based on the user-specified display start position. (16)

[0279] According to the display device of (1), after the output of the timing controller that controls the operation timing of the display controller including vertical logic circuit and horizontal logic circuit, the insertion of black data into the image data is performed. (17)

[0281] According to the display device of (15), the display device receives input from an external device in a specific format of input data containing image data and synchronization signals. (18)

[0283] According to the display device of (15), image data is input synchronously with a first clock as an input clock, and black data is inserted into the image data synchronously with a second clock generated inside the display device. (19)

[0285] According to (1), the display device is part of a wearable electronic device. (20)

[0287] According to the display device of (19), the electronic device is a head-mounted display including the display device, and the display start position is determined based on the eye position of the user wearing the head-mounted display.

[0288] Reference Symbol List

[0289] 1 Display device

[0290] 2 External devices

[0291] 11 Data Input Interface

[0292] 12. Timer Controller

[0293] 13 Display Controller

[0294] 14 Display Units

[0295] 15 Oscillators

[0296] 16 Serial Interface

[0297] 17 Registers

[0298] 18 Electronic fuses

[0299] 20 MIPI DSI interface

[0300] 20' MIPI DSI interface

[0301] 21. Clock Control Unit

[0302] 22 Synchronization signal generation unit

[0303] 23 Serial-to-Parallel Conversion Unit

[0304] 24 Command Interface

[0305] 25-line memory

[0306] 31 Clock Generation Unit

[0307] 32 Timed Generation Unit

[0308] 33 Image Processing Units

[0309] 34 Brightness control unit

[0310] 41 Vertical Logic Circuits

[0311] 42 Horizontal Logic Circuits

[0312] 43 Shift Register

[0313] 44 Selector

[0314] 45 triggers

[0315] 46 Selector Switch

[0316] 47 Address Decoder

[0317] 51-pixel array

[0318] 52 Vertical Drivers

[0319] 53 Horizontal Driver

[0320] 54 Gamma correction circuit

[0321] 110 Head-mounted Display

[0322] 111 Display Unit

[0323] 112 Ear hook part

[0324] 120 Head-Mounted Display

[0325] 121 Main Body

[0326] 122 Arm

[0327] 123 Lens tube section 123

[0328] 128 Glasses

[0329] 129 Lens

[0330] 130 digital camera

[0331] 131 Camera body

[0332] 132 Imaging Lens Units

[0333] 133 Grip section

[0334] 134 monitor

[0335] 135 Electronic Viewfinder

[0336] 140 Television Unit

[0337] 141 Image display screen section

[0338] 142 Front Panel

[0339] 143 Filter Glass

[0340] 150 smartphones

[0341] 151 display units

[0342] 152 operating units

[0343] 200 vehicles

[0344] 201 Central Display

[0345] 202 Console Display

[0346] 203 Head-up Display

[0347] 204 Digital Rearview Mirror

[0348] 205 Steering Wheel Display

[0349] 206 Rear Seat Entertainment Monitor

[0350] 261 Dashboard

[0351] 262 Driver's Seat

[0352] 263 passenger seats

[0353] 264 Central Control Console

[0354] 265 gear shift lever

[0355] 266 Windshield

[0356] 267. Steering wheel.

Claims

1. A display device comprising: a pixel array section in which a plurality of pixels are arranged in a two-dimensional array; a memory that receives image data as input and temporarily stores the image data; an image processing unit that inserts black data into the image data output from the memory and generates output data; a vertical logic circuit that controls a vertical driver that determines a display position of the output data in a vertical direction; and a horizontal logic circuit that controls a horizontal driver that supplies a gray scale voltage corresponding to a gray scale information of the output data to each pixel of the output data in a horizontal direction; wherein an insertion position of the black data and the display position in the vertical direction are determined based on a display start position specified by a user. The image data is input in synchronization with a timing of a first clock that is an input clock, and the black data is inserted into the image data in synchronization with a timing of a second clock that is generated inside the display device.

2. The display device according to claim 1, wherein A clock frequency of the second clock is higher than a clock frequency of the first clock.

3. The display device according to claim 2, wherein 4. The display device according to claim 2, further comprising: an oscillator or a PLL circuit, wherein the second clock is generated by the oscillator or the PLL circuit.

5. The display device according to claim 1, the vertical driver includes: wherein one or more flip-flops that perform a shift operation, one or more selection switches that are connected to the one or more flip-flops and supply a selection pulse to the pixel array section, and a selector that supplies a vertical start pulse to the one or more flip-flops, and the selector includes an n-th group of shift registers (n is a natural number) connected to a leading flip-flop among the one or more flip-flops. The selector to which the vertical start pulse is input and the shift register that starts to supply the selection pulse to the pixel array section are both determined based on the display start position.

6. The display device of claim 5, wherein, The vertical driver performs a blank transmission in which a scan operation is performed by advancing the vertical start pulse with respect to the output data, and determines the display start position in the vertical direction.

7. The display device according to claim 5, wherein A line that performs the blank transmission becomes a black area.

8. The display device of claim 7, wherein, The memory is a line memory or a frame memory.

9. The display device according to claim 1, wherein The memory is provided on an output side of a data input interface that receives the image data as input.

10. The display device according to claim 1, wherein The display device receives input from an external device in an input data format of a specific format that contains the image data and a synchronization signal.

11. The display device according to claim 1, wherein A light emitting element included in the pixel is an organic EL element or a liquid crystal element.

12. The display device of claim 1, wherein, The vertical driver includes one or more address decoders that receive an address signal indicating the display start position in the vertical direction as input to determine the display start position.

13. The display device of claim 1, wherein, The horizontal driver subjects a potential state of a signal line of the pixel in the black area to a fixed processing.

14. The display device of claim 8, wherein, 15. A display device comprising: a pixel array section in which a plurality of pixels are arranged in a two-dimensional array; ​ a first horizontal logic circuit that receives image data as input and temporarily stores the image data; an image processing unit that inserts black data into the image data output from the first horizontal logic circuit and generates output data; a vertical logic circuit that controls a vertical driver that determines a display position of the output data in a vertical direction; and a second horizontal logic circuit that controls a horizontal driver that provides a gray voltage corresponding to gray information of the output data to each pixel of the output data in a horizontal direction; wherein an insertion position of the black data and the display position in the vertical direction are determined based on a display start position specified by a user.

16. The display device of claim 1, wherein, Inserting the black data into the image data is performed after output of a timing controller that controls an operation timing of a display controller including the vertical logic circuit and the horizontal logic circuit.

17. The display device of claim 15, wherein, A display device receives input from an external device in an input data format of a specific format that contains image data and a synchronization signal.

18. The display device of claim 15, wherein, The image data is input in synchronization with timing of a first clock that is an input clock, and the black data is inserted into the image data in synchronization with timing of a second clock that is generated inside the display device.

19. The display device of claim 1, wherein, The display device is part of a wearable electronic device.

20. The display device of claim 19, wherein, The electronic device is a head-mounted display including the display device, and the display start position is determined based on a line-of-sight position of a user wearing the head-mounted display.

Images