Cancer cell impedance spectrum detection system and method based on FPGA digital orthogonal phase locking

Abstract

The invention discloses a cancer cell impedance spectrum detection system and method based on FPGA digital orthogonal phase locking, and the method comprises the steps: S1, carrying out phase accumulation and table look-up operation based on a target excitation frequency, and generating a digital sinusoidal signal and a digital cosine signal; s2, converting the digital sinusoidal signal into an analog excitation signal, applying the analog excitation signal to a to-be-detected biological sample, collecting a response signal flowing through the to-be-detected biological sample, and converting the response signal into a digital response signal; s3, multiplying the digital response signal with the digital sinusoidal signal and the digital cosine signal to generate an in-phase frequency mixing signal and an orthogonal frequency mixing signal; s4, performing multi-stage down-sampling and low-pass filtering processing on the in-phase mixing signal and the orthogonal mixing signal to generate an in-phase baseband signal and an orthogonal baseband signal; s5, performing coordinate transformation operation on the in-phase baseband signal and the orthogonal baseband signal to generate impedance amplitude data and impedance phase data; and S6, packaging and outputting the impedance amplitude data and the impedance phase data.

Description

Technical Field

[0001] This invention relates to bioimpedance spectroscopy analysis technology, and more particularly to a cancer cell impedance spectroscopy detection system and method based on FPGA digital orthogonal phase-locked loop. Background Technology

[0002] Bioimpedance spectroscopy, as a label-free and non-destructive cell detection method, has shown great potential in cancer diagnosis, drug screening, and cell biology research. Cancer cells, due to significant differences in their physiological morphology and structure, such as cell membrane capacitance and cytoplasmic conductivity, compared to normal cells, exhibit unique electrical impedance response characteristics under alternating electric fields. By accurately measuring these impedance differences, effective identification and state analysis of cancer cells can be achieved, providing a new technical approach for early clinical diagnosis.

[0003] However, existing bioimpedance spectroscopy detection technologies still suffer from numerous technical limitations when applied to clinical-grade cancer cell detection. First, in the electrolyte environment of microfluidic chips, the measurement signal is susceptible to polarization effects at the electrode-electrolyte interface, electrode drift, and external electromagnetic interference. Traditional dual-electrode systems struggle to effectively suppress common-mode noise, leading to unstable background signals and severely impacting measurement sensitivity. Second, the impedance changes generated by a single cell are extremely weak, with response currents typically in the nanoampere or even picoampere range, making them highly susceptible to thermal noise and environmental interference, imposing stringent requirements on the system's signal-to-noise ratio. Third, acquiring a complete impedance spectrum requires frequency scanning, presenting a technical bottleneck in achieving rapid detection while maintaining measurement accuracy, making it difficult to balance the conflict between integration time and frequency sweep speed. Furthermore, existing detection systems are mostly built with discrete components, resulting in large size and high cost, hindering miniaturization and portability, and limiting their application in point-of-care testing devices.

[0004] Therefore, there is an urgent need to develop a highly sensitive, interference-resistant, rapid, and easily integrated impedance spectroscopy detection system and method for cancer cells. Summary of the Invention

[0005] This invention provides a cancer cell impedance spectroscopy detection system and method based on FPGA digital quadrature phase-locked loop to solve the above-mentioned problems in the prior art.

[0006] To achieve the above objectives, the present invention provides the following technical solution: An impedance spectroscopy detection method for cancer cells based on FPGA digital quadrature phase-locked loop includes: S1: Based on the target excitation frequency, perform phase accumulation and table lookup operations to generate digital sine and digital cosine signals; S2: Convert the digital sinusoidal signal into an analog excitation signal and apply it to the biological sample to be tested, collect the response signal flowing through the biological sample to be tested and convert it into a digital response signal; S3: Multiply the digital response signal with the digital sine signal and the digital cosine signal respectively to generate an in-phase mixer signal and a quadrature mixer signal; S4: Perform multi-stage downsampling and low-pass filtering on the in-phase and quadrature mixed signals to generate in-phase and quadrature baseband signals; S5: Perform coordinate transformation operations on in-phase and quadrature baseband signals to generate impedance amplitude data and impedance phase data; S6: Encapsulate and output the impedance amplitude data and impedance phase data.

[0007] Furthermore, step S1 includes: S11: Calculate the frequency control word based on the target excitation frequency and the system clock frequency; S12: The frequency control word is accumulated using a phase accumulator to generate a phase address; S13: Input the phase address into the sine lookup table and the cosine lookup table respectively, and generate the initial sine signal and the initial cosine signal by looking up the tables; S14: Perform pipelined delay alignment processing on the initial sine and initial cosine signals to generate digital sine and digital cosine signals with a phase difference of one-quarter of a cycle.

[0008] Furthermore, the storage depth of the sine lookup table and the cosine lookup table is determined by the bit width of the phase address. The sine lookup table stores the discrete sampled values ​​of the sine function within one period, and the cosine lookup table stores the discrete sampled values ​​of the cosine function within one period.

[0009] Furthermore, step S2 includes: S21: Convert the digital sine wave signal into an analog excitation voltage using a digital-to-analog converter; S22: Apply the simulated excitation voltage to the excitation electrode of the biological sample to be tested; S23: The response current flowing through the biological sample to be tested is converted into a response voltage through a transimpedance amplifier; S24: Sample the response voltage using an analog-to-digital converter to generate a digital response signal.

[0010] Furthermore, step S3 includes: S31: The digital response signal and the digital sine signal are multiplied point by point by the first digital multiplier to generate an in-phase mixer signal; S32: The digital response signal and the digital cosine signal are multiplied point by point by the second digital multiplier to generate an orthogonal mixing signal.

[0011] Furthermore, step S4 includes: S41: Input the in-phase mixer signal and the quadrature mixer signal into the first-stage integral comb filter respectively for downsampling processing at the first downsampling rate to generate the first-stage downsampled signal; S42: Input the first-stage downsampled signal into the second-stage integral comb filter for downsampling processing at the second downsampling rate to generate the second-stage downsampled signal; S43: Input the second-stage downsampled signal into the third-stage integral comb filter for downsampling processing at the third downsampling rate to generate the third-stage downsampled signal; S44: Input the third-stage downsampled signal into the finite impulse response filter for low-pass filtering to generate in-phase baseband signal and quadrature baseband signal; Among them, the first downsampling rate is greater than the second downsampling rate, and the second downsampling rate is greater than the third downsampling rate.

[0012] Furthermore, step S5 includes: S51: Use the in-phase baseband signal as the horizontal axis input value and the quadrature baseband signal as the vertical axis input value; S52: Rotate the x-coordinate input value and y-coordinate input value in the rectangular coordinate system to the polar coordinate system through iterative rotation operation to generate the modulus output and angle output; S53: The magnitude output is used as impedance amplitude data, and the angle output is used as impedance phase data.

[0013] Furthermore, step S6 includes: S61: Combine the impedance amplitude data and impedance phase data with the preset frame header identifier; S62: Calculate the checksum for the combined data; S63: Encapsulate the frame header identifier, impedance amplitude data, impedance phase data, and checksum into a data frame according to a predetermined format; S64: Outputs data frames to external devices via a serial communication interface.

[0014] Furthermore, a cancer cell impedance spectroscopy detection system based on FPGA digital quadrature phase-locked loop includes: The digital direct frequency synthesis module is located inside the FPGA and includes a phase accumulator, a sine lookup table, and a cosine lookup table. The phase accumulator is used to accumulate phase based on the input frequency control word to generate a phase address. The sine lookup table and the cosine lookup table are used to look up the phase address and output digital sine and digital cosine signals, respectively. A digital-to-analog converter, whose input is connected to the sinusoidal signal output of a digital direct frequency synthesis module, is used to convert digital sinusoidal signals into analog excitation voltages; A transimpedance amplifier, whose input is connected to the detection electrode of the biological sample to be tested, is used to convert the response current flowing through the biological sample to the response voltage. An analog-to-digital converter, whose input is connected to the output of a transimpedance amplifier, is used to convert the sampled response voltage into a digital response signal; The digital quadrature mixer module, located inside the FPGA, includes a first digital multiplier and a second digital multiplier. The two inputs of the first digital multiplier receive a digital response signal and a digital sine signal, respectively, and the two inputs of the second digital multiplier receive a digital response signal and a digital cosine signal, respectively. A multi-stage digital filtering module, located inside the FPGA, includes a cascaded first-stage integral comb filter, a second-stage integral comb filter, a third-stage integral comb filter, and a finite impulse response filter, used to downsample and filter the output signals of the first and second digital multipliers. The coordinate transformation module, located inside the FPGA, has its input connected to the output of the multi-stage digital filtering module. It is used to convert the filtered in-phase and quadrature signals into impedance amplitude data and impedance phase data. The data encapsulation communication module, located inside the FPGA, has its input connected to the output of the coordinate transformation module. It is used to encapsulate impedance amplitude data and impedance phase data into data frames and output them through a serial interface.

[0015] Compared with the prior art, the present invention has the following advantages: A fully digital quadrature lock-in amplification system and method based on field-programmable gate array (FPGA) for detecting weak impedance signals in cancer cells. Compared to existing technologies, this invention uses a three-electrode system with two cross-group amplifiers and one differential amplifier to initially achieve noise reduction. It integrates a high-precision signal source (DDS), digital mixer, multi-stage filter chain, coordinate transformation module (CORDIC), and communication interface all onto a single FPGA chip, significantly reducing system size and hardware costs, laying the foundation for developing portable, low-cost point-of-care testing devices. Because the core demodulation and filtering processes are implemented entirely in the digital domain, the temperature drift, noise, and nonlinearity problems caused by analog devices are completely eliminated. The system exhibits extremely high signal-to-noise ratio, long-term stability, and excellent measurement repeatability. By modifying the FPGA's logic code, key parameters such as the excitation signal frequency, filter cutoff frequency, and system bandwidth can be easily adjusted to adapt to the detection needs of different types of cancer cells or biological samples, greatly shortening the development cycle. The powerful parallel processing capability of the FPGA allows it to easily replicate multiple digital phase-locked loop processing channels within a single chip, enabling parallel, high-speed scanning and impedance imaging of microelectrode arrays, with a detection throughput far exceeding that of traditional instruments.

[0016] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention.

[0017] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0018] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 This is a flowchart of a cancer cell impedance spectroscopy detection method based on FPGA digital quadrature phase-locked loop in an embodiment of the present invention; Figure 2 This is a block diagram of the overall structure of a cancer cell impedance spectroscopy detection system based on FPGA digital quadrature phase-locked loop in an embodiment of the present invention. Detailed Implementation

[0019] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0020] Example 1: The embodiments of the present invention provide, as follows Figure 1 As shown, a method for detecting the impedance spectrum of cancer cells based on FPGA digital quadrature phase-locked loop includes: S1: Based on the target excitation frequency, perform phase accumulation and table lookup operations to generate digital sine and digital cosine signals; S2: Convert the digital sinusoidal signal into an analog excitation signal and apply it to the biological sample to be tested, collect the response signal flowing through the biological sample to be tested and convert it into a digital response signal; S3: Multiply the digital response signal with the digital sine signal and the digital cosine signal respectively to generate an in-phase mixer signal and a quadrature mixer signal; S4: Perform multi-stage downsampling and low-pass filtering on the in-phase and quadrature mixed signals to generate in-phase and quadrature baseband signals; S5: Perform coordinate transformation operations on in-phase and quadrature baseband signals to generate impedance amplitude data and impedance phase data; S6: Encapsulate and output the impedance amplitude data and impedance phase data.

[0021] The following is a detailed description with reference to specific embodiments.

[0022] This embodiment provides a method for detecting the impedance spectrum of cancer cells based on FPGA digital quadrature phase-locked loop, which includes the following steps: S1: Perform phase accumulation and table lookup operations based on the target excitation frequency to generate digital sine and digital cosine signals.

[0023] Specifically, step S1 includes: S11: Calculate the frequency control word based on the target excitation frequency and the system clock frequency. In this embodiment, the system master clock clk is 50MHz.

[0024] S12: The phase accumulator performs an accumulation operation on the frequency control word to generate the phase address. The phase accumulator adds the frequency control word to the current phase value in each clock cycle, and the high-order bits of the accumulation result are output as the phase address.

[0025] S13: Input the phase address into the sine lookup table and cosine lookup table respectively, and generate the initial sine and initial cosine signals by looking up the tables. The storage depth of the sine and cosine lookup tables is determined by the bit width of the phase address. The sine lookup table stores the discrete sampled values ​​of the sine function within one period, and the cosine lookup table stores the discrete sampled values ​​of the cosine function within one period. The lookup tables are implemented using ROM and store the pre-calculated sine and cosine function values.

[0026] S14: Pipeline delay alignment is performed on the initial sine and cosine signals to generate digital sine signals osin and ocos with a phase difference of one-quarter of a cycle. Since the DDSCompilerIP core inside the FPGA has different pipeline delays when generating sine and cosine signals, the pipeline delay difference between the two outputs is accurately measured through simulation. A pipeline register is added to the FPGA logic to compensate for the delay of the faster signal, ensuring that the osin and ocos signals ultimately provided to the mixer are strictly orthogonal with a precise phase difference of 90 degrees.

[0027] S2: Convert the digital sinusoidal signal into an analog excitation signal and apply it to the biological sample to be tested. Collect the response signal flowing through the biological sample to be tested and convert it into a digital response signal.

[0028] Specifically, step S2 includes: S21: The digital sine wave signal osin is converted into an analog excitation voltage V_exc via a digital-to-analog converter (DAC). The DAC receives the digital sine wave signal output from the FPGA and converts it into a continuous analog voltage signal.

[0029] Bidirectional lock-in amplifier principle: The signal received by the DAC is: SI(t) = AIsin(ωt+φ) + B(t), where AIsin(ωt+φ) is the useful signal and B(t) is noise. The two reference signals emitted by the DDS are: Ssin(t)=ARsin(ωt+δ), Scos(t)=ARcos(ωt+δ) The two signals are 90 degrees out of phase. Multiplying the received signal by the two reference signals yields: Sp = SI(t)Ssin(t) =[AIsin(ωt+φ)+B(t)]ARsin(ωt+δ) =0.5AIAR AIARcos(2ωt+φ+δ)+ARB(t)sin(ωt+δ)= Sq = SI(t)Scos(t) =[AIsin(ωt+φ)+B(t)]ARcos(ωt+δ) =0.5AIAR AIARsin(2ωt+φ+δ)+ARB(t)cos(ωt+δ) Their output consists of three parts: the first part is a DC signal; the second part is a signal at twice the frequency, which can be filtered out by a low-pass filter; and the third part is the product of noise and the reference signal. Because the sinusoidal signal is periodic and uncorrelated with the noise signal, this integral is 0 (and will be filtered out by the LPF). Passing Sp and Sq through the low-pass filter yields: The amplitude and phase of the input signal can be calculated using X and Y, and this calculation is noise-free. θ = = arctan S22: Apply the simulated excitation voltage V_exc to the excitation electrode of the biological sample to be tested. In this embodiment, the biological sample to be tested is a cancer cell in a microfluidic chip, and the simulated excitation voltage is applied to the electrolyte environment where the cancer cell is located through the excitation electrode of the microfluidic chip.

[0030] S23: The response current I_resp flowing through the biological sample under test is converted into a response voltage V_resp by a transimpedance amplifier (TIA). When an alternating electric field is applied to cancer cells, a weak response current is generated, typically in the nanoampere (nA) or even picoampere (pA) range. The transimpedance amplifier converts this weak current signal into a measurable voltage signal, and the amplitude and phase of the response voltage V_resp carry information about the cell impedance.

[0031] S24: The response voltage V_resp is sampled by an analog-to-digital converter (ADC) to generate a digital response signal adc_data. In this embodiment, the ADC samples the response voltage at a rate of 25MHz, digitizes the analog signal, and then sends it to the FPGA for further processing.

[0032] S3: Multiply the digital response signal with the digital sine signal and the digital cosine signal respectively to generate the in-phase mixer signal and the quadrature mixer signal.

[0033] Specifically, step S3 includes: S31: The digital response signal adc_data is multiplied point by point by the digital sine signal osin through the first digital multiplier to generate the in-phase mixer signal product_I.

[0034] S32: The digital response signal adc_data is multiplied point by point with the digital cosine signal ocos by the second digital multiplier to generate the quadrature mixing signal product_Q.

[0035] The mixed signal consists of three parts: the first part is the DC signal component, which contains the amplitude and phase information of the signal under test; the second part is the second harmonic signal component; and the third part is the product of noise and the reference signal. This process shifts the signal's spectrum to zero frequency (baseband) and the second harmonic.

[0036] S4: Perform multi-stage downsampling and low-pass filtering on the in-phase and quadrature mixed signals to generate in-phase and quadrature baseband signals.

[0037] Specifically, step S4 includes: S41: The in-phase mixer signal product_I and the quadrature mixer signal product_Q are respectively input into the first-stage integrator comb filter CIC1 for downsampling processing at the first downsampling rate to generate the first-stage downsampled signal. In this embodiment, the downsampling rate of the first-stage CIC filter is 25 times, reducing the sampling rate from 50MHz to 2MHz.

[0038] S42: The first-stage downsampled signal is input into the second-stage integrator-comb filter CIC2 for downsampling at the second downsampling rate, generating the second-stage downsampled signal. The downsampling rate of the second-stage CIC filter is 20 times, reducing the sampling rate from 2MHz to 100kHz.

[0039] S43: The second-stage downsampled signal is input into the third-stage integrator-comb filter (CIC3) for downsampling at the third downsampling rate, generating the third-stage downsampled signal. The downsampling rate of the third-stage CIC filter is 10 times, reducing the sampling rate from 100kHz to 10kHz. By cascading the three CIC filters, a total downsampling rate of 5000 times (25×20×10=5000) is achieved.

[0040] The first downsampling rate (25x) is greater than the second downsampling rate (20x), and the second downsampling rate (20x) is greater than the third downsampling rate (10x). This multi-level downsampling and progressive gain compensation strategy effectively controls the data bit width, preventing data overflow and precision loss while ensuring anti-aliasing performance.

[0041] S44: The third-stage downsampled signal is input into a Finite Impulse Response (FIR) filter for low-pass filtering, generating an in-phase baseband signal `filtered_I` and a quadrature baseband signal `filtered_Q`. In this embodiment, the FIR filter is of order 101, and its coefficients are designed using Python's SciPy library to achieve a cutoff frequency of 10Hz. The coefficients are quantized as 16-bit integers and loaded into the Vivado FIRCompiler IP core as a COE file. This FIR filter is used to precisely set the system measurement bandwidth, filter out second harmonic components and broadband noise, and compensate for the passband attenuation caused by the CIC filter, ultimately outputting an extremely smooth and clean DC signal.

[0042] Since the sine and cosine reference signals are periodic and not correlated with the noise signal, the noise term is zero after integration and will be filtered out by the low-pass filter.

[0043] S5: Perform coordinate transformation operations on in-phase and quadrature baseband signals to generate impedance amplitude data and impedance phase data.

[0044] Specifically, the S5 steps include: S51: Use the in-phase baseband signal filtered_I as the horizontal axis input value X_IN, and the quadrature baseband signal filtered_Q as the vertical axis input value Y_IN. In this embodiment, both filtered_I and filtered_Q are 16-bit data.

[0045] S52: The x-coordinate and y-coordinate input values ​​in the Cartesian coordinate system are rotated to the polar coordinate system through iterative rotation operations, generating the magnitude and angle outputs. This embodiment uses the CORDIC (COordinate Rotation Digital Computer) algorithm to implement coordinate transformation. The CORDIC algorithm is an efficient iterative algorithm that achieves the conversion between coordinate systems through a series of simple addition, subtraction, and shift operations. The CORDIC module is configured in "Cartesian to Polar Coordinate Transformation (Vector Translation)" mode, rotating the input vector iteratively to align it with the x-axis, thereby calculating the vector's magnitude and angle.

[0046] S53: The magnitude output is used as impedance amplitude data (Magnitude), and the angle output is used as impedance phase data (Phase). The amplitude and phase of the input signal can be calculated using X and Y values. θ= =arctan In this embodiment, the CORDIC kernel efficiently calculates... It outputs 16-bit amplitude and phase results. Since the core demodulation and filtering processes are implemented entirely in the digital domain, the temperature drift, noise, and nonlinearity problems caused by analog devices are completely eliminated, and the obtained impedance amplitude and phase data have extremely high accuracy and stability.

[0047] S6: Encapsulate and output the impedance amplitude data and impedance phase data.

[0048] Specifically, step S6 includes: S61: Combine the impedance amplitude data (Magnitude) and impedance phase data (Phase) with a preset frame header identifier. In this embodiment, the frame header identifier is a fixed value of 0xAA, used to identify the start position of the data frame.

[0049] S62: Calculate the checksum for the combined data. The checksum is obtained by summing the impedance amplitude data and the impedance phase data, and is used by the receiver to verify the integrity of the data.

[0050] S63: Encapsulate the frame header identifier, impedance amplitude data, impedance phase data, and checksum into a data frame according to a predetermined format. In this embodiment, the data frame format is: 1-byte frame header (0xAA) + 2-byte amplitude data high and low bytes + 2-byte phase data high and low bytes + 1-byte checksum, totaling 6 bytes.

[0051] S64: Output the data frame to an external device via the serial communication interface. In this embodiment, a UART (Universal Asynchronous Receiver / Transmitter) interface is used to send the data frame to the host computer at a baud rate of 115200. The host computer receives, parses, and plots the data in real time using a Python script to visualize the impedance spectrum.

[0052] By modifying the FPGA's logic code, key parameters such as the excitation signal frequency, filter cutoff frequency, and system bandwidth can be easily adjusted to meet the detection needs of different types of cancer cells or biological samples. Simultaneously, the FPGA's powerful parallel processing capabilities allow it to easily replicate multiple digital phase-locked loop (PLL) processing channels within a single chip, enabling parallel, high-speed scanning and impedance imaging of microelectrode arrays.

[0053] Example 2: This invention provides an FPGA-based digital quadrature phase-locked loop (QPL) system for detecting the impedance spectrum of cancer cells, comprising: The digital direct frequency synthesis module is located inside the FPGA and includes a phase accumulator, a sine lookup table, and a cosine lookup table. The phase accumulator is used to accumulate phase based on the input frequency control word to generate a phase address. The sine lookup table and the cosine lookup table are used to look up the phase address and output digital sine and digital cosine signals, respectively. A digital-to-analog converter, whose input is connected to the sinusoidal signal output of a digital direct frequency synthesis module, is used to convert digital sinusoidal signals into analog excitation voltages; A transimpedance amplifier, whose input is connected to the detection electrode of the biological sample to be tested, is used to convert the response current flowing through the biological sample to the response voltage. An analog-to-digital converter, whose input is connected to the output of a transimpedance amplifier, is used to convert the sampled response voltage into a digital response signal; The digital quadrature mixer module, located inside the FPGA, includes a first digital multiplier and a second digital multiplier. The two inputs of the first digital multiplier receive a digital response signal and a digital sine signal, respectively, and the two inputs of the second digital multiplier receive a digital response signal and a digital cosine signal, respectively. A multi-stage digital filtering module, located inside the FPGA, includes a cascaded first-stage integral comb filter, a second-stage integral comb filter, a third-stage integral comb filter, and a finite impulse response filter, used to downsample and filter the output signals of the first and second digital multipliers. The coordinate transformation module, located inside the FPGA, has its input connected to the output of the multi-stage digital filtering module. It is used to convert the filtered in-phase and quadrature signals into impedance amplitude data and impedance phase data. The data encapsulation communication module, located inside the FPGA, has its input connected to the output of the coordinate transformation module. It is used to encapsulate impedance amplitude data and impedance phase data into data frames and output them through a serial interface.

[0054] The following is a detailed description with reference to specific embodiments.

[0055] This embodiment provides an FPGA-based digital quadrature phase-locked loop (QPL) cancer cell impedance spectroscopy detection system applied to the method described in Embodiment 1, such as... Figure 2 As shown, the system consists of two parts: an analog front-end and an FPGA digital processing core.

[0056] The Digital Direct Frequency Synthesis (DDS) module is located inside the FPGA and includes a phase accumulator, a sine lookup table, and a cosine lookup table. The phase accumulator is used to accumulate phases based on the input frequency control word to generate a phase address. The sine and cosine lookup tables output digital sine signals osin and ocos signals respectively based on the phase address.

[0057] In this embodiment, the DDS module is implemented by instantiating a DDSCompilerIP core inside the FPGA, configuring its output to be sine and cosine signals. The phase accumulator accumulates the frequency control word in each system clock cycle (50MHz), and the generated phase addresses are sent to the sine lookup table and cosine lookup table, respectively. The lookup tables are implemented in ROM form, storing discrete sampled values ​​of the sine and cosine functions for one complete cycle.

[0058] To ensure that the output sine and cosine signals are strictly orthogonal, this embodiment accurately measures the pipeline delay difference between the two outputs through simulation and adds a pipeline register to the FPGA logic to compensate for the delay of the faster signal, so that the phase difference between the osin and ocos signals finally provided to the subsequent mixer is exactly 90 degrees. The digital sine signal osin is sent to the digital-to-analog converter (DAC).

[0059] The input of the digital-to-analog converter (DAC) is connected to the sinusoidal signal output of the digital direct frequency synthesis module, used to convert the digital sinusoidal signal osin into an analog excitation voltage V_exc. The DAC receives the digital sinusoidal signal from the FPGA, converts it into a continuous analog voltage signal, and applies it to the electrolyte environment of the cancer cells being tested in the microfluidic chip through the excitation electrodes.

[0060] The input of the transimpedance amplifier (TIA) is connected to the detection electrode of the biological sample to convert the response current I_resp flowing through the sample into a response voltage V_resp. When an analog excitation voltage is applied to cancer cells, a weak response current is generated, typically in the nanoampere (nA) or even picoampere (pA) range. The transimpedance amplifier converts this extremely weak current signal into a measurable voltage signal, the amplitude and phase of which carry information about the cell impedance.

[0061] In this embodiment, to more effectively eliminate interference from common-mode noise and electrode polarization effects, the system employs a three-electrode configuration (excitation electrode, working electrode, and reference electrode), along with two transimpedance amplifiers and a differential amplifier for initial noise reduction. Common-mode interference signals on the working and reference electrodes cancel each other out through the differential amplifier, thereby extracting the differential-mode signal caused by a single cancer cell, significantly improving measurement sensitivity and baseline stability.

[0062] The input of the analog-to-digital converter (ADC) is connected to the output of the transimpedance amplifier to sample and convert the response voltage V_resp into a digital response signal adc_data. In this embodiment, the ADC samples the response voltage at a high speed of 25MHz, digitizes the analog signal, and then sends it to the FPGA for subsequent digital signal processing. The high sampling rate ensures sufficient sampling of the signal, providing a good foundation for subsequent digital filtering and downsampling.

[0063] The digital quadrature mixer module is located inside the FPGA and includes a first digital multiplier and a second digital multiplier. The two inputs of the first digital multiplier receive the digital response signal adc_data and the digital sine signal osin, respectively, and output the in-phase mixer signal product_I. The two inputs of the second digital multiplier receive the digital response signal adc_data and the digital cosine signal ocos, respectively, and output the quadrature mixer signal product_Q.

[0064] Two digital multipliers operate in parallel within the FPGA, multiplying the digital response signal acquired by the ADC point-by-point with the quadrature reference signal generated by the DDS, thus achieving quadrature demodulation in the digital domain. The spectrum of the mixed signal is shifted to the baseband (zero frequency) and second harmonics, creating conditions for subsequent low-pass filtering.

[0065] The multi-stage digital filtering module is located inside the FPGA and includes a cascaded first-stage integral comb filter CIC1, a second-stage integral comb filter CIC2, a third-stage integral comb filter CIC3, and a finite impulse response filter FIR, which are used to downsample and filter the output signals of the first and second digital multipliers.

[0066] The first-stage integral comb filter CIC1 receives the in-phase mixing signal product_I and the quadrature mixing signal product_Q from the digital quadrature mixer module, and performs a 25x downsampling, reducing the sampling rate from 50MHz to 2MHz.

[0067] The second-stage integral comb filter CIC2 receives the output signal from the first stage and performs a 20-fold downsampling, reducing the sampling rate from 2MHz to 100kHz.

[0068] The third-stage integral comb filter CIC3 receives the output signal from the second stage and performs a 10-fold downsampling, reducing the sampling rate from 100kHz to 10kHz.

[0069] By cascading three CIC filters, a high-efficiency downsampling rate of 5000 times was achieved. The multi-stage downsampling and step-by-step gain compensation strategy effectively controlled the data bit width while ensuring anti-aliasing performance, preventing data overflow and precision loss.

[0070] The Finite Impulse Response (FIR) filter receives the output signal from the third-stage CIC filter and performs fine low-pass filtering. In this embodiment, the FIR filter is a 101st-order filter with a cutoff frequency of 10Hz. Its coefficients are designed using the window function method in Python's SciPy library, quantized into 16-bit integers, and loaded into the Vivado FIRCompiler IP core as a COE file. The FIR filter precisely sets the system measurement bandwidth, filters out second harmonic components and broadband noise, compensates for the passband attenuation caused by the CIC filter, and finally outputs extremely smooth and clean in-phase baseband signal filtered_I and quadrature baseband signal filtered_Q.

[0071] Since the core demodulation and filtering processes are implemented entirely in the digital domain, the temperature drift, noise, and nonlinearity problems caused by analog devices are completely eliminated, resulting in a system with extremely high signal-to-noise ratio, long-term stability, and excellent measurement repeatability.

[0072] The coordinate transformation module is located inside the FPGA, and its input is connected to the output of the multi-stage digital filtering module. It is used to convert the filtered in-phase signal filtered_I and the quadrature signal filtered_Q into impedance amplitude data Magnitude and impedance phase data Phase.

[0073] In this embodiment, the coordinate transformation module is implemented by instantiating the CORDICIP core and configured in "Cartesian to Polar Coordinate Conversion (VectorTranslation)" mode. A 16-bit filtered_I is used as the x-coordinate input value (X_IN), and a 16-bit filtered_Q is used as the y-coordinate input value (Y_IN). The CORDIC core efficiently calculates Magnitude = sqrt(I^2 + Q^2) and Phase = atan2(I, Q) using an iterative rotation algorithm, and outputs 16-bit magnitude and phase results.

[0074] The CORDIC algorithm requires only simple addition, subtraction, and shift operations, eliminating the need for complex multiplication and division, making it highly efficient for FPGA implementation. The coordinate transformation module directly outputs the amplitude and phase of the signal, facilitating subsequent data analysis and impedance spectrum plotting.

[0075] The data encapsulation and communication module is located inside the FPGA. Its input is connected to the output of the coordinate transformation module. It is used to encapsulate the impedance amplitude data (Magnitude) and impedance phase data (Phase) into data frames and output them through a serial interface.

[0076] Specifically, the data encapsulation communication module combines the 16-bit impedance amplitude data and 16-bit impedance phase data with a preset frame header identifier (0xAA) and calculates a checksum. The checksum is obtained by summing the amplitude and phase data. Then, the frame header identifier, impedance amplitude data, impedance phase data, and checksum are encapsulated into a 6-byte data frame according to a predetermined format: 1-byte frame header + 2-byte amplitude data + 2-byte phase data + 1-byte checksum.

[0077] The encapsulated data frame is sent to an external device (such as a host computer) via the UART serial communication interface at a baud rate of 115200. The host computer receives and parses the data frame using a Python script, verifies the checksum, extracts amplitude and phase information, and performs real-time plotting to visualize and analyze the impedance spectrum.

[0078] The system operates under a 50MHz system clock. The DDS module generates digital sine and cosine signals based on the target excitation frequency. The digital sine signals are converted into analog excitation voltages by a DAC and applied to the cancer cells under test. The response current flowing through the cells is converted into a response voltage by a TIA, and then digitized into a digital response signal by an ADC at a sampling rate of 25MHz. After entering the FPGA, the digital response signal is multiplied by orthogonal sine and cosine reference signals in the digital quadrature mixer module to obtain in-phase and quadrature mixed signals. These two signals are downsampled to 10kHz by a three-stage CIC filter cascade, and then finely filtered by a 101st-order FIR filter to obtain a clean baseband signal. The coordinate transformation module converts the baseband signal into amplitude and phase data in polar coordinate form, and finally, the data encapsulation and communication module encapsulates it into a data frame and outputs it through the UART interface.

[0079] This system features high integration and miniaturization, integrating a high-precision signal source (DDS), digital mixer, multi-stage filter chain, coordinate transformation module (CORDIC), and communication interface onto a single FPGA chip. This significantly reduces the system size and hardware costs, laying the foundation for developing portable, low-cost real-time detection devices.

[0080] The system boasts exceptional performance and stability. Since the core demodulation and filtering processes are implemented entirely in the digital domain, it completely eliminates the temperature drift, noise, and nonlinearity issues caused by analog devices. The system exhibits extremely high signal-to-noise ratio, long-term stability, and excellent measurement repeatability.

[0081] The system has extremely high design flexibility and reconfigurability. By modifying the FPGA logic code, key parameters such as excitation signal frequency, filter cutoff frequency, and system bandwidth can be easily adjusted to adapt to the detection needs of different types of cancer cells or biological samples, greatly shortening the research and development cycle.

[0082] The system is easily expandable to achieve large-scale parallel detection. The powerful parallel processing capability of the FPGA enables it to easily replicate multiple digital phase-locked loop processing channels within a single chip, achieving parallel, high-speed scanning and impedance imaging of the microelectrode array, with a detection throughput far exceeding that of traditional instruments.

[0083] Through the above embodiments, the present invention constructs a complete closed-loop system from signal generation, acquisition, digital demodulation to result output, realizing high-precision and high-flexibility detection of cancer cell impedance, and providing strong technical support for the clinical application of bioimpedance spectroscopy technology in early cancer diagnosis, drug screening and cell biology research.

[0084] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from the spirit and scope of this invention.

Claims

1. A method for detecting the impedance spectrum of cancer cells based on FPGA digital quadrature phase-locked loop, characterized in that, include: S1: Based on the target excitation frequency, perform phase accumulation and table lookup operations to generate digital sine and digital cosine signals; S2: Convert the digital sinusoidal signal into an analog excitation signal and apply it to the biological sample to be tested, collect the response signal flowing through the biological sample to be tested and convert it into a digital response signal; S3: Multiply the digital response signal with the digital sine signal and the digital cosine signal respectively to generate an in-phase mixer signal and a quadrature mixer signal; S4: Perform multi-stage downsampling and low-pass filtering on the in-phase and quadrature mixed signals to generate in-phase and quadrature baseband signals; S5: Perform coordinate transformation operations on in-phase and quadrature baseband signals to generate impedance amplitude data and impedance phase data; S6: Encapsulate and output the impedance amplitude data and impedance phase data.

2. The method for detecting cancer cell impedance spectroscopy based on FPGA digital quadrature phase-locked loop according to claim 1, characterized in that, Step S1 includes: S11: Calculate the frequency control word based on the target excitation frequency and the system clock frequency; S12: The frequency control word is accumulated using a phase accumulator to generate a phase address; S13: Input the phase address into the sine lookup table and the cosine lookup table respectively, and generate the initial sine signal and the initial cosine signal by looking up the tables; S14: Perform pipelined delay alignment processing on the initial sine and initial cosine signals to generate digital sine and digital cosine signals with a phase difference of one-quarter of a cycle.

3. The method for detecting cancer cell impedance spectroscopy based on FPGA digital quadrature phase-locked loop according to claim 2, characterized in that, The storage depth of the sine lookup table and the cosine lookup table is determined by the bit width of the phase address. The sine lookup table stores the discrete sampled values ​​of the sine function within one period, and the cosine lookup table stores the discrete sampled values ​​of the cosine function within one period.

4. The method for detecting cancer cell impedance spectroscopy based on FPGA digital quadrature phase-locked loop according to claim 1, characterized in that, Step S2 includes: S21: Convert the digital sine wave signal into an analog excitation voltage using a digital-to-analog converter; S22: Apply the simulated excitation voltage to the excitation electrode of the biological sample to be tested; S23: The response current flowing through the biological sample to be tested is converted into a response voltage through a transimpedance amplifier; S24: Sample the response voltage using an analog-to-digital converter to generate a digital response signal.

5. The method for detecting cancer cell impedance spectroscopy based on FPGA digital quadrature phase-locked loop according to claim 1, characterized in that, Step S3 includes: S31: The digital response signal and the digital sine signal are multiplied point by point by the first digital multiplier to generate an in-phase mixer signal; S32: The digital response signal and the digital cosine signal are multiplied point by point by the second digital multiplier to generate an orthogonal mixing signal.

6. The method for detecting cancer cell impedance spectroscopy based on FPGA digital quadrature phase-locked loop according to claim 1, characterized in that, Step S4 includes: S41: Input the in-phase mixer signal and the quadrature mixer signal into the first-stage integral comb filter respectively for downsampling processing at the first downsampling rate to generate the first-stage downsampled signal; S42: Input the first-stage downsampled signal into the second-stage integral comb filter for downsampling processing at the second downsampling rate to generate the second-stage downsampled signal; S43: Input the second-stage downsampled signal into the third-stage integral comb filter for downsampling processing at the third downsampling rate to generate the third-stage downsampled signal; S44: Input the third-stage downsampled signal into the finite impulse response filter for low-pass filtering to generate in-phase baseband signal and quadrature baseband signal; Among them, the first downsampling rate is greater than the second downsampling rate, and the second downsampling rate is greater than the third downsampling rate.

7. The method for detecting cancer cell impedance spectroscopy based on FPGA digital quadrature phase-locked loop according to claim 1, characterized in that, The S5 steps include: S51: Use the in-phase baseband signal as the horizontal axis input value and the quadrature baseband signal as the vertical axis input value; S52: Rotate the x-coordinate input value and y-coordinate input value in the rectangular coordinate system to the polar coordinate system through iterative rotation operation to generate the modulus output and angle output; S53: The magnitude output is used as impedance amplitude data, and the angle output is used as impedance phase data.

8. The method for detecting cancer cell impedance spectroscopy based on FPGA digital quadrature phase-locked loop according to claim 1, characterized in that, Step S6 includes: S61: Combine the impedance amplitude data and impedance phase data with the preset frame header identifier; S62: Calculate the checksum for the combined data; S63: Encapsulate the frame header identifier, impedance amplitude data, impedance phase data, and checksum into a data frame according to a predetermined format; S64: Outputs data frames to external devices via a serial communication interface.

9. A system applied to the FPGA-based digital quadrature phase-locked loop method for detecting cancer cell impedance spectroscopy as described in any one of claims 1-9, characterized in that, include: The digital direct frequency synthesis module is located inside the FPGA and includes a phase accumulator, a sine lookup table, and a cosine lookup table. The phase accumulator is used to accumulate phase based on the input frequency control word to generate a phase address. The sine lookup table and the cosine lookup table are used to look up the phase address and output digital sine and digital cosine signals, respectively. A digital-to-analog converter, whose input is connected to the sinusoidal signal output of a digital direct frequency synthesis module, is used to convert digital sinusoidal signals into analog excitation voltages; A transimpedance amplifier, whose input is connected to the detection electrode of the biological sample to be tested, is used to convert the response current flowing through the biological sample to the response voltage. An analog-to-digital converter, whose input is connected to the output of a transimpedance amplifier, is used to convert the sampled response voltage into a digital response signal; The digital quadrature mixer module, located inside the FPGA, includes a first digital multiplier and a second digital multiplier. The two inputs of the first digital multiplier receive a digital response signal and a digital sine signal, respectively, and the two inputs of the second digital multiplier receive a digital response signal and a digital cosine signal, respectively. A multi-stage digital filtering module, located inside the FPGA, includes a cascaded first-stage integral comb filter, a second-stage integral comb filter, a third-stage integral comb filter, and a finite impulse response filter, used to downsample and filter the output signals of the first and second digital multipliers. The coordinate transformation module, located inside the FPGA, has its input connected to the output of the multi-stage digital filtering module. It is used to convert the filtered in-phase and quadrature signals into impedance amplitude data and impedance phase data. The data encapsulation communication module, located inside the FPGA, has its input connected to the output of the coordinate transformation module. It is used to encapsulate impedance amplitude data and impedance phase data into data frames and output them through a serial interface.

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