Zero DSP assembly line IQ converter applied to navigation array anti-interference antenna
By using a zero-DSP pipelined IQ converter, the problems of high power consumption and high hardware resource consumption of the traditional Hilbert transform method in satellite navigation array anti-jamming receivers are solved, and low-cost and low-power orthogonal signal conversion is achieved.
Patent Information
- Application Number
- CN202511551792.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-28
- Publication Date
- 2026-02-03
AI Technical Summary
Traditional Hilbert transform methods suffer from high power consumption and high hardware resource consumption in satellite navigation array anti-jamming receivers, especially in FPGA/ASIC implementations, leading to bottlenecks in engineering deployment.
By employing a zero-DSP pipelined IQ converter, and through hardware connections such as combinational number operations, data rearrangement, and sign adjustment, the conversion from real signals to quadrature complex signals is achieved, avoiding dependence on DSP units and optimizing the use of hardware resources.
It achieves efficient and low-power conversion from real signals to quadrature complex signals, reducing hardware resource consumption. In particular, the total LUT resource consumption in Xilinx 7K series FPGAs is ≤310, and the DSP resource consumption is 0.
Smart Images
Figure CN121454566A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of navigation technology, and specifically relates to a zero-DSP pipelined IQ converter for use in anti-interference antennas of navigation arrays. Background Technology
[0002] In satellite navigation array anti-jamming receivers, the real signals acquired by the ADC need to be converted into orthogonal IQ complex signals to meet spatial interference suppression requirements (such as space-time adaptive processing). Traditional solutions use Hilbert transform for orthogonal transformation (e.g., Figure 2 As shown in the diagram): the input data is used as the I branch, and the Hilbert transform result is used as the Q branch output. However, the hardware implementation of this method faces significant resource consumption, mainly because the Hilbert transform requires a precise 90-degree phase shift of the signal to construct an analytic signal. In the digital domain, it relies on high-order FIR filters or fast convolution (based on FFT / IFFT): the former requires a large number of multipliers and delay units, while the latter, although reducing the amount of computation, introduces frequent time-frequency domain conversions, resulting in additional storage overhead and increased timing control complexity; in addition, to maintain phase accuracy, the data word length or multi-stage pipeline needs to be increased, further occupying register resources and logic units. Taking a typical 8-point FFT implementation as an example ( Figure 3 As shown in the figure, its resource consumption is as follows: the first 8-point FFT operation consumes 900 LUTs and 8 DSP units; the operation of retaining the first 4 points of data and clearing the last 4 points occupies 30 LUTs; the second 8-point FFT operation reuses 900 LUTs and 8 DSP units, consuming a total of 1830 LUTs and 16 DSP resources (actual data source: traditional Hilbert transform FPGA implementation). In FPGA / ASIC implementation, these characteristics significantly increase the utilization rate of DSP slices, BRAM and logic gate resources, and the demand for multi-channel parallel processing makes the hardware consumption grow exponentially with the number of channels (e.g., 8 channels are expanded to 14,640 LUTs and 128 DSPs). It can be seen that although the Hilbert transform can theoretically provide ideal orthogonal components, its high hardware cost has become a key bottleneck in engineering deployment. Summary of the Invention
[0003] (a) Technical problems to be solved To overcome the drawbacks of high power consumption and high cost in the traditional Hilbert transform method, this invention provides a zero-DSP pipelined IQ converter for use in navigation array anti-interference antennas that can achieve lower cost and lower power consumption.
[0004] (II) Technical Solution This invention is achieved through the following technical solution: This invention proposes a zero-DSP pipelined IQ converter for use in navigation array anti-interference antennas, including an input data module for outputting eight real signals u0~u7, and also including the following components: The combinational number arithmetic unit, connected to the input data module, is used to process eight real signals u0~u7. Perform a rearrangement operation to output 8 sets of intermediate variables; The eight sets of intermediate variables are: x0=u0+u4, x1=u0-u4, x2=u1+u5, x3= u1-u5, x4= u2+u6, x5=u2-u6, x6= u3+u7, x7= u3-u7; Data rearrangers A1~A8 are connected to the combinational number arithmetic unit respectively, and input the intermediate variable sequence in a preset order. In each of the eight consecutive clock cycles, the intermediate variable at the corresponding position in the intermediate variable sequence is output. The data rearrangers A1~A8 cyclically input the intermediate variable sequence in a preset order, specifically as follows: The input intermediate variable sequence for data rearranger A1 is: x2, x4, x6, x0, x2, x4, x6, x0; The input intermediate variable sequence for data rearranger A2 is: x6, x0, x2, x4, x6, x0, x2, x4; The input intermediate variable sequence for data rearranger A3 is: x0, x2, x4, x6, x0, x2, x4, x6; The input intermediate variable sequence for data rearranger A4 is: x1, x3, x5, x7, x1, x3, x5, x7; The input intermediate variable sequence for data rearranger A5 is: x6, x0, x2, x4, x6, x0, x2, x4; The input intermediate variable sequence for data rearranger A6 is: x2, x4, x6, x0, x2, x4, x6, x0; The input intermediate variable sequence for data rearranger A7 is: x3, x5, x7, x1, x3, x5, x7, x1; The input intermediate variable sequence for data rearranger A8 is: x7, x1, x3, x5, x7, x1, x3, x5; Sign adjuster B1, connected to the output of data rearranger A4, is used to perform sign transformation on the intermediate output variables of data rearranger A4; specifically, sign adjuster B1 performs sign transformation on the intermediate output variables of data rearranger A4 as follows: The output of the first four clock cycles is equal to the intermediate output variable of the data rearranger A4, and the output of the next four clock cycles is equal to the opposite value of the intermediate output variable of the data rearranger A4. Sign adjuster B2 is connected to the output of data rearranger A8 and is used to perform sign transformation on the intermediate output variables of data rearranger A8. The sign adjuster B2 is used to perform sign transformation on the intermediate output variables of the data rearranger A8, specifically: The output results of the 1st, 6th, 7th and 8th clock cycles are equal to the intermediate output variable of the data rearranger A8, and the output results of the 2nd, 3rd, 4th and 5th clock cycles are equal to the opposite values of the intermediate output variable of the data rearranger A8. Adder C1 is connected to the outputs of data rearrangers A1 and A2, and is used to add the outputs of data rearrangers A1 and A2. Adder C2 is connected to the output of data rearranger A3 and sign adjuster B1, and is used to add the outputs of data rearranger A3 and sign adjuster B1. Subtractor D1 is connected to the output of data rearranger A5 and data rearranger A6, and is used to subtract the output results of data rearranger A5 and data rearranger A6. Adder C3 is connected to the output of data rearranger A7 and sign adjuster B2, and is used to add the outputs of data rearranger A7 and sign adjuster B2. The left shifter, connected to the adder C2, is used to shift the output of the adder C2 left by 1 bit in binary, which is equivalent to multiplying the input result by 2 before outputting it. The shift accumulator, connected to adder C3, is used to perform calculations on the output of adder C3 to obtain the accumulated value. The shift accumulator performs calculations on the output j of adder C3 to obtain the accumulated value k, specifically satisfying: The accumulated value k = j1 + j2 + j3 + j4, where j1 = j, j2 = j arithmetic right shift by 1 bit, j3 = j arithmetic right shift by 4 bits, and j4 = j arithmetic right shift by 5 bits. Adder C4 is connected to the output of adder C1 and left shifter, and is used to add the outputs of adder C1 and left shifter. The I-channel output module is connected to adder C4 and is used to output the operation result of adder C4 as the I-channel signal. Subtractor D2 is connected to the outputs of subtractor D1 and shift accumulator, and is used to subtract the outputs of subtractor D1 and shift accumulator. The Q-channel output module is connected to subtractor D2 and is used to output the result of subtractor D2 as the Q-channel signal.
[0005] Preferably, it also includes a timing controller for providing the same clock to drive all components and pipeline eight sets of IQ quadrature signals over eight consecutive clock cycles.
[0006] Preferably, the arithmetic right shift operation is implemented using an FPGA lookup table (LUT) hardware.
[0007] All of the above-mentioned arithmetic modules (combinatorial number arithmetic unit, adders C1-C4, subtractors D1 / D2, left shifter, shift accumulator) do not occupy DSP units; When implemented on a Xilinx 7K series FPGA, the total LUT resource consumption is ≤ 310, and the DSP resource consumption is 0.
[0008] This invention is applicable to the conversion of real signals to orthogonal complex signals in Beidou navigation anti-interference receivers.
[0009] (III) Beneficial Effects This invention is applicable to the conversion of real signals to orthogonal complex signals in Beidou navigation anti-interference receivers, achieving efficient, low-power, and zero-DSP-dependent conversion from real signals to orthogonal complex signals. Attached Figure Description
[0010] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a system block diagram of the IQ converter of the present invention.
[0011] Figure 2 This is a flowchart illustrating the traditional Hilbert transform method.
[0012] Figure 3 This is a resource consumption table for the traditional Hilbert transform method.
[0013] Figure 4 This is a flowchart illustrating the derivation of formulas in an embodiment of the present invention.
[0014] Figure 5 This is the resource consumption table for this invention. Detailed Implementation
[0015] This invention combines the characteristics of anti-interference receivers and further optimizes the traditional Hilbert transform method, such as... Figure 4As shown, assuming the eight input real signals are u0~u7, the result of the first FFT butterfly transformation in the traditional method is assumed to be x0~x7, the result of the second FFT butterfly transformation is assumed to be y0~y7, the result of the third FFT butterfly transformation is assumed to be X0~X7, and after the last four numbers are cleared to zero, they become X0~X3,0,0,0,0. The result of the first IFFT butterfly transformation is assumed to be Y0~Y7, the result of the second IFFT butterfly transformation is assumed to be Z0~Z7, and the result of the second IFFT butterfly transformation is assumed to be h0~h7. The corresponding h0~h7 signals are the Shell transform results of u0~u7. This invention, by performing mathematical equivalent derivation and hardware pipeline reconstruction of the above transformation process, directly reuses the addition and subtraction operation rules in the FFT butterfly structure, avoiding repeated calls to the complete FFT / IFFT module, thereby achieving efficient orthogonal transformation. Specifically, the mathematical equivalent derivation is as follows: Based on the 8-point FFT / IFFT properties and the definition of the twist factor: ; ; ; ; Next, the derivation is performed based on the calculation formulas for FFT and IFFT (see details). Figure 4 (Process), to obtain the closed-form expression of the Hilbert transform result: ; The same method can be used to deduce it; ; ; ; ; ; ; ; Based on the above derivation results, the present invention can realize IQ transformation through simple hardware connection, wherein the real part of the above equation corresponds to the I-path output and the imaginary part (i) corresponds to the Q-path output; Based on the above, this invention proposes a zero-DSP pipelined IQ converter for use in navigation array anti-interference antennas, including an input data module for outputting eight real signals u0~u7, and also including the following components: The combinational number arithmetic unit, connected to the input data module, is used to process eight real signals u0~u7. Perform a rearrangement operation to output 8 sets of intermediate variables; The eight sets of intermediate variables are: x0=u0+u4, x1=u0-u4, x2=u1+u5, x3= u1-u5, x4= u2+u6, x5=u2-u6, x6= u3+u7, x7= u3-u7; Data rearrangers A1~A8 are connected to the combinational number arithmetic unit respectively, and input the intermediate variable sequence in a preset order. In each of the eight consecutive clock cycles, the intermediate variable at the corresponding position in the intermediate variable sequence is output. The data rearrangers A1~A8 cyclically input the intermediate variable sequence in a preset order, specifically as follows: The input intermediate variable sequence for data rearranger A1 is: x2, x4, x6, x0, x2, x4, x6, x0; The input intermediate variable sequence for data rearranger A2 is: x6, x0, x2, x4, x6, x0, x2, x4; The input intermediate variable sequence for data rearranger A3 is: x0, x2, x4, x6, x0, x2, x4, x6; The input intermediate variable sequence for data rearranger A4 is: x1, x3, x5, x7, x1, x3, x5, x7; The input intermediate variable sequence for data rearranger A5 is: x6, x0, x2, x4, x6, x0, x2, x4; The input intermediate variable sequence for data rearranger A6 is: x2, x4, x6, x0, x2, x4, x6, x0; The input intermediate variable sequence for data rearranger A7 is: x3, x5, x7, x1, x3, x5, x7, x1; The input intermediate variable sequence for data rearranger A8 is: x7, x1, x3, x5, x7, x1, x3, x5; Sign adjuster B1, connected to the output of data rearranger A4, is used to perform sign transformation on the intermediate output variables of data rearranger A4; specifically, sign adjuster B1 performs sign transformation on the intermediate output variables of data rearranger A4 as follows: The output of the first four clock cycles is equal to the intermediate output variable of the data rearranger A4, and the output of the next four clock cycles is equal to the opposite value of the intermediate output variable of the data rearranger A4. Sign adjuster B2 is connected to the output of data rearranger A8 and is used to perform sign transformation on the intermediate output variables of data rearranger A8. The sign adjuster B2 is used to perform sign transformation on the intermediate output variables of the data rearranger A8, specifically: The output results of the 1st, 6th, 7th and 8th clock cycles are equal to the intermediate output variable of the data rearranger A8, and the output results of the 2nd, 3rd, 4th and 5th clock cycles are equal to the opposite values of the intermediate output variable of the data rearranger A8. Adder C1 is connected to the outputs of data rearrangers A1 and A2, and is used to add the outputs of data rearrangers A1 and A2. Adder C2 is connected to the output of data rearranger A3 and sign adjuster B1, and is used to add the outputs of data rearranger A3 and sign adjuster B1. Subtractor D1 is connected to the output of data rearranger A5 and data rearranger A6, and is used to subtract the output results of data rearranger A5 and data rearranger A6. Adder C3 is connected to the output of data rearranger A7 and sign adjuster B2, and is used to add the outputs of data rearranger A7 and sign adjuster B2. The left shifter, connected to the adder C2, is used to shift the output of the adder C2 left by 1 bit in binary, which is equivalent to multiplying the input result by 2 before outputting it. The shift accumulator, connected to adder C3, is used to perform calculations on the output of adder C3 to obtain the accumulated value. The shift accumulator performs calculations on the output j of adder C3 to obtain the accumulated value k, specifically satisfying: The accumulated value k = j1 + j2 + j3 + j4, where j1 = j, j2 = j arithmetic right shift by 1 bit, j3 = j arithmetic right shift by 4 bits, and j4 = j arithmetic right shift by 5 bits. Adder C4 is connected to the output of adder C1 and left shifter, and is used to add the outputs of adder C1 and left shifter. The I-channel output module is connected to adder C4 and is used to output the operation result of adder C4 as the I-channel signal. Subtractor D2 is connected to the outputs of subtractor D1 and shift accumulator, and is used to subtract the outputs of subtractor D1 and shift accumulator. The Q-channel output module is connected to subtractor D2 and is used to output the result of subtractor D2 as the Q-channel signal.
[0016] This invention utilizes the commonalities in the derivation results of formulas h0~h7, and by dividing the input signal into 8 clock cycles arranged sequentially, corresponding to the 8 input parameters in each h formula, it enables the hardware to sequentially output the results of h0~h7 in 8 clock cycles. Figure 5 As shown in the figure, Estimation represents the number of resources used in this invention, Available represents the total available resources of the FPGA, Utilization % represents the utilization rate, Resource represents resources, LUT represents lookup table, LUTRAM represents lookup table memory, FF represents flip-flops, BRAM represents block random access memory, IO represents input / output units, and BUFG represents global clock buffer.
[0017] It also includes a timing controller to provide the same clock to drive all components and output eight sets of IQ quadrature signals in eight consecutive clock cycles.
[0018] The arithmetic right shift operation is implemented in hardware using an FPGA lookup table (LUT).
[0019] All of the above-mentioned arithmetic modules (combinatorial number arithmetic unit, adders C1-C4, subtractors D1 / D2, left shifter, shift accumulator) do not occupy DSP units; When this invention is implemented on a Xilinx 7K series FPGA, the total LUT resource consumption is ≤ 310, and the DSP resource consumption is 0. A comparison with the Hilbert transform method is shown in the table below: plan Lut resources DSP resources Hilbert Transform 1830 16 This invention 310 0 This invention is applicable to the conversion of real signals to orthogonal complex signals in Beidou navigation anti-interference receivers, achieving efficient, low-power, and zero-DSP-dependent conversion from real signals to orthogonal complex signals.
Claims
1. A zero-DSP pipelined IQ converter for use in anti-interference antennas of navigation arrays, comprising an input data module for outputting eight real signals u0~u7, characterized in that: It also includes the following components: The combinational number arithmetic unit, connected to the input data module, is used to process eight real signals u0~u7. Perform a rearrangement operation to output 8 sets of intermediate variables; Data rearrangers A1~A8 are connected to the combinational number arithmetic unit respectively, and input the intermediate variable sequence in a preset order. In each of the eight consecutive clock cycles, the intermediate variable at the corresponding position in the intermediate variable sequence is output. Sign adjuster B1 is connected to the output of data rearranger A4 and is used to perform sign transformation on the intermediate output variables of data rearranger A4. Sign adjuster B2 is connected to the output of data rearranger A8 and is used to perform sign transformation on the intermediate output variables of data rearranger A8. Adder C1 is connected to the outputs of data rearrangers A1 and A2, and is used to add the outputs of data rearrangers A1 and A2. Adder C2 is connected to the output of data rearranger A3 and sign adjuster B1, and is used to add the outputs of data rearranger A3 and sign adjuster B1. Subtractor D1 is connected to the output of data rearranger A5 and data rearranger A6, and is used to subtract the output results of data rearranger A5 and data rearranger A6. Adder C3 is connected to the output of data rearranger A7 and sign adjuster B2, and is used to add the outputs of data rearranger A7 and sign adjuster B2. The left shifter, connected to the adder C2, is used to shift the output of the adder C2 left by 1 bit in binary, which is equivalent to multiplying the input result by 2 before outputting it. The shift accumulator, connected to adder C3, is used to perform calculations on the output of adder C3 to obtain the accumulated value. Adder C4 is connected to the output of adder C1 and left shifter, and is used to add the outputs of adder C1 and left shifter. The I-channel output module is connected to adder C4 and is used to output the operation result of adder C4 as the I-channel signal. Subtractor D2 is connected to the outputs of subtractor D1 and shift accumulator, and is used to subtract the outputs of subtractor D1 and shift accumulator. The Q-channel output module is connected to subtractor D2 and is used to output the result of subtractor D2 as the Q-channel signal.
2. The zero-DSP pipelined IQ converter for an anti-interference antenna of a navigation array according to claim 1, characterized in that: It also includes a timing controller to provide the same clock to drive all components, and to pipeline eight sets of IQ quadrature signals over eight consecutive clock cycles.
3. The zero-DSP pipelined IQ converter for an anti-interference antenna of a navigation array according to claim 1, characterized in that: The eight sets of intermediate variables are: x0=u0+u4, x1=u0-u4, x2=u1+u5, x3= u1-u5, x4= u2+u6, x5=u2-u6, x6= u3+u7, x7= u3-u7.
4. A zero-DSP pipelined IQ converter for an anti-interference antenna of a navigation array according to claim 1, characterized in that: The data rearrangers A1~A8 cyclically input the intermediate variable sequence in a preset order, specifically as follows: The input intermediate variable sequence for data rearranger A1 is: x2, x4, x6, x0, x2, x4, x6, x0; The input intermediate variable sequence for data rearranger A2 is: x6, x0, x2, x4, x6, x0, x2, x4; The input intermediate variable sequence for data rearranger A3 is: x0, x2, x4, x6, x0, x2, x4, x6; The input intermediate variable sequence for data rearranger A4 is: x1, x3, x5, x7, x1, x3, x5, x7; The input intermediate variable sequence for data rearranger A5 is: x6, x0, x2, x4, x6, x0, x2, x4; The input intermediate variable sequence for data rearranger A6 is: x2, x4, x6, x0, x2, x4, x6, x0; The input intermediate variable sequence for data rearranger A7 is: x3, x5, x7, x1, x3, x5, x7, x1; The input intermediate variable sequence for data rearranger A8 is: x7, x1, x3, x5, x7, x1, x3, x5.
5. A zero-DSP pipelined IQ converter for an anti-interference antenna of a navigation array according to claim 1, characterized in that: The sign adjuster B1 is used to perform sign transformation on the intermediate output variables of the data rearranger A4, specifically: The output of the first four clock cycles is equal to the intermediate output variable of the data rearranger A4, and the output of the next four clock cycles is equal to the opposite value of the intermediate output variable of the data rearranger A4.
6. A zero-DSP pipelined IQ converter for an anti-interference antenna of a navigation array according to claim 1, characterized in that: The sign adjuster B2 is used to perform sign transformation on the intermediate output variables of the data rearranger A8, specifically: The output results of the 1st, 6th, 7th, and 8th clock cycles are equal to the intermediate output variable of the data rearranger A8, and the output results of the 2nd, 3rd, 4th, and 5th clock cycles are equal to the opposite values of the intermediate output variable of the data rearranger A8.
7. A zero-DSP pipelined IQ converter for an anti-interference antenna of a navigation array according to claim 1, characterized in that: The shift accumulator performs calculations on the output j of adder C3 to obtain the accumulated value k, specifically satisfying: The accumulated value k = j1 + j2 + j3 + j4, where j1 = j, j2 = j arithmetic right shift by 1 bit, j3 = j arithmetic right shift by 4 bits, and j4 = j arithmetic right shift by 5 bits.
8. A zero-DSP pipelined IQ converter for an anti-interference antenna of a navigation array according to claim 7, characterized in that: The arithmetic right shift operation is implemented in FPGA lookup table (LUT) hardware.