A multi-dimensional doping profile optimized ultra-thin body MOSFET device and a preparation process thereof

Abstract

The application discloses a kind of multi-dimensional doped profile optimization type ultra-thin body MOSFET device and preparation process thereof, belong to semiconductor device technical field, including by a plurality of mutually juxtaposed MOS cell is formed, single MOS cell includes drain, semiconductor epitaxial layer, source and gate;The semiconductor epitaxial layer includes N substrate layer, N drift layer, P+ layer, N well layer and P well layer, the middle of N drift layer of single MOS cell is equipped with lightly doped N layer, the inside of single MOS cell and located N drift layer left and right sides are equipped with side symmetry P- layer, the side symmetry P- layer is rectangular profile, and the top of side symmetry P- layer is in contact with the gate;In embodiment one, side symmetry P- layer and N drift layer form PN junction, produce lateral depletion region when reverse bias, expand lateral electric field range, avoid local electric field concentration.

Description

Technical Field

[0001] This invention relates to semiconductor device technology, and more particularly to a multi-dimensional doped profile optimized ultrathin MOSFET device. Background Technology

[0002] Throughout the decades-long development of semiconductor devices, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) have always held a central position, widely used in smartphones, computers, industrial control, and other fields, serving as the cornerstone of the modern electronics and information industry. However, as chip manufacturing processes continue to approach physical limits, traditional silicon-based MOSFETs are gradually facing performance bottlenecks that are difficult to overcome: breakdown voltage and on-resistance are inversely related, and increasing the withstand voltage often leads to increased conduction losses; the short-channel effect causes the device threshold voltage to drift, exacerbating leakage problems; at the same time, energy density increases with high integration, resulting in significant heat dissipation pressure. These problems severely restrict the development of electronic devices towards high power, high efficiency, and miniaturization, driving the industry to urgently explore new materials and innovative structures. A multi-dimensional doped profile-optimized ultrathin MOSFET device, employing an array structure design, is composed of several parallel MOS cells. When the gate is turned on, a positive voltage is applied and exceeds the threshold. An N-type channel is formed on the surface of the P-well layer below the gate through inversion. Source electrons are efficiently injected into the N-drift layer through the channel. The lightly doped N-layer uniformly disperses the electric field and reduces the on-resistance. When the gate voltage is turned off, the channel disappears. The depletion region formed by the side-symmetric P-layer and the N-drift layer widens rapidly, blocking the drain-source current, reducing charge storage, and improving the switching speed.

[0003] This device demonstrates enormous application potential in fields such as new energy vehicles, smart grids, switching power supplies, and aerospace, meeting the demands for high power density and high reliability. Although challenges remain, including high complexity in fabrication processes and high costs associated with large-scale mass production, continuous breakthroughs in material synthesis and device manufacturing technologies suggest that ultrathin molybdenum disulfide-based MOSFETs are poised to lead a new wave of innovation in semiconductor devices, propelling the electronics industry towards leapfrog development. Summary of the Invention

[0004] Purpose of the Invention: The purpose of this invention is to achieve precise control over electric field distribution and carrier transport, thereby balancing the on-resistance, withstand voltage, and switching characteristics of the device. This meets the demands of electronic devices for high power, high efficiency, and miniaturization, while also adapting to the application requirements of high power density and high reliability devices in fields such as new energy vehicles and smart grids. Another purpose of this invention is to provide electrodes with good contact and stable performance, providing reliable process support for the large-scale production and practical application of this MOSFET device, and promoting the industrialization of molybdenum disulfide-based semiconductor device technology.

[0005] Technical solution: A multi-dimensional doped profile optimized ultrathin MOSFET device, comprising a plurality of parallel MOS cells, each MOS cell including a drain, a semiconductor epitaxial layer, a source, and a gate; the semiconductor epitaxial layer includes an N substrate layer, an N drift layer, a P+ layer, an N well layer, and a P well layer, wherein a lightly doped N layer is provided in the middle of the N drift layer of each MOS cell;

[0006] A laterally symmetrical P-layer is provided inside a single MOS cell and on the left and right sides of the N-drift layer. The laterally symmetrical P-layer has a rectangular outline and its top end is in contact with the gate.

[0007] Furthermore, an intermediate N+ is formed inside the lightly doped N layer by ion implantation. The intermediate N+ is semi-circular, and its top end is in contact with the gate.

[0008] Furthermore, a bottom P+ layer is formed inside the lightly doped N layer by ion implantation. The bottom P+ layer is rectangular, with its bottom end in contact with the N substrate layer and its top end being arc-shaped.

[0009] Furthermore, the middle N+ outer wall is ion-implanted with a symmetrical P- layer, which is circular in shape and does not contact the gate or the N substrate layer.

[0010] A multi-dimensional doped profile optimized ultrathin MOSFET device comprises several parallel MOS cells, each MOS cell including a drain, a semiconductor epitaxial layer, a source, and a gate; the semiconductor epitaxial layer includes an N substrate layer, an N drift layer, a P+ layer, an N well layer, and a P well layer, and a lightly doped N layer is provided in the middle of the N drift layer of each MOS cell;

[0011] A rectangular P-layer is provided inside a single MOS cell and on the left and right sides of the N drift layer. The top of the rectangular P-layer has an arc-shaped profile, and one end of the rectangular P-layer is in contact with the N substrate layer.

[0012] Furthermore, a bottom N+ layer is formed in the central region of the lightly doped N layer by ion implantation, and the top of the bottom N+ layer is in contact with the N substrate layer.

[0013] Furthermore, a semi-circular P-layer is formed in the central region of the lightly doped N-layer by ion implantation, and the top of the semi-circular P-layer is in contact with the gate.

[0014] Furthermore, a top N+ layer is formed in the central region of the lightly doped N layer by ion implantation, and the top of the bottom N+ layer is in contact with the gate.

[0015] Furthermore, a laterally symmetrical semicircular P-layer is formed in the central region of the lightly doped N-layer by ion implantation. The laterally symmetrical semicircular P-layer is arc-shaped, and its bottom end is in contact with the N-substrate layer.

[0016] According to another aspect of the present invention, a fabrication process for a multi-dimensional doped profile-optimized ultrathin bulk MOSFET device is provided, comprising the following steps:

[0017] A method for fabricating a multi-dimensional doped profile-optimized ultrathin bulk MOSFET device includes the following steps:

[0018] S1. Substrate and Epitaxial Layer Fabrication: An N-type substrate is selected, and an N-drift layer is grown on its surface using chemical vapor deposition. The deposition parameters are controlled to ensure the layer thickness and doping uniformity. Subsequently, a P-well layer, an N-well layer, and a P+ layer are epitaxially grown sequentially on the surface of the N-drift layer to form a basic semiconductor epitaxial structure.

[0019] S2. Preparation of lightly doped N-layer and side-symmetric P-layer: The middle region of the N-drift layer is defined by photolithography, and a lightly doped N-layer is formed by ion implantation; then the left and right sides of the N-drift layer are defined by photolithography, and P-type impurities are implanted to form a rectangular side-symmetric P-layer, ensuring that its top is aligned with the subsequent gate region.

[0020] S3. Preparation of intermediate N+ and symmetrical P- layers: For the lightly doped N-layer, the central region is defined by photolithography, and a high dose of N-type impurities is injected to form a semi-circular intermediate N+ layer, ensuring that its top extends to the gate contact position; with the intermediate N+ as the center, the outer circular region is defined by photolithography, and a low dose of P-type impurities is injected to form a symmetrical P- layer, controlling the injection depth so that it does not contact the gate and the substrate.

[0021] S4. Preparation of the bottom P+ layer: A rectangular region is defined at the bottom of the lightly doped N layer by photolithography. A high dose of P-type impurities is implanted to form the bottom P+ layer. The top of the layer is adjusted to be arc-shaped by annealing to ensure good contact between the bottom and the N substrate.

[0022] S5. Source and drain electrode fabrication: The source and drain regions are defined by photolithography. Ohmic contact electrodes are formed by metal evaporation and lift-off processes. Contact resistance is reduced by rapid thermal annealing.

[0023] S6. Gate fabrication: A gate oxide layer is grown on the device surface. The gate region is defined by photolithography. The gate metal is deposited and patterned to ensure effective contact between the gate and the side-symmetric P- layer and the middle N+ top.

[0024] Beneficial Effects: In Example 1, the laterally symmetric P-layer and the N-drift layer form a PN junction, generating a lateral depletion region under reverse bias, expanding the lateral electric field range and avoiding local electric field concentration. Example 2 adds a bottom P+ layer and a circularly symmetric P-layer. The arc-shaped design at the top of the bottom P+ layer causes the depletion region to extend longitudinally in an arc shape, while the circularly symmetric P-layer forms a surrounding depletion region. These two elements respectively enhance the longitudinal and gate-near electric field modulation. The rectangular P-layer, the semi-circular P-layer, and the laterally symmetric semi-circular P-layer in Example 2 all utilize multi-dimensional doping profile and position design to allow the depletion region to extend in different dimensions under reverse bias. These structures work together to disperse the strong electric field regions in both the longitudinal and lateral directions, preventing gate oxide breakdown or drift layer breakdown, enabling the device to operate stably under high voltage conditions and meeting the requirements of high-voltage applications.

[0025] In Example 2, the lightly doped N-layer can uniformly disperse the electric field, reducing the on-resistance of the N-drift layer. Simultaneously, the middle N+ layer contacts the gate, enhancing the carrier concentration near the gate and reducing the contact resistance between the channel and the drift layer. The lightly doped N-layer in Example 2 continues this advantage, with the bottom N+ layer further forming a low-resistance vertical path, accelerating electron transport from the drift layer to the substrate. Both the bottom and top N+ layers in Example 2 form low-resistance regions through high-concentration N-type doping, reducing obstacles during electron transport. Furthermore, the position of the P-layer in each example is designed to avoid the carrier transport path during conduction, preventing the generation of additional resistance. These designs enable electrons to transport with lower resistance in the on-state, reducing energy loss during current transport and improving overall energy efficiency.

[0026] In Example 3, the lightly doped N-layer works in conjunction with the middle N+ layer to reduce the amount of charge stored during turn-off, and the depletion region of the laterally symmetric P-layer widens rapidly, shortening the current blocking time. In Example 3, the symmetric P-layer and the bottom P+ layer simultaneously expand the depletion region during turn-off, while the middle N+ layer accelerates the dissipation of residual charge. The bottom N+ layer in Example 3 can quickly release stored charge, reducing turn-off delay. The semi-circular P-layer in Example 3 not only optimizes the electric field but also accelerates the lateral dissipation of residual charge, reducing turn-off tail current. The top N+ layer and the laterally symmetric semi-circular P-layer in Example 3 complement each other; the former releases charge near the gate, while the latter rapidly expands the depletion region. These designs allow the device to quickly clear residual carriers from the drift layer and channel region after the gate voltage is removed, shortening the turn-off time, reducing dynamic losses during switching, and adapting to high-frequency switching applications.

[0027] The laterally symmetrical P-layer, circularly symmetrical P-layer, semi-circular P-layer, and laterally symmetrical semi-circular P-layer of Embodiment 4 all employ arc-shaped or circular contours to reduce abrupt changes in the potential barrier during carrier transport and avoid heating or structural damage caused by localized current concentration. The arc-shaped top design of the bottom P+ layer and the rectangular P-layer of Embodiment 4 reduces stress concentration caused by abrupt changes in impurity concentration and minimizes lattice defects. Furthermore, all embodiments employ symmetrical structural designs, such as bilaterally symmetrical P-layers and centrally symmetrical N+ layers, to ensure uniform current distribution during transport and prevent localized overheating. These designs reduce structural losses during long-term device operation, lower the risk of overall damage due to localized failures, extend the stable operating life of the device, and improve reliability.

[0028] Example 5 achieves an initial balance among the basic lightly doped N-layer, side-symmetric P-layer, and intermediate N+ layer, meeting the requirements of conventional high-voltage switching. Example 5 adds a bottom P+ layer and a circular symmetric P-layer to further improve voltage withstand and switching speed, adapting to higher voltage and high-frequency scenarios. Example 6 focuses on optimizing voltage withstand and conduction losses with its rectangular P-layer and bottom N+ layer, suitable for scenarios with high energy efficiency requirements. Example 7 enhances electric field control and switching characteristics with its semi-circular P-layer, adapting to high-frequency, high-voltage scenarios. Example 8 balances low loss and high stability with its top N+ layer and side-symmetric semi-circular P-layer, suitable for long-term high-load applications. These designs cover different performance emphasis requirements, allowing the device to flexibly adapt to diverse applications in power electronics, new energy, and other fields. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of Embodiment 1 of the present invention;

[0030] Figure 2 This is a schematic diagram of Embodiment 1 of the present invention;

[0031] Figure 3 This is a schematic diagram of Embodiment 2 of the present invention;

[0032] Figure 4 This is a schematic diagram of Embodiment 2 of the present invention;

[0033] Figure 5 This is a schematic diagram of Embodiment 3 of the present invention;

[0034] Figure 6 This is a schematic diagram of Embodiment 4 of the present invention;

[0035] Figure 7 This is a schematic diagram of Embodiment 5 of the present invention;

[0036] Figure 8 This is a schematic diagram of Embodiment 5 of the present invention.

[0037] In the diagram: 1. Drain; 2. N-substrate layer; 3. N-drift layer; 4. Source; 5. Gate; 6. Lightly doped N-layer; 7. Laterally symmetric P-layer; 8. P+ layer; 9. N-well layer; 10. P-well layer; 11. Middle N+ layer; 12. Bottom P+ layer; 13. Symmetric P-layer; 14. Bottom N+ layer; 15. Rectangular P-layer; 16. Top N+ layer; 17. Laterally symmetric P-layer; 18. Semicircular P-layer; Detailed Implementation

[0038] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0039] Example 1

[0040] It consists of several parallel MOS cells. Each MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 4, and a gate 5. The semiconductor epitaxial layer includes an N substrate layer 2, an N drift layer 3, a P+ layer 8, an N well layer 9, and a P well layer 10. A lightly doped N layer 6 is provided in the middle of the N drift layer 3 of each MOS cell. Laterally symmetrical P- layers 7 are provided inside the MOS cell and on the left and right sides of the N drift layer 3. The laterally symmetrical P- layers 7 have a rectangular outline and their tops are in contact with the gate 5. An intermediate N+11 is formed inside the lightly doped N layer 6 by ion implantation. The intermediate N+11 is semi-circular and its tops are in contact with the gate 5.

[0041] When this MOS structure is operating, the gate voltage controls the channel conduction state. When a forward voltage is applied to the gate and exceeds the threshold, an N-type channel is formed on the surface of the P-well layer below the gate through inversion. Source electrons enter the N-drift layer through the channel. When a forward voltage is applied to the drain, electrons are injected into the N-drift layer from the source through the channel. The lightly doped N-layer 6 can uniformly disperse the electric field and reduce the on-resistance of the drift region. The side-symmetric P-layer 7 forms a PN junction with the N-drift layer. When reverse biased, it generates a depletion region, expands the lateral electric field range, and improves the device's breakdown voltage capability. The central N+11 is semi-circular and in contact with the gate, which can enhance the carrier concentration near the gate, reduce the contact resistance between the channel and the drift layer, and accelerate carrier transport. When the device is turned off, the gate voltage is removed, the channel disappears, and the depletion region of the side-symmetric P- layer and N drift layer rapidly widens, blocking the drain-source current. The structure of the lightly doped N layer and the middle N+ layer reduces the charge storage during turn-off and improves the switching speed. Overall, through layered doping and symmetrical structure design, the on-resistance, breakdown voltage and switching characteristics are balanced.

[0042] Example 2

[0043] A bottom P+ layer 12 is formed inside the lightly doped N layer 6 by ion implantation. The bottom P+ layer 12 is rectangular, and the bottom end of the bottom P+ layer 12 is in contact with the N substrate layer 2. The top end of the bottom P+ layer 12 is arc-shaped. A symmetrical P- layer 13 is formed on the outer wall of the middle N+11 by ion implantation. The symmetrical P- layer 13 is circular in shape and does not contact the gate 5 and the N substrate layer 2.

[0044] When this MOS structure is operating, after the forward voltage applied to the gate exceeds the threshold, an N-type channel is formed on the surface of the P-well layer below the gate through inversion. Electrons are injected from the source into the N-drift layer through the channel. When the drain is forward-biased, electrons enter the N-drift layer through the channel. The lightly doped N-layer 6 uniformly disperses the vertical electric field, reducing the on-resistance. The bottom P+ layer 12 contacts the N-substrate layer 2, and its arc-shaped top design causes the depletion region to expand in an arc shape, enhancing the vertical electric field modulation capability. Together with the lateral symmetrical P- layer 7, it expands the depletion region range and improves the device breakdown voltage. The circular symmetrical P- layer 13 outside the middle N+11 forms a surrounding depletion region when reverse biased, further dispersing the electric field concentration near the gate and reducing the risk of gate oxide breakdown. At the same time, it does not contact the gate and the substrate, avoiding affecting the carrier transport path during conduction. When turned off, the channel disappears after the gate voltage is removed, and the depletion regions of the bottom P+ layer and the symmetrical P- layer 13 expand rapidly, blocking the drain-source current. The combination of the intermediate N+11 layer and the symmetrical P-layer 13 accelerates the dissipation of residual charge and improves the switching speed. The overall structure balances breakdown voltage, on-resistance, and switching characteristics through multi-dimensional doping control.

[0045] Example 3

[0046] It consists of several parallel MOS cells. Each MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 4, and a gate 5. The semiconductor epitaxial layer includes an N substrate layer 2, an N drift layer 3, a P+ layer 8, an N well layer 9, and a P well layer 10. A lightly doped N layer 6 is provided in the middle of the N drift layer 3 of each MOS cell. A rectangular P- layer 15 is provided inside the MOS cell and on the left and right sides of the N drift layer 3. The top of the rectangular P- layer 15 has an arc-shaped profile. One end of the rectangular P- layer 15 is in contact with the N substrate layer 2. A bottom N+ layer 14 is formed in the central region of the lightly doped N layer 6 through ion implantation. The top of the bottom N+ layer 14 is in contact with the N substrate layer 2.

[0047] When this MOS structure is operating, after the gate is forward-biased beyond the threshold voltage, an N-type channel is formed on the surface of the P-well layer below the gate through inversion. Electrons are injected from the source into the N-drift layer through the channel. When the drain is forward-biased, electrons enter the N-drift layer through the channel. The lightly doped N-layer 6 can uniformly disperse the vertical electric field, reducing the on-resistance. The arc-shaped design at the top of the rectangular P-layer 15 causes the depletion region to expand in an arc shape. When the PN junction formed with the N-drift layer is reverse-biased, the vertical depletion region expands. Combined with its contact with the N-substrate layer 2, this enhances the vertical electric field modulation capability and improves the device's breakdown voltage. The bottom N+ layer 14 at the center of the lightly doped N-layer 6 contacts the N-substrate layer 2, forming a low-resistance vertical path, accelerating the transport of electrons from the drift layer to the substrate, and reducing conduction losses. When turned off, the channel disappears after the gate voltage is removed, and the depletion region of the rectangular P-layer 15 and the N-drift layer rapidly widens, blocking the drain-source current. The bottom N+ layer 14 can quickly release stored charge, reducing turn-off delay. Through layered doping and structural design, the overall performance of the device is improved by balancing voltage withstand capability, on-resistance and switching speed.

[0048] Example 4

[0049] A semi-circular P-layer 18 is formed in the central region of the lightly doped N-layer 6 by ion implantation, and the top of the semi-circular P-layer 18 is in contact with the gate 5.

[0050] When this MOS structure is in operation, after a forward voltage exceeding the threshold is applied to the gate, an N-type channel is formed on the surface of the P-well layer below the gate through inversion. Electrons are injected into the N-drift layer from the source through the channel. When a forward voltage is applied to the drain, electrons enter the N-drift layer through the channel. The lightly doped N-layer 6 uniformly disperses the longitudinal electric field, reducing the on-resistance. The top of the semi-circular P-layer 18 in the center of the lightly doped N-layer 6 contacts the gate. During forward conduction, its semi-circular profile creates a gradual doping distribution near the gate, reducing the abrupt change in the potential barrier for carrier transport and accelerating the injection efficiency of electrons from the channel to the drift layer. During reverse breakdown, the depletion region of the PN junction formed by the semicircular P-layer and the surrounding N-type region expands in an arc shape, which can disperse the concentrated electric field directly below the gate and prevent the gate oxide from being broken down by the local strong electric field. Combined with the vertical depletion region expansion of the rectangular P-layers 15 on both sides, this further enhances the device's breakdown voltage capability. During turn-off, after the gate voltage is removed, the channel disappears, and the depletion region of the semicircular P-layer 18 rapidly spreads into the lightly doped N-layer, working in conjunction with the depletion region of the rectangular P-layer 15 to block the drain-source current. Its semicircular structure also accelerates the lateral dissipation of residual charge, reducing the tail current during turn-off and improving the switching speed. Overall, through doping profile optimization, conduction losses, breakdown voltage performance, and switching characteristics are balanced.

[0051] Example 5

[0052] A top N+ layer 16 is formed in the central region of the lightly doped N layer 6 by ion implantation. The top end of the top N+ layer 16 is in contact with the gate 5. A laterally symmetrical semicircular P- layer 17 is formed in the central region of the lightly doped N layer 6 by ion implantation. The laterally symmetrical semicircular P- layer 17 is arc-shaped, and the bottom end of the laterally symmetrical semicircular P- layer 17 is in contact with the N substrate layer 2.

[0053] When this MOS structure is operating, after the forward voltage applied to the gate exceeds the threshold, an N-type channel is formed on the surface of the P-well layer below the gate through inversion. Electrons are injected from the source into the N-drift layer through the channel. When the drain is forward-biased, the top N+ layer 16 at the center of the lightly doped N-layer 6 contacts the gate, forming a low-resistance channel. This accelerates the injection of electrons from the channel into the drift layer, reducing the on-resistance. The bottom of the laterally symmetrical semi-circular P-layer 17 contacts the N-substrate layer 2. Its arc-shaped profile causes the depletion region to extend longitudinally in an arc shape when reverse-biased. Together with the PN junction formed by the N-drift layer, it expands the depletion region range, disperses the longitudinal electric field, and improves the device's breakdown voltage capability. At the same time, the top N+ layer 16 and the laterally symmetrical semi-circular P-layer 17 form a complementary structure. The former ensures efficient carrier transport during conduction, while the latter enhances electric field control during turn-off. When turn-off, the channel disappears after the gate voltage is removed, and the depletion region of the laterally symmetrical semi-circular P-layer 17 rapidly spreads into the lightly doped N-layer, working together with the depletion regions of the rectangular P-layers 15 on both sides to block the drain-source current. The top N+ layer 16 can quickly release residual charge near the gate, reducing turn-off delay. Overall, the spatial arrangement of the N+ and P- layers balances conduction losses, breakdown voltage performance, and switching speed.

[0054] According to another aspect of the present invention, a multi-dimensional doped profile-optimized ultrathin MOSFET device and its fabrication process are provided, comprising the following steps:

[0055] 1. Substrate and Epitaxial Layer Fabrication

[0056] First, an N-type substrate 2 was selected as the device base, and an N-drift layer 3 was grown on its surface using chemical vapor deposition (CVD). During the process, parameters such as deposition temperature and gas flow rate were precisely controlled to ensure uniform thickness and stable doping concentration of the N-drift layer. Then, on the surface of the N-drift layer 3, a P-well layer 10, an N-well layer 9, and a P+ layer 8 were sequentially formed using epitaxial growth techniques, constructing the basic semiconductor epitaxial structure required for the device and laying the foundation for subsequent processes.

[0057] S2, Preparation of lightly doped N-layer and side-symmetric P-layer

[0058] First, a central region is defined on the surface of the N-drift layer 3 using photolithography. Then, a low dose of N-type impurities is implanted into this region to form a lightly doped N-layer 6 through ion implantation. After completion, photolithography is used again to define specific regions on the left and right sides of the N-drift layer 3, and a medium dose of P-type impurities is implanted into these regions to form a rectangular, laterally symmetric P-layer 7. At the same time, the process precision is strictly controlled to ensure that the top of the P-layer can be precisely aligned with the gate region subsequently fabricated.

[0059] Preparation of S3, intermediate N+ and symmetric P- layers

[0060] For the already formed lightly doped N-layer 6, its central region is defined using photolithography. A high-dose N-type impurity is implanted into this region to form a semi-circular central N+11, ensuring that the N+ tip extends to the subsequent gate contact position. Next, using the central N+11 as the center, a circular region on its outer side is defined again using photolithography. A low-dose P-type impurity is implanted into this region to form a symmetrical P-layer 13, with precise control of the implantation depth to prevent contact between the layer and the gate and substrate.

[0061] S4, Preparation of the bottom P+ layer

[0062] A rectangular region was defined at the bottom of the lightly doped N-layer 6 using photolithography, and a high-dose P-type impurity was implanted into this region to form the bottom P+ layer 12. After implantation, an annealing process was performed. By controlling the annealing temperature and time, the top of the bottom P+ layer 12 was adjusted to an arc-shaped structure. At the same time, it was ensured that the bottom end of the bottom P+ layer 12 could make good contact with the N substrate 2 to guarantee the electrical performance of the device.

[0063] S5, Source / Drain electrode fabrication

[0064] Photolithography was used to define the source electrode 4 and drain electrode 1 regions at specific locations on the device. Then, a metal evaporation process, such as evaporating a Ti / Au metal combination, combined with a lift-off process, was employed to form electrodes with ohmic contact characteristics in the defined regions. Finally, rapid thermal annealing was performed; short-time high-temperature heating effectively reduced the contact resistance between the source and drain electrodes, improving their conductivity.

[0065] S6, Gate fabrication

[0066] First, a gate oxide layer, commonly Al2O3, is grown on the overall surface of the device to ensure uniform oxide layer thickness and good insulation performance. Then, the gate 5 region is defined on the oxide layer surface using photolithography. Next, a gate metal, such as Mo, is deposited using an evaporation process, and the metal layer is patterned to form the required gate shape. Finally, it is ensured that the fabricated gate can effectively contact the top of the side-symmetric P-layer 7 and the central N+11, guaranteeing the gate's control function.

[0067] The embodiments described above are merely examples of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A MOSFET device comprising a plurality of parallel MOS cells, each MOS cell including a drain (1), a semiconductor epitaxial layer, a source (4), and a gate (5); the semiconductor epitaxial layer including an N-substrate layer (2), an N-drift layer (3), a P+ layer (8), an N-well layer (9), and a P-well layer (10), wherein the drain (1) is located below the N-substrate layer (2), characterized in that: A lightly doped N layer (6) is provided in the middle of the N drift layer (3) of a single MOS cell; The lightly doped N layer (6) penetrates the N drift layer (3). P-layers (7) are symmetrically arranged inside a single MOS cell and on the left and right sides of the lightly doped N layer (6). The P-layers (7) have a trapezoidal outline, and the top of the P-layers (7) is in contact with the bottom of the P well layer (10).

2. The MOSFET device according to claim 1, characterized in that: The top of the lightly doped N layer (6) is formed with an intermediate N+ (11) by ion implantation. The intermediate N+ (11) is semi-circular and the top of the intermediate N+ (11) is in contact with the gate (5).

3. A MOSFET device according to claim 1, characterized in that: The interior of the lightly doped N layer (6) is formed by ion implantation of a bottom P+ layer (12). The bottom end of the bottom P+ layer (12) is in contact with the N substrate layer (2), and the top end of the bottom P+ layer (12) is arc-shaped.

4. A MOSFET device according to claim 2, characterized in that: The outer wall of the middle N+ (11) is implanted with a symmetrical P- layer (13), which is circular in shape and does not contact the gate (5).

5. A method for fabricating a MOSFET device as described in any one of claims 1-4, characterized in that, Includes the following steps: S1, Substrate and epitaxial layer fabrication; S2, preparation of lightly doped N-layer and P-layer; S3, Source and drain electrode fabrication; S4, Gate fabrication.

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