MOSFET device
By forming a second Schottky metal layer at the bottom of the trench in the SiC Trench MOSFET, the reliability problem caused by electric field concentration at the corner of the gate oxide layer is solved, thereby improving the reliability of the device and increasing the switching speed.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- XIAMEN XINERGY MICROELECTRONICS CO LTD
- Filing Date
- 2025-04-30
- Publication Date
- 2026-05-01
AI Technical Summary
SiC Trench MOSFET devices are prone to a large electric field concentration at the corner of the gate oxide layer, which can lead to breakdown and pose a reliability problem.
A second Schottky metal layer is formed at the bottom of the trench to reduce electric field concentration and improve device reliability.
By forming a second Schottky metal layer at the bottom of the trench, the electric field strength at the bottom of the gate trench is reduced, improving the reliability of the device, reducing Miller capacitance, and increasing switching speed.
Smart Images
Figure CN224192336U_ABST
Abstract
Description
A MOSFET device Technical Field
[0001] This utility model relates to the field of semiconductor power device technology, and in particular to a MOSFET device. Background Technology
[0002] Silicon carbide (SiC), a third-generation semiconductor material, is a crystal formed by the stable combination of carbon and silicon elements, possessing unique physical and chemical properties. Its superior performance, including a wide bandgap, high thermal conductivity, and high carrier saturation mobility, gives it unique advantages and broad prospects in high-power, high-frequency, and high-voltage applications. Currently, silicon carbide MOSFETs have been widely used in automotive electronics, photovoltaics, and energy storage.
[0003] In recent years, trench MOSFETs have emerged as a significant advancement over planar MOSFETs. They not only eliminate the JFET effect and reduce internal impedance, bringing the on-resistance closer to the ideal value, but also reduce cell size and increase cell density, thereby increasing current density and effectively saving chip area. Therefore, SiC trench MOSFETs, with their advantages of lower on-resistance and higher cell density, have become a research hotspot in SiC power devices. However, SiC has an exceptionally high critical breakdown field and poor gate oxide quality. Due to the structural characteristics of SiC trench MOSFETs, a very large electric field tends to concentrate at the corners of the gate oxide layer, causing the gate oxide layer to break down and resulting in serious reliability issues.
[0004] It should be noted that the information disclosed in this background section is intended only to enhance the understanding of the overall background of this utility model, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0005] To address the challenges of existing technologies, this invention provides a novel SiC Trench MOSFET that effectively reduces the electric field strength at the bottom of the gate trench, thereby improving device reliability.
[0006] This invention provides a MOSFET device comprising a substrate, an N-type drift region, a P-type base region, an N+ source region, a P+ ohmic contact region, and a second Schottky metal layer. The N-type drift region is disposed on the substrate, the P-type base region is disposed on the N-type drift region, and the N+ source region is disposed on the P-type base region. A trench is formed between the N-type drift region, the P-type base region, and the N+ source region. The P+ ohmic contact region is disposed on the P-type base region and connects to the N+ source region. The second Schottky metal layer is located within the N-type drift region and connects the sidewalls and bottom of the trench.
[0007] Furthermore, the MOSFET device also includes a polysilicon layer, a gate, and a gate oxide layer. The polysilicon layer is deposited at the bottom of the trench, the gate oxide layer is disposed on the polysilicon layer, and the gate is disposed within the gate oxide layer.
[0008] Furthermore, the MOSFET device also includes a drain, which is disposed on the gate oxide layer, the P+ ohmic contact region, and the N+ source region.
[0009] Furthermore, the thickness of the N-type drift region ranges from 5 to 15 μm.
[0010] Furthermore, the doping concentration range of the N-type drift region is 7 × 10⁻⁶. 15 / cm 3 ~1.1×10 16 / cm 3 .
[0011] Furthermore, the substrate material includes silicon carbide.
[0012] Furthermore, the second Schottky metal layer is located beneath the P-type base region.
[0013] The present invention provides a MOSFET device that reduces the electric field concentration at the bottom of the trench gate and improves the reliability of the device by forming a second Schottky metal layer at the bottom of the trench.
[0014] Other features and beneficial effects of this invention will be set forth in the following description, and some of the technical features and beneficial effects may be apparent from the description or learned by practicing this invention. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, some of the drawings in the following description are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0016] Figure 1 is a schematic flowchart of a method for manufacturing a MOSFET device according to an embodiment of the present invention;
[0017] Figures 2 to 5 are schematic diagrams of the MOSFET device provided in an embodiment of the present invention at various stages of the manufacturing process;
[0018] Figure 6 is a schematic diagram of the structure of a MOSFET device provided in an embodiment of the present invention.
[0019] Figure label:
[0020] 12-Substrate; 14-N-type drift region; 16-Trench; 18-P-type base region; 20-N+ source region; 22-P+ ohmic contact region; 24-First Schottky metal layer; 26-Oxide layer; 28-Second Schottky metal layer; 30-Polysilicon layer; 32-Gate; 34-Gate oxide layer; 36-Drain; H1-Distance from oxide layer to bottom of trench; H2-Depth of trench. Detailed Implementation
[0021] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. The technical features designed in the different embodiments of this utility model described below can be combined with each other as long as they do not conflict with each other. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the protection scope of this utility model.
[0022] In the description of this utility model, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, unless otherwise stated, "a plurality of" means two or more. Additionally, the term "comprising" and any variations thereof mean "at least comprising."
[0023] Please refer to Figures 1 to 5. Figure 1 is a flowchart illustrating a method for manufacturing a MOSFET device according to an embodiment of the present invention, and Figures 2 to 5 are structural schematic diagrams of the MOSFET device according to an embodiment of the present invention at each stage of the manufacturing process.
[0024] As shown in the figure, a method for manufacturing a MOSFET device according to an embodiment of the present invention includes the following steps:
[0025] S100: An N-type drift region 14 is grown on the substrate 12. The thickness of the N-type drift region 14 ranges from 5 to 15 μm.
[0026] S200: Etch the N-type drift region 14 to form the trench 16.
[0027] S300: A P-type base region 18 is set on the N-type drift region 14.
[0028] S400: Set N+ source region 20 on P-type base region 18.
[0029] S500: A P+ ohmic contact area 22 is provided on the P-type base region 18, and the P+ ohmic contact area 22 is connected to the N+ source region 20.
[0030] S600: First, a first Schottky metal layer 24 is deposited on the surface of the N-type drift region 14, the P-type base region 18, the N+ source region 20, and the P+ ohmic contact region 22. Then, an oxide layer 26 is filled into the trench 16, with the oxide layer 26 located on top of the first Schottky metal layer 24. The material of the first Schottky metal layer 24 may include Ti, Mo, Pt, or Ni.
[0031] S700: Etch oxide layer 26 and first Schottky metal layer 24 so that oxide layer 26 and first Schottky metal layer 24 are below the P-type base region 18. This facilitates subsequent via formation.
[0032] S800: A rapid thermal annealing process is performed to form a second Schottky metal layer 28 by connecting the first Schottky metal layer 24 and the N-type drift region 14. Then, the oxide layer 26 and the first Schottky metal layer 24 are etched away. The material of the second Schottky metal layer 28 includes metal silicide, which is formed by the reaction of Schottky metal and silicon in a high-temperature annealing environment. The metal silicide acts at the interface to form a depletion layer, generating a built-in electric field, reducing the electric field strength at the bottom of the gate of the trench 16, and improving the reliability of the device.
[0033] Furthermore, the manufacturing method of MOSFET devices also includes the following steps:
[0034] A polysilicon layer 30 is deposited in the trench 16, followed by oxidation of the gate 32 to form a gate oxide layer 34, and then polysilicon deposition to form the gate 32.
[0035] An interlayer dielectric layer is grown on the surface of the gate oxide layer 34, the N+ source region 20 and the P+ ohmic contact region 22. Ni is then deposited by photolithography etching, and after annealing, a contact region is formed. Then, metal is deposited by photolithography etching to form the source electrode.
[0036] Before depositing the first Schottky metal layer 24, a carbon film is deposited as a protective layer on the surfaces of the N-type drift region 14, the P-type base region 18, the N+ source region 20, and the P+ ohmic contact region 22. Then, a high-temperature annealing process is performed at 1800–2000 °C for 10–30 min, followed by removal of the carbon film. This step protects the device surface morphology and suppresses the increase in surface roughness. During the high-temperature activation annealing process of SiC ion implantation, the carbon film acts as a protective layer covering the wafer surface. By suppressing the sublimation and redeposition of Si at the surface, the carbon film effectively prevents the degradation of the SiC surface morphology.
[0037] Referring to Figures 2 to 5, as shown in Figure 2, a silicon carbide substrate 12 is grown with a thickness of 10 μm and a doping concentration of 7 × 10⁻⁶. 15 / cm 3 ~1.1×10 16 / cm 3 The N-type drift region 14 is formed. Then, a new mask is deposited according to the trench 16 pattern, the trench 16 is etched, and the surface mask is removed. Next, a new mask is deposited according to the P-type base region 18 pattern, and Al ions with a dose of 4E12 are implanted to form the P-type base region 18. The surface mask is then removed, and a new mask is deposited according to the N+ source region 20 pattern, and N ions with a dose of 6E14 are implanted to form the N+ source region 20. After removing the surface mask, a new mask is deposited according to the P+ ohmic contact region 22 pattern, and Al ions with a dose of 8E14 are implanted to form the ohmic contact region, and the surface mask is then removed. A carbon film is deposited on the surface as a protective layer to reduce surface degradation caused by Si desorption and surface atom migration. Then, a high-temperature annealing treatment is performed at a temperature of 1800~2000℃ for 10min~30min. After annealing, the carbon film is removed. Next, after depositing a first Schottky metal layer 24 on the surface, an oxide layer 26 is deposited to fill the trench 16.
[0038] As shown in Figure 3, the oxide layer 26 is etched back to 1 / 4 of the distance from the bottom of the trench 16. That is, the distance H1 from the etched oxide layer 26 to the bottom of the trench 16 is 1 / 4 of the depth H2 of the trench 16. Then, the Schottky metal is wet-etched to 1 / 4 of the distance from the bottom of the trench 16.
[0039] As shown in Figure 4, a rapid thermal annealing process is performed under high temperature and nitrogen conditions to form a second Schottky metal layer 28 on the surface of the first Schottky metal layer 24 and the N-type drift region 14 of silicon carbide. Then, the oxide layer 26 and the first Schottky metal layer 24 are etched away. The second Schottky metal layer 28 formed at this time is disposed on the sidewalls and bottom of the trench 16. The second Schottky metal layer 28 is continuous and complete, covering the bottom corner of the trench 16.
[0040] As shown in Figure 5, a polysilicon layer 30 is deposited in trench 16, with a thickness approximately 1 / 4 of the depth H2 of trench 16. Next, gate oxide 34 is formed by oxidizing gate 32, followed by polysilicon deposition to form gate 32. An interlayer dielectric (ILD) is grown on the surfaces of the gate oxide 34, the N+ source region 20, and the P+ ohmic contact region 22. Ni is then deposited by photolithography etching, followed by annealing to form the contact region. Finally, metal is deposited and photolithographically etched to form the source. The final cell structure is shown in Figure 5.
[0041] A passivation layer can be deposited again by photolithography etching to form passivation. After the front-side process is completed, the back-side is ground to the required thickness, and then polished, cleaned, evaporated, and alloyed to form the back-side metal as the drain electrode 36.
[0042] Please refer to Figure 6, which is a schematic diagram of the structure of a MOSFET device provided in an embodiment of the present invention. The MOSFET device shown in Figure 6 can be fabricated using the manufacturing method described above. As shown in the figure, the MOSFET device includes a substrate 12, an N-type drift region 14, a P-type base region 18, an N+ source region 20, a P+ ohmic contact region 22, and a second Schottky metal layer 28.
[0043] An N-type drift region 14 is disposed on the substrate 12, a P-type base region 18 is disposed on the N-type drift region 18, and an N+ source region 20 is disposed on the P-type base region 18. A trench 16 is formed between the N-type drift region 14, the P-type base region 18, and the N+ source region 20. A P+ ohmic contact region 22 is disposed on the P-type base region 18 and connects to the N+ source region 20. A second Schottky metal layer 28 is located within the N-type drift region 14 and connects to the sidewalls and bottom of the trench 16. By providing a second Schottky metal layer 28 connecting the trench 16 within the N-type drift region 14, the electric field concentration at the bottom of the gate of the trench 16 is reduced, thereby improving the reliability of the device.
[0044] Furthermore, the MOSFET device may also include a polysilicon layer 30, a gate 32, and a gate oxide layer 34. The polysilicon layer 30 is deposited at the bottom of the trench 16, the gate oxide layer 34 is disposed on the polysilicon layer 30, and the gate 32 is disposed within the gate oxide layer 34.
[0045] Furthermore, the MOSFET device also includes a drain 36, which is disposed on the gate oxide layer 34, the P+ ohmic contact region 22 and the N+ source region 20.
[0046] Furthermore, the second Schottky metal layer 28 is located below the P-type base region 18.
[0047] In summary, the MOSFET device provided by this invention reduces the electric field concentration at the bottom of the gate of the trench 16 by forming a second Schottky metal layer 28 at the bottom of the trench 16, thereby improving the reliability of the device. Furthermore, since the bottom of the gate 32 is composed of a Schottky metal and a polysilicon layer 30, the Miller capacitance Cgd can be reduced, increasing the switching speed.
[0048] Furthermore, those skilled in the art should understand that although many problems exist in the prior art, each embodiment or technical solution of this utility model can be improved in only one or a few aspects, without necessarily solving all the technical problems listed in the prior art or background art simultaneously. Those skilled in the art should understand that any content not mentioned in a claim should not be construed as a limitation on that claim.
[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.
Claims
1. A MOSFET device, characterized in that: The MOSFET device includes: a substrate; an N-type drift region disposed on the substrate; a P-type base region disposed on the N-type drift region; an N+ source region disposed on the P-type base region, wherein a trench is formed between the N-type drift region, the P-type base region, and the N+ source region; a P+ ohmic contact region disposed on the P-type base region, wherein the P+ ohmic contact region is connected to the N+ source region; and a second Schottky metal layer located within the N-type drift region and connecting the sidewalls and bottom of the trench.
2. The MOSFET device according to claim 1, characterized in that: The MOSFET device further includes a polysilicon layer, a gate, and a gate oxide layer. The polysilicon layer is deposited at the bottom of the trench, the gate oxide layer is disposed on the polysilicon layer, and the gate is disposed within the gate oxide layer.
3. The MOSFET device according to claim 2, characterized in that: The MOSFET device further includes a drain electrode disposed on the gate oxide layer, the P+ ohmic contact region, and the N+ source region.
4. The MOSFET device according to claim 1, characterized in that: The thickness of the N-type drift region ranges from 5 to 15 μm.
5. The MOSFET device according to claim 1, characterized in that: The doping concentration range of the N-type drift region is 7 × 10⁻⁶. 15 / cm 3 ~1.1×10 16 / cm 3 .
6. The MOSFET device according to claim 1, characterized in that: The substrate is made of silicon carbide.
7. The MOSFET device according to claim 1, characterized in that: The second Schottky metal layer is located beneath the P-type base region.