Method for manufacturing sigma trench in semiconductor device

Abstract

The application belongs to the technical field of semiconductor, and discloses a manufacturing method of sigma trench in semiconductor device, which comprises the following steps: providing a substrate, the substrate comprising a first device area and a second device area; forming a PMOS area gate and a PMOS gate mask layer on a first active area of the first device area; exposing the top of the PMOS gate mask layer outside a photoresist layer of the first device area; depositing a deposited silicon oxide layer on the top of the second device area and the top of the PMOS gate mask layer; removing the photoresist layer of the first device area; etching to remove the natural silicon oxide layer on the surface of the first active area, and then etching the silicon of the first active area to form a U-shaped trench in the semiconductor substrate of the first device area; and using TMAH etching to form a sigma trench on the U-shaped trench. In the process of embedding germanium silicon into the source and drain, the height difference between the PMOS and the NMOS is avoided, and the subsequent process is not affected.

Description

Technical Field

[0001] This application belongs to the field of semiconductor manufacturing technology, and more specifically, relates to a method for fabricating sigma trenches in a semiconductor device. Background Technology

[0002] Source-drain embedded germanium silicon (SiGe) technology is an important technology in semiconductor device manufacturing. It is widely used in semiconductor devices below 90nm to improve the speed of PMOS (P-type metal oxide semiconductor).

[0003] The SiGe source / drain embedding technique utilizes the difference between the lattice constants of germanium (Ge) and silicon (Si). Silicon has a lattice constant of 5.431 Å, while germanium has a lattice constant of 5.653 Å. Therefore, the lattice constant of the SiGe alloy lies between the two and increases with increasing germanium content. When SiGe strain material is embedded in the source / drain regions, the lattice constant mismatch generates stress on the substrate silicon. This stress alters the band structure of the silicon valence band, reducing the effective mass of hole conductance and thus improving the speed of PMOS devices.

[0004] Source / drain embedded SiGe technology is typically achieved through epitaxial growth. Epitaxial growth is a method of growing one or more new crystals on a single-crystal substrate. In source / drain embedded SiGe technology, grooves are first etched into the source / drain regions of the MOS device, and then SiGe source / drain materials are epitaxially grown using methods such as chemical vapor deposition (CVD). CVD can specifically employ PECVD (plasma-enhanced chemical vapor deposition) or LPCVD (low-pressure chemical vapor deposition). During growth, the stress and lattice quality of the SiGe strained material can be controlled by adjusting parameters such as germanium content, growth temperature, and growth rate.

[0005] Please see Figures 1 to 5 The diagram shown is a schematic of an existing structure for forming Sigma-type germanium-silicon trenches. Figure 1 and 2 As shown, a germanium-silicon mask layer 101 is first formed on a substrate 100 having a PMOS region gate 21 and an NMOS region gate 31; as Figure 3 As shown, the germanium-silicon mask layer 101 on top of the PMOS region is removed; as Figure 4 As shown, U-shaped trench 4 is etched in the PMOS region substrate using a plasma etching process; as Figure 5 As shown, sigma trench 5 was formed using TMAH (Tetramethylammonium Hydroxide); germanium-silicon deposition was performed within the sigma trench 5 using an epitaxial growth process. Figures 4-5As shown, in the SiGe process, the active area (AA region) of the PMOS needs to be opened by dry etching, then a sigma trench 5 is formed by TMAH chemical etching, and SiGe is grown in the trench by epitaxy. During the dry and wet etching of the AA region of the PMOS, the PMOS gate mask layer 22 (usually oxide semiconductor OX) on top of the gate 21 of the PMOS region is also damaged, resulting in a height difference between the PMOS and NMOS, which has an adverse effect on subsequent processes. Summary of the Invention

[0006] The purpose of this invention is to provide a method for fabricating sigma trenches in semiconductor devices, in order to solve the technical problem in the existing SiGe process that, during the dry and wet etching of the AA region of PMOS, the PMOS gate mask layer at the top of the PMOS gate is also damaged, resulting in a height difference between PMOS and NMOS that affects subsequent processes.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] This invention provides a method for fabricating sigma trenches in a semiconductor device, comprising:

[0009] A substrate is provided, the substrate including a first device region and a second device region; the first device region includes a first active region, a PMOS gate is formed on the first active region, and a PMOS gate mask layer is provided on top of the PMOS gate.

[0010] A photoresist layer is formed in the first device region, and the top of the PMOS gate mask layer is exposed outside the photoresist layer;

[0011] A deposited silicon oxide layer is formed on top of the second device region and on top of the PMOS gate mask layer;

[0012] Remove the photoresist layer from the first device region;

[0013] The native silicon oxide layer on the surface of the first active region is removed by etching, and then the silicon in the first active region is etched to form a U-shaped trench in the semiconductor substrate of the first device region.

[0014] The U-shaped trench is formed into a sigma trench using TMAH etching.

[0015] A further improvement of the present invention is that the first device region is a PMOS region and the second device region is an NMOS region.

[0016] A further improvement of the present invention is that the step of forming a photoresist layer in the first device region and exposing the top of the PMOS gate mask layer outside the photoresist layer specifically includes:

[0017] Photoresist is spin-coated onto a substrate, covering a first device region and a second device region; photoresist is removed from the second device region; a portion of the photoresist in the first device region is etched away, such that the top height of the photoresist layer is equal to or lower than the top height of the PMOS gate mask layer, thereby exposing the top of the PMOS gate mask layer to the outside of the photoresist layer.

[0018] A further improvement of the present invention is that the step of depositing a silicon oxide layer on top of the second device region and on top of the PMOS gate mask layer specifically includes:

[0019] Silicon oxide is deposited on the substrate surface using liquid phase deposition to obtain a deposited silicon oxide layer; the deposited silicon oxide layer covers the second device region and the top of the PMOS gate mask layer.

[0020] A further improvement of the present invention is that: in the step of depositing silicon oxide on the substrate surface by liquid phase deposition, the substrate surface is treated with a Si-saturated fluorosilicic acid solution, and Si in the fluorosilicic acid solution precipitates out and forms a deposited silicon oxide layer on top of the second device region and the PMOS gate mask layer.

[0021] A further improvement of the present invention is that the step of etching away the natural silicon oxide layer on the surface of the first active region, and then etching the silicon of the first active region to form a U-shaped trench in the semiconductor substrate of the first device region, specifically includes:

[0022] Dry etching is used to remove the natural silicon oxide layer on the surface of the first active region, while the deposited silicon oxide layer on top of the PMOS gate mask layer is consumed in the same way; after the natural silicon oxide layer on the surface of the first active region is removed by etching, the silicon of the first active region is then etched to form a U-shaped trench in the semiconductor substrate of the first device region.

[0023] A further improvement of the present invention is that it also includes a step of depositing germanium-silicon in the sigma trench using an epitaxial process.

[0024] A further improvement of the present invention is that, in the step of depositing a silicon oxide layer on top of the second device region and on top of the PMOS gate mask layer, the thickness of the deposited silicon oxide layer is 10 Å to 500 Å.

[0025] A further improvement of the present invention is that, in the step of forming sigma trenches by etching the U-shaped trenches with TMAH, the concentration of TMAH is 1wt% to 30wt%, and the temperature is 20℃ to 80℃.

[0026] A further improvement of the present invention is that the thickness of the deposited silicon oxide layer is greater than the thickness of the natural silicon oxide layer on the surface of the first active region.

[0027] Compared with the prior art, the present invention has the following unexpected technical effects:

[0028] This invention provides a method for fabricating sigma trenches in a semiconductor device, comprising: providing a substrate, the substrate including a first device region and a second device region; the first device region including a first active region, a PMOS gate formed on the first active region, and a PMOS gate mask layer on top of the PMOS gate; forming a photoresist layer in the first device region, exposing the top of the PMOS gate mask layer outside the photoresist layer; depositing a silicon oxide layer on top of the second device region and on top of the PMOS gate mask layer; removing the photoresist layer in the first device region; etching away the native silicon oxide layer on the surface of the first active region, and then etching the silicon in the first active region to form a U-shaped trench in the semiconductor substrate of the first device region; and forming a sigma trench by TMAH etching of the U-shaped trench. In existing technologies, when forming SiGe trenches, a SiN PMOS gate mask layer is used as a barrier layer, which creates a height difference between the NMOS and PMOS. This invention proposes forming a photoresist layer in the first device region and exposing the top of the PMOS gate mask layer outside the photoresist layer; depositing a silicon oxide layer as a barrier layer on the top of the second device region and on the top of the PMOS gate mask layer; the barrier layer is formed not only on the NMOS but also on the PMOS gate, thus avoiding the height difference.

[0029] The unexpected technical effect of this application is as follows: This invention uses liquid phase deposition to form silicon oxide on the substrate surface. Due to the difference in surface properties, the photoresist surface is hydrophobic, and silicon oxide will not form on the surface in the liquid phase deposition method. Silicon oxide is easy to deposit on the surface of silicon-containing materials. In addition, even if a small amount of silicon oxide is formed on the photoresist surface, the silicon oxide on the photoresist surface will be stripped off simultaneously when the photoresist layer is removed by sulfuric acid and hydrogen peroxide. Therefore, in the process of forming the silicon oxide layer by liquid phase deposition, the silicon oxide layer is only deposited on the surface of the second device region (NMOS region) and the top of the PMOS gate mask layer, and will not cover the AA region of the first device region (PMOS region), which facilitates the subsequent dry etching.

[0030] The unexpected technical effect of this application is that the thickness of the deposited silicon oxide layer is greater than the thickness of the natural silicon oxide layer on the surface of the first active region. This setting enables the dry etching of the AA region to be performed normally without etching the PMOS gate mask layer, thus avoiding the height difference between PMOS and NMOS and not affecting subsequent processes. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the structure of a semiconductor device in the prior art;

[0033] Figure 2 This is a schematic diagram of the structure for forming a germanium-silicon mask layer on the surface of a semiconductor device in the prior art;

[0034] Figure 3 This is a schematic diagram of the structure for removing the germanium-silicon mask layer on top of the PMOS region on the surface of a semiconductor device in the prior art;

[0035] Figure 4 This is a schematic diagram of a U-shaped trench formed in the PMOS region of a semiconductor device in the prior art;

[0036] Figure 5 This is a schematic diagram of a structure for forming sigma trenches in the PMOS region of a semiconductor device in the prior art;

[0037] Figure 6 This is a schematic diagram of the structure of a semiconductor device in one embodiment of the present invention;

[0038] Figure 7 This is a schematic diagram of the structure of a photoresist layer formed in the PMOS region of a semiconductor device according to an embodiment of the present invention;

[0039] Figure 8 This is a schematic diagram of the structure in which a silicon oxide layer is deposited on top of the NMOS region and the PMOS gate mask layer of a semiconductor device in one embodiment of the present invention.

[0040] Figure 9 This is a schematic diagram of the structure for removing the photoresist layer from the surface of a semiconductor device in one embodiment of the present invention;

[0041] Figure 10 This is a schematic diagram of a U-shaped trench formed in the PMOS region of a semiconductor device according to an embodiment of the present invention;

[0042] Figure 11 This is a schematic diagram of a structure forming a sigma trench in the PMOS region of a semiconductor device according to an embodiment of the present invention;

[0043] Figure 12 This is a schematic diagram of a germanium-silicon epitaxial growth structure formed in a sigma trench in the PMOS region of a semiconductor device according to an embodiment of the present invention.

[0044] Explanation of reference numerals in the attached figures:

[0045] 100. Substrate; 101. Germanium-silicon mask layer; 102. Photoresist layer; 103. Deposited silicon oxide layer;

[0046] 2. First active region; 20. Natural silicon oxide layer on the surface of the first active region; 21. PMOS gate; 22. PMOS gate mask layer; 23. First gate sidewall;

[0047] 3. Second active region; 30. Natural silicon oxide layer on the surface of the second active region; 31. NMOS gate; 32. NMOS gate mask layer; 33. Second gate sidewall;

[0048] 4. U-shaped groove;

[0049] 5. Sigma trenches;

[0050] 6. Germanium-silicon epitaxial growth structure. Detailed Implementation

[0051] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0053] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0054] Please see Figures 6 to 11 As shown, the present invention provides a method for fabricating sigma trenches in a semiconductor device, comprising the following steps:

[0055] Step S1: Provide a substrate 100, the substrate 100 including a first device region and a second device region;

[0056] For example, the substrate 100 is a semiconductor material; specifically, the material of the substrate 100 may be silicon (Si) or other materials.

[0057] For example, the first device region is a PMOS region, and the second device region is an NMOS region. The first device region includes a first active region 2, on which a first active region surface natural silicon oxide layer 20 is formed. A PMOS region gate 21 is formed on the first active region surface natural silicon oxide layer 20, and a PMOS region gate mask layer 22 is provided on top of the PMOS region gate 21. A first gate sidewall 23 is provided next to the PMOS region gate 21. The second device region includes a second active region 3, on which a second active region surface natural silicon oxide layer 30 is formed. An NMOS region gate 31 is formed on the second active region surface natural silicon oxide layer 30, and an NMOS region gate mask layer 32 is provided on top of the NMOS region gate 31. A second gate sidewall 33 is provided next to the NMOS region gate 31.

[0058] Step S2: Photoresist (PR) is spin-coated onto a substrate 100 having a first device region and a second device region to form a photoresist layer 102; the photoresist layer 102 covers the PMOS gate 21 and the NMOS gate 31; the photoresist in the NMOS region is removed to open the NMOS region, and then a portion of the photoresist layer 102 in the PMOS region is removed by dry etching, so that the height of the photoresist layer 102 is lower than the height of the PMOS gate mask layer 22, exposing the top of the PMOS gate mask layer 22 (e.g., ...). Figure 6 , 7 (As shown).

[0059] Step S3: Deposit silicon oxide of 10 Å to 500 Å on the surface of substrate 100 using liquid phase deposition to obtain a deposited silicon oxide layer 103; the deposited silicon oxide layer 103 includes a first deposited silicon oxide layer covering the PMOS gate mask layer 22 and a second deposited silicon oxide layer covering the NMOS region. This invention employs a liquid phase deposition method to form chemical silicon oxide on the surface of substrate 100. Due to differences in surface properties, the photoresist surface is hydrophobic, and silicon oxide will not form on its surface during liquid phase deposition. Silicon oxide, however, easily deposits on the surface of silicon-containing materials. Furthermore, even if a small amount of silicon oxide forms on the photoresist surface, it will be simultaneously stripped away during the subsequent removal of the photoresist layer 102 using sulfuric acid and hydrogen peroxide. Therefore, during the liquid phase deposition process of forming the silicon oxide layer 103, the silicon oxide layer 103 is deposited only on the surface of the NMOS region (the first active region surface natural silicon oxide layer 20, the first gate sidewall 23, and the PMOS gate mask layer 22 are all silicon-containing materials) and on the top of the PMOS gate mask layer 22 (which is a silicon-containing material). Figure 8 (As shown).

[0060] For example, the present invention employs a liquid phase deposition method to treat the surface of substrate 100 with a Si-saturated fluorosilicic acid solution, causing Si in the fluorosilicic acid solution to precipitate and form a deposited silicon oxide layer 103 on top of the NMOS region and the PMOS gate mask layer 22; the specific reaction formula is shown below:

[0061] H₂SiF₆ + 2H₂O → SiO₂↓ + 6HF

[0062] Step S4: Remove the photoresist layer 102 in the PMOS region (e.g., Figure 9 (As shown).

[0063] For example, concentrated sulfuric acid is a strong oxidizing and corrosive agent, and at high concentrations, its oxidizing power is much stronger than that of hydrogen peroxide. Hydrogen peroxide is also an oxidizing agent, but its oxidizing power is relatively weak, and it can generally only oxidize substances with lower oxidizing power. In wet cleaning methods for removing photoresist, hydrogen peroxide is injected into a sulfuric acid solution. When the two are mixed, an exothermic reaction occurs, forming a high-temperature cleaning solution. This cleaning solution has strong oxidizing properties and can react with the photoresist, thereby removing it.

[0064] In this invention, the photoresist layer 102 on the surface of the substrate 100 is soaked or sprayed with sulfuric acid hydrogen peroxide (piranha solution). The sulfuric acid hydrogen peroxide reacts with the photoresist to remove the photoresist layer 102. Then, ultrasonic cleaning is performed in ultrapure water. After cleaning, the substrate is dried with nitrogen gas to remove the photoresist layer 102 in the PMOS region.

[0065] For example, the sulfuric acid hydrogen peroxide solution is a mixture of concentrated sulfuric acid hydrogen peroxide solution in a volume ratio of 3:1 to 7:1; the specific mixing ratio is adjusted according to the specific situation of the photoresist to obtain the best cleaning effect.

[0066] Step S5: Remove the native silicon oxide layer on the surface of the PMOS AA region using dry etching, and then etch the silicon in the AA region to form a U-shaped trench 4 of a predetermined depth in the PMOS region semiconductor substrate 100 (e.g., Figure 10 (As shown).

[0067] For example, dry etching of the PMOS surface natural silicon oxide layer to form a U-groove involves first etching the surface natural silicon oxide layer and then etching the silicon beneath it. Etching the surface natural silicon oxide layer consumes the deposited silicon oxide layer 103 simultaneously, but etching the silicon does not consume the deposited silicon oxide layer 103, effectively protecting the PMOS gate mask layer 22 from etching.

[0068] For example, the thickness of the deposited silicon oxide layer 103 is much greater than the thickness of the natural silicon oxide layer on the surface, for example, the thickness of the deposited silicon oxide layer is 400 Å to 500 Å, and the thickness of the natural silicon oxide layer is 10 Å to 50 Å.

[0069] For example, a U-shaped trench 4 of a predetermined depth is formed in a PMOS region semiconductor substrate 100, the predetermined depth being 100 Å to 500 Å;

[0070] For example, while the dry etching removes the natural silicon oxide layer 20 on the surface of the first active region of the PMOS AA region, the first deposited silicon oxide layer on top of the PMOS gate mask layer 22 is also consumed, so that the PMOS gate mask layer 22 is not consumed, and there is no height difference between the PMOS gate mask layer 22 and the NMOS gate mask layer 32, which will not affect the subsequent process and solves the technical problem of the prior art that this invention aims to solve.

[0071] In this invention, the NMOS AA has two layers: natural silicon oxide and liquid phase chemically deposited silicon oxide, which can therefore serve as a barrier layer for Si etching.

[0072] Step S6: Etch the U-shaped trench 4 again with a preset concentration of TMAH to form a sigma trench 5, and then remove the remaining deposited silicon oxide layer 103 with HF acid (e.g. Figure 11 (as shown); then remove the remaining deposited silicon dioxide with HF acid.

[0073] For example, the concentration range of TMAH can be adjusted according to process requirements, such as 1wt% to 30wt%, and the temperature range is 20℃ to 80℃.

[0074] Please see Figures 6 to 12As shown, the present invention provides a method for fabricating sigma trenches in a semiconductor device, comprising the following steps:

[0075] Step S1: Provide a substrate 100, which includes a first device region and a second device region. The substrate 100 can be made of silicon (Si). The first device region is a PMOS region, and the second device region is an NMOS region. The first device region includes a first active region 2, and a native silicon oxide layer 20 is formed on the surface of the first active region 2. A PMOS gate 21 is formed on the native silicon oxide layer 20 of the first active region, and a PMOS gate mask layer 22 is provided on top of the PMOS gate 21. A first gate sidewall 23 is provided next to the PMOS gate 21. The second device region includes a second active region 3, and a native silicon oxide layer 30 is formed on the surface of the second active region 3. An NMOS gate 31 is formed on the native silicon oxide layer 30 of the second active region, and an NMOS gate mask layer 32 is provided on top of the NMOS gate 31. A second gate sidewall 33 is provided next to the NMOS gate 31.

[0076] Step S2: Photoresist is spin-coated onto the substrate 100 having the first device region and the second device region to form a photoresist layer 102; the photoresist layer 102 covers the PMOS gate 21; then, a portion of the photoresist layer 102 in the PMOS region is removed by dry etching, so that the height of the photoresist layer 102 is lower than or equal to the height of the PMOS gate mask layer 22, exposing the top of the PMOS gate mask layer 22 (e.g., ...). Figure 6 , 7 (As shown).

[0077] Step S3: Deposit silicon oxide 50 Å to 400 Å on the surface of substrate 100 using liquid phase deposition to obtain a deposited silicon oxide layer 103; the deposited silicon oxide layer 103 includes a first deposited silicon oxide layer covering the PMOS gate mask layer 22, and a second deposited silicon oxide layer covering the NMOS region (e.g., Figure 8 (As shown).

[0078] Step S4: Remove the photoresist layer 102 in the PMOS region using sulfuric acid and hydrogen peroxide (e.g., Figure 9 (As shown).

[0079] Step S5: Remove the native silicon oxide layer on the surface of the PMOS AA region using dry etching. First, etch the native silicon oxide layer, then etch the silicon beneath the native silicon oxide layer to form a U-shaped trench 4 of a predetermined depth in the PMOS region semiconductor substrate 100 (e.g., Figure 10 (As shown). When etching the natural silicon oxide layer on the surface, the deposited silicon oxide layer 103 is consumed simultaneously, but when etching silicon, the deposited silicon oxide layer 103 is not consumed, effectively protecting the PMOS gate mask layer 22 from being etched.

[0080] Step S6: Etch the U-shaped trench 4 again with a preset concentration of TMAH to form a sigma trench 5, and then remove the remaining deposited silicon oxide layer 103 with HF acid (e.g. Figure 11 (as shown); then remove the remaining deposited silicon dioxide with HF acid.

[0081] Step S7: Deposit germanium-silicon in sigma trench 5 to obtain germanium-silicon epitaxial growth structure 6.

[0082] For example, in step S6, germanium-silicon deposition is performed in the sigma trench 5 using an epitaxial growth process (epitaxy growth process).

[0083] In existing technologies, when forming SiGe trenches, using a SiN PMOS gate mask layer as a barrier layer creates a height difference between the NMOS and PMOS. This invention proposes forming a photoresist layer in the first device region, exposing the top of the PMOS gate mask layer outside the photoresist layer. A deposited silicon oxide layer is deposited as a barrier layer on top of the second device region and on top of the PMOS gate mask layer. This barrier layer is formed not only in the NMOS region but also on the NMOS gate mask layer of the PMOS. While dry etching removes the natural silicon oxide layer 20 on the surface of the first active region of the PMOS AA region, the first deposited silicon oxide layer on top of the PMOS gate mask layer 22 is also consumed, preventing the PMOS gate mask layer 22 from being consumed. This eliminates the height difference between the PMOS gate mask layer 22 and the NMOS gate mask layer 32, thus avoiding any impact on subsequent processes and solving the technical problems of the prior art.

[0084] As is known from common technical knowledge, this invention can be implemented through other embodiments that do not depart from its spirit or essential characteristics. Therefore, the disclosed embodiments described above are merely illustrative in all respects and are not the only ones. All modifications within the scope of this invention or equivalent to the scope of this invention are included in this invention.

Claims

1. A method for fabricating sigma trenches in a semiconductor device, characterized in that, include: A substrate is provided, the substrate including a first device region and a second device region; the first device region includes a first active region, a PMOS gate is formed on the first active region, and a PMOS gate mask layer is provided on top of the PMOS gate. A photoresist layer is formed in the first device region, and the top of the PMOS gate mask layer is exposed outside the photoresist layer; A deposited silicon oxide layer is formed on top of the second device region and on top of the PMOS gate mask layer; Remove the photoresist layer from the first device region; The native silicon oxide layer on the surface of the first active region is removed by etching, and then the silicon in the first active region is etched to form a U-shaped trench in the semiconductor substrate of the first device region. The U-shaped trenches are formed into sigma trenches using TMAH etching; The thickness of the deposited silicon oxide layer is greater than the thickness of the natural silicon oxide layer on the surface of the first active region.

2. The method for fabricating a sigma trench in a semiconductor device according to claim 1, characterized in that, The first device region is a PMOS region, and the second device region is an NMOS region.

3. The method for fabricating a sigma trench in a semiconductor device according to claim 1, characterized in that, The step of forming a photoresist layer in the first device region and exposing the top of the PMOS gate mask layer outside the photoresist layer specifically includes: Photoresist is spin-coated onto a substrate, covering a first device region and a second device region; the photoresist in the second device region is removed; a portion of the photoresist in the first device region is etched away, such that the top height of the photoresist layer is equal to or lower than the top height of the PMOS gate mask layer, thereby exposing the top of the PMOS gate mask layer to the outside of the photoresist layer.

4. The method for fabricating a sigma trench in a semiconductor device according to claim 1, characterized in that, The step of depositing a silicon oxide layer on top of the second device region and on top of the PMOS gate mask layer specifically includes: Silicon oxide is deposited on the substrate surface using liquid phase deposition to obtain a deposited silicon oxide layer; the deposited silicon oxide layer covers the second device region and the top of the PMOS gate mask layer.

5. The method for fabricating a sigma trench in a semiconductor device according to claim 4, characterized in that, In the step of depositing silicon oxide on the substrate surface using liquid phase deposition, the substrate surface is treated with a Si-saturated fluorosilicic acid solution, and Si in the fluorosilicic acid solution precipitates out, forming a deposited silicon oxide layer on top of the second device region and the PMOS gate mask layer.

6. The method for fabricating a sigma trench in a semiconductor device according to claim 1, characterized in that, The step of etching away the native silicon oxide layer on the surface of the first active region, and then etching the silicon in the first active region to form a U-shaped trench in the semiconductor substrate of the first device region, specifically includes: Dry etching is used to remove the natural silicon oxide layer on the surface of the first active region, while the deposited silicon oxide layer on top of the PMOS gate mask layer is consumed in the same way; after the natural silicon oxide layer on the surface of the first active region is removed by etching, the silicon of the first active region is then etched to form a U-shaped trench in the semiconductor substrate of the first device region.

7. The method for fabricating a sigma trench in a semiconductor device according to claim 1, characterized in that, It also includes the step of depositing germanium-silicon in the sigma trench using an epitaxial process.

8. The method for fabricating a sigma trench in a semiconductor device according to claim 1, characterized in that, In the step of depositing a silicon oxide layer on top of the second device region and on top of the PMOS gate mask layer, the thickness of the deposited silicon oxide layer is 10 Å to 500 Å.

9. The method for fabricating a sigma trench in a semiconductor device according to claim 1, characterized in that, In the step of forming sigma trenches by etching the U-shaped trenches with TMAH, the concentration of TMAH is 1wt% to 30wt%, and the temperature is 20℃ to 80℃.

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