Laminated cell and preparation method thereof, photovoltaic module and photovoltaic system

Abstract

The invention relates to the technical field of solar cells, and particularly discloses a laminated cell, a preparation method thereof, a photovoltaic module and a photovoltaic system. The laminated cell comprises a bottom cell and a top cell; the first surface of the silicon substrate of the bottom cell is provided with a composite film layer, the composite film layer is formed by laminating a passivation layer and an antireflection layer, and the composite film layer is provided with a through graphical opening; and the top cell is arranged on one side, far away from the silicon substrate, of the composite film layer and is electrically connected with the bottom cell through the patterned opening. The preparation method comprises the following steps: providing a bottom cell with a composite film layer; etching a patterned opening on the composite film layer by using laser; and forming a top cell on the composite film layer and the patterned opening. According to the invention, the charge transmission channel is formed by locally removing the composite film layer, and meanwhile, most of the film layers are kept to maintain passivation and anti-reflection effects, so that the contradiction between charge transmission and bottom cell performance protection in the laminated cell is solved, the process is accurate, the compatibility is high, and the photoelectric conversion efficiency of the laminated cell is remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and in particular to a tandem solar cell and its preparation method, photovoltaic module, and photovoltaic system. Background Technology

[0002] While crystalline silicon solar cell technology is mature, its photoelectric conversion efficiency is nearing its theoretical limit. Perovskite / crystalline silicon tandem cells, by combining the spectral response advantages of the two materials, can theoretically achieve efficiencies exceeding 30%, making them a hot topic in industry research and development.

[0003] In a two-terminal tandem solar cell structure, achieving efficient electrical connection between the top and bottom cells is crucial. Taking a tunneling oxide passivated contact (TOPCon) cell with excellent passivation performance as the bottom cell as an example, its front side is typically deposited with Al2O3 / SiN. x Composite films are used to provide excellent surface passivation and anti-reflection properties. However, the insulating or high-resistivity characteristics of these composite films severely hinder carrier transport between the phosphorus-doped polycrystalline silicon layer (N-poly layer) of the bottom cell and the perovskite top cell, resulting in the inability of the stacked cells to form an effective current loop.

[0004] Existing technologies mainly employ two solutions to address this problem: one is to completely remove the Al2O3 / SiN from the surface of the N-poly layer using wet etching. x Two approaches exist: one is to deposit a composite film layer, and the other is to leave the N-poly layer undeposited. However, the first approach results in the N-poly layer losing its passivation protection, leading to a sharp increase in surface recombination rate, higher reflectivity, and significant degradation of the open-circuit voltage and short-circuit current of the bottom cell. Furthermore, the hydrofluoric acid and other etchants used in wet etching are prone to lateral diffusion, damaging the passivation film on the back of the cell. The second approach, due to the lack of a passivation layer on the N-poly layer surface, suffers from low carrier lifetime and high surface roughness, hindering uniform coverage of the perovskite film and easily generating interface defects and leakage channels, thus limiting the improvement of the stacked cell efficiency.

[0005] Therefore, existing technologies cannot achieve efficient charge transfer between tandem cells while maintaining the high performance of crystalline silicon bottom cells. This is a key technological bottleneck that restricts the further improvement of the performance and industrialization of perovskite / crystalline silicon tandem cells. Summary of the Invention

[0006] The purpose of this invention is to provide a tandem solar cell and its preparation method, photovoltaic module, and photovoltaic system, so as to solve the problem that the existing technology cannot simultaneously achieve the passivation and anti-reflection performance of the bottom cell and the charge transport between the layers.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] In a first aspect, the present invention provides a stacked battery, comprising:

[0009] A bottom cell, the bottom cell comprising a silicon substrate having a first side and a second side disposed opposite to each other;

[0010] A composite film layer located on the first surface of the silicon substrate, the composite film layer comprising a passivation layer and an antireflection layer sequentially stacked along a direction away from the silicon substrate, and the composite film layer having a patterned opening penetrating the passivation layer and the antireflection layer;

[0011] A top cell is located on the side of the composite film layer away from the silicon substrate, and the top cell is electrically connected to the bottom cell through the patterned opening.

[0012] This invention provides a physical channel for photogenerated carriers generated by the top cell to reach the core functional layer of the bottom cell by setting a "patterned opening that penetrates the passivation layer and the antireflection layer". This ensures that a complete current loop can be formed inside the stacked cell, avoiding current drop and fill factor loss caused by the blocking of the insulating film layer. By retaining the recombination film layer region that is not patterned (i.e., the film layer outside the opening region), the key surface passivation (reducing carrier recombination) and antireflection (enhancing light absorption) functions of the bottom cell are preserved. This significantly improves the photoelectric conversion efficiency, open-circuit voltage and short-circuit current of the stacked cell.

[0013] Furthermore, the patterned opening is in the form of a grid and / or a mesh, and the total area of ​​the patterned opening accounts for 10%-50% of the surface area of ​​the first surface.

[0014] Furthermore, the passivation layer comprises an Al2O3 layer with a thickness of 5nm-10nm; the antireflection layer comprises SiN. x The layer has a thickness of 50nm-100nm.

[0015] Furthermore, the bottom cell is a TOPCon cell, an HJT cell, or a PERC cell; the top cell is a perovskite cell.

[0016] Furthermore, the bottom cell further includes: a tunneling oxide layer located on the first surface of the silicon substrate, and a phosphorus-doped polycrystalline silicon layer located on the side of the tunneling oxide layer away from the silicon substrate; a boron-doped emitter located on the second surface of the silicon substrate, and a second passivation layer, a second antireflection layer, and a metal electrode sequentially stacked on the side of the boron-doped emitter away from the silicon substrate; wherein, the composite film layer is located on the side of the phosphorus-doped polycrystalline silicon layer away from the silicon substrate, and the top cell is electrically connected to the phosphorus-doped polycrystalline silicon layer through the patterned opening.

[0017] In a second aspect, the present invention provides a method for preparing a tandem battery, comprising the following steps:

[0018] S1: Provide a bottom cell, the bottom cell including a silicon substrate having a first side and a second side disposed opposite to each other, a composite film layer formed on the first side of the silicon substrate, the composite film layer including a passivation layer and an anti-reflection layer sequentially stacked along a direction away from the silicon substrate;

[0019] S2: Use a laser to etch the first surface of the silicon substrate to form a patterned opening that penetrates the passivation layer and the antireflection layer;

[0020] S3: A top cell is formed on the side of the composite film layer away from the silicon substrate, and the top cell is electrically connected to the bottom cell through the patterned opening.

[0021] Furthermore, in S2, the parameters for laser etching are: laser power 20W-40W, spot size 20μm-100μm, scanning rate 50000 mm / s-80000 mm / s, and frequency 100 kHz-500 kHz.

[0022] Furthermore, in S1, the method for preparing the bottom battery includes:

[0023] S11: Provides an N-type silicon substrate and polishes it on both sides;

[0024] S12: Boron diffusion is performed on the second surface of the silicon substrate to form a boron-doped emitter;

[0025] S13: Remove the boron-doped layer and borosilicate glass layer that are spread around the first and side surfaces;

[0026] S14: Texturing the first surface of the silicon substrate;

[0027] S15: Prepare a tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer on the first surface;

[0028] S16: Remove the phosphorus-silicon glass layer and phosphorus-doped polycrystalline silicon layer that are wrapped around the second side;

[0029] S17: A passivation layer and an antireflection layer are sequentially deposited on the first surface to form a composite film; a second passivation layer and a second antireflection layer are sequentially deposited on the second surface;

[0030] S18: Print metal electrodes on the second surface and sinter them;

[0031] In step S3, the formation step of the top battery includes:

[0032] S31: Cleaning removes residue and damage from laser etching of the first surface of the silicon substrate;

[0033] S32: Deposit a first transparent conductive layer on the surface of the composite film layer and the patterned opening;

[0034] S33: Deposit a hole transport layer on the surface of the first transparent conductive layer;

[0035] S34: Deposit a light-absorbing layer on the surface of the hole transport layer;

[0036] S35: Deposit an electron transport layer on the surface of the light-absorbing layer;

[0037] S36: Deposit a second transparent conductive layer on the surface of the electron transport layer;

[0038] S37: A top electrode is formed on the surface of the second transparent conductive layer.

[0039] Thirdly, the present invention provides a photovoltaic module, including a battery string, the battery string being formed by connecting multiple stacked cells as described above or stacked cells prepared by the above-described method for preparing stacked cells; an encapsulation layer for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulation layer away from the battery string.

[0040] Fourthly, the present invention provides a photovoltaic system including the photovoltaic module described above.

[0041] Compared with the prior art, the present invention has the following beneficial effects:

[0042] (1) This invention maintains the top-level surface passivation quality and low reflectivity of the bottom cell in the reserved area by laser patterning local openings, while establishing an efficient charge transport channel in the opening area. This fundamentally solves the inherent contradiction between "high-performance passivation" and "efficient charge transport", so that the open-circuit voltage (Voc), short-circuit current density (Jsc) and fill factor (FF) of the tandem cell are synergistically optimized, and finally achieves a significant improvement in photoelectric conversion efficiency.

[0043] (2) The laser etching process used in this invention has the advantages of high precision, non-contact, strong selectivity and high efficiency. It can accurately control the shape and size of the patterned opening, completely avoid the lateral drilling, chemical contamination and potential damage to the sensitive functional area on the back of the battery (such as the P-side passivation film) caused by wet etching, and improve the product yield and consistency. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a schematic diagram of the structure of the stacked battery provided in the embodiments of this application;

[0046] Figure 2 This is a process flow diagram of the method for preparing a stacked battery according to an embodiment of the present invention.

[0047] Explanation of key figure labels:

[0048] 100. Bottom cell; 101. Silicon substrate; 102. Tunneling oxide layer; 103. Phosphorus-doped polycrystalline silicon layer; 104. Passivation layer; 105. Antireflection layer; 106. Patterned opening; 107. Boron-doped emitter; 108. Second passivation layer; 109. Second antireflection layer; 110. Metal electrode; 200. Top cell; 201. First transparent conductive layer; 202. Hole transport layer; 203. Light-absorbing layer; 204. Electron transport layer; 205. Second transparent conductive layer; 206. Top electrode. Detailed Implementation

[0049] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other embodiments, well-known materials or methods have not been specifically described in order to avoid obscuring the invention.

[0050] Throughout this specification, references to “an embodiment,” “an example,” or “an example” mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases “an embodiment,” “an example,” “an example,” or “an example” appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0051] Terminology Explanation:

[0052] TOPCon: Tunnel Oxide Passivated Contact.

[0053] ALD: Atomic Layer Deposition;

[0054] PVD: Physical Vapor Deposition;

[0055] PSG: Phosphosilicate Glass.

[0056] BSG: Boron Silicate Glass.

[0057] In a first aspect, the present invention provides a stacked battery, comprising: a bottom battery 100, the bottom battery 100 including a silicon substrate 101 having a first side and a second side disposed opposite to each other, a composite film layer located on the first side of the silicon substrate 101, the composite film layer including a passivation layer 104 and an antireflection layer 105 sequentially stacked along a direction away from the silicon substrate 101, and the composite film layer having a patterned opening 106 penetrating the passivation layer 104 and the antireflection layer 105; and a top battery 200, the top battery 200 being located on the side of the composite film layer away from the silicon substrate 101, and the top battery 200 being electrically connected to the bottom battery 100 through the patterned opening 106.

[0058] In one specific embodiment, the patterned openings 106 are in the form of grid lines and / or meshes, and the total area of ​​the patterned openings 106 accounts for 10%-50% of the surface area of ​​the first surface of the silicon substrate 101. For example, the total area of ​​the patterned openings 106 can be 10%, 20%, 30%, 40%, 50% of the surface area of ​​the first surface of the silicon substrate 101, or between any two of the above values.

[0059] In one specific embodiment, the passivation layer 104 includes an Al2O3 layer with a thickness of 5nm-10nm; the antireflection layer 105 includes SiN. x The passivation layer 104 has a thickness of 50nm-100nm. For example, the thickness of the passivation layer 104 can be 5nm, 6nm, 7nm, 8nm, 9nm, 10nm or between any two of the above values; the thickness of the antireflection layer 105 can be 50nm, 60nm, 70nm, 80nm, 90nm, 100nm or between any two of the above values.

[0060] In one specific embodiment, the bottom cell 100 is a TOPCon cell, an HJT cell, or a PERC cell; the top cell 200 is a perovskite cell.

[0061] In one specific embodiment, the bottom cell 100 further includes: a tunneling oxide layer 102 located on a first surface of the silicon substrate 101, and a phosphorus-doped polycrystalline silicon layer 103 located on the side of the tunneling oxide layer 102 away from the silicon substrate 101; a boron-doped emitter 107 located on a second surface of the silicon substrate 101, and a second passivation layer 108, a second antireflection layer 109, and a metal electrode 110 sequentially stacked on the side of the boron-doped emitter 107 away from the silicon substrate 101; wherein, the composite film layer is located on the side of the phosphorus-doped polycrystalline silicon layer 103 away from the silicon substrate 101, and the top cell 200 is electrically connected to the phosphorus-doped polycrystalline silicon layer 103 through a patterned opening 106.

[0062] In one specific embodiment, the silicon substrate 101 is an N-type monocrystalline silicon wafer with a thickness of 100μm-200μm and a resistivity of 0.5Ω / cm. 2 -10Ω / cm 2 For example, the thickness of the silicon wafer can be 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 180μm, 200μm, or between any two of the above values, and the resistivity can be 0.5Ω / cm. 2 1Ω / cm 2 2Ω / cm 2 5Ω / cm 2 6Ω / cm 2 7Ω / cm 2 8.5Ω / cm 2 9Ω / cm 2 10Ω / cm 2 Or it may be between any two of the above values.

[0063] In one specific embodiment, the boron-doped emitter 107 has a thickness of 0.5 μm-1.5 μm and a sheet resistance of 200-400 Ω / cm. 2 For example, the thickness of the boron-doped emitter 107 can be 0.5 μm, 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, or between any two of the above values; the sheet resistance can be 200 Ω / cm. 2 250Ω / cm 2 300Ω / cm 2 350Ω / cm 2 400Ω / cm 2 Or it may be between any two of the above values.

[0064] In one specific embodiment, the thickness of the tunneling oxide layer 102 is 1nm-2nm. For example, the thickness of the tunneling oxide layer 102 can be 1nm, 1.2nm, 1.4nm, 1.6nm, 1.8nm, 2nm or between any two of the above values.

[0065] In one specific embodiment, the thickness of the phosphorus-doped polycrystalline silicon layer 103 is 20 nm to 100 nm, and the phosphorus doping concentration ranges from (0.1 to 2.0) E21 cm. -3 For example, the thickness of the phosphorus-doped polycrystalline silicon layer 103 can be 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 80 nm, 100 nm, or between any two of the above values; the phosphorus doping concentration can be 0.1 × 21 cm⁻¹. -3 0.5 E21cm -3 0.8E21cm -3 1 E21cm -3 1.5 E21cm -3 1.8 E21cm -3 2E21cm -3 Or it may be between any two of the above values.

[0066] In one specific embodiment, the top battery 200 includes a first transparent conductive layer 201, a hole transport layer 202, a light-absorbing layer 203, an electron transport layer 204, a second transparent conductive layer 205, and a top electrode 206, which are sequentially stacked along a direction away from the composite film layer.

[0067] Secondly, this application provides a method for preparing the above-mentioned stacked battery, comprising the following steps:

[0068] S1: A bottom cell 100 is provided. The bottom cell 100 includes a silicon substrate 101 having a first side and a second side disposed opposite to each other. A composite film layer is formed on the first side of the silicon substrate 101. The composite film layer includes a passivation layer 104 and an anti-reflection layer 105 sequentially stacked along the direction away from the silicon substrate 101.

[0069] S2: Use a laser to etch the first surface of the silicon substrate 101 to form a patterned opening 106 that penetrates the passivation layer 104 and the anti-reflection layer 105;

[0070] S3: A top cell 200 is formed on the side of the composite film layer away from the silicon substrate 101, and the top cell 200 is electrically connected to the bottom cell 100 through a patterned opening 106.

[0071] In one specific embodiment, in S2, the parameters of laser etching are: laser power 20W-40W, spot size 20μm-100μm, scanning rate 50000 mm / s-80000 mm / s, and frequency 100 kHz-500 kHz. For example, the laser power can be 20W, 25W, 30W, 35W, 38W, 40W, or any two of the above values; the spot size can be 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 100μm, or any two of the above values; the scanning rate can be 50000 mm / s, 55000 mm / s, 60000 mm / s, 65000 mm / s, 70000 mm / s, 75000 mm / s, 80000 mm / s, or any two of the above values; and the frequency can be 100 kHz, 200 kHz, 300 kHz, 400 kHz, 500 kHz, or any two of the above values.

[0072] Specifically, a laser etches a grid-like and / or mesh-like region on the first surface of the silicon substrate to form a patterned opening 106, and the area removed by the etching is the area of ​​the patterned opening 106. Laser etching removes 10%-50% of the area of ​​the grid-like and / or mesh-like region to achieve charge transfer between the bottom cell 100 and the top cell 200. 50%-90% of the area of ​​the passivation layer 104 and the anti-reflection layer 105 (composite film layer) is retained to achieve passivation and anti-reflection effects, avoiding poor performance of the bottom cell.

[0073] In a specific embodiment, in S1, the method for preparing the bottom battery 100 includes:

[0074] S11: Provides an N-type silicon substrate 101 and polishes it on both sides;

[0075] S12: Boron diffusion is performed on the second surface of silicon substrate 101 to form boron-doped emitter 107;

[0076] S13: Remove the boron-doped layer and borosilicate glass layer from the first and side surfaces;

[0077] S14: Texturing the first surface of the silicon substrate;

[0078] S15: Prepare a tunneling oxide layer 102 and a phosphorus-doped polysilicon layer 103 on the first surface;

[0079] S16: Remove the second-side phosphosilicate glass layer and phosphorus-doped polycrystalline silicon layer 103;

[0080] S17: A passivation layer 104 and an anti-reflection layer 105 are sequentially deposited on the first surface to form a composite film; a second passivation layer 108 and a second anti-reflection layer 109 are sequentially deposited on the second surface.

[0081] S18: Print metal electrodes 110 on the second side and sinter them;

[0082] In S3, the steps for forming the top battery 200 include:

[0083] S31: Cleaning removes residue and damage from the first surface of silicon substrate 101 after laser etching;

[0084] S32: Deposit a first transparent conductive layer 201 on the surface of the composite film layer and the patterned opening 106;

[0085] S33: Deposit a hole transport layer 202 on the surface of the first transparent conductive layer 201;

[0086] S34: Deposit a light-absorbing layer 203 on the surface of hole transport layer 202;

[0087] S35: An electron transport layer 204 is deposited on the surface of the light-absorbing layer 203;

[0088] S36: Deposit a second transparent conductive layer 205 on the surface of electron transport layer 204;

[0089] S37: A top electrode 206 is formed on the surface of the second transparent conductive layer 205.

[0090] In one specific embodiment, the temperature for boron diffusion is 800℃-1000℃, and the time is 20 min-60 min. Exemplarily, the temperature for boron diffusion can be 800℃, 840℃, 880℃, 900℃, 930℃, 950℃, 980℃, 1000℃, or any two of the above values, and the time can be 20 min, 30 min, 40 min, 50 min, 60 min, or any two of the above values.

[0091] In a specific embodiment, in S32, a first transparent conductive layer 201 is deposited using the PVD (Physical Vapor Deposition) method, and the material of the first transparent conductive layer 201 is ITO (Indium Tin Oxide).

[0092] In one specific embodiment, a hole transport layer 202 is deposited using a sputtering process, and the material of the hole transport layer 202 is NiO. x (Nickel oxide).

[0093] In one specific embodiment, a light-absorbing layer 203 is deposited using a spin-coating / drying method, and the material of the light-absorbing layer 203 is a perovskite material.

[0094] In one specific embodiment, the electron transport layer 204 is made of LiF / C60 and / or SnO2. More specifically, a layer of LiF / C60 is first deposited on the surface of the light-absorbing layer 203 by vapor deposition, and then SnO2 is deposited on the LiF / C60 layer by ALD (Atomic Layer Deposition) to serve as the electron transport layer 204.

[0095] In one specific embodiment, a second transparent conductive layer 205 is deposited using the PVD (Physical Vapor Deposition) method, and the material of the second transparent conductive layer 205 is IZO (indium zinc oxide).

[0096] In one specific embodiment, a low-temperature Ag gate electrode is formed on the surface of the second transparent conductive layer 205 as the top electrode 206 by printing and low-temperature curing.

[0097] Thirdly, this application provides a photovoltaic module, including a battery string, which is formed by connecting multiple stacked cells as described above or stacked cells prepared by the above-described method for preparing stacked cells; an encapsulation layer for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulation layer away from the battery string.

[0098] Exemplarily, the tandem solar cells are electrically connected in a single sheet or in multiple segments to form multiple cell strings, which are then electrically connected in series and / or parallel. Specifically, in some embodiments, the multiple cell strings can be electrically connected through conductive links. An encapsulation layer covers the surface of the solar cell. Exemplarily, the encapsulation layer can be an organic encapsulation film such as an ethylene-vinyl acetate copolymer film, a polyethylene octene co-elastomer film, or a polyethylene terephthalate film. The cover plate can be a glass cover plate, a plastic cover plate, or other light-transmitting cover plate.

[0099] Fourthly, this application also provides a photovoltaic system, including the photovoltaic module described in the third aspect.

[0100] Specifically, photovoltaic (PV) systems can be applied in PV power plants, such as ground-mounted, rooftop, and floating power plants, as well as in equipment or devices that utilize solar energy to generate electricity, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it's understandable that the application scenarios for PV systems are not limited to these; that is, PV systems can be applied in all areas that require solar energy for power generation. Taking a PV power grid as an example, a PV system can include PV arrays, combiner boxes, and inverters. A PV array can be an array of multiple PV modules; for example, multiple PV modules can form multiple PV arrays. The PV arrays are connected to combiner boxes, which collect the current generated by the PV arrays. The collected current then flows through an inverter, converting it into AC power required by the mains grid before being connected to the mains grid to achieve solar power supply.

[0101] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The technical solution of the present invention will be clearly and completely described below with reference to specific embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0103] Example 1

[0104] like Figure 1 As shown, this embodiment provides a stacked battery, which includes a bottom battery 100 and a top battery 200;

[0105] The bottom cell 100 is a TOPCon cell, including an N-type silicon substrate 101;

[0106] On the first (front) side of the silicon substrate 101, a tunneling oxide layer 102, a phosphorus-doped polycrystalline silicon layer 103, and a composite film layer are sequentially formed. The composite film layer consists of an Al2O3 passivation layer 104 and a SiN... x The antireflection layer 105 is composed of multiple layers. A penetrating Al2O3 passivation layer 104 and SiN are formed on this composite film. x The antireflective layer 105 has a patterned opening 106; the patterned opening 106 is in the shape of a gate line, and its total area accounts for 10% of the surface area of ​​the first surface of the silicon substrate 101.

[0107] On the second side (back side) of the silicon substrate 101, a boron-doped emitter 107 is formed, and an Al2O3 second passivation layer 108, a SiNx second antireflection layer 109, and a metal electrode 110 are sequentially stacked and covered thereon. The back side is also deposited with;

[0108] The top cell 200 is located on the side of the composite film layer away from the silicon substrate 101; from bottom to top, it includes: a first transparent conductive layer 201, a hole transport layer 202, a light-absorbing layer 203, an electron transport layer 204, a second transparent conductive layer 205, and a top electrode 206; the top cell 200 achieves ohmic contact and electrical connection with the phosphorus-doped polycrystalline silicon layer 103 of the bottom cell 100 through a patterned opening 106.

[0109] like Figure 2 As shown, this embodiment also provides a method for preparing the above-mentioned stacked battery, which includes the following steps:

[0110] S1. Preparation of bottom cell 100:

[0111] S11: Provides N-type monocrystalline silicon wafer 101 (as silicon substrate), 100μm thick, resistivity 0.5Ω / cm 2 And then polish it on both sides;

[0112] S12: Boron diffusion is performed on the back side of the silicon wafer at 800℃ for 20 minutes to form a boron-doped emitter 107 with a sheet resistance of 0.5 Ω / cm. 2 The thickness is 0.5μm;

[0113] S13: Remove the boron-doped layer and borosilicate glass layer from the front and side surfaces of the silicon wafer;

[0114] S14: Texturing the front side of the silicon wafer to form a pyramid structure.

[0115] S15: A tunneling silicon oxide layer 102 (1 nm thick) and a phosphorus-doped silicon layer 103 (20 nm thick, phosphorus doping concentration 0.1E21 cm⁻¹) are fabricated on the front side of the aforementioned silicon wafer. -3 );

[0116] S16: Remove the phosphorosilicate glass layer and phosphorus-doped polysilicon layer 103 wrapped around the back of the silicon wafer and the phosphorosilicate glass layer on the front.

[0117] S17: An Al2O3 passivation layer 104 (5nm thick) and a SiN layer are sequentially deposited on the front side of the silicon wafer. x An antireflection layer 105 (50 nm thick) is formed to create a composite film; an Al2O3 second passivation layer 108 and SiN are sequentially deposited on the back side of the silicon wafer. x Second antireflective layer 109;

[0118] S18: Print metal electrodes 110 on the back of the silicon wafer and sinter them to form ohmic contacts.

[0119] S2. Formation of the graphic opening 106:

[0120] The front side of the silicon wafer is etched using a laser to create a grid-like area, forming a patterned opening 106 that penetrates the passivation layer 104 and the antireflection layer 105 (composite film layer). The area removed by the etching is the area of ​​the patterned opening 106. The total area of ​​the patterned opening 106 accounts for 10% of the front surface area of ​​the silicon wafer 101. The laser parameters are: power 20W, spot size 20μm, scanning rate 50000mm / s, and frequency 100kHz.

[0121] S3. Fabrication of the top cell:

[0122] S31: Cleaning removes the residue and damage from the laser etching of the front side of the silicon wafer 101.

[0123] S32: An ITO first transparent conductive layer 201 is deposited on the front side of the silicon wafer 101 using the PVD method;

[0124] S33: NiO is deposited on the surface of the above-mentioned ITO layer using a sputtering process. x Hole transport layer 202;

[0125] S34: The above NiO is coated / dried using a spin-coating / drying method. x A perovskite light-absorbing layer 203 is deposited on the surface of hole transport layer 202;

[0126] S35: A LiF / C60 layer is deposited on the surface of the perovskite light-absorbing layer 203 by vapor deposition; then SnO2 is deposited on the surface of the LiF / C60 layer by ALD as an electron transport layer 204.

[0127] S36: An IZO second transparent conductive layer 205 is deposited on the surface of electron transport layer 204 using PVD method;

[0128] S37: Low-temperature Ag gate electrode 206 is formed on the surface of the second transparent conductive layer 205 of IZO by printing and low-temperature curing.

[0129] Example 2

[0130] This embodiment provides a stacked battery and its preparation method, which differs from Embodiment 1 in that:

[0131] The patterned opening 106 is in the form of a grid, and the total area of ​​the opening accounts for 30% of the surface area of ​​the first surface of the silicon substrate 101;

[0132] Laser parameters: power 30W, spot size 60μm, scanning speed 65000mm / s, frequency 300kHz;

[0133] The silicon substrate 101 has a thickness of 150 μm and a resistivity of 5.5 Ω·cm. 2 ;

[0134] Boron diffusion process: temperature 900℃, time 40 min, resulting in a sheet resistance of 300 Ω / cm. 2 A boron-doped emitter 107 with a thickness of 1 μm;

[0135] The tunneling oxide layer 102 has a thickness of 1.5 nm, and the phosphorus-doped polycrystalline silicon layer 103 has a thickness of 60 nm with a phosphorus doping concentration of 1.0E21 cm⁻¹. -3 ;

[0136] The passivation layer 104 (Al2O3) has a thickness of 7 nm, and the antireflection layer 105 (SiN) has a thickness of 7 nm. x The thickness is 75nm.

[0137] The remaining process steps and parameters are consistent with those in Example 1.

[0138] Example 3

[0139] This embodiment provides a stacked battery and its preparation method, which differs from Embodiment 1 in that:

[0140] The total area of ​​the patterned openings 106 accounts for 50% of the surface area of ​​the first surface of the silicon substrate 101;

[0141] Laser parameters: power 40W, spot size 100μm, scanning speed 80000mm / s, frequency 500kHz;

[0142] Boron diffusion process: temperature 1000℃, time 60 min, resulting in a sheet resistance of 200 Ω / cm. 2 A boron-doped emitter 107 with a thickness of 1.5 μm;

[0143] The tunneling oxide layer 102 has a thickness of 2 nm, and the phosphorus-doped polycrystalline silicon layer 103 has a thickness of 100 nm and a phosphorus doping concentration of 2.0E21 cm⁻¹. -3 ;

[0144] The passivation layer 104 (Al2O3) has a thickness of 10 nm, and the antireflection layer 105 (SiN) has a thickness of 10 nm. x The thickness is 100nm.

[0145] The remaining process steps and parameters are consistent with those in Example 1.

[0146] Example 4

[0147] This embodiment provides a stacked battery and its preparation method, which differs from Embodiment 1 in that:

[0148] The total area of ​​the patterned openings 106 accounts for 5% of the surface area of ​​the first surface of the silicon substrate;

[0149] Laser parameters: power 18W, spot size 18μm, scanning rate 49000mm / s, frequency 90kHz.

[0150] The remaining process steps and parameters are consistent with those in Example 1.

[0151] Example 5

[0152] This embodiment provides a stacked battery and its preparation method, which differs from Embodiment 1 in that:

[0153] The total area of ​​the patterned openings 106 accounts for 55% of the surface area of ​​the first surface of the silicon substrate;

[0154] Laser parameters: power 45W, spot size 120μm, scanning rate 81000mm / s, frequency 510kHz.

[0155] The remaining process steps and parameters are consistent with those in Example 1.

[0156] Comparative Example 1

[0157] This comparative example provides a tandem solar cell and its fabrication method. The main difference between this fabrication process and that of Example 2 lies in step S2. Specifically, the silicon wafer with the front composite film deposited after step S1 is immersed in a hydrofluoric acid buffer solution for wet etching to expose the Al2O3 / SiN front surface. x The composite film layer was completely and non-selectively removed before proceeding to step S3 to fabricate the perovskite top solar cell. The remaining process steps and parameters remained consistent with those in Example 2.

[0158] Comparative Example 2

[0159] This comparative example provides a tandem solar cell and its fabrication method. The main difference between this fabrication process and that of Example 2 is that step S17, which involves depositing Al2O3 / SiN on the front side of the silicon wafer, is completely omitted. x The composite film layer process involves directly proceeding to step S3 after completing step S16 and cleaning the front side. The remaining process steps and parameters are consistent with those in Example 2.

[0160] Performance testing

[0161] For all the tandem battery samples prepared in the above embodiments and comparative examples, under standard test conditions (AM 1.5G, 1000 W / m²), 2The current-voltage (IV) characteristics were tested at 25℃ to obtain the open-circuit voltage (Voc), short-circuit current density (Jsc), fill factor (FF), and photoelectric conversion efficiency (η). The results are shown in the table below:

[0162] Table 1. Battery test results for the examples and comparative examples.

[0163] Percentage of graphically represented opening area (%) Voc(V) Jsc(mA / cm²) FF (%) η(%) Example 1 10% 1.82 19.59 75.48 26.74 Example 2 30% 1.81 19.30 78.61 27.35 Example 3 50% 1.77 18.62 80.72 26.57 Example 4 5% 1.82 19.73 72.68 25.93 Example 5 55% 1.76 18.16 81.12 25.73 Comparative Example 1 100% (complete removal) 1.58 17.41 80.59 22.13 Comparative Example 2 0% (no film layer) 1.43 18.13 81.81 21.09

[0164] Performance test data conclusions and analysis:

[0165] As shown in the test data in the table above, the stacked battery efficiencies of Examples 1-5 using the technical solution of this invention are significantly higher than those of the comparative examples, proving the effectiveness and superiority of the solution of this invention. Specific analysis is as follows:

[0166] Effects of Embodiments (1-5) of the Present Invention: All embodiments (2-5) of the present invention exhibit significantly better overall performance than the comparative examples. In particular, embodiments 1, 2, and 3, with patterned aperture areas of 10%, 30%, and 50%, demonstrate excellent overall performance, outperforming embodiments 4-5. This indicates that there exists an optimal aperture area range (10%-50%) within the patterned apertures of the present invention. Within this range, sufficient aperture area ensures efficient charge transport (manifested as higher Jsc and FF), while maintaining excellent passivation effects (manifested as higher φ and Voc) by retaining sufficient area of ​​the composite film layer. Among them, embodiment 1 (30% aperture ratio) achieves the best performance balance, with a photoelectric conversion efficiency of 27.35%.

[0167] In Example 4 (5% opening ratio), the charge transport channels were insufficient, resulting in a low FF. In Example 5 (55% opening ratio), the passivation area was too small, leading to a decrease in Voc. Both of these examples had lower efficiency than Examples 1-3. This, in turn, verifies the rationality and necessity of setting the opening area to (10%-50%).

[0168] Compared with Comparative Example 1 (wet full removal): Due to the complete removal of the passivation layer, the open-circuit voltage (Voc) of the bottom cell in Comparative Example 1 dropped significantly to 1.58V, proving that its surface passivation had severely deteriorated. This directly led to a reduction in the Voc of the stacked cell. Although Jsc and FF were still acceptable, the final efficiency (22.13%) was far lower than that of the embodiments of the present invention, fully exposing the defects of the wet etching full removal scheme.

[0169] Compared to Comparative Example 2 (without composite film): Comparative Example 2's bottom cell has the lowest Voc (1.43 mV), indicating that its surface recombination is the most intense. Meanwhile, due to the lack of SiN... xThe antireflection layer also negatively impacts its Jsc (Judges per inch). Its final efficiency (21.09%) is the lowest, strongly demonstrating the importance of composite films for the performance of bottom-layer and tandem cells.

[0170] This invention provides a physical channel for photogenerated carriers from the top cell to reach the core functional layer of the bottom cell by setting a "patterned opening that penetrates the passivation layer and the antireflection layer." This ensures that a complete current loop can be formed inside the tandem cell, avoiding current drop and fill factor loss caused by the insulating film layer blocking the circuit. By retaining the recombination film layer region that is not patterned (i.e., the film layer outside the opening region), the key surface passivation (reducing carrier recombination) and antireflection (enhancing light absorption) functions of the bottom cell are preserved. This significantly improves the photoelectric conversion efficiency, open-circuit voltage, and short-circuit current of the tandem cell. Through the core technology of "laser-patterned local opening," the contradiction between charge transport and bottom cell performance protection in tandem cells is successfully resolved, providing a reliable technical path for achieving high-efficiency, industrially viable tandem cells.

[0171] The present invention has been further described above with reference to specific embodiments. However, it should be understood that the specific description herein should not be construed as limiting the nature and scope of the present invention. Various modifications made to the above embodiments by those skilled in the art after reading this specification are all within the scope of protection of the present invention.

Claims

1. A stacked battery, characterized in that, include: A bottom cell, the bottom cell comprising a silicon substrate having a first side and a second side disposed opposite to each other; A composite film layer located on the first surface of the silicon substrate, the composite film layer comprising a passivation layer and an antireflection layer sequentially stacked along a direction away from the silicon substrate, and the composite film layer having a patterned opening penetrating the passivation layer and the antireflection layer; A top cell is located on the side of the composite film layer away from the silicon substrate, and the top cell is electrically connected to the bottom cell through the patterned opening.

2. The stacked battery according to claim 1, characterized in that, The patterned openings are in the form of grid lines and / or meshes, and the total area of ​​the patterned openings accounts for 10%-50% of the surface area of ​​the first surface.

3. The stacked battery according to claim 1, characterized in that, The passivation layer comprises an Al2O3 layer with a thickness of 5nm-10nm; the antireflection layer comprises SiN. x The layer has a thickness of 50nm-100nm.

4. The stacked battery according to claim 1, characterized in that, The bottom cell is a TOPCon cell, an HJT cell, or a PERC cell; the top cell is a perovskite cell.

5. The stacked battery according to claim 1, characterized in that, The bottom cell further includes: a tunneling oxide layer located on the first surface of the silicon substrate, and a phosphorus-doped polycrystalline silicon layer located on the side of the tunneling oxide layer away from the silicon substrate; a boron-doped emitter located on the second surface of the silicon substrate, and a second passivation layer, a second antireflection layer, and a metal electrode sequentially stacked on the side of the boron-doped emitter away from the silicon substrate; The composite film layer is located on the side of the phosphorus-doped polycrystalline silicon layer away from the silicon substrate, and the top cell is electrically connected to the phosphorus-doped polycrystalline silicon layer through the patterned opening.

6. A method for preparing a tandem battery as described in any one of claims 1 to 5, characterized in that, Includes the following steps: S1: Provide a bottom cell, the bottom cell including a silicon substrate having a first side and a second side disposed opposite to each other, a composite film layer formed on the first side of the silicon substrate, the composite film layer including a passivation layer and an anti-reflection layer sequentially stacked along a direction away from the silicon substrate; S2: Use a laser to etch the first surface of the silicon substrate to form a patterned opening that penetrates the passivation layer and the antireflection layer; S3: A top cell is formed on the side of the composite film layer away from the silicon substrate, and the top cell is electrically connected to the bottom cell through the patterned opening.

7. The method for preparing a stacked battery according to claim 6, characterized in that, In S2, the laser etching parameters are: laser power 20W-40W, spot size 20μm-100μm, scanning rate 50000 mm / s-80000 mm / s, and frequency 100kHz-500 kHz.

8. The method for preparing a stacked battery according to claim 6, characterized in that, In step S1, the preparation steps of the bottom battery include: S11: Provides an N-type silicon substrate and polishes it on both sides; S12: Boron diffusion is performed on the second surface of the silicon substrate to form a boron-doped emitter; S13: Remove the boron-doped layer and borosilicate glass layer that are spread around the first and side surfaces; S14: Texturing the first surface of the silicon substrate; S15: Prepare a tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer on the first surface; S16: Remove the phosphorus-silicon glass layer and phosphorus-doped polycrystalline silicon layer that are wrapped around the second side; S17: A passivation layer and an antireflection layer are sequentially deposited on the first surface to form a composite film; a second passivation layer and a second antireflection layer are sequentially deposited on the second surface; S18: Print metal electrodes on the second surface and sinter them; In step S3, the formation step of the top cell includes: S31: Cleaning removes residue and damage from laser etching of the first surface of the silicon substrate; S32: Deposit a first transparent conductive layer on the surface of the composite film layer and the patterned opening; S33: Deposit a hole transport layer on the surface of the first transparent conductive layer; S34: Deposit a light-absorbing layer on the surface of the hole transport layer; S35: Deposit an electron transport layer on the surface of the light-absorbing layer; S36: Deposit a second transparent conductive layer on the surface of the electron transport layer; S37: A top electrode is formed on the surface of the second transparent conductive layer.

9. A photovoltaic module, characterized in that, The battery string is formed by connecting multiple stacked batteries as described in any one of claims 1-5 or by the method of preparing stacked batteries as described in any one of claims 6-8; and an encapsulation layer for covering the surface of the battery string. A cover plate for covering the surface of the encapsulation layer away from the battery string.

10. A photovoltaic system, characterized in that, The photovoltaic system includes the photovoltaic module as described in claim 9.

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