Electrostatic protection structure of display panel and display panel and display device using same

Abstract

The invention discloses an electrostatic protection structure of a display panel, the display panel applying the electrostatic protection structure and a display device. The display panel comprises a substrate, a pixel array, a plurality of scanning lines, a plurality of data lines and an electrostatic protection structure. The electrostatic protection structure is arranged in at least part of the frame area and comprises a first metal layer, a first insulating layer, a second metal layer and a second insulating layer which are arranged in a stacked mode, and at least one of the first metal layer and the second metal layer is provided with a hole structure. And a discontinuous island-shaped structure is formed in the section of the electrostatic protection structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an electrostatic protection structure of a display panel, a display panel using the same and a display device. BACKGROUND

[0002] In modern display technology, display devices play a crucial role. These devices are widely used in televisions, computer monitors, smartphones, and other devices. Display panels are the core part of display devices, which are responsible for generating images visible to users. Existing display panel technologies include liquid crystal display (LCD), organic light-emitting diode (OLED), and quantum dot display (QLED), etc. Among them, liquid crystal display technology relies on a backlight module to illuminate the display panel. The backlight module usually includes light-emitting diodes (LEDs) as light sources and a light guide plate to evenly distribute light. In addition, the pixel array in the display panel is crucial for generating high-quality images. Each pixel contains red, green, and blue sub-pixels, which work together to produce a rich and colorful image. However, existing technologies often face challenges in providing high resolution and high color accuracy while maintaining energy efficiency and manufacturing costs.

[0003] In the manufacturing process of display devices, there are usually three stages of fabrication process, including array fabrication process, cell fabrication process, and module integration fabrication process. In the array fabrication process, thin film transistor arrays (or TFT array substrates or pixel array substrates) are formed on glass substrates through cleaning, thin film deposition, photolithography, etching, and metallization steps. Then, in the cell fabrication process, the thin film transistor array and color filter are combined together and liquid crystal material is injected to encapsulate and form a display unit / panel. In the module integration fabrication process, multiple display panels arranged on a mother substrate are segmented and assembled with corresponding driving circuits to form independent display devices.

[0004] In the array fabrication process, high-speed airflow and glass substrate friction can easily generate static electricity during film formation, mask exposure, and etching processes. In addition, static electricity is also easily generated during the glass substrate handling process of the TFT array substrate, which can cause electrostatic discharge. Static electricity is a common phenomenon in nature, which occurs when two materials with different dielectric constants rub against each other. When an object with static electricity releases its charge and returns to neutral, it is called electrostatic discharge (ESD), which can significantly reduce the yield of display panels.

[0005] More specifically, when the above-mentioned electrostatic discharge (electrostatic explosion) occurs, a high temperature is generated, which is higher than the metal used in the manufacturing process of the TFT array substrate. The temperature of the electrostatic discharge is 3000°C or higher, which is higher than the melting point of the commonly used materials (e.g., aluminum, copper, molybdenum, etc.) in the manufacturing of the TFT array substrate, and thus electrostatic damage to the metal circuit in the TFT array substrate is caused. For example, when a large current flows through the indium tin oxide (ITO) electrode instantaneously, the oxygen atoms therein are lost, leaving indium tin and making it opaque. In addition, when a large voltage breaks through the insulating layer instantaneously, defects are left, causing a leakage between the electrodes, resulting in an inaccurate voltage setting. Although the above-mentioned defects occur under a large electrostatic voltage, the structure of the TFT array substrate is still damaged under a small electrostatic voltage.

[0006] In a common mother substrate design, there are test circuit traces on the glass substrate of the mother substrate, which surround the display panels on the glass substrate of the mother substrate. Each test circuit trace is connected to the corresponding display panel. When static electricity is generated due to friction between high-speed airflow and the glass substrate during the manufacturing process or due to static electricity generated during the handling of the glass substrate, the charges generated by the static electricity can be dispersed to the entire glass substrate of the mother substrate through the test circuit traces, thereby reducing the damage of the static electricity to the lines on the display panel.

[0007] However, since the size of the glass substrate of the mother substrate is fixed, when a small-size display panel is made, the person skilled in the art will try to design as many display panels as possible on one glass substrate. In other words, the number of display panels designed to be placed on the glass substrate becomes a very important factor in the production and manufacturing of display panels. Therefore, in order to increase the utilization rate of the glass substrate, no gap is provided between the display panels to maximize the utilization rate of the glass substrate. However, in this design, there is no extra space to further configure the test circuit traces, which increases the electrostatic explosion during the manufacturing process of the display panel, resulting in yield loss.

[0008] Currently, the electrostatic protection structure of the mother substrate mainly relies on the test circuit traces to achieve the purpose of electrostatic protection, but this limits the number of display panels that can be configured on one mother substrate. Specifically, the test circuit traces of the array substrate occupy a lot of space. In the prior art, the distance from the side of one line away from another line to the side of another line close to one line is 90-160 μm. Typically, the test circuit traces on one array substrate need to have a space of at least 7 to 14 pitches or more, and the test points on the array substrate also need a space of 5000 μm or more. In other words, the space of the test circuit traces for one display panel on one array substrate must be 6120-7240 μm or more.

[0009] In addition, in order to further reduce the influence of static electricity, in some applications, a static discharge ring is arranged around the periphery of the display panel in the frame area of the display panel to dissipate static electricity accumulated in the panel during the manufacturing process and improve the static protection capability of the display panel. However, during the assembly of the display panel, screen printing or scattering process is used to coat the frame glue, so that the pixel array substrate and the color filter substrate are attached to the appropriate position, and the two substrates are sealed to prevent moisture and other substances from entering the liquid crystal box, cut off the contact between the liquid crystal molecules and the outside world, prevent the leakage of liquid crystal, and ensure the reliability of the product.

[0010] After the frame glue is coated on the frame area of the display panel, the curing rate is improved by scanning with UV light. However, the traditional static discharge ring design is wide, which will block a large area of UV light for curing the auxiliary frame glue, reduce the curing rate of the frame glue, and cause the liquid crystal display panel to leak, water vapor to enter and corrode the panel, and other adverse consequences, resulting in panel display defects.

[0011] Generally, the test circuit trace will only be arranged on the array substrate when a large-size display panel is configured. When a larger number of small-size display panels are configured on the array substrate, the configuration of the test circuit trace is omitted. In this case, because the array substrate does not have the test circuit trace, it will cause the display panel to be unable to avoid static discharge. On the other hand, as the market requires narrower and narrower frame width of the panel, the distance between the static discharge ring and the cutting line becomes smaller, which may cause the cutting knife wheel to cut the metal layer, resulting in poor conductivity of the static discharge ring.

[0012] Therefore, for those skilled in the art, how to increase the number of display panels that can be configured while achieving the purpose of static protection when configuring small-size display panels on the array substrate is also an important issue in the art.

[0013] On the other hand, in the manufacturing process of the display device, the packaging technology is a key link, which affects the performance and reliability of the equipment. The main goal of the packaging technology is to effectively integrate the micro electronic components of the display screen on the display panel. Among them, the Chip on Glass (COG) packaging technology is a technology that directly installs the integrated driving circuit (i.e., driving chip, or driving IC) in the display device to the glass substrate, so that the driving IC directly outputs the voltage or signal required by the display module to each pixel. The COG packaging technology is relatively mature, has cost advantage, and the production capacity is easy to adjust, but relatively because it needs to set the driving IC on the glass substrate, the size of the IC, the trace requirement and other restrictions will cause the display device using COG packaging to be difficult to realize narrow frame design.

[0014] In the COG packaging technology, the scan driving integrated design on the glass substrate can be referred to as GOP driving (Gate Driver on Panel). In the design using GOP driving, the scan driving circuit (or scan driving circuit) is a circuit made by the same manufacturing process as the thin film transistor (TFT) in the pixel array, which can save the integrated circuit related to scan driving, and reduce the manufacturing cost of the liquid crystal display. In addition, since the GOP driving design only needs a few timing control signals to operate, the space requirement of the signal wiring of the external circuit can be optimized, thereby increasing the effective display area.

[0015] With the evolution of technology, the Chip on Film (COF) packaging technology appears, which can directly package the driving IC on the flexible circuit board and bend and arrange on the back of the display panel. Because the driving IC does not need to be arranged on the glass substrate, the frame area can be effectively reduced, so that the narrow frame requirement can be easily met. However, although the COF packaging technology can reduce the frame size, the technical threshold is high, the manufacturing cost is relatively high, and the production capacity is also limited. The above two types of technologies have their limitations in realizing narrow frame design, and it is difficult to consider cost and effect at the same time.

[0016] For example, in the COF packaged display panel design, the scan lines of the pixel array are usually connected through fan-out wiring and driving chips. The line design used by the general fan-out wiring is only single-layer metal or double-layer metal staggered arrangement, but no matter which one is selected, it is difficult to balance the narrow frame design requirement and the line corrosion resistance reliability requirement.

[0017] On the other hand, in the GOP packaged display panel design, the scan line voltage is generated in the gate circuit on the panel, rather than being provided by the integrated circuit, but the data line voltage is still directly provided by the driving chip. Since only a few pins of the driving chip are used to drive the gate circuit on the panel to generate the scan line voltage signal in the GOP packaging, the use of integrated circuit chips can be reduced, and the design of the panel edge can be optimized. When designing small size models, it has relatively better advantages.

[0018] During the panel design from the array to the cell stage, the pixel array part and the color filter of the panel will be adhered using a sealing agent. During the adhesion process, ultraviolet light is used for irradiation, which is beneficial to the curing of the sealing agent and maintains the reliability of the panel adhesion. However, at present, the design of the gate circuit on most panels is capacitive, and the metal on both sides is opaque metal and occupies a relatively large edge design area, which will result in very low ultraviolet light transmittance, affecting the curing effect of the sealing agent, and thus reducing the reliability of the panel.

[0019] On the other hand, as the current market requires higher and higher resolution, the size of the pixel in the pixel array design of the display panel is required to be smaller and smaller. Although the size of the pixel is reduced, the line width and the line distance of the scanning line and the data line are not reduced with the pixel. Therefore, the smaller the pixel is, the smaller the overlapping area between the pixel electrode and the common electrode is. Under the specification limit, the general pixel design has the problem of insufficient storage capacitance, so that the requirements of pixel voltage stabilization and leakage current reduction are difficult to achieve.

[0020] If the touch function is integrated into the display device, the touch panel is usually embedded into the display panel in the on-cell or in-cell manner to form a touch display panel. The on-cell touch display panel has the advantages of simple structure and relatively low manufacturing cost. Moreover, because the touch electrode only needs to be attached to the upper layer of the existing display panel, the structure of the display panel does not need to be modified complicatedly, and the production yield is high. However, in the on-cell touch display panel, the distance between the touch sensing electrode and the finger is large (usually through the encapsulation glass or the color filter), which results in a weak capacitance signal and affects the sensitivity of touch recognition. In addition, because the touch electrode is attached to the display panel, the thickness of the overall device is difficult to reduce, which is not conducive to the development direction of the current light and thin.

[0021] The in-cell touch display panel directly integrates the touch electrode into the display panel, which coexists with the pixel structure of the display panel, so that the thickness of the overall panel can be reduced. However, in the in-cell touch display panel, the touch electrode coexists with the display pixel electrode, so that the display driving signal may affect the touch signal and generate noise interference. In general design, in order to avoid interference, the touch sensing timing needs to be accurately designed to stagger the touch scanning and the display refreshing to avoid signal aliasing, so that the driving design of the display device is complex. In addition, in the display panel with high picture update rate (such as 120Hz, 240Hz), how to coordinate the scanning period of touch and display to ensure high-precision touch while avoiding display flicker is also a great technical challenge. SUMMARY

[0022] One of the purposes of the present application is to provide an electrostatic protection structure of a display panel and a display panel and a display device applying the same to solve the above problems, including but not limited to the influence of electrostatic discharge on the manufacturing yield of the display panel, the poor electrostatic protection effect of the small-size display panel, the insufficient storage capacitance, the low reliability of the sealing glue curing manufacturing process, the high complexity of the driving design of the display driving panel, the high cost, and the difficulty to ensure the surface flatness of the display panel in the manufacturing process.

[0023] Embodiments of the present application provide a display panel, which includes a substrate, a pixel array, a plurality of scan lines, a plurality of data lines, and an electrostatic protection structure. The substrate has a display area and a non-display area, wherein the non-display area includes a frame area. The pixel array is disposed on the display area of the substrate and has a plurality of pixel units arranged in an array. The plurality of scan lines are formed on the substrate and electrically connected to each row of pixel units of the pixel array. The plurality of data lines are formed on the substrate and electrically connected to each column of pixel units of the pixel array. The electrostatic protection structure is disposed in at least part of the frame area and includes a first metal layer, a first insulating layer, a second metal layer, and a second insulating layer arranged in a stack, wherein at least one of the first metal layer and the second metal layer has a hole structure to form a discontinuous island structure in a cross-section of the electrostatic protection structure.

[0024] In some embodiments of the present application, the display panel further includes a first fan-out transmission portion and a second fan-out transmission portion. The first fan-out transmission portion is disposed on one side of the non-display area and has a plurality of fan-out wires, wherein the plurality of fan-out wires of the first fan-out transmission portion are respectively electrically connected to an odd number of scan lines. The second fan-out transmission portion is disposed on the other side of the non-display area opposite to the first fan-out transmission portion and has a plurality of fan-out wires, wherein the plurality of fan-out wires of the second fan-out transmission portion are respectively electrically connected to an even number of scan lines. The plurality of scan lines include a first scan line group and a second scan line group, the plurality of fan-out wires electrically connected to the first scan line group are formed on the substrate in a first wire structure, and the plurality of fan-out wires electrically connected to the second scan line group are formed on the substrate in a second wire structure.

[0025] In some embodiments of the present application, the plurality of pixel units include a first pixel unit, and the first pixel unit includes a thin film transistor, a third insulating layer, a third metal layer, a fourth insulating layer, a common electrode, and an extension metal layer. The thin film transistor has a first terminal, a second terminal, and a control terminal, wherein the first terminal is electrically connected to a corresponding data line, and the control terminal is electrically connected to a corresponding scan line. The third insulating layer is formed on the substrate. The third metal layer is formed on the third insulating layer and electrically connected to the second terminal of the thin film transistor. The fourth insulating layer covers the third metal layer. The common electrode has a gate structure and is formed on the fourth insulating layer, wherein the common electrode has a first part and a second part, the first part of the common electrode and the third metal layer at least partially overlap in a projection area, and the second part of the common electrode and the third metal layer substantially do not overlap in the projection area. The extension metal layer is electrically connected to the third metal layer and covered by the fourth insulating layer, wherein at least part of the extension metal layer is formed in the projection area of the second part of the common electrode.

[0026] In some embodiments of the present application, the plurality of pixel units comprises a first pixel unit and a second pixel unit. The first pixel unit is electrically connected to the nth scan line, and the second pixel unit is electrically connected to the (n+1)th scan line, where n is a natural number. The second pixel unit comprises a thin film transistor, a third insulating layer, a third metal layer, a fourth insulating layer, and a common electrode. The thin film transistor has a first terminal, a second terminal, and a control terminal. The first terminal is electrically connected to a corresponding data line, and the control terminal is electrically connected to the (n+1)th scan line. The third insulating layer is formed on the substrate and covers the nth scan line. The third metal layer is formed on the third insulating layer and is electrically connected to the second terminal of the thin film transistor. The third metal layer has a first portion and a second portion. The fourth insulating layer covers the third metal layer. The common electrode has a gate structure and is formed on the fourth insulating layer. The common electrode has a first portion and a second portion. The first portion of the third metal layer and the first portion of the common electrode at least partially overlap. The second portion of the third metal layer, the second portion of the common electrode, and the nth scan line at least partially overlap.

[0027] In some embodiments of the present application, the display panel further comprises a scan driving circuit disposed on the non-display area and comprising a plurality of scan units electrically connected to the plurality of scan lines. Each of the scan units comprises at least one holding capacitor. The structure of the holding capacitor comprises the first metal layer, the first insulating layer, the second metal layer, the second insulating layer, a third conductive layer, and a fourth conductive layer. The third conductive layer and the fourth conductive layer are light-transmitting conductive layers. The third conductive layer is disposed on the second insulating layer, and the fourth conductive layer is disposed on the first insulating layer and at least partially covered by the second insulating layer. One end of the fourth conductive layer is connected to the second metal layer. At least a portion of the first metal layer is formed with a via hole to expose the at least a portion of the first metal layer from the first insulating layer and the second insulating layer. The third conductive layer is connected to the exposed at least a portion of the first metal layer via the via hole.

[0028] In some embodiments of the present application, the display panel further comprises a third metal layer, a plurality of light emitting elements, a protective layer, and a fourth metal layer. The third metal layer is formed in the display region on the substrate and comprises a plurality of first electrode regions and a plurality of second electrode regions, wherein the plurality of first electrode regions and the plurality of second electrode regions are electrically independent of each other, and the plurality of first electrode regions and the plurality of second electrode regions are alternately arranged on the substrate with intervals. Each of the light emitting elements comprises a first electrode and a second electrode formed on opposite sides, and the first electrode is electrically connected to the corresponding first electrode region. The protective layer is filled between the plurality of light emitting elements and covers at least part of the surface of each of the light emitting elements. The fourth metal layer is formed on the protective layer and comprises a plurality of third electrode regions, wherein the plurality of third electrode regions are respectively formed on the plurality of light emitting elements and are electrically connected to the second electrode of the corresponding light emitting element. Each of the pixel units comprises a display unit and a touch sensing unit, the display unit comprises the corresponding light emitting element and the first electrode region and the third electrode region electrically connected to the corresponding light emitting element, and the touch sensing unit comprises the second electrode region and the fourth electrode region adjacent to the display unit.

[0029] Embodiments of the present application provide an electrostatic protection structure of a display panel, which comprises a mother substrate and a plurality of display panels. The mother substrate comprises a plurality of array blocks. The plurality of display panels are sequentially arranged on each of the array blocks on the mother substrate, wherein each of the array blocks comprises a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a first conductive layer. The first metal layer is formed on each of the array blocks in a manner of surrounding at least two of the plurality of display panels, so as to form a plurality of first electrostatic discharge lines on each of the array blocks. The first insulating layer covers the first metal layer and exposes at least part of the first metal layer. The second metal layer is formed on the first insulating layer in a manner of surrounding at least two of the plurality of display panels, so as to form a plurality of second electrostatic discharge lines corresponding to the plurality of first electrostatic discharge lines on each of the array blocks. The second insulating layer covers the second metal layer and exposes at least part of the second metal layer. The first conductive layer is formed in a bridge region, wherein at least part of the first conductive layer is connected through the exposed part of the first insulating layer and the first metal layer, and at least another part of the first conductive layer is connected through the exposed part of the second insulating layer and the second metal layer, so as to electrically connect the plurality of first electrostatic discharge lines and the plurality of second electrostatic discharge lines to each other in the bridge region.

[0030] The application provides a display panel. The display panel comprises a substrate, a pixel array, a plurality of scan lines, a first fan-out transmission unit and a second fan-out transmission unit. The substrate has a display area and a non-display area. The pixel array is arranged on the display area of the substrate. The plurality of scan lines are sequentially formed on the substrate and electrically connected to the pixel array. The first fan-out transmission unit is arranged on one side of the non-display area and has a plurality of fan-out wires, wherein the plurality of fan-out wires of the first fan-out transmission unit are respectively electrically connected to an odd number of scan lines. The second fan-out transmission unit is arranged on the other side of the non-display area opposite to the first fan-out transmission unit and has a plurality of fan-out wires, wherein the plurality of fan-out wires of the second fan-out transmission unit are respectively electrically connected to an even number of scan lines. The plurality of scan lines comprise a first scan line group and a second scan line group, the plurality of fan-out wires electrically connected to the first scan line group are formed on the substrate in a first wire structure, and the plurality of fan-out wires electrically connected to the second scan line group are formed on the substrate in a second wire structure.

[0031] In some embodiments of the application, the display panel has a first metal layer, a first insulating layer, a second metal layer and a second insulating layer sequentially formed on the substrate, and the plurality of scan lines are formed by the first metal layer. The first wire structure comprises a single-layer metal wire structure formed by the first metal layer, and the second wire structure comprises a double-layer metal wire structure formed by the first metal layer and the second metal layer arranged alternately.

[0032] In some embodiments of the application, the fan-out wires formed by the second metal layer are connected to the corresponding scan lines through a bridge structure.

[0033] In some embodiments of the application, the bridge structure comprises a first via, a second via and a conductive layer. The first via is formed on the part of the second insulating layer covering the second metal layer. The second via is formed on the part of the first insulating layer and the second insulating layer covering the first metal layer. The conductive layer is arranged on the second insulating layer, connected to the second metal layer through the first via and connected to the first metal layer through the second via. The first metal layer and the second metal layer are electrically connected through the conductive layer.

[0034] Embodiments of the present application provide a display panel, which includes a substrate, a pixel array, a plurality of scan lines, and a scan driving circuit. The substrate has a display area and a non-display area. The pixel array is disposed on the display area of the substrate. The plurality of scan lines are sequentially formed on the substrate and electrically connected to the pixel array. The scan driving circuit includes a plurality of scan units electrically connected to the plurality of scan lines, wherein each of the scan units includes at least one holding capacitor, and a structure of the holding capacitor includes a first metal layer, a second metal layer, a first insulating layer, a second insulating layer, a first light-transmitting conductive layer, and a second light-transmitting conductive layer. The first metal layer is formed on the substrate. The first insulating layer is disposed on the first metal layer. The second metal layer is disposed on the first insulating layer. The first light-transmitting conductive layer is disposed on the first insulating layer and electrically connected to the second metal layer at one end. The second insulating layer is disposed on the second metal layer and the first light-transmitting conductive layer. The second light-transmitting conductive layer is disposed on the second insulating layer. At least a part of the first metal layer is formed with a via hole, so that the at least a part of the first metal layer is exposed from the first insulating layer and the second insulating layer. The second light-transmitting conductive layer is electrically connected to the at least a part of the first metal layer exposed through the via hole.

[0035] In some embodiments of the present application, a part of the second metal layer is extended and formed on the second light-transmitting conductive layer, so that the second metal layer and the second light-transmitting conductive layer at least partially overlap in a normal direction of the substrate.

[0036] In some embodiments of the present application, the holding capacitor is a sum of a first capacitor, a second capacitor, and a third capacitor, wherein the first capacitor is formed based on a first overlapping area of the first metal layer and the second metal layer and the first insulating layer located in the first overlapping area, the second capacitor is formed based on a second overlapping area of the second metal layer and the first light-transmitting conductive layer and the second insulating layer located in the second overlapping area, and the third capacitor is formed based on a third overlapping area of the first light-transmitting conductive layer and the second light-transmitting conductive layer and the second insulating layer located in the third overlapping area.

[0037] A display panel is provided. The display panel includes a substrate, a pixel array, a plurality of scan lines, and a plurality of data lines. The substrate has a display area and a non-display area. The pixel array is disposed on the display area of the substrate and has a plurality of pixel units arranged in an array. The plurality of scan lines are formed on the substrate and electrically connected to each row of pixel units of the pixel array. The plurality of data lines are formed on the substrate and electrically connected to each column of pixel units of the pixel array. The plurality of pixel units includes a first pixel unit. The first pixel unit includes a thin film transistor, a first insulating layer, a first metal layer, a second insulating layer, a common electrode, and an extension metal layer. The thin film transistor has a first terminal, a second terminal, and a control terminal. The first terminal is electrically connected to a corresponding data line, and the control terminal is electrically connected to a corresponding scan line. The first insulating layer is formed on the substrate. The first metal layer is formed on the first insulating layer and is electrically connected to the second terminal of the thin film transistor. The second insulating layer covers the first metal layer. The common electrode has a gate structure and is formed on the second insulating layer. The common electrode has a first portion and a second portion. A projection area of the first portion of the common electrode and the first metal layer at least partially overlaps, and a projection area of the second portion of the common electrode and the first metal layer does not substantially overlap. The extension metal layer is electrically connected to the first metal layer and is covered by the second insulating layer. At least a portion of the extension metal layer is formed in the projection area of the second portion of the common electrode.

[0038] In some embodiments of the present application, the first pixel unit further includes a counter substrate, a liquid crystal layer, and a black matrix. The liquid crystal layer is formed between the common electrode and the counter substrate. The black matrix is formed on a side of the counter substrate facing the substrate. At least a portion of the black matrix and the projection area of the second portion of the common electrode overlap each other. The extension metal layer is located in the projection area of the at least a portion of the black matrix.

[0039] In some embodiments of the present application, the pixel unit further includes a second pixel unit, and the second pixel unit includes an extension metal layer. The extension metal layer of the first pixel unit and the extension metal layer of the second pixel unit are both located in the projection area of the second portion of the common electrode.

[0040] Embodiments of the present application provide a display panel, which includes a substrate, a pixel array, a plurality of scan lines and a plurality of data lines. The substrate has a display area and a non-display area. The pixel array is disposed on the display area of the substrate and has a plurality of pixel units arranged in an array. The plurality of scan lines are formed on the substrate and electrically connected to each row of pixel units of the pixel array. The plurality of data lines are formed on the substrate and electrically connected to each column of pixel units of the pixel array. The plurality of pixel units includes a first pixel unit and a second pixel unit. The first pixel unit is electrically connected to an nth scan line, and the second pixel unit is electrically connected to an (n+1)th scan line, where n is a natural number. The second pixel unit includes a thin film transistor, a first insulating layer, a first metal layer and a common electrode. The thin film transistor has a first terminal, a second terminal and a control terminal, wherein the first terminal is electrically connected to a corresponding data line, and the control terminal is electrically connected to the (n+1)th scan line. The first insulating layer is formed on the substrate and covers the nth scan line. The first metal layer is formed on the first insulating layer and electrically connected to the second terminal of the thin film transistor, wherein the first metal layer has a first portion and a second portion. The common electrode has a gate structure and is formed on the second insulating layer, wherein the common electrode has a first portion and a second portion. The first portion of the first metal layer and the first portion of the common electrode at least partially overlap, and the second portion of the first metal layer, the second portion of the common electrode and the nth scan line at least partially overlap.

[0041] In some embodiments of the present application, the nth scan line between two adjacent rows of pixel units includes a first line segment and a second line segment connected to each other, wherein the first line segment and the second line segment are not parallel to each other.

[0042] In some embodiments of the present application, the overlapping area of the second portion of the first metal layer and the first line segment of the nth scan line is substantially the same as the overlapping area of the second portion of the first metal layer and the second line segment.

[0043] In some embodiments of the present application, the overlapping area of the second portion of the first metal layer and one of the first line segment and the second line segment of the nth scan line is greater than the overlapping area of the second portion of the first metal layer and the other of the first line segment and the second line segment.

[0044] Embodiments of the present application provide an electrostatic protection structure of an array substrate, which includes a glass substrate and a plurality of display panels. The plurality of display panels are arranged adjacent to each other on the glass substrate. The common electrode of each display panel is connected to the common electrode of the adjacent display panel.

[0045] In some embodiments of the present application, the display panels are arranged in the same direction.

[0046] In some embodiments of the present application, two adjacent rows or columns of the display panels are arranged in opposite directions with reference to a virtual symmetry line.

[0047] In some embodiments of the present application, the common electrode of each display panel is connected to the common electrode of an adjacent display panel by at least one line.

[0048] An electrostatic protection structure of an array substrate is provided in embodiments of the present application. The structure comprises a glass substrate divided into a plurality of array blocks, and a plurality of display panels arranged adjacent to each other in each array block of the glass substrate. Each array block has at least one first metal layer arranged on the glass substrate to surround at least two of the display panels, a first insulating layer covering the first metal layer and exposing at least a portion of the first metal layer, at least one second metal layer arranged on the first insulating layer to surround at least two of the display panels, a second insulating layer covering the second metal layer and exposing at least a portion of the second metal layer, and a plurality of conductive layers electrically connecting the first metal layer and the second metal layer by passing through the first insulating layer and the second insulating layer at a plurality of bridging regions of the first metal layer.

[0049] In some embodiments of the present application, when there are a plurality of first metal layers, the bridging regions are located at least at turns of the first metal layers.

[0050] In some embodiments of the present application, when there are a plurality of first metal layers, the first insulating layer separates the plurality of first metal layers.

[0051] In some embodiments of the present application, when there are a plurality of second metal layers, the second insulating layer separates the plurality of second metal layers.

[0052] In some embodiments of the present application, the distance between the side of the first metal layer close to the second metal layer and the side of the second metal layer away from the first metal layer, which are electrically connected by the conductive layers, is 200-300 μm when viewed from the top.

[0053] In some embodiments of the present application, the distance between the parallel sides of the first metal layer, which are electrically connected by the conductive layers, is 150-300 μm when viewed from the top.

[0054] The application further provides an electrostatic protection structure, which comprises a glass substrate divided into a plurality of array blocks, and a plurality of display panels arranged adjacent to each other in each of the array blocks of the glass substrate; each of the array blocks comprises a plurality of metal layers arranged on the glass substrate in a manner of surrounding at least two of the display panels and sequentially stacked, a plurality of insulating layers separating the metal layers and exposing at least part of the metal layers, and a plurality of conductive layers electrically connecting the metal layers in a stacked manner at least in a plurality of bridging regions of the metal layers.

[0055] The application provides a pixel array substrate, which comprises a substrate, a pixel array, and an electrostatic protection structure. The substrate has a display area and a non-display area. The pixel array is arranged in the display area of the substrate. The electrostatic protection structure is arranged in the non-display area of the substrate and surrounds at least part of a frame area of the substrate, wherein the electrostatic protection structure has a plurality of light-transmitting parts arranged in sequence and at intervals.

[0056] The application provides an electrostatic protection structure, which is arranged on a non-display area of a pixel array substrate of a display panel. The electrostatic protection structure comprises a plurality of metal strip patterns. Each of the metal strip patterns is arranged in a frame area of the non-display area, wherein each of the metal strip patterns has a plurality of light-transmitting parts arranged in sequence and at intervals, and the light-transmitting parts are formed by at least an insulating layer and a transparent conductive layer.

[0057] The application provides a display device, which comprises a display panel, a display driving chip, and a touch sensing chip. The cross-sectional structure of the display panel along a cutting direction comprises a substrate, a first metal layer, a plurality of light emitting elements, a protective layer, and a second metal layer. The first metal layer is formed on the substrate and comprises a plurality of first electrode areas and a plurality of second electrode areas, wherein the plurality of first electrode areas and the plurality of second electrode areas are electrically independent of each other, and the plurality of first electrode areas and the plurality of second electrode areas are alternately arranged on the substrate at intervals. Each of the light emitting elements comprises a first electrode and a second electrode formed on opposite sides, and the first electrode is electrically connected to a corresponding first electrode area. The protective layer is filled between the plurality of light emitting elements and covers at least part of the surface of each of the light emitting elements. The second metal layer is formed on the protective layer and comprises a plurality of third electrode areas, wherein each of the third electrode areas is formed on a corresponding light emitting element and is electrically connected to the second electrode of the corresponding light emitting element. The orthographic projection area of the plurality of third electrode areas on the substrate does not completely overlap with the orthographic projection area of the plurality of second electrode areas on the substrate.

[0058] The display panel provided by the embodiments of the present application includes a substrate, a first metal layer, a plurality of light emitting elements, a protective layer, and a second metal layer. The first metal layer is formed on the substrate and includes a plurality of first electrode regions and a plurality of second electrode regions, wherein the plurality of first electrode regions and the plurality of second electrode regions are electrically independent of each other, and the plurality of first electrode regions and the plurality of second electrode regions are alternately arranged on the substrate with intervals. Each of the light emitting elements includes a first electrode and a second electrode formed on opposite sides, and the first electrode is electrically connected to the corresponding first electrode region. The protective layer is filled between the plurality of light emitting elements and covers at least part of the surface of each of the light emitting elements. The second metal layer is formed on the protective layer and includes a plurality of third electrode regions, wherein the plurality of third electrode regions are respectively formed on the plurality of light emitting elements and are electrically connected to the second electrode of the corresponding light emitting element. The projection area of the plurality of third electrode regions on the substrate and the projection area of the plurality of second electrode regions on the substrate are completely non-overlapping.

[0059] In some embodiments, the second metal layer further includes a plurality of fourth electrode regions, wherein the plurality of third electrode regions and the plurality of fourth electrode regions are electrically independent of each other, and the plurality of fourth electrode regions are respectively electrically connected to the corresponding plurality of second electrode regions.

[0060] The display panel provided by the embodiments of the present application includes a pixel array substrate or an electrostatic protection structure as described above.

[0061] Through one or more technical solutions described in the present application, the display panel and the pixel array thereof provided by the embodiments of the present application can expand the equivalent area of the pixel electrode by forming an additional extended metal layer. Since the extended metal layer is formed in the area covered by the common electrode and the black matrix, the pixel storage capacitance can be increased while the aperture ratio / transmittance of the display panel is maintained.

[0062] In addition, through one or more technical solutions described in the present application, the array substrate electrostatic protection structure and the liquid crystal display panel provided by the embodiments of the present application can connect the capacitances of a plurality of display panels on the array substrate in series to form a larger capacitance, thereby helping to absorb static electricity generated in the manufacturing process. In this way, the glass substrate of the array substrate is less likely to cause electrostatic discharge (electrostatic explosion), thereby avoiding high temperature and causing electrostatic damage to the metal lines in the TFT array substrate, and preventing the indium tin oxide (ITO) electrode from becoming opaque and reducing the defects of the insulating layer, so that the voltage between the electrodes can be accurately set. In addition, the embodiments of the present application can effectively prevent the structure of the array substrate from being damaged. Furthermore, the embodiments of the present application can be applied regardless of the arrangement of the plurality of display panels on the glass substrate of the array substrate.

[0063] In addition, through one or more technical solutions described in the present application, the electrostatic protection structure of the array substrate proposed in the embodiments of the present application can achieve electrostatic protection even when a small-size display panel is configured on the array substrate without test circuit traces. Moreover, because the first metal layer and the second metal layer are a double-layer structure, the horizontal area generated by the configuration on the array substrate can be reduced, thereby increasing the number of display panels that can be configured on the array substrate. Furthermore, because the first metal layer and the second metal layer are a double-layer structure, the overall impedance of the array substrate is smaller, thereby more easily achieving the functions of adsorbing and dissipating static electricity.

[0064] In addition, through one or more technical solutions described in the present application, the electrostatic protection structure of the pixel array substrate proposed in the embodiments of the present application has a design of multiple light-transmitting portions, which can reduce the area of the metal blockage, so that, when the display panel is subjected to the frame bonding manufacturing process, UV light can irradiate the frame glue FP coating through the light-transmitting portions, so that the UV light can better irradiate the frame glue and thus improve the curing rate of the frame glue, thereby improving the yield and reliability of the panel assembly. In addition, because the light-transmitting portions of the electrostatic protection structure are formed of transparent conductive material, the light-transmitting portions do not reduce the equivalent area of the metal strip-shaped pattern, so that the electrostatic dissipation capability of the electrostatic protection structure can be maintained and will not be reduced due to the arrangement of the light-transmitting portions.

[0065] On the other hand, compared with the traditional electrostatic discharge ring design, the electrostatic protection structure having the inner ring structure and the outer ring structure proposed in the embodiments of the present application has a greater width in the cross-sectional direction, so that the effective conductive area of the electrostatic protection structure can be increased, and the electrostatic dissipation capability can be further improved.

[0066] In addition, through one or more technical solutions described in the embodiments of the present application, the display device and the display panel proposed in the embodiments of the present application can form independent electrodes in the display panel for touch sensing, so that the signal timing during display and during touch sensing can be independent of each other, avoiding the need to make a trade-off.

[0067] In addition, through one or more technical solutions described in the embodiments of the present application, the display device and the display panel proposed in the embodiments of the present application can basically maintain the upper surfaces of all the light-emitting elements at the same level, without height differences, so that subsequent manufacturing processes will not be affected by the flatness of the display panel, thereby effectively improving the manufacturing process yield and reliability. BRIEF DESCRIPTION OF DRAWINGS

[0068] FIG. 1 A configuration schematic diagram of the display device of the embodiments of the present application;

[0069] FIG. 2A and FIG. 2B A configuration diagram of a display device and a component of a display panel thereof according to some embodiments of the present application;

[0070] FIG. 3A and FIG. 3B A schematic diagram of a scan driving circuit according to some embodiments of the present application;

[0071] FIG. 4A to FIG. 6B Circuit schematic diagrams of scan driving circuits according to different embodiments of the present application;

[0072] FIG. 7A to FIG. 8B Configuration schematic diagrams of holding capacitors of scan driving circuits according to different embodiments of the present application;

[0073] FIG. 9A to FIG. 12 Configuration schematic diagrams of display panels and fan-out wirings thereof according to different embodiments of the present application;

[0074] FIG. 13 Equivalent circuit schematic diagrams of pixel arrays according to embodiments of the present application;

[0075] FIG. 14A to FIG. 18C Configuration schematic diagrams of pixel arrays according to different embodiments of the present application;

[0076] FIG. 19 Voltage-current relationship diagrams of thin film transistors of pixel units according to some embodiments of the present application;

[0077] FIG. 20 Configuration schematic diagrams of array substrates according to some embodiments of the present application;

[0078] FIG. 21 Configuration schematic diagrams of adjacent display panels on array substrates according to some embodiments of the present application;

[0079] FIG. 22A and FIG. 22B Configuration schematic diagrams of display panels on array substrates according to the present application;

[0080] FIG. 23A to FIG. 24B Schematic diagrams of configuration of electrostatic protection structures within array blocks of array substrates according to different embodiments of the present application;

[0081] FIG. 25A and FIG. 25B Configuration schematic diagrams of pixel array substrates according to different embodiments of the present application;

[0082] FIG. 26A and FIG. 26B Different perspective schematic diagrams of pixel array substrates and electrostatic protection structures thereof according to embodiments of the present application;

[0083] FIG. 27A to FIG. 27C FIG. 1 is a schematic diagram of a top view and a cross-sectional view of a display panel according to an embodiment of the present application;

[0084] FIG. 28A to FIG. 30G FIG. 2 is a schematic diagram of a top view and a cross-sectional view of a display panel according to another embodiment of the present application; and

[0085] FIG. 31 FIG. 3 is a schematic diagram of a signal waveform of a display device according to some embodiments of the present application. DETAILED DESCRIPTION

[0086] In order to more clearly and specifically describe the technical solutions of the present application, specific embodiments of the technical solutions of the present application are described in detail below. The following descriptions of the embodiments of the present application are only for example and illustration, and do not represent all embodiments of the present application or limit the present application to specific embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts should fall within the scope of the present application.

[0087] It should be noted that the terms "vertical", "left", "right", "upper", "lower", and similar expressions used herein are only for indicating relative positional relationships based on the drawings, and do not limit the components to which the terms are applied to be implemented only in the indicated manner. When the absolute position of the described object changes, the description of the relative position may also change accordingly.

[0088] For the purpose of consistency and ease of understanding, the same features are indicated by reference numerals in the exemplary drawings (although in some examples they are not so indicated). However, features in different embodiments can differ in other respects, and therefore should not be narrowly limited to the features shown in the drawings.

[0089] The terms "first", "second", and "third" and the like in the descriptions of the embodiments of the present application and in the above drawings are used to distinguish different objects, regions, levels, or steps, and are not intended to describe a specific order (except for claims with explicit requirements).

[0090] The terms "connected" or "coupled" and the like mentioned in the embodiments of the present application are not limited to that there is no any intervening object between the objects. That is, the connection or coupling between the two objects can mean that the two objects are directly connected / coupled with each other, or are connected / coupled with each other through other objects.

[0091] In all descriptions herein of embodiments related to specific values, although not directly described, all contain the connotation of "about", that is, such specific values will cover the possible range of numerical errors, in order to show the possible unintended effects and deviations in the manufacturing process or material selection. The numerical error range can include numerical changes that do not significantly change the material structure, characteristics, effects, such as a range of 0% to 10% deviation, which is clear to those skilled in the art.

[0092] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0093] FIG. 1 Configuration schematic diagram of the display device of the embodiments of the present application. Please refer to FIG. 1 The display device 10 of the embodiments of the present application may, for example, be a liquid crystal display device (LCD device) comprising a backlight module 100 and a display panel D100, wherein the backlight module 100 and the display panel D100 are disposed on an x-y plane, and the display panel D100 is disposed on the backlight module 100 along a z axis. The backlight module 100 is used to provide sufficient brightness and uniformly distributed light sources towards the display panel D100. The display panel D100 is used to control and adjust the passing light for presenting corresponding images thereon. In the embodiments of the present application, the display device 10 can be any electronic device with display function, such as a television, a screen, a notebook computer or a mobile phone, and the present application is not limited thereto.

[0094] The backlight module 100 comprises a light-emitting layer 110, wherein the light-emitting layer 110 comprises a plurality of light-emitting components LEDs arranged in an array. The light-emitting components LEDs can be used to emit light sources towards the display panel D100. In some embodiments, the light-emitting components LEDs can be white light, red light, green light or blue light emitting diodes (or can be said to be light-emitting diodes with light-emitting wavelengths between the white light, red light, green light or blue light segments), or a combination of the above-mentioned colored light-emitting diodes, and the present application is not limited thereto.

[0095] In addition, in some embodiments, the backlight module 100 can further comprise a quantum dot film 120 and an optical adjustment layer 130, wherein the quantum dot film 120 is disposed on the light-emitting layer 110, and the optical adjustment layer 130 is disposed on the quantum dot film 120, that is, the quantum dot film 120 is disposed between the light-emitting layer 110 and the optical adjustment layer 130. In the embodiments provided with the quantum dot film 120, the light-emitting components LEDs may, for example, be blue light-emitting diodes.

[0096] The quantum dot film 120 is disposed on the light transmission path of the light emitting layer 110, and is used to adjust the wavelength of part of the light emitted by the light emitting component LEDs, and to allow another part of the light emitted by the light emitting component LEDs to pass directly without adjustment. For example, in the case where the light emitting component LEDs emit light in the blue wavelength range (for example, 400 μm ~ 520 μm), the quantum dot film 120 can adjust the wavelength of the first part of the received light to the red wavelength range (for example, 610 μm ~ 720 μm), adjust the wavelength of the second part of the received light to the green wavelength range (for example, 520 μm ~ 610 μm), and maintain the third part of the received light in the blue wavelength range directly without adjustment. In this way, the first to third parts of the light emitted by the light emitting layer 110 can be mixed to form white light after passing through the quantum dot film 120.

[0097] The optical adjustment layer 130 is also located on the light transmission path of the light emitting layer 110, and is used to adjust the direction of the received light to make the transmitted light source more uniform. In some embodiments, the optical adjustment layer 130 includes a plurality of optical microstructures (not shown) and / or optical films (not shown) for adjusting the direction of the light, but the present application is not limited thereto.

[0098] The display panel D100 includes, for example, a pixel array, a counter substrate, and a non-self-emitting display medium, wherein the pixel array and the counter substrate are oppositely disposed, and the non-self-emitting display medium is disposed between the pixel array and the counter substrate. In some embodiments, the non-self-emitting display medium may, for example, be a liquid crystal, but the present application is not limited thereto. Specific configuration embodiments related to the pixel array will be further described later.

[0099] From the perspective of circuit configuration and display driving, in some embodiments, the display device 20 and the configuration of the display panel D100 thereof can be as shown in FIG. 2A and FIG. 2B , wherein FIG. 2A is a top view configuration schematic diagram of the display device 20, and FIG. 2B is a side view configuration schematic diagram of the display device 20. For ease of description, FIG. 2A is represented in the manner that the internal components of the display device 20 are unfolded in the x-y plane, FIG. 2B is the configuration state of the internal components of the display device 20 in the shell. From the perspective of packaging, the present embodiment is a display device applying GOP packaging technology.

[0100] Please refer to FIG. 2A and FIG. 2BIn the embodiment, the display device 20 can further include a scan driving circuit D120, a data driving circuit D130, a connection module D140, and a control circuit D150 to drive the display panel D100 in addition to the backlight module and the display panel D100. The display panel D100 has a display region DR and a non-display region SR, wherein the display region DR is a region to display an image, and the non-display region SR is a region where the display panel D100 does not display an image. The non-display region SR usually surrounds the display region DR, and can also be regarded as a frame region of the display panel D100. The scan driving circuit D120 and the data driving circuit D130 are disposed in the non-display region SR of the display panel D100. In the illustration, the scan driving circuit D120 is taken as an example disposed in the non-display region SR on the left and right sides of the display panel D100, and the data driving circuit D130 is taken as an example disposed in the non-display region SR on the lower side of the display panel D100, but the present application is not limited thereto. One end of the connection module D140 is disposed in the non-display region SR close to the data driving circuit D130, and the other end of the connection module D140 is coupled to the control circuit D150.

[0101] Specifically, the display panel D100 can include a substrate D111 and a pixel array D112 in the display region DR. The pixel array D112 is disposed on the substrate D111, and is, for example, a pixel unit Pu arranged in an m x n array, i.e., m rows and n columns, wherein m and n can be natural numbers selected according to design requirements, and the present application is not limited thereto.

[0102] From the electrical relationship between the components, the scan driving circuit D120 is electrically connected to the display panel D100 through the traces on the substrate D111. The data driving circuit D130 is electrically connected to the display panel D100 through the first transmission part WR1, and is electrically connected to the connection module D140 through the second transmission part WR2. On the other hand, the control circuit D150 is electrically connected to the data driving circuit D130 through the connection module D140 and the second transmission part WR2. The first transmission part WR1 and the second transmission part WR2 can be transmission lines formed on the substrate D111.

[0103] The scan driving circuit D120 is configured to generate scan signals for row-by-row enabling of the pixels according to timing control signals. In the present embodiment, the scan driving circuit D120 is illustrated as an example of a configuration including two scan driving circuits D120 respectively configured to enable odd and even rows of pixels, in which the left scan driving circuit D120 is configured to include scan units s121_1, s121_3,..., s121_m-1 respectively connected to odd scan lines, and the right scan driving circuit D120 is configured to include scan units s121_2, s121_4, s121_m respectively connected to even scan lines, but the present application is not limited thereto. In the present embodiment, the scan unit s121_x represents any one of the left scan units s121_1, s121_3,..., s121_m-1, and the scan unit s121_y represents any one of the right scan units s121_2, s121_4, s121_m. In other words, x can be any odd number less than m, and y can be any even number less than or equal to m, where m is an even number, but the present application is not limited thereto.

[0104] The data driving circuit D130 is configured to generate driving signals for driving the pixel array D112 according to data control signals. Although the present embodiment illustrates a single data driving circuit D130 as an example, the present application is not limited thereto. The data driving circuit D130 can be integrated as a plurality of driving chips in some embodiments, in which the plurality of driving chips can cooperatively drive pixels in different portions / regions of the pixel array D112.

[0105] More specifically, the same row of pixels in the pixel array D112 corresponds to the same scan line, and the same column of pixels in the pixel array D112 corresponds to the same data line. The pixel array D112 can be electrically connected to the scan driving circuit D120 through the scan lines to receive the scan signals, and can be electrically connected to the data driving circuit D130 through the data lines and the first transmission portion WR1 to receive the data driving signals provided by the data driving circuit D130. The data driving circuit D130 can provide the data driving signals in cooperation with the enable timing of the pixel array D112, so that the pixel array D112 adjusts the light passing according to the data driving signals, for presenting corresponding images in the display region DR.

[0106] The connection module D140 is configured to provide a signal transmission path between the data driving circuit D130 and the control circuit D150, so that the data control signals generated by the control circuit D150 can be transmitted to the data driving circuit D130 through the connection module D140 and the second transmission portion WR2. In some embodiments, the connection module D140 can be a flexible circuit board (hereinafter referred to as a flexible circuit board D140) that can be bent, such as FIG. 2BAs shown, there are a plurality of connection terminals on both ends of the flexible circuit board D140. The connection terminals on the side of the flexible circuit board D140 close to the data driving circuit D130 are arranged on the substrate D111, and the connection terminals on the side close to the control circuit D150 are arranged on the circuit board of the control circuit D150. The portion of the flexible circuit board D140 close to the data driving circuit D130 and provided with the connection terminals is attached to the substrate D111, and the width of the attached portion is approximately the distance from the top of the connection terminals of the flexible circuit board D140 to the edge 111e of the substrate.

[0107] When the display device 20 is assembled, the flexible circuit board D140 is bent so that the control circuit D150 is arranged on the back of the display panel D100 (i.e., the other side of the substrate D111 relative to the display region DR). In other words, in the assembled state of the display device 20, the control circuit D150, the substrate D111, and the data driving circuit D130 inside the display device 20 are sequentially arranged along the z-axis.

[0108] In the pixel array D112 of the display panel D100, a plurality of thin film transistors (not shown) are included. The plurality of thin film transistors are turned on or off in response to the received signals to control the operation of the corresponding pixels, so as to achieve the above-mentioned effect of adjusting the light passing through according to the data driving signal, for presenting the corresponding image in the display region DR. From another perspective, the display panel D100 also includes a common electrode (not shown), wherein the display region DR can be regarded as the region where the common electrode and the pixel array D112 overlap, and the (at least part of) non-display region SR can be regarded as the region where the common electrode and the pixel array D112 do not overlap.

[0109] The functional module configuration of each scanning unit s121_1~s121_m in the scanning driving circuit D120 described in this embodiment can be as shown in FIG. 3A and FIG. 3B wherein FIG. 3A is the circuit schematic diagram of the scanning unit s121_x (i.e., x can be any odd number between 1 and m, such as s121_1, s121_3,..., s121_m-1) connecting the odd-numbered scan lines, and FIG. 3B is the circuit schematic diagram of the scanning unit s121_y (i.e., x can be any even number between 1 and m, such as s121_2, s121_4,..., s121_m) connecting the even-numbered scan lines.

[0110] Please refer to FIG. 3A In this embodiment, the scanning unit 121x includes a first module MD1, a second module MD2, and a third module MD3. The first module MD1 is electrically connected to the scan output ends G x-2and the scan output end G of the latter two stages x+2 and based on the scan output end G x-2 and the scan signal of G x+2 generates a driving signal on node N1. The second module MD2 is electrically connected to the first module MD1 through node N1, and determines the pull-up time point of the scan signal output from the scan output end G x based on the driving signal on node N1, the clock signal CK1 and the reference signal VSS. The third module MD3 is electrically connected to the second module MD2 and the scan output end G x and determines the pull-down time point of the scan signal output from the scan output end G x based on the clock signal CK2 and the reference signal VSS.

[0111] Please refer to FIG. 3B In the embodiment, the scan unit 121y includes a fourth module MD4, a fifth module MD5 and a sixth module MD6, wherein the connection relationship and the relative arrangement of the fourth to sixth modules MD4~MD6 can be similar to the first to third modules MD1~MD3 of the foregoing embodiment respectively. The difference between them can only be that the timing of the received clock signals CK3 and CK4 is different.

[0112] In some embodiments, the clock signals CK1 and CK2 are mutually inverted, and the clock signals CK3 and CK4 are mutually inverted. In some embodiments, the phase of the clock signal CK3 is about 90 degrees behind the phase of the clock signal CK1, the phase of the clock signal CK2 is about 90 degrees behind the phase of the clock signal CK3, and the phase of the clock signal CK4 is about 90 degrees behind the phase of the clock signal CK2.

[0113] In addition, the related description of the fourth to sixth modules MD4~MD6 of the scan unit 121y can refer to the description of the first to third modules MD1~MD3 described above, which will not be repeated here.

[0114] The following FIG. 4A to FIG. 6B further illustrates the specific circuit configuration embodiments of the scan driving circuit D120 described above, wherein FIG. 4A and FIG. 4B draws a circuit configuration embodiment of a scan unit 121_x and 121_y, FIG. 5A and FIG. 5B draws another circuit configuration embodiment of a scan unit 121_x and 121_y, and Figure 6A and FIG. 6B draws another circuit configuration embodiment of a scan unit 121_x and 121_y.

[0115] Please refer to FIG. 4AThe scanning unit 121_x in this embodiment includes transistors M1~M7 and capacitors C1 and C2, wherein transistors M1 and M2 can be configured as follows: FIG. 3A The first module MD1, transistors M3~M5, and capacitors C1 and C2 can be configured as follows: FIG. 3A The second module MD2, along with transistors M6 and M7, can be configured as follows: FIG. 3A The third module, MD3. In other words, FIG. 3A The first module MD1 may include, for example, transistors M1 and M2, the second module MD2 may include, for example, transistors M3 to M5 and capacitors C1 and C2, and the third module MD3 may include, for example, transistors M6 and M7. However, this application is not limited to these.

[0116] In this embodiment, transistors M1 to M7 each have a first terminal, a second terminal, and a control terminal, and transistors M1 to M7 can be, for example, N-type transistors or P-type transistors, and this application is not limited thereto. If the transistor is an N-type transistor, the first terminal can be, for example, the drain, the second terminal can be, for example, the source, and the control terminal can be, for example, the gate; if the transistor is a P-type transistor, the first terminal can be, for example, the source, the second terminal can be, for example, the drain, and the control terminal can be, for example, the gate.

[0117] The first terminal of transistor M1 is used to receive the first scan control signal D2U, the second terminal of transistor M1 is electrically connected to node N1, and the control terminal of transistor M1 is used to receive the scan output terminal G of the first two stages of the scan unit. x-2 The first terminal of transistor M2 is electrically connected to the second terminal of transistor M1. The second terminal of transistor M2 is used to receive the second scan control signal U2D, and the control terminal of transistor M2 is used to receive the scan output terminal G of the subsequent two scanning units. x+2 .

[0118] The first terminal of transistor M3 is electrically connected to the second terminal of transistor M1 and the first terminal of transistor M2 via node N1, and the second terminal of transistor M3 is used to receive the clock signal CK1. The first terminal of transistor M4 is electrically connected to the control terminal of transistor M3, the second terminal of transistor M4 is used to receive the reference signal VSS, and the control terminal of transistor M4 is electrically connected to node N1. In this embodiment, the reference signal VSS is taken as a reference low level. The first terminal of transistor M5 is electrically connected to the scan output terminal G of scan unit 121_x. xThe second terminal of transistor M5 is used to receive the clock signal CK1, and the control terminal of transistor M5 is electrically connected to the first terminal of transistor M3 and node N1. The first terminal of capacitor C1 is electrically connected to the control terminal of transistor M3 and the first terminal of transistor M4, and the second terminal of capacitor C1 is used to receive the clock signal CK1. The first terminal of capacitor C2 is electrically connected to the first terminal of transistor M5 and the scan output terminal G. x Furthermore, the second terminal of capacitor C2 is electrically connected to the first terminal of transistor M3, the control terminal of transistor M5, and node N1.

[0119] The first terminal of transistor M6 is electrically connected to the scan output terminal G. x The second terminal of transistor M6 is used to receive the reference signal VSS, and the control terminal of transistor M6 is electrically connected to the control terminal of transistor M3, the first terminal of transistor M4, and the first terminal of capacitor C1. The first terminal of transistor M7 is electrically connected to the first terminal of transistor M6 and the scan output terminal G. x The second terminal of transistor M7 is used to receive the reference signal VSS, and the control terminal of transistor M7 is used to receive the clock signal CK2.

[0120] Please refer to the following: FIG. 4B The scanning unit 121_y in this embodiment includes transistors M8~M14 and capacitors C3 and C4, wherein transistors M8 and M9 can be configured as follows: FIG. 3B The fourth module MD5, transistors M10~M12, and capacitors C3 and C4 can be configured as follows: FIG. 3B The fifth module MD5, along with transistors M13 and M14, can be configured as follows: FIG. 3B The sixth module, MD6. In other words, FIG. 3B The fourth module MD4 may include, for example, transistors M8 and M9; the fifth module MD5 may include, for example, transistors M10 to M12 and capacitors C3 and C4; and the sixth module MD6 may include, for example, transistors M13 and M14. However, this application is not limited to these.

[0121] In this embodiment, transistors M8 to M14 each have a first terminal, a second terminal, and a control terminal, and transistors M8 to M14 can be, for example, N-type transistors or P-type transistors, and this application is not limited thereto. If the transistor is an N-type transistor, the first terminal can be, for example, the drain, the second terminal can be, for example, the source, and the control terminal can be, for example, the gate; if the transistor is a P-type transistor, the first terminal can be, for example, the source, the second terminal can be, for example, the drain, and the control terminal can be, for example, the gate.

[0122] The first end of the transistor M8 is used to receive a first scan control signal D2U, the second end of the transistor M1 is electrically connected to the node N2, and the control end of the transistor M8 is used to receive a scan output end G of a scan cell of the former two stages y-2 . The first end of the transistor M9 is electrically connected to the second end of the transistor M8, the second end of the transistor M9 is used to receive a second scan control signal U2D, and the control end of the transistor M9 is used to receive a scan output end G of a scan cell of the latter two stages y+2 .

[0123] The first end of the transistor M10 is electrically connected to the second end of the transistor M8 and the first end of the transistor M9 via the node N2, and the second end of the transistor M10 is used to receive a clock signal CK3. The first end of the transistor M11 is electrically connected to the control end of the transistor M10, the second end of the transistor M11 is used to receive a reference signal VSS, and the control end of the transistor M11 is electrically connected to the node N2. The reference signal VSS of the present embodiment is taken as an example of a reference low level. The first end of the transistor M12 is electrically connected to a scan output end G of the scan cell 121_y y , the second end of the transistor M12 is used to receive the clock signal CK3, and the control end of the transistor M12 is electrically connected to the first end of the transistor M10 and the node N2. The first end of the capacitor C3 is electrically connected to the control end of the transistor M10 and the first end of the transistor M11, and the second end of the capacitor C3 is used to receive the clock signal CK3. The first end of the capacitor C4 is electrically connected to the first end of the transistor M12 and the scan output end G y , and the second end of the capacitor C4 is electrically connected to the first end of the transistor M10, the control end of the transistor M12, and the node N2.

[0124] The first end of the transistor M13 is electrically connected to the scan output end G y , the second end of the transistor M13 is used to receive a reference signal VSS, and the control end of the transistor M13 is electrically connected to the control end of the transistor M10, the first end of the transistor M11, and the first end of the capacitor C3. The first end of the transistor M14 is electrically connected to the first end of the transistor M13 and the scan output end G y , the second end of the transistor M14 is used to receive the reference signal VSS, and the control end of the transistor M14 is used to receive a clock signal CK4.

[0125] In other words, the configuration of the transistors M8-M14 of the present embodiment is similar to that of the transistors M1-M7 of the foregoing FIG. 4A embodiment, and the configuration of the capacitors C3 and C4 is similar to that of the capacitors C1 and C2 of the foregoing FIG. 4A embodiment. The present embodiment and the foregoing FIG. 4AThe difference between the embodiments is that the transistors M10-M12 mainly operate with reference to the clock signal CK3, and the transistor M14 operates with reference to the clock signal CK4. In the above-described embodiments, the capacitors C1-C4 can also be referred to as holding capacitors, which can be used to stabilize the voltage at the connected nodes. If viewed from the structure, the holding capacitors can be formed by the arrangement between the metal layers and the insulating layers on the display panel. This part will be further described in the subsequent embodiments.

[0126] In the above-described FIG. 4A and FIG. 4B driving architecture, it is necessary to provide a direct current voltage to control the operation of the transistor, and the long-term application of the direct current voltage to the transistor is easy to cause the characteristics of the transistor to deviate, thereby causing the display panel to have display abnormalities in long-term use or aging test. For example, in the case of FIG. 4A and 4B , the transistor M1 / M8 continuously receives a direct current voltage from the first scan control signal D2U during operation, and as the operation time is prolonged, the current-voltage characteristic curve (I-V curve) of the transistor M1 / M8 gradually deviates to the right, so that the drain current of the transistor M1 / M8 gradually increases, which eventually causes display abnormalities.

[0127] In addition, through the above-described FIG. 4A and FIG. 4B arrangement, at least 7 or more signal lines need to be provided on the display panel to provide the control signals and clock signals (such as U2D, D2U, CK1-CK4, VSS, etc.) required for the operation of the scan unit 121_x / 121_y. This limits the size of the non-display area of the display panel, making it difficult to achieve a narrow frame design.

[0128] FIG. 5A to FIG. 6B The driving architecture shown can solve the problems of the above-described embodiments, and can effectively improve the quality of the display panel, prolong the service life of the display panel, and further achieve a narrow frame design.

[0129] Please refer to FIG. 5A and FIG. 5B , the configuration of the transistors M1-M7 is similar to that of the transistors M1-M7 in the foregoing FIG. 4A embodiments, and the configuration of the capacitors C1 and C2 is similar to that of the capacitors C1 and C2 in the foregoing FIG. 4A embodiments; the configuration of the transistors M8-M14 is similar to that of the transistors M8-M14 in the foregoing FIG. 4B embodiments, and the configuration of the capacitors C3 and C4 is similar to that of the capacitors C3 and C4 in the foregoing

[0130] The present embodiment and the foregoing FIG. 4A and FIG. 4BThe main difference of the embodiment is that the first terminal of the transistor M1 / M8 is electrically connected to its control terminal to replace the original first scan control signal D2U with the scan signal of the previous two stages of scan output terminals G x-2 / G y-2 In addition, the second terminal of the transistor M2 / M9 is electrically connected to a signal line with a reference signal VSS to replace the original second scan control signal U2D with the reference signal VSS.

[0131] From another perspective, the transistor M1 is equivalent to a diode element by the connection configuration as shown in FIG. 5A Therefore, when the control terminal of the transistor M1 is applied with a scan signal of an enable level (such as a high level), the transistor M1 can directly transmit the enable level to its second terminal. Similarly, the transistor M8 is equivalent to a diode element by the connection configuration as shown in FIG. 5B Therefore, when the control terminal of the transistor M8 is applied with a scan signal of an enable level (such as a high level), the transistor M8 can directly transmit the enable level to its second terminal.

[0132] FIG. 6A and FIG. 6B is a circuit schematic diagram of a scan driving circuit of another embodiment of the present application. Please refer to FIG. 6A and FIG. 6B The configuration of the transistors M1-M7 is similar to the capacitors C1 and C2 of the aforementioned FIG. 4A embodiment; the configuration of the transistors M8-M14 is similar to the capacitors C3 and C4 of the aforementioned FIG. 4B embodiment.

[0133] The main difference of the present embodiment and the aforementioned FIG. 4A and FIG. 4B embodiments is that the first terminal of the transistor M1 is electrically connected to a signal line of a clock signal CK2 to replace the original first scan control signal D2U with the clock signal CK2, which is originally a direct-current high level. In addition, the second terminal of the transistor M2 is electrically connected to a signal line with a reference signal VSS to replace the original second scan control signal U2D with the reference signal VSS. Similarly, the first terminal of the transistor M8 is electrically connected to a signal line of a clock signal CK4 to replace the original first scan control signal D2U with the clock signal CK4, which is originally a direct-current high level. In addition, the second terminal of the transistor M9 is electrically connected to a signal line with a reference signal VSS to replace the original second scan control signal U2D with the reference signal VSS.

[0134] More specifically, through the above configuration, the scan circuit 121_x / 121_y can apply a direct current high level on the first end of the transistor M1 / M8 through the clock signal CK2 / CK4 when the transistor M1 / M8 is turned on (i.e. the control end receives the enabled scan signal), i.e. without affecting the operation of the transistor M1 / M8; similarly, for the transistor M2 / M9, the second end electrically connected to the reference signal VSS has the same effect as connecting the second scan control signal U2D. Therefore, by electrically connecting the first end of the transistor M1 / M8 to the signal line of the clock signal CK2 / CK4 to use the clock signal CK2 / CK4 as the first scan control signal D2U, and electrically connecting the second end of the transistor M2 / M9 to the signal line transmitting the reference signal VSS, the signal line for transmitting the first scan control signal D2U and the second scan control signal U2D can be omitted, thereby further reducing the non-display area width of the display panel.

[0135] FIG. 7A to FIG. 8B The configuration of the holding capacitor of the scan driving circuit of different embodiments of the present application is shown in the schematic diagram, wherein FIG. 7A and FIG. 7B The configuration of the holding capacitor is shown in the schematic diagram, and FIG. 8A and FIG. 8B The configuration of the holding capacitor is shown in the schematic diagram.

[0136] Please refer to FIG. 7A and FIG. 7B , wherein FIG. 7A is a top view schematic diagram of the display panel D100 of the present embodiment in the holding capacitor area, and FIG. 7B is a cross-sectional structure schematic diagram of the display panel D100 along the section line AA'. In the present embodiment, the display panel D100 includes a first metal layer ML1, a first insulating layer IL1, a second metal layer ML2 and a second insulating layer IL2 which are sequentially stacked on the substrate D111, wherein the first metal layer ML1 is covered by the first insulating layer IL1, the second metal layer ML2 is disposed on the first insulating layer IL1, and the second insulating layer IL2 covers the first insulating layer IL1 and the second metal layer ML2. The above-mentioned stacked structure of the display panel D100 is adhered by the sealing glue SG and the upper substrate D111'. In other words, the first metal layer ML1, the first insulating layer IL1, the second metal layer ML2 and the second insulating layer IL2 are fixed between the substrates D111 and D111' by the sealing glue SG.

[0137] In the present embodiment, the first metal layer ML1, the second metal layer ML2 and the first insulating layer IL1 interposed therebetween constitute the holding capacitor Ch, wherein the capacitance value of the holding capacitor Ch is related to the area of the overlapping portion of the first metal layer ML1 and the second metal layer ML2 and the equivalent distance between the first metal layer ML1 and the second metal layer ML2 (i.e. the thickness of the first insulating layer IL1 in the overlapping portion of the first metal layer ML1 and the second metal layer ML2).

[0138] Specifically, in the process of assembling the display device, the display panel D100 and the color filter (not shown) disposed thereon are usually adhered by using the sealing glue, and the process of adhesion is irradiated and cured by using the ultraviolet light. However, from the perspective of the top view structure shown in the figure, the area of the holding capacitor Ch is mostly composed of the overlapping metal layers ML1 and ML2 which are opaque, and the holding capacitor Ch is usually disposed close to the frame area of the display panel D100 in the corresponding scanning unit s121_1~s121_m. Therefore, in the process of irradiating the ultraviolet light for curing, the curing effect of the sealing glue is affected due to the fact that the ultraviolet light cannot penetrate the holding capacitor which is opaque, thereby reducing the assembly reliability of the display device. FIG. 7A

[0139] In order to solve the problem of the above-mentioned embodiment, the present application proposes a holding capacitor structure as shown in FIG. 8A and FIG. 8B , wherein FIG. 8A is a top view schematic diagram of the display panel D100 in the holding capacitor area of the present embodiment, and FIG. 8B is a cross-sectional structure schematic diagram of the display panel D100 along the section line BB'.

[0140] Please refer to FIG. 8A and FIG. 8B , in the present embodiment, the display panel D100 comprises a first metal layer ML1, a first insulating layer IL1, a second metal layer ML2 and a second insulating layer IL2 which are sequentially stacked on the substrate D111, wherein the first metal layer ML1 is covered by the first insulating layer IL1, the second metal layer ML2 is disposed on the first insulating layer IL1, and the second insulating layer IL2 covers the first insulating layer IL1 and the second metal layer ML2. In addition, at least part of the area of the first metal layer ML1 is formed with a through hole THx, so that the first metal layer ML1 can be exposed from the first insulating layer IL1 and the second insulating layer IL2 through the through hole THx.

[0141] ​The display panel D100 further comprises a first conductive layer CL1 and a second conductive layer CL2. The first conductive layer CL1 is formed on the second insulating layer IL2 and is electrically connected with the first metal layer ML1 through the via THx. Specifically, the first conductive layer CL1 extends from the upper surface of the second insulating layer IL2 to the sidewall of the via THx and covers the first metal layer ML1 exposed at the bottom of the via THx through the second insulating layer IL2 and the first insulating layer IL1. The second conductive layer CL2 is formed on the first insulating layer IL1 and is electrically connected with the second metal layer ML2. The first conductive layer CL1 and the second conductive layer CL2 in the present embodiment are implemented by using a light-transmissive conductive material, such as an ITO conductive film, and thus the first conductive layer CL1 and the second conductive layer CL2 in the present embodiment can also be referred to as a first light-transmissive conductive layer CL1 and a second light-transmissive conductive layer CL2.

[0142] In the present embodiment, the side of the second metal layer ML2 electrically connected with the second conductive layer CL2 can be a part of the second metal layer ML2 extending to be formed on the second conductive layer CL2, so that the second metal layer ML2 and the second conductive layer CL2 at least partially overlap in the z direction (i.e., the normal direction of the substrate D111). However, the present application is not limited thereto.

[0143] Specifically, the first metal layer ML1, the second metal layer ML2 and the first insulating layer IL1 interposed therebetween constitute a capacitor Ceq1, the second metal layer ML2, the first conductive layer CL1 and the second insulating layer IL2 interposed therebetween constitute a capacitor Ceq2, and the first conductive layer CL1, the second conductive layer CL2 and the second insulating layer IL2 interposed therebetween constitute a capacitor Ceq3. Since the first metal layer ML1 and the first conductive layer CL1 are short-circuited together and the second metal layer ML2 and the second conductive layer CL2 are short-circuited together, the holding capacitor Ch in the present embodiment can be equivalent to the sum of the capacitors Ceq1, Ceq2 and Ceq3. In other words, the capacitor Ceq1 is constituted based on the first overlapping area of the first metal layer ML1 and the second metal layer ML2 and the first insulating layer IL1 located at the first overlapping area. The capacitor Ceq2 is constituted based on the second overlapping area of the second metal layer ML2 and the first conductive layer CL1 and the second insulating layer IL2 located at the second overlapping area. The capacitor Ceq3 is constituted based on the third overlapping area of the first light-transmissive conductive layer CL1 and the second light-transmissive conductive layer CL2 and the second insulating layer IL2 located at the third overlapping area.

[0144] Further, the capacitance value of the holding capacitor Ch is related to the area of the overlapping portion between the first metal layer ML1 and the second metal layer ML2, the equivalent distance between the first metal layer ML1 and the second metal layer ML2 (i.e., the thickness of the first insulating layer IL1 at the overlapping portion between the first metal layer ML1 and the second metal layer ML2), the area of the overlapping portion between the second metal layer ML2 and the first conductive layer CL1, the equivalent distance between the second metal layer ML2 and the first conductive layer CL1 (i.e., the thickness of the second insulating layer IL2 at the overlapping portion between the second metal layer ML2 and the first conductive layer CL1), and the area of the overlapping portion between the first conductive layer CL1 and the second conductive layer CL2 (excluding the portion overlapping with the second metal layer ML2) and the equivalent distance between the first conductive layer CL1 and the second conductive layer CL2 (i.e., the thickness of the second insulating layer IL2 at the overlapping portion between the first conductive layer CL1 and the second conductive layer CL2).

[0145] Compared with the foregoing FIG. 7A and FIG. 7B embodiments, the present embodiment is equivalent to forming additional parallel capacitors Ceq2 and Ceq3 using the light-transmissive first conductive layer CL1 and the second conductive layer CL2, so that the overall capacitance value can be maintained at the design value even if the capacitance Ceq1 between the original first metal layer ML1 and the second metal layer ML2 is reduced due to the reduction in area.

[0146] In this way, in the process of curing by irradiation of ultraviolet light, the transmittance of the ultraviolet light through the scan driving circuit can be effectively improved, thereby improving the curing effect of the sealant during assembly of the display device and improving the reliability of the display device.

[0147] In other embodiments, the display device 30 and the display panel D100 thereof can also be configured as shown in FIG. 9A and FIG. 9B , wherein FIG. 9A is a top view configuration schematic diagram of the display device 30, and FIG. 9B is a side view configuration schematic diagram of the display device 30. For ease of illustration, FIG. 9A is represented in a manner that the internal components of the display device 30 are unfolded in the x-y plane, FIG. 9B is presented in a configuration state of the internal components of the display device 30 in the housing.

[0148] Please refer to FIG. 9A and FIG. 9B , in addition to the backlight module and the display panel D200 described above, the display device 30 of the present embodiment can also include a driving chip D220 for driving the display panel D200, a connection module D240, and a control circuit D250. The display panel D200 includes a substrate D211 and a pixel array D212. The present embodiment and the foregoing FIG. 2A andFIG. 2B The configurations are largely the same, so the repetitive parts can be referred to the description of the above embodiments, and will not be repeated here.

[0149] This embodiment is similar to the aforementioned FIG. 2A and FIG. 2B The difference in this embodiment is that the scan driving circuit D120 and data driving circuit D130 of the aforementioned embodiment are integrated into a driver chip D220 in this embodiment, wherein the driver chip D220 is configured on the lower side of the non-display area SR of the display panel D200. To accommodate the connection configuration of the driver chip D220, the display panel D220 also includes fan-out transmission units WRG1 and WRG2 disposed on the left and right non-display areas SR (relative to the display area DR). Fan-out transmission unit WRG1 is used to electrically connect odd-numbered scan lines GL1, GL3, ..., GLm-1 to the driver chip D220, and fan-out transmission unit WRG2 is used to electrically connect even-numbered scan lines GL2, GL4, ..., GLm to the driver chip D220. Specifically, fan-out transmission units WRG1 and WRG2 include multiple fan-out traces FOL for connecting scan lines GL1~GLm.

[0150] On the other hand, in the embodiment of the display device 10 / 20 / 30 integrating touch function (which may be referred to as a touch display device), the touch display device 10 / 20 / 30 further includes a touch sensing chip (not shown) disposed on the substrate D111, and the upper side (On-cell) or the inside (In-cell) of the display panel D100 / D200 is integrated with a plurality of touch sensing units (not shown) formed by touch electrodes arranged in an array, wherein the touch sensing chip can be used to drive the touch sensing units to detect the capacitance change on the panel and realize the touch sensing function.

[0151] The following is further... FIG. 10A to FIG. 12 To illustrate different implementation designs of the fan-out routing (FOL) of the display panel D200, in which... FIG. 10A and FIG. 10B An example of wiring design for a single-layer metal structure is illustrated. FIG. 11A and FIG. 11B This illustration depicts an example of a routing design for a double-layer metal interlace structure, and... FIG. 12 An example of a wiring design for a single-layer-double-layer staggered hybrid structure is illustrated.

[0152] Please refer to the following at the same time FIG. 10A and FIG. 10B The cross-sectional structure of the display panel D200 at the cutoff line CC' is as follows FIG. 10BAs shown, the circuit structure of the display panel D200 includes a first metal layer ML1, a first insulating layer IL1, a second metal layer ML2, and a second insulating layer IL2 formed in sequence on the substrate D211. The first metal layer ML1 is covered by the first insulating layer IL1, the second metal layer ML2 is disposed on the first insulating layer IL1, and the second insulating layer IL2 covers the first insulating layer IL1 and the second metal layer ML2. In the display region DR, the first metal layer ML1 will be used as the scan lines GL1~GLm to transmit signals.

[0153] In the single-layer metal structure wiring design of the present embodiment, the fan-out wirings FOL of the fan-out transmission portions WRG1 and WRG2 are formed on the substrate D211 and are directly connected to the first metal layer ML1 of the corresponding scan lines GL1~GLm. In other words, the fan-out wirings FOL are equivalent to the wiring patterns of the first metal layer ML1 formed on the substrate D211 to electrically connect the scan lines GL1~GLm and the driving chip D220.

[0154] Since the fan-out wirings FOL of the present embodiment are implemented by the first metal layer ML1 directly formed on the substrate D211, which is covered by two insulating layers IL1 and IL2, the first metal layer ML1 can be completely covered to reduce the corrosion resistance and moisture resistance of the first metal layer ML1, thereby prolonging the service life of the display panel D200.

[0155] However, since the fan-out wirings FOL are composed of a single layer of metal, in order to avoid the problem of short circuit between the wirings, the wiring spacing of the fan-out wirings FOL needs to meet certain design specifications. In this way, the use of the single-layer structure fan-out wiring FOL design of the present embodiment will inevitably cause the width of the non-display region SR to be difficult to reduce, which is not conducive to the narrow frame design requirements of current small-size display devices.

[0156] Please also refer to FIG. 11A and FIG. 11B , the circuit structure of the display panel D200 of the present embodiment is similar FIG. 10B to the embodiment, each scan line GL1~GLm is also implemented by the first metal layer ML1. The main difference between the present embodiment and the aforementioned FIG. 10A and FIG. 10B embodiments is that the fan-out wirings FOL of the fan-out transmission portions WRG1 and WRG2 are composed of a double-layer metal staggered arrangement structure.

[0157] Specifically, in this embodiment, the fan-out traces FOL of each fan-out transmission unit WRG1 and WRG2 are staggered and sequentially connected to the corresponding scan lines GL1~GLm using the first metal layer ML1 and the second metal layer ML2. Taking the trace design of the fan-out transmission unit WRG1 as an example, the fan-out trace FOL connecting scan line GL1 is formed with the first metal layer ML1, the fan-out trace FOL connecting scan line GL3 is formed with the second metal layer ML2, the fan-out trace FOL connecting scan line GL5 is formed with the first metal layer ML1, and so on. Similarly, in the fan-out transmission unit WRG2, the fan-out trace FOL connecting scan line GL2 is formed with the second metal layer ML2, the fan-out trace FOL connecting scan line GL4 is formed with the first metal layer ML1, and so on.

[0158] In other words, in each fan-out transmission section WRG1 and WRG2, adjacent traces of each fan-out trace FOL are located on different metal layers. Observing the fan-out connection configuration of the overall scan lines GL1~GLm, scan lines GL2 and GL3 are electrically connected to the driver chip D220 through the fan-out trace FOL formed on the second metal layer ML2, scan lines GL4 and GL5 are electrically connected to the driver chip D220 through the fan-out trace FOL formed on the first metal layer ML1, and so on.

[0159] More specifically, since scan lines GL1~GLm transmit signals through the first metal layer ML1, in the configuration where the fan-out trace FOL is used through the second metal layer ML2, a bridging structure BA is used to electrically connect the fan-out trace FOL and the corresponding scan line. The cross-sectional structure of the bridging structure BA at the cutoff line DD' is as follows. FIG. 11B As shown, in the bridging structure BA, vias TH1 and TH2 are formed in the regions of the first insulating layer IL1 and the second insulating layer IL2 covering the first metal layer ML1 and the second metal layer ML2, respectively. Via TH1 exposes the second metal layer ML2, and via TH2 exposes the first metal layer ML1. The bridging structure BA also includes a conductive layer CL. The conductive layer CL covers the second insulating layer IL2 and the vias TH1 and TH2, allowing the first metal layer ML1 and the second metal layer ML2 to be electrically connected to each other through the conductive layer CL. In some embodiments, the conductive layer CL may be implemented, for example, as an ITO conductive film, but this application is not limited to this.

[0160] In the double-layer metal staggered structure routing design of this embodiment, since the fan-out routing FOL is arranged in an alternating configuration of different layers of first metal layer ML1 and second metal layer ML2, and there is a first insulating layer IL1 between the routing lines, the design specification of the routing spacing of the fan-out routing FOL can be smaller than that of the single-layer metal structure routing design, thus better meeting the narrow bezel design requirements of current small-size display devices.

[0161] However, on the contrary, in the configuration of using the second metal layer ML2 as the fan-out wire FOL, due to only a single layer of the insulating layer IL2 on the second metal layer ML2, when the edge inclination angle of the second metal layer ML2 is too large, the second insulating layer IL2 on the second metal layer ML2 can be broken or discontinuous at the edge of the second metal layer ML2 (also known as "undercut"), causing the second metal layer ML2 to be exposed, and thus the corrosion resistance and moisture resistance of the second metal layer ML2 are lower than those of the first metal layer ML1. This can cause the display panel D200 to display a poor picture.

[0162] To solve the above-mentioned FIG. 10A to FIG. 11B problems of the wire design, embodiments of the present application propose a single-layer and double-layer staggered mixed structure of the wire design, as shown in FIG. 12 In the embodiments, the scan lines GL1~GLm can be divided into a first scan line group GLo and a second scan line group GLi, wherein the first scan line group GLo includes the scan lines GL1~GLa, and the second scan line group GLi includes the scan lines GLa+1~GLm, 2≤a<m. In other words, at least two scan lines of the display panel D200 from top to bottom belong to the first scan line group GLo, and the (m-a) consecutive scan lines belong to the second scan line group GLi.

[0163] In the fan-out transmission portions WRG1 and WRG2, the fan-out wires FOL connected to the first scan line group GLo adopt the single-layer metal structure of the wire design as shown in FIG. 10A , and the fan-out wires FOL connected to the second scan line group GLi adopt the double-layer metal staggered arrangement structure of the wire design as shown in FIG. 11A .

[0164] That is, the fan-out wires FOL electrically connected to the first a scan lines GL1~GLa are formed on the substrate D211 by the first metal layer (such as ML1 in FIG. 10B and FIG. 10B ). On the other hand, the fan-out wires FOL electrically connected to the a+1th to mth scan lines GLa+1~GLm are formed on the substrate D211 by the first metal layer and the second metal layer (such as ML2 in FIG. 10B and FIG. 11B ) staggered arrangement, so that each fan-out wire FOL in each fan-out transmission portion WRG1 and WRG2 is formed with a different metal layer from the adjacent fan-out wire FOL.

[0165] In some embodiments, a is, for example, 4. That is, the fan-out lines FOL of the first to fourth scan lines GL1~GL4 of the display panel D200 are formed by the first metal layer, and the fifth to mth scan lines GL5~GLm of the display panel D200 are formed by the first metal layer and the second metal layer in an interleaved arrangement.

[0166] Specifically, because the layout of the fan-out lines FOL has the arrangement characteristic of from top to bottom and from outside to inside (that is, the closer the connection of the scan lines GL1~GLm to the top side, the closer the layout to the edge of the substrate D211), the closer the area of the display panel D200 to the edge of the substrate D211, the higher the risk of under cut.

[0167] Therefore, by arranging the gate fan-out lines FOL (that is, the fan-out lines FOL connected to the first scan line group GLo) close to the edge of the substrate D211 as a single-layer metal structure, and arranging the fan-out lines (that is, the fan-out lines FOL connected to the second scan line group GLi) close to the display area DR as a double-layer metal interleaved arrangement structure, the risk of under cut is maximally reduced while maintaining the minimum arrangement of the pitch of part of the fan-out lines, thereby simultaneously meeting the requirements of the corrosion resistance and moisture resistance capability of the display panel D200 and the design requirement of the narrow frame.

[0168] In some embodiments, the line width of the fan-out lines FOL electrically connected to the first scan line group GLo is greater than the line width of the fan-out lines FOL electrically connected to the second scan line group GLi.

[0169] The configuration of the pixel array in the display panel D100 / D200 described above is further illustrated below. FIG. 13 to FIG. 18B For ease of illustration, the following description takes the display panel D100 and its components as the description subject, but the present application is not limited thereto.

[0170] FIG. 13 is an equivalent circuit schematic diagram of the pixel array of the embodiments of the present application. Please refer to FIG. 13 , the pixel array D112 includes a plurality of pixel units Pu arranged in an array, wherein the first row of pixel units Pu are commonly electrically connected to the first scan line GL1, the second row of pixel units Pu are commonly electrically connected to the second scan line GL2, the first column of pixel units Pu are commonly electrically connected to the first data line DL1, and the second column of pixel units Pu are commonly electrically connected to the second data line DL2, and the connection relationship of other pixel units can be similarly deduced.

[0171] From the perspective of the equivalent circuit, taking the pixel unit Pu in the first row and first column as an example, the pixel unit Pu includes a thin-film transistor M and capacitors Cp1, Cp2, and Cp3. Capacitor Cp1 is composed of a common electrode COM and a data line DL1, and can be considered as being electrically connected to the data line DL1 and the common voltage V. COM Between. Capacitor Cp2 is composed of the common electrode COM and the scan line GL1, and can be considered as electrically connected between the scan line GL1 and the common voltage V. COM Between. Capacitor Cp3 is composed of the common electrode COM and the pixel electrode Ep of the thin-film transistor M, and can be considered as electrically connected between the pixel electrode Ep and the common voltage V. COM It is located between and in parallel with the liquid crystal cell (LC).

[0172] FIG. 14A and FIG. 14B This is a schematic diagram of the structural configuration of the pixel array in some embodiments of this application, wherein... FIG. 14A and FIG. 14B Taking a pixel structure with dual gates as an example, FIG. 14A This is a top view of pixel array D112, and FIG. 14B This is a cross-sectional view of pixel array D112. Please also refer to... FIG. 14A and FIG. 14B The pixel array D112 includes thin-film transistors M11, M12, M21, and M22. The control terminals of thin-film transistors M11 and M12 are electrically connected to scan line GL1, and the control terminals of thin-film transistors M21 and M22 are electrically connected to scan line GL2. The first terminals of thin-film transistors M11 and M21 are electrically connected to data line DL1, and the first terminals of thin-film transistors M12 and M22 are electrically connected to data line DL2. The second terminals of thin-film transistors M11, M12, M21, and M22 are respectively electrically connected to the corresponding pixel electrodes EP11, EP12, EP21, and EP22. In this embodiment, the control terminal of thin-film transistors M11 to M22 can be, for example, a gate; the first terminal of thin-film transistors M11 to M22 can be, for example, one of the source and drain terminals; and the second terminal of thin-film transistors M11 to M22 can be, for example, the other of the source and drain terminals, but this application is not limited thereto.

[0173] Take the pixel unit Pu corresponding to the thin film transistor M11 as an example. From the perspective of the top view structure, the portion of the common electrode COM and the pixel electrode EP11 formed by the panel-shaped metal layer MP1 overlap, forming part of the pixel storage capacitor (i.e., the capacitor Cp3 in the equivalent circuit) of the pixel unit Pu, wherein the pixel electrode EP11 is disposed in the area overlapping with the grid structure of the common electrode COM. On the other hand, the pixel array D112 of the present embodiment also includes a black matrix BMX, wherein the shape of the black matrix BMX is designed to generally correspond to the shape of the common electrode COM, and is configured to be stacked on one side of the common electrode COM, but generally exposes the area of the grid structure of the common electrode COM.

[0174] From the perspective of the cross-sectional structure at the section line EE', in the pixel array D112, the first insulating layer IL1 is formed on the substrate D111. The metal layer MP1 and MP2 are formed on the first insulating layer IL1 with a gap therebetween, and are covered by the second insulating layer IL2. The common electrode COM in the grid structure is formed on the second insulating layer IL2, wherein the width of the first portion COMa of the common electrode COM covering the metal layer MP1 is smaller than the second portion COMb of the common electrode COM covering the gap between the metal layer MP1 and MP2. In other words, the orthographic projection area of the first portion COMa of the common electrode COM and the metal layer MP1 at least partially overlap, and the orthographic projection area of the second portion COMb of the common electrode COM and the metal layer MP1 generally do not overlap. In the present embodiment, the metal layer MP1 constitutes the pixel electrode EP11 corresponding to the thin film transistor M11. From the perspective of the configuration of the black matrix, the orthographic projection area of the common electrode COM and the black matrix BMX generally overlap each other, wherein the orthographic projection area of the first portion COMa of the common electrode COM and the black matrix BMX generally do not overlap, and the black matrix BMX in the area corresponding to the second portion COMb of the common electrode COM has an orthographic projection area that overlaps with the orthographic projection area of the second portion COMb of the common electrode COM.

[0175] The liquid crystal layer LCL can be formed by injecting a liquid crystal material between the common electrode COM and the upper substrate D111'. The black matrix BMX is disposed on the side of the substrate D111' facing the substrate D111 and is located above the second portion COMb of the common electrode COM, wherein the stacked structures on the left and right sides of the black matrix BMX can be considered as two adjacent pixel units Pu.

[0176] Specifically, the size of the pixel storage capacitor is mainly determined by the overlapping area between the metal layer MP1 and the common electrode COM and the thickness of the insulating layer IL2 therebetween. The larger the overlapping area / thinner the insulating layer IL2, the greater the capacitance value of the pixel storage capacitor can be. A larger pixel storage capacitor can effectively maintain the display quality, reduce the problems of flicker and crosstalk of the display panel, etc.

[0177] However, under the design of a general pixel array, the thickness of the insulating layer IL2 is limited, and if the area of the metal layer MP1 is increased, the aperture ratio and the light transmittance of the display panel will be reduced. In other words, under the existing design, it is difficult to simultaneously achieve the effects of increasing the pixel storage capacitance and maintaining the aperture ratio / light transmittance.

[0178] To solve the foregoing problems, embodiments of the present application propose a structure configuration of a pixel array as shown in FIG. 15A to FIG. 16B , wherein FIG. 15A and FIG. 15B are a top view and a cross-sectional view of a structure configuration of a pixel array according to an embodiment of the present application, and FIG. 16A and FIG. 16B are a top view and a cross-sectional view of a structure configuration of a pixel array according to another embodiment of the present application.

[0179] Please refer to FIG. 15A and FIG. 15B , the pixel array D112 of the present embodiment comprises thin film transistors M11, M12, M21 and M22. From the perspective of the stack structure of the pixel unit Pu corresponding to the thin film transistor M11, the pixel array D112 comprises a substrate D111 and D111', a first insulating layer IL1, a metal layer MP1, a second insulating layer IL2, a liquid crystal layer LCL and a black matrix BMX, which are similar to the foregoing FIG. 14B . The configuration of each component described above can refer to the description of the foregoing FIG. 14A and FIG. 14B , which will not be repeated here.

[0180] The main difference between the foregoing FIG. 14A and FIG. 14B is that the pixel array D112 of the present embodiment further comprises an extended metal layer MP1e. The extended metal layer MP1e is electrically connected to the drain of the thin film transistor M11 and the metal layer MP1, wherein the extended metal layer MP1e extends from the metal layer MP1 to form a gap region GR between the metal layers MP1 and MP2, and at least part of the extended metal layer MP1e is formed within the orthographic projection region of the black matrix BMX (or can be referred to as being formed within the orthographic projection region of the second part of the common electrode COMb).

[0181] By the above-mentioned configuration of the extended metal layer MP1e, the area of the pixel electrode EP11 of the thin film transistor M11 can be equivalent to the sum of the orthographic projection areas of the metal layer MP1 and the extended metal layer MP1e, so as to effectively increase the pixel storage capacitance of the pixel unit Pu. In addition, since the extended metal layer MP1e is located in the shielding area / orthographic projection area of the black matrix BMX, the extended metal layer MP1e does not increase the shielding area and reduce the aperture ratio / transmittance. Thus, the effects of increasing the pixel storage capacitance and maintaining the aperture ratio / transmittance are achieved at the same time.

[0182] More specifically, in the present embodiment, the first portion of the extended metal layer MP1e extends horizontally from the drain of the thin film transistor M11 to the interval region GR between the metal layers MP1 and MP2, and the second portion of the extended metal layer MP1e extends along the orthographic projection area of the second portion common electrode COMb to be substantially parallel to the grid structure of the common electrode COM. In other words, the first portion and the second portion of the extended metal layer MP1e form a "7" shape structure in the top view. FIG. 15A

[0183] In the present embodiment, the extended metal layer MP1e can be formed in the same layer as the data lines DL1 and DL2 and be made of an opaque metal material, but the present application is not limited thereto. In the application of the extended metal layer MP1e in the same layer as the data lines DL1 and DL2, the width of the extended metal layer MP1e is designed to be less than or equal to the width of the data lines DL1 and DL2 to prevent the extended metal layer MP1e from short-circuiting with the adjacent pixel electrode.

[0184] In some embodiments, the pixel unit corresponding to the diagonally adjacent thin film transistor M22 also has an extended metal layer MP1e similar to that shown in FIG. 15A and FIG. 15B , and the extended metal layer of the thin film transistor M22 is formed in the same orthographic projection area of the second portion common electrode COMb as the extended metal layer MP1e of the thin film transistor M11.

[0185] Please refer to FIG. 16A and FIG. 16B , the structural configuration and effects of the present embodiment are substantially the same as those of FIG. 15A and FIG. 15B , and the similar parts will not be repeated. The main difference between the present embodiment and the aforementioned FIG. 15A and FIG. 15B is that FIG. 15A and FIG. 15B ​The extended metal layer MP1e of the embodiment is implemented in the same layer as the data lines DL1, DL2, and is formed extending from the drain of the thin film transistor M11, so the second portion of the extended metal layer MP1e will extend from the upper side to the lower side of the pixel array, and will be closer to the scan line GL1 connected to the thin film transistor M11.

[0186] In contrast, in FIG. 16A and FIG. 16B , the extended metal layer MP1e is formed extending from the metal layer MP1 in the gap region GR, that is, the extended metal layer MP1e is arranged in the same layer as the metal layer MP1, and extends from the lower side to the upper side of the pixel array. In other words, the extended metal layer MP1e of the present embodiment will be closer to the next row of scan lines GL2 connected to the thin film transistor M11.

[0187] In some embodiments, the pixel unit corresponding to the obliquely adjacent thin film transistor M22 will also have an extended metal layer MP1e similar to that shown in FIG. 16A and FIG. 16B , and the extended metal layer of the thin film transistor M22 will be formed in the same orthographic projection region of the second portion common electrode COMb as the extended metal layer MP1e of the thin film transistor M11.

[0188] FIG. 17A FIG. 17B are schematic diagrams of the structure of the pixel array of some embodiments of the present application, in which FIG. 17A and FIG. 17B are shown as examples of pixel structures with three gates, FIG. 17A is a top view of the pixel array D112, and FIG. 17B is a cross-sectional view of the pixel array D112. Please refer to FIG. 17A and FIG. 17B ​The pixel array D112 includes thin film transistors M11, M12, M21, M22, M31, and M32. The control terminals of the thin film transistors M11 and M12 are electrically connected to the scan line GL1, the control terminals of the thin film transistors M21 and M22 are electrically connected to the scan line GL2, and the control terminals of the thin film transistors M31 and M32 are electrically connected to the scan line GL3. The first terminals of the thin film transistors M11, M21, and M31 are electrically connected to the data line DL1, and the first terminals of the thin film transistors M12, M22, and M32 are electrically connected to the data line DL2. The second terminals of the thin film transistors M11, M12, M21, M22, M31, and M32 are respectively electrically connected to the corresponding pixel electrodes EP11, EP12, EP21, EP22, EP31, and EP32. In the present embodiment, the control terminals of the thin film transistors M11-M32 can be, for example, gates, one of the first terminals of the thin film transistors M11-M32 can be, for example, a source or a drain, and the other of the first terminals of the thin film transistors M11-M32 can be, for example, a source or a drain, but the present application is not limited thereto.

[0189] In addition, in some embodiments of the three-gate pixel structure, the scan line segment connecting two adjacent columns of thin film transistors can be divided into two line segments connected to each other, wherein the extension directions of the two line segments are not parallel to each other. Taking the scan line GL2 as an example, the scan line segment connecting the thin film transistors M21 and M22 can be divided into a first line segment Ls1 close to the thin film transistor M21 on one side and a second line segment Ls2 close to the thin film transistor M22 on the other side, wherein the extension direction of the first line segment Ls1 and the extension direction of the second line segment Ls2 are not parallel to each other. The other scan lines GL1 and GL3 can also be configured in a similar manner, which will not be repeated here.

[0190] Taking the pixel unit Pu corresponding to the thin film transistor M21 as an example, from the perspective of the top view structure, the portion of the pixel electrode EP21 formed by the common electrode COM and the panel-shaped metal layer MP1 overlaps, forming part of the pixel storage capacitor (i.e., the capacitor Cp3 in the equivalent circuit) of the pixel unit Pu, wherein the pixel electrode EP21 is arranged in the area overlapping with the grid-shaped structure (i.e., the first portion of the common electrode COMa) of the common electrode COM. On the other hand, the pixel array D112 of the present embodiment also includes a black matrix BMX, wherein the shape of the black matrix BMX is designed to generally correspond to the shape of the common electrode COM, and is arranged to be stacked on one side of the common electrode COM, but generally exposes the area of the grid-shaped structure of the common electrode COM.

[0191] From the cross-sectional structure at the cut line EE', in the pixel array D112, a scan line GL2 is disposed on the substrate D111, and a first insulating layer IL1 is formed on the substrate D111 and covers the scan line GL2. Metal layers MP1 and MP2 are formed on the first insulating layer IL1 with a space therebetween. In some embodiments, the metal layers MP1 and MP2 and the first insulating layer IL1 form a coplanar surface. A second insulating layer IL2 is formed on the metal layers MP1 and MP2 and the first insulating layer IL1, and a common electrode COM is formed on the second insulating layer IL2, wherein a first portion COMa of the common electrode COM located on the metal layers MP1 and MP2 has a width smaller than a second portion COMb of the common electrode COM located at the space between the metal layers MP1 and MP2.

[0192] In other words, the first portion COMa of the common electrode COM and the metal layer MP1 have at least partially overlapping orthogonal projection regions, and the second portion COMb of the common electrode COM and the metal layers MP1 / MP2 have substantially non-overlapping orthogonal projection regions. In the present embodiment, the metal layer MP1 constitutes a pixel electrode EP21 corresponding to the thin film transistor M21. In terms of the configuration with respect to the black matrix BMX, the common electrode COM and the black matrix BMX have substantially overlapping orthogonal projection regions, wherein the black matrix BMX and the first portion COMa of the common electrode COM have substantially non-overlapping orthogonal projection regions, and the black matrix BMX located at the corresponding region with the second portion COMb of the common electrode COM have overlapping orthogonal projection regions.

[0193] A liquid crystal layer LCL can be formed between the common electrode COM and the substrate D111' on the upper side by injecting a liquid crystal material. A black matrix BMX is disposed on the substrate D111' toward the substrate D111 on the side of the second portion COMb of the common electrode COM, wherein the stacked structure on the left and right sides of the black matrix BMX can be considered as two adjacent pixel units Pu.

[0194] Specifically, in terms of the pixel unit Pu corresponding to the thin film transistor M21, the size of the pixel storage capacitor is mainly determined by the overlapping area between the metal layer MP1 and the common electrode COM and the thickness of the insulating layer IL2 therebetween. The larger the overlapping area / thinner the insulating layer IL2, the greater the capacitance value of the pixel storage capacitor.

[0195] However, similar to FIG. 14A and FIG. 14BThe problem is that, in the design of a pixel array of a general three-gate pixel structure, the thickness of the insulating layer IL2 is also limited, and if the area of the metal layer MP1 is increased, the aperture ratio and light transmittance of the display panel will decrease. In other words, it is difficult to increase the pixel storage capacitance and maintain the aperture ratio / light transmittance under the existing design, and in the case of insufficient pixel storage capacitance, the problem of unstable pixel voltage will occur.

[0196] In addition, in the design of the double-layer staggered fan-out wire, when the transistor M21 is turned on, the charge on the pixel electrode EP21 no longer flows to the data line, thus entering a charge conservation state and causing a capacitive coupling effect between the overlapping scan lines, resulting in an increase in coupling and a relative increase in leakage current.

[0197] To solve the foregoing problems, embodiments of the present application propose a pixel array structure configuration as shown in FIG. 18A to FIG. 18C , wherein FIG. 18A and FIG. 18B are top view schematic diagrams of the pixel array structure configuration of different embodiments of the present application, and FIG. 18C are cross-sectional schematic diagrams of the pixel array structure configuration according to the FIG. 18A or FIG. 18B embodiment.

[0198] Please refer to FIG. 18A and FIG. 18C at the same time, the pixel array D112 of the present embodiment includes thin film transistors M11, M12, M21, M22, M31 and M32. From the perspective of the stacked structure of the pixel unit Pu corresponding to the thin film transistors M21 and M32, it is similar to the foregoing FIG. 17B , the pixel array D112 includes substrates D111 and D111', a first insulating layer IL1, a metal layer MP1, a second insulating layer IL2, a liquid crystal layer LCL and a black matrix BMX. The configuration of each component described above can refer to the description of the foregoing FIG. 17A and FIG. 17B , which will not be repeated here.

[0199] and the foregoing FIG. 17A and FIG. 17BThe main difference is that in this embodiment, the pixel electrodes EP21 / EP32 extend to the area on the scan lines GL1 / GL2 of the preceding pixel unit. For example, the metal layer MP1, which is the pixel electrode EP21, extends to the area on the scan line GL1, and the metal layer MP2, which is the pixel electrode EP32, extends to the area on the scan line GL2. In this embodiment, the coverage area of ​​the pixel electrodes EP21 / EP32 on the first line segment Ls1 is approximately the same as the coverage area of ​​the pixel electrodes EP21 / 32 on the second line segment Ls2. In other words, in this embodiment, the pixel electrodes EP21 / EP32 simultaneously cover the first line segment Ls1 and the second line segment Ls2 of the corresponding scan lines GL1 / GL2 (also referred to as "full coverage configuration"). From another perspective, the full coverage configuration means that the metal layer MP1 / MP2, which serves as the pixel electrode EP21 / EP32, at least partially overlaps with the orthographic projection areas of the first line segment Ls1 and the second line segment Ls2 of the corresponding scan line GL1 / GL2, wherein the overlap area of ​​the metal layer MP1 / MP2 and the orthographic projection area of ​​the first line segment Ls1 is approximately the same as the overlap area of ​​the orthographic projection areas of the metal layer MP1 / MP2 and the second line segment Ls2.

[0200] More specifically, such as FIG. 18C As shown, from the cross-sectional structure at the cut-off line EE', the metal layer MP2 extends to form on the first insulating layer IL1 covering the scan line GL2. The metal layer MP2 can be divided into a first portion MP2a and a second portion MP2b. The first portion MP2a is located below the first common electrode COMa and does not overlap with the scan line GL2. The second region MP2b of the metal layer MP2 is at least partially located above the scan line GL2 and below the second common electrode COMb. In other words, in this embodiment, the orthographic projection regions of the first portion MP2a of the metal layer MP2 and the first common electrode COMa at least partially overlap. The orthographic projection regions of the second portion MP2b of the metal layer MP2, the second common electrode COMb, and the scan line GL2 at least partially overlap.

[0201] With the above-described configuration of the metal layer MP2, the pixel storage capacitance corresponding to the pixel electrode EP32 of the thin-film transistor M11 can be considered as the capacitance formed by the first part MP2a and the first common electrode COMa of the metal layer MP2, plus the capacitance formed by the second part MP2b and the second common electrode COMb of the metal layer MP2. In other words, the area of ​​the pixel electrode EP32 can be considered as the sum of the projected areas of the first part MP2a and the second part MP2b of the metal layer MP2, compared to... FIG. 17A and FIG. 17BRegarding the pixel structure, this embodiment increases the area of ​​the pixel electrode EP32, thereby effectively increasing the pixel storage capacitance of the pixel unit Pu.

[0202] Experiments have verified that FIG. 18A Compared to traditional pixel structures, the full-coverage pixel structure allows for increased pixel capacitance (i.e., ...) without any shift in the manufacturing process. FIG. 13 The capacitance value of the capacitor Cp3 is increased by approximately 13%, and the scan line capacitance (i.e., FIG. 13 The capacitance value of the capacitor Cp2 is increased by approximately 8.2%. Furthermore, the overlap between the second portion MP2b of the metal layer MP2 and the scan line GL2 of the previous stage effectively increases the scan line capacitance Cp2. Since the coupling between the upper and lower traces in a double-layer staggered fan-out trace design is generally inversely proportional to the value of the scan line capacitance Cp2, increasing the scan line capacitance Cp2 in this embodiment reduces the trace coupling, thereby reducing the gate-source voltage of the transistor M32. FIG. 19 As shown, compared to FIG. 17A and FIG. 17B The voltage-current characteristic curve CV1 of the pixel array configuration, and the voltage-current characteristic curve CV2 of this embodiment, show a significant leftward shift, causing the gate-source voltage V... GS and leakage current I DS It can be effectively reduced.

[0203] Please refer to the following at the same time FIG. 18B and FIG. 18C , FIG. 18B Pixel structure of the embodiment and FIG. 18A The pixel structure of the embodiments is largely the same, so related or similar parts can be referred to the description of the above embodiments, and will not be repeated here. This embodiment is similar to the one described above. FIG. 18A The main difference between the embodiments is that the pixel electrode EP21 / EP32 in this embodiment only covers the first segment Ls1 / second segment Ls2 of the corresponding scan line GL1 / GL2 on one side (also known as "single-side coverage configuration").

[0204] by FIG. 18BThe pixel electrode EP21 covers a first line segment Ls1 of a majority of the scan line GL1 and a second line segment Ls2 of a portion of the scan line GL1, and the pixel electrode EP32 covers a first line segment Ls1 of a majority of the scan line GL2 and a second line segment Ls2 of a portion of the scan line GL2. That is, in the present embodiment, the pixel electrode EP21 / EP32 covers a larger area on the first line segment Ls1 than on the second line segment Ls2 (i.e., left-side single-side coverage configuration), but the present application is not limited thereto. In other embodiments, the pixel structure can also be designed to cover a smaller area on the first line segment Ls1 than on the second line segment Ls2 (i.e., right-side single-side coverage configuration).

[0205] In other words, the pixel electrode EP21 / EP32 of the present embodiment covers a larger area on one of the first line segment Ls1 and the second line segment Ls2 of the corresponding scan line GL1 / GL2 than on the other of the first line segment Ls1 and the second line segment Ls2. In another aspect, the single-side coverage configuration refers to the overlapping area between the metal layer MP1 / MP2 of the pixel electrode EP21 / EP32 and the orthographic projection area of one of the first line segment Ls1 and the second line segment Ls2 of the corresponding scan line GL1 / GL2 being larger than the overlapping area between the metal layer MP1 / MP2 and the orthographic projection area of the other of the first line segment Ls1 and the second line segment Ls2 of the corresponding scan line GL1 / GL2.

[0206] From the cross-section structure passing through the first line segment Ls1, FIG. 18A the cross-section structure will be as shown in FIG. 18B If the cross-section structure passing through the second line segment Ls2 is considered, FIG. 18C the cross-section structure will be as shown in FIG. 18A but FIG. 18C the cross-section structure will be as shown in FIG. 18B FIG. 17B Experiments have shown that, compared with the conventional pixel structure, the single-side coverage configuration of the pixel structure of the present application can increase the pixel capacitance (i.e., the capacitance Cp3) by about 10.4% and the scan line capacitance (i.e., the capacitance Cp2) by about 15% without causing the manufacturing process to deviate.

[0207] FIG. 18B FIG. 13 FIG. 13

[0208] ​​​​​More specifically, during the manufacturing process of the pixel array D112, the fabrication process offset of pixel electrodes EP21 / EP32 is generally between 1.35μm (3 sigma) and 2.7μm (6 sigma). Therefore, to cover the scan lines GL1 / GL2 with pixel electrodes EP21 / EP32, the overlap width between pixel electrodes EP21 / EP32 and scan lines GL1 / GL2 needs to be at least between 1.35μm and 2.7μm to avoid failing to achieve the desired coverage structure due to the fabrication process offset. Furthermore, in FIG. 18A and FIG. 18B In the pixel structure, the manufacturing process deviation of pixel electrodes EP21 / EP32 will also affect the estimated capacitance values ​​of capacitors Cp2 and Cp3. If the capacitance value change caused by this manufacturing process deviation is too large, it may affect the design considerations of various performance aspects of the display panel.

[0209] FIG. 18B Compared to the example FIG. 18A The embodiment employs a single-sided coverage configuration design, which effectively reduces the impact of manufacturing process offsets on the capacitance values ​​of pixel electrodes EP21 / EP32. Experimental verification confirms this.

[0210] With pixel electrodes EP21 / EP32 offset vertically, calculations are performed based on an offset of 3 sigma, using... FIG. 18B The pixel capacitance offset of the pixel structure in the single-sided coverage configuration is 5.3%, which is higher than... FIG. 18A The pixel capacitance offset of the full-coverage pixel structure was reduced by about half, by 10.9%; on the other hand, adopting a method such as FIG. 18B The scan line capacitance offset of the pixel structure in the single-sided coverage configuration is 10.5%, compared to FIG. 18A The pixel capacitance offset of the full-coverage configuration pixel structure was reduced by about half by 20.2%.

[0211] As can be seen from the above, compared with the full coverage configuration, the single-sided coverage configuration can not only effectively increase the capacitance values ​​of the pixel capacitor and the scan line capacitor, but also further reduce the impact of manufacturing process deviation on the pixel capacitor and the scan line capacitor. This can make the common electrode voltage uniformity in the panel better and significantly optimize the panel's flicker problem.

[0212] The following is further... FIG. 20 to FIG. 24B This document describes some technical features of the aforementioned display devices 10 / 20 / 30 and display panels D100 / D200 during the assembly and manufacturing process. For ease of explanation, the following description will focus on display device 10 and display panel D100, but this application is not limited to these.

[0213] FIG. 20FIG. 1 shows a schematic diagram of an array substrate according to an embodiment of the present application. FIG. 20 The array substrate 1 of the present application comprises a glass substrate SUB (or referred to as a mother substrate SUB) and a plurality of display panels D100, wherein the area of the glass substrate SUB on which the plurality of display panels D100 are formed can be divided into a plurality of array blocks ABLK. In some embodiments, in each array block ABLK, the edges of the display panels D100 are adjacently arranged such that no test circuit trace can be arranged between the display panels D100, preferably, the plurality of display panels D100 are arranged on the array substrate 1 without any gap therebetween. In the present embodiment, the common electrode on each of the display panels D100 overlaps with the metal of the scan lines, data lines, pixel electrodes, etc. in the display area to form corresponding capacitors, respectively. In the process of manufacturing the display panels D100, the display panels D100 are first formed on the array substrate 1, and then are divided and assembled into independent display devices 20 as shown in FIGS. 2 and 3 or independent display devices 30 as shown in FIGS. 4 and 5. FIG. 2A FIG. 2B FIG. 9A FIG. 9B

[0214] For example, the configuration of the adjacent display panels D100a and D100b is described as follows. FIG. 21 FIG. 6 shows a schematic diagram of the configuration of the adjacent display panels on the array substrate according to an embodiment of the present application. The common electrode COM1 of the display panel D100a overlaps with the metal of the scan lines GL, data lines DL and pixel electrode Ep of the thin film transistor M in the display area; similarly, the display panel D100b also has a similar configuration. As shown in FIG. 7, the pixel unit Pu on the display panel D100a is taken as an example to describe the equivalent circuit. The pixel unit Pu can be equivalent to having the thin film transistor M and capacitors Cp1, Cp2 and Cp3, and the specific connection relationship can refer to the description of the foregoing FIG. 21 FIG. 13 FIG. 13 Therefore, the total capacitance of the display area of the display panel D100a / D100b is equal to the sum of the capacitances of the capacitors Cp1, Cp2 and Cp3 multiplied by the number of pixel units Pu in the display area.

[0215] ​​​​​​The adjacent display panels D100a and D100b of the present embodiment are electrically connected to each other by at least one line 3. In the present embodiment, the display panels D100a and D100b are shown as being connected to each other by two lines 3, but the present application is not limited thereto. In some embodiments, the display panels D100a and D100b can be electrically connected to each other by more lines 3.

[0216] By way of reference FIG. 20 and FIG. 21 In the present embodiment, the display panels D100 in each array block ABLK in the array substrate 1 are electrically connected to each other by at least one line 3. In the present embodiment, the display panels D100a and D100b are shown as being connected to each other by two lines 3, but the present application is not limited thereto. In some embodiments, the display panels D100a and D100b can be electrically connected to each other by more lines 3.

[0217] FIG. 22A and FIG. 22B FIG. 1 is a schematic diagram of the configuration of the display panels of the present application on the array substrate. In the present embodiment, the display panels D100 are configured similarly to the embodiments described above, and have a display region DR and a non-display region SR. The specific structural configuration of the display panels D100 can be referred to the description of the embodiments described above, and will not be repeated here. In the present embodiment, the display panels D100 are arranged in the same configuration and in the same direction. That is, in the vertical direction, the foot region of the display panel D100 (the lower side of the figure, i.e., the side of the non-display region SR with a wider width, or the side on which the data driving circuit D130 is arranged) is adjacent to the head region of the adjacent display panel D100 (the upper side of the figure, i.e., the side of the non-display region SR with a narrower width). In addition, the display panels D100 are connected to each other by a plurality of lines 3. For example, FIG. 22A In the present embodiment, the display panels D100 are arranged in the same configuration and in the same direction. That is, in the vertical direction, the foot region of the display panel D100 (the lower side of the figure, i.e., the side of the non-display region SR with a wider width, or the side on which the data driving circuit D130 is arranged) is adjacent to the head region of the adjacent display panel D100 (the upper side of the figure, i.e., the side of the non-display region SR with a narrower width). In addition, the display panels D100 are connected to each other by a plurality of lines 3. For example, FIG. 22A In the present embodiment, the display panels D100 are arranged in the same configuration and in the same direction. That is, in the vertical direction, the foot region of the display panel D100 (the lower side of the figure, i.e., the side of the non-display region SR with a wider width, or the side on which the data driving circuit D130 is arranged) is adjacent to the head region of the adjacent display panel D100 (the upper side of the figure, i.e., the side of the non-display region SR with a narrower width). In addition, the display panels D100 are connected to each other by a plurality of lines 3. For example, FIG. 22A The arrangement configuration of the present embodiment can be referred to as a head-to-tail configuration.

[0218] In addition, FIG. 22B In this arrangement, the upper row of multiple display panels D100 and the lower row of multiple display panels D100 are arranged facing opposite directions. That is, the head region of the upper row display panel D100 is adjacent to the head region of the adjacent lower row display panel D100. Furthermore, the display panels D100 are interconnected via multiple lines 3, for example, FIG. 22B The top left display panel D100 is connected to the adjacent display panel D100 below it by two lines 3, and the top left display panel D100 is connected to the adjacent display panel to its right by three lines 3. In other words, FIG. 22B The arrangement of the embodiment can be described as a head-to-head configuration.

[0219] Experimental tests, as shown in the table below, revealed a 4.38% probability of electrostatic discharge (ESD) damage to the metal lines in the array substrate when there are no test circuit traces on the array substrate and the common electrodes of adjacent display panels are not connected. In contrast, the embodiments of this application, through the aforementioned structural configuration, reduce the probability of ESD damage to 0%.

[0220]

[0221] [Table 1]

[0222] In another embodiment of this application, FIG. 23A This is a schematic diagram showing the electrostatic discharge (ESD) protection structure configured within the array block of the array substrate according to an embodiment of this application. Please refer to... FIG. 23A As described above, the array substrate 1 of this application includes a glass substrate SUB and a plurality of display panels D100. The glass substrate SUB can be divided into a plurality of array blocks ABLK, and the display panels D100 in each array block ABLK can be arranged, for example, edge-to-edge. In this embodiment, each array block ABLK has, for example, twelve display panels D100, but is not limited thereto. More or fewer can be configured, for example, four, six, eight, etc., and this application is not limited thereto.

[0223] Next, please refer to FIG. 23A , FIG. 23B and FIG. 23C ,in FIG. 23B for FIG. 23A The cross-sectional view of the FF' line is also a cross-sectional view of the electrostatic protection structure of the embodiment of this application. FIG. 23C for FIG. 23A A partially enlarged schematic diagram of the electrostatic protection structure.

[0224] Each of the array blocks ABLK has metal layers ML1 and ML2, insulating layers IL1 and IL2, and multiple conductive layers CL.

[0225] like FIG. 23A and FIG. 23B As shown, in each array block ABLK, a metal layer ML1 is disposed on the glass substrate SUB in such a manner that it surrounds at least six of the plurality of display panels D100, thereby forming a plurality of electrostatic discharge lines EDL1 on each array block ABLK. An insulating layer IL1 covers the metal layer ML1, leaving at least a portion of the metal layer ML1 exposed. A metal layer ML2 is disposed on the insulating layer IL1 in such a manner that it surrounds at least six of the plurality of display panels D100, thereby forming a plurality of electrostatic discharge lines EDL2 on each array block ABLK corresponding to the plurality of electrostatic discharge lines EDL1. An insulating layer IL2 covers the metal layer ML2, leaving at least a portion of the metal layer ML2 exposed.

[0226] exist FIG. 23A In this embodiment, metal layer ML2 is outside metal layer ML1. More specifically, metal layer ML2 is closer to the edge of array block ABLK than metal layer ML1, but it is not limited to this. Although not shown in the figure, it can also be the other way around, that is, metal layer ML1 is outside metal layer ML2. Whether metal layer ML1 or metal layer ML2 is closer to the plurality of display panels D100, it can effectively conduct static electricity. The key point is that metal layers ML1 and ML2 are a stacked structure. FIG. 23A In one embodiment, metal layer ML1 surrounds two display panels D100, and metal layer ML2 surrounds six of the display panels D100, but is not limited thereto, and may also surround two, four or eight or more of the display panels D100.

[0227] like FIG. 23A The dashed line between the metal layers ML1 and ML2 is shown, representing the conductive layer CL, as... FIG. 23A The area enclosed by the dashed line is the bridging structure BA (or bridging region BA). The conductive layer CL is formed within the bridging structure BA, and the bridging structure BA is located at least at the bend of the metal layer ML1 (i.e., at the corner of the array block ABLK). Furthermore, as... FIG. 23B As shown by the dashed lines, at least a portion of the conductive layer CL is connected to the metal layer ML1 through the portion exposed by the insulating layer IL1, and at least another portion of the conductive layer CL is connected to the metal layer ML2 through the portion exposed by the insulating layer IL2, such that the conductive layer CL passes through the insulating layers IL1 and IL2, electrically connecting the metal layers ML1 and ML2. In other words, the conductive layer CL electrically connects the metal layers ML1 and ML2 to each other.

[0228] The plurality of electrostatic discharge lines EDL1 and EDL2 are electrically connected to each other through the plurality of conductive layers CL, which electrically connect the metal layers ML1 and ML2 at the plurality of bridge structures BA. In the present embodiment, although the bridge structures BA are shown as being disposed at the turns of the metal layer ML1, the present application is not limited thereto. The bridge structures BA can also be disposed at other positions other than the turns of the metal layer ML1, as long as the metal layer ML1 and the metal layer ML2 are electrically connected to each other. In addition, it should be understood that the effect of dissipating static electricity is better when the bridge structures BA are disposed at the turns of the metal layer ML1.

[0229] Through the above configuration, the effect of electrostatic protection can be achieved even when a small-size display panel D100 is disposed on the array substrate 1 without test circuit traces. Moreover, because the metal layers ML1 and ML2 are double-layer structures, the horizontal area generated by the array substrate 1 can be reduced, thereby increasing the number of display panels D100 that can be disposed on each array block ABLK of the mother substrate SUB. Furthermore, because the electrostatic protection structure is a double-layer structure including the metal layers ML1 and ML2, the overall impedance of the mother substrate SUB is smaller and the equivalent area is larger, thereby more easily achieving the effects of adsorbing and dissipating static electricity.

[0230] As shown in FIG. 23C In the present embodiment, the pitch P1 (or can be referred to as the line pitch) between two adjacent electrostatic discharge lines EDL1 / EDL2 can be greater than 200 μm. More specifically, the line pitch can be, for example, the pitch P1 between the side of the metal layer ML1 close to the metal layer ML2 and the side of the metal layer ML2 away from the metal layer ML1 electrically connected by the conductive layer CL can be 200-300 μm (i.e., the line pitch of adjacent electrostatic discharge lines EDL1 / EDL2 can be between 200-300 μm) when viewed from the top. In addition, the pitch P2 between the two parallel sides of the metal layer ML1 electrically connected by the conductive layer CL can be 150-300 μm.

[0231] Through the above embodiments of the present application, in combination with the sizes of the above pitch P1 and pitch P2, the configuration space required by the electrostatic protection structure of one array block ABLK only needs to be 900-1500 μm, and compared with the prior art, a lot of space is saved. Thus, more small-size display panels D100 can be disposed.

[0232] Please refer to FIG. 24A and FIG. 24B , wherein FIG. 24B is FIG. 24A a cross-sectional view along the GG' line, which is also a cross-sectional view of the electrostatic protection structure of another embodiment of the present application. As shown in FIG. 24A and FIG. 24BAs shown, the metal layer ML2 is two, respectively arranged on both sides of the metal layer ML1, and located at a different height from the metal layer ML1, and the metal layer ML1 is also two in some areas on the glass substrate SUB. When the metal layer ML1 is multiple, it will form multiple electrostatic discharge lines EDL1, and the insulating layer IL1 will electrically isolate each electrostatic discharge line EDL1 in the non-bridge area. Similarly, when the metal layer ML2 is multiple, it will form multiple electrostatic discharge lines EDL2, and the insulating layer IL2 will electrically isolate each electrostatic discharge line EDL2 in the non-bridge area. Through such a setting, it is not necessary to additionally set more insulating layers, and the thickness of the array substrate 1 can also be reduced.

[0233] In addition, in another embodiment of the present application, although the figure is not shown, in each array block ABLK, there are multiple metal layers, multiple insulating layers and multiple conductive layers. The multiple metal layers are arranged in a manner surrounding at least two of the multiple display panels D100 on the glass substrate SUB, and are sequentially stacked. The multiple insulating layers separate the multiple metal layers and expose at least part of the multiple metal layers. The multiple conductive layers at least in the multiple bridge structures of the multiple metal layers, pass through the multiple insulating layers, and electrically connect the multiple metal layers stacked at different layers.

[0234] Through the above embodiments of the present application, the small size display panel D100 is arranged on the array substrate 1 without test circuit traces, and electrostatic protection can also be achieved.

[0235] FIG. 25A And FIG. 25B is a schematic diagram of the pixel array substrate of different embodiments of the present application. Please refer to FIG. 25A , the pixel array substrate D110 of the present embodiment is similar to the configuration of the above FIGS. 1-2B , which includes a display region DR and a non-display region SR, wherein the display region DR is the region on the substrate D111 where the pixel array D112 is arranged, and the non-display region SR is the region on the substrate D111 other than the display region DR. In the non-display region SR, it can also be divided into a frame region BA and a circuit fan-out region FA, wherein the frame region BA is the region for applying frame glue, and the circuit fan-out region FA is the region for arranging the scan driving circuit (such as D120) and / or the data driving circuit (such as D130).

[0236] In some embodiments, the non-display region SR can be arranged in a biased manner on the substrate D111, that is, the width of the non-display region SR on the two sides of the display region SR can be different. For example, in FIG. 25AAs can be seen, the width of the non-display area SR on the lower side of the substrate D111 is greater than the width on the upper side. The lower non-display area SR can serve as the circuit fan-out area FA of the data driving circuit, but this application is not limited to this. In addition, the non-display areas SR on the left and right sides of the display area DR can be symmetrically arranged, that is, the non-display areas SR on both sides have the same width.

[0237] On the other hand, considering the relative configuration of the pixel array substrate D110, the bezel area BA is closer to the edge of the substrate D111 than the circuit fan-out area FA. In other words, the circuit fan-out area FA is closer to the display area DR than the bezel area BA.

[0238] In this embodiment, the pixel array substrate D110, in addition to including the substrate D111 and the pixel array D112, also includes an electrostatic discharge (ESD) protection structure D113. The ESD protection structure D113 is formed by a metal strip pattern on the substrate D111. The metal strip pattern surrounds the substrate D111 and is at least partially located within the bezel area BA, forming an open annular structure. In other words, when the frame adhesive is applied to the display panel, at least a portion of it is applied to the area where the ESD protection structure is located.

[0239] by FIG. 25A For example, the metal strip pattern of the electrostatic protection structure D113 surrounds the left, top, and right sides of the substrate D111; the metal strip pattern is only provided on the two sides of the lower side of the substrate D111, while the middle area of ​​the lower side of the substrate D111 does not have a metal strip pattern, and the middle area without a metal strip pattern is the opening of the annular structure. However, this application is not limited to this.

[0240] To ensure the effectiveness of electrostatic discharge, in some embodiments, the width of the metal strip pattern is greater than or equal to 40 micrometers. Furthermore, to prevent the electrostatic protection structure D113 from being damaged during display panel cutting, in some embodiments, the metal strip pattern may have a gap (e.g., 20 millimeters) between it and the edge of the substrate D111.

[0241] In the manufacturing process of applying and bonding frame adhesive to a display panel using a pixel array substrate D110, when a UV light source shines from the back of the pixel array substrate D110 toward the display panel, the electrostatic discharge structure D113, which is made of opaque metal, blocks part of the UV light that assists in the curing of the frame adhesive, reducing the curing rate of the frame adhesive and resulting in poor display performance of the liquid crystal display panel.

[0242] Please refer to the following: FIG. 25B The pixel array substrate D110' in this embodiment is similar to the one described above. FIG. 25AThe pixel array substrate D110 of the embodiment, the main difference between the two is that the design of the electrostatic protection structure D113' of the embodiment is different from the electrostatic protection structure D113 of the previous embodiment.

[0243] Specifically, the electrostatic protection structure D113' of the embodiment is also taken as an example of being composed of a metal strip pattern formed around the substrate D111, and the main difference between the electrostatic protection structure D113' and the electrostatic protection structure D113 is that the metal strip pattern of the electrostatic protection structure D113' has a plurality of light transmission parts TRP, wherein the plurality of light transmission parts TRP can be formed by a transparent conductive material (such as ITO), and are sequentially and spacedly arranged along the extension direction of the metal strip pattern, so that the electrostatic protection structure D113' forms a ring structure with a hole formed by the light transmission part TRP in appearance.

[0244] Through the design of the electrostatic protection structure D113', when the frame glue is cured, the UV light irradiated from the back of the substrate D111 can pass through the light transmission part TRP to irradiate the frame glue on the front of the substrate D111, thereby improving the curing rate of the frame glue, and thus improving the yield and reliability of the panel assembly. In addition, because the light transmission part TRP of the electrostatic protection structure D113' is formed by a transparent conductive material, the light transmission part TRP does not reduce the equivalent area of the metal strip pattern, so that the electrostatic dissipation capacity of the electrostatic protection structure can be maintained, and the electrostatic dissipation capacity will not be reduced due to the setting of the light transmission part TRP.

[0245] The design of the electrostatic protection structure D113' of the embodiment of the application is further illustrated below. FIG. 26A and FIG. 26B wherein FIG. 26A is a top view of the pixel array substrate D210 of the embodiment of the application, and FIG. 26B is a partial sectional view of the pixel array substrate D210 of the embodiment of the application.

[0246] Please refer to FIG. 26AThe pixel array substrate D210 of the present embodiment is similar to the pixel array substrate D110' of the previous embodiment. The pixel array substrate D210 comprises a substrate D211 and an electrostatic protection structure D213. The display region DR of the pixel array is arranged on the substrate D211. The non-display region SR of the substrate D211 is outside the display region DR. The non-display region SR can be divided into a frame region BA, a scan circuit fan-out region GFA, and a data circuit fan-out region DFA. The frame region BA is used for applying frame glue. The scan circuit fan-out region GFA is used to arrange a scan driving circuit (such as D120). The data circuit fan-out region DFA is used to arrange a data driving circuit (such as D130). The frame region BA includes a first frame region BA1 and a second frame region BA2 on opposite sides of the substrate D211, and a third frame region BA3 between the first frame region BA1 and the second frame region BA2.

[0247] In the present embodiment, the electrostatic protection structure D213 comprises a first metal strip pattern MSP1, a second metal strip pattern MSP2, and a third metal strip pattern MSP3. The first metal strip pattern MSP1 is arranged in the first frame region BA1. The second metal strip pattern MSP2 is arranged in the second frame region BA2. The third metal strip pattern MSP3 is arranged in the third frame region BA3.

[0248] Specifically, the first metal strip pattern MSP1, the second metal strip pattern MSP2, and the third metal strip pattern MSP3 are electrically connected to each other to form a metal pattern surrounding the first to third frame regions BA1-BA3. In the present embodiment, the first metal strip pattern MSP1, the second metal strip pattern MSP2, and the third metal strip pattern MSP3 are formed continuously and integrally, but the present application is not limited thereto.

[0249] Please refer to FIG. 26A and FIG. 26B In the present embodiment, the electrostatic protection structure D213 is composed of a metal layer ML1, an insulating layer IL1, a transparent conductive layer TC, a metal layer ML2, and an insulating layer IL2 arranged in sequence, for forming the first to third metal strip patterns MSP1-MSP3.

[0250] For example, the cross-sectional structure of the first metal strip pattern MSP1 on the cutting line HH' is as follows: FIG. 26BAs shown, the electrostatic protection structure D213 has a porous structure in its metal layer ML1 and second metal layer ML2, so that the metal layers ML1 and ML2 form discontinuous island-like structures in their cross-sectional structure, wherein at least some of the island-like structures are arranged sequentially at approximately fixed intervals. The intervals between adjacent island-like structures form the porous structure.

[0251] It should be noted that although the cross-section at line HH' shows the island-like structures in metal layer ML1 / second metal layer ML2 as independent, these island-like structures are actually electrically connected to each other at different cross-sections, thus forming a perforated structure. This perforated structure corresponds to the shape of the light-transmitting portion TRP. FIG. 26A This application uses a rectangular hole as an example, but it is not limited to this.

[0252] Metal layer ML1 is formed on the first side of substrate D211 (with FIG. 26B On the direction shown (i.e., the upper side of the substrate), an insulating layer IL1 is formed and covers the metal layer ML1, and a transparent conductive layer TC is formed on the insulating layer IL1 and electrically connected to the second metal layer ML2. The spacer region (i.e., the hole structure) between the island structures in the metal layer ML1 and the second metal layer ML2, as well as the insulating layer IL1, the transparent conductive layer TC, and the insulating layer IL2 covering the spacer region, form the light-transmitting part TRP of the electrostatic protection structure D213.

[0253] During the manufacturing process of bonding the bezel of the display panel, the bezel adhesive FP is applied onto the insulating layer IL2, and UV light is emitted from the second side of the substrate D211 (with... FIG. 26B The direction shown is the direction from the bottom of the substrate towards the first side. At this time, UV light can irradiate from each light-transmitting part TRP in the electrostatic protection structure D213 to the frame adhesive FP, so that the frame adhesive FP will undergo a curing reaction in response to the UV light.

[0254] Compared to the traditional electrostatic discharge ring design, the electrostatic protection structure D213 in this embodiment has a higher UV light transmittance because it reduces the large area of ​​metal obstruction. This allows UV light to reach the frame adhesive FP coating area through the light-transmitting part TRP, thus better assisting the curing of the frame adhesive.

[0255] In some embodiments, metal layer ML1 and second metal layer ML2 may have different widths in the cross-sectional direction of the metal strip pattern (e.g., in the direction of the truncated line HH'). FIG. 26B As shown, in this embodiment, the metal layer ML1 has a first width W1 in the direction of the cut-off line HH', and the second metal layer ML2 has a second width W2 in the direction of the cut-off line HH', wherein the first width W1 is greater than the second width W2.

[0256] In some embodiments, the ratio of the second width W2 and the first width W1 (W2 / W1) can be, for example, between 1 / 2 and 2 / 3, but the present application is not limited thereto. In some embodiments, the first width W1 can be, for example, between 50 mm and 70 mm, preferably 60 mm; and the second width W2 can be, for example, between 30 mm and 50 mm, preferably 40 mm, but the present application is not limited thereto.

[0257] More specifically, the part of the electrostatic protection structure D213 having the two metal layer ML1 and ML2 structure can be referred to as the inner ring structure ER1, and the part of the electrostatic protection structure D213 having only the single metal layer ML1 structure can be referred to as the outer ring structure ER2. The first width W1 described above is the width of the inner ring structure ER1 plus the width of the outer ring structure ER2, and the second width W2 described above is the width of the inner ring structure ER1.

[0258] Compared with the conventional electrostatic discharge ring design, the electrostatic protection structure D213 having the inner ring structure ER1 and the outer ring structure ER2 has a greater width in the cross-sectional direction, i.e., the outer ring structure ER2 extends closer to the edge of the substrate D211. In this way, the effective conductive area of the electrostatic protection structure D213 can be increased, so that the electrostatic dissipation capability is further improved.

[0259] On the other hand, in some embodiments, within the region of the first metal strip pattern MSP1 / second metal strip pattern MSP2 / third metal strip pattern MSP3, the metal layer ML1 and the second metal layer ML2 are electrically independent of each other, i.e., are isolated by the insulating layer IL1, wherein the metal layer ML1, the second metal layer ML2 and the transparent conductive layer TC are only electrically connected together at the bridge region BR of the electrostatic protection structure D213.

[0260] In other words, the inner ring structure ER1 (mainly composed of the metal layer ML1, the transparent conductive layer TC and the second metal layer ML2) and the outer ring structure ER2 (mainly composed of the metal layer ML1) of the electrostatic protection structure D213 are only electrically connected through the bridge region BR located below the substrate D211. In this way, when the pixel array substrate D210 is cut, even if the outer ring structure ER2 is damaged by the cutting wheel due to cutting errors, the electrostatic protection structure D213 will still have the inner ring structure ER1 to maintain a certain electrostatic dissipation capability, thereby reducing the risk of cutting wheel damaging the electrostatic protection capability of the panel.

[0261] FIGS. 27A-27C FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present application. Please refer to FIG. 1 first. FIG. 27AIn the display panel D300 of the present embodiment, each pixel unit Pu can correspond to a light emitting element LED, which can be, for example, a white light emitting diode or a blue light emitting diode, without being limited thereto. The light emitting element LED can be a mini-LED, a micro-LED, or an OLED, without being limited thereto. In other embodiments, the light emitting element LED can also be of other sizes and / or kinds. Depending on the type of light emitting element selected, the display panel D300 can be, for example, a ULED panel, a mini-LED panel, a micro-LED panel, or an OLED panel, without being limited thereto.

[0262] In some embodiments, each pixel unit Pu can include a plurality of sub-pixels, such as a first sub-pixel R, a second sub-pixel G, and a third sub-pixel B. The first sub-pixel R, the second sub-pixel G, and the third sub-pixel B are respectively controlled to emit light having different wavelengths. For example, the first sub-pixel R can include a light emitting element having a red light wavelength range (e.g., 610 μm ~ 720 μm), the second sub-pixel G can include a light emitting element having a green light wavelength range (e.g., 520 μm ~ 610 μm), and the third sub-pixel B can include a light emitting element having a blue light wavelength range (e.g., 400 μm ~ 520 μm). In some embodiments, the light emitting elements of the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B can respectively be a red light emitting diode (or can be said to be a light emitting diode having a light emitting wavelength in the red light section), a green light emitting diode (or can be said to be a light emitting diode having a light emitting wavelength in the green light section), and a blue light emitting diode (or can be said to be a light emitting diode having a light emitting wavelength in the blue light section). Similarly, the light emitting elements of the sub-pixels R / G / B can be mini-LEDs or micro-LEDs, without being limited thereto.

[0263] Please refer to FIG. 27B wherein FIG. 27BThis is a schematic cross-sectional view of the display panel D100 along section II'. In this embodiment, the display panel D300 includes light-emitting elements LED1~LED3, a substrate D111, a metal layer ML3, a protective layer PL, a metal layer ML4, a sealing layer SL, a circuit layer WL, a bonding portion AD, and an isolation layer CDL. The metal layer ML3 includes first electrode regions 1121, 1122, and 1123 formed on the substrate D111, wherein each electrode region 1121~1123 is electrically connected to each other through the corresponding circuit layer WL. The light-emitting elements LED1~LED3 are respectively disposed on the first electrode regions 1121~1123 of the metal layer ML3, wherein each light-emitting element LED has two electrodes, which are located on opposite sides of the light-emitting elements LED1~LED3. The electrode (or lower electrode) of each light-emitting element LED1~LED3 on the side (or lower side) closer to the metal layer ML1 is electrically connected to the corresponding first electrode region 1121~1123 through the bonding portion AD. A protective layer PL fills the spaces between light-emitting elements LED1 to LED3 and covers at least a portion of the surface of each LED1 to LED3 to prevent unintended short circuits between the LED1 to LED3. The protective layer PL exposes at least the electrode (or upper electrode) on the other side of each LED1 to LED3 (i.e., the side away from the metal layer ML3, or the upper side). A metal layer ML4 is disposed on the protective layer PL and electrically connected to the upper electrode of the LED1 to LED3. The LEDs can receive drive signals controlling their illumination through the metal layers ML3 and ML4. A sealing layer SL is formed and covers the metal layer ML4.

[0264] Specifically, in FIG. 27B In the embodiment, the light-emitting elements LED1~LED3 can be, for example, vertically packaged light-emitting diodes, wherein the electrodes of each light-emitting diode are disposed on opposite sides, so that the driving signal can be received through the metal layers ML3 and ML4 located on both sides of the light-emitting elements LED1~LED3.

[0265] In short, in the display panel 100 configuration of this embodiment, the first electrode regions 1121-1123 of the metal layer ML3 can be respectively regarded as the lower electrodes (hereinafter referred to as lower electrodes 1121-1123) of the light-emitting elements LED1-LED3, and the metal layer ML4, which is connected to each light-emitting element LED1-LED3, can be regarded as the upper electrode (hereinafter referred to as upper electrode ML4) of the light-emitting elements LED1-LED3. Therefore, the driver chip 140 can provide signals through the upper electrode ML2 and the corresponding lower electrodes 1121-1123 of the light-emitting elements LED1-LED3 to control the lighting state of the light-emitting elements LED1-LED3.

[0266] In adopting suchFIG. 27A and FIG. 27B In the display panel D300 with vertically packaged light-emitting elements, to achieve an in-cell embedded touch design, the upper and lower electrodes of each pixel unit Pu need to be used as touch electrodes to sense capacitance changes during touch. In other words, the display panel D300 needs to share upper and lower electrodes to achieve display and touch functions respectively. To achieve electrode sharing, each driving cycle of the display panel D300 needs to be further divided into a display period and a touch sensing period, such as... FIG. 31 As shown.

[0267] In this embodiment, the display panel D300 enters the display period in response to the reset signal RST. During the display period, the driver chip 140 provides display scan signals GLs through the upper and lower electrodes to sequentially control the illumination state of the pixel units Pu, thereby realizing the display of the screen on the display panel 100. After the display period ends, the display panel 100 enters the touch sensing period in response to the control signal EM (which can also be regarded as the display blank period within the driving cycle). During the touch sensing period, each pixel unit Pu can be regarded as a touch sensing unit, used to receive the touch scan signal TX issued by the touch sensing chip (not shown) and to send back the sensing signal associated with the electrical changes of the display panel D300 to the touch sensing chip, thereby determining whether a touch behavior has occurred.

[0268] Under the aforementioned control method, the D300 display panel needs to periodically switch between display and touch sensing periods. This necessitates a trade-off between pixel charging time and touch sensing time, creating difficulties in drive timing design. Furthermore, increasing the D300 display panel's frame rate per second (FPS) inevitably leads to a decrease in touch sensing sensitivity due to the reduced display blanking time.

[0269] Secondly, in the manufacturing process of touch display panels using vertically packaged LED1~LED3 light-emitting elements, due to the differences in the actual size and arrangement of each LED, the position of the upper electrode of each LED will vary, and they will not be on the same plane. For example... FIG. 27C As shown, where FIG. 27C This is a schematic diagram of the cross-sectional structure of the display panel D300 along the cut line JJ'.

[0270] Please refer to FIG. 27C ,exist FIG. 27CThe left side of the light emitting element LED1 is an ideal state of configuration, that is, when the light emitting element LED1 is disposed on the substrate D111 through the bonding portion AD and connected with the first electrode area 1211 (or can be referred to as the lower electrode lead), the height H1 of both the bonding portion AD and the light emitting element LED1 (i.e., the shortest distance from the upper side surface of the first electrode area 1121 to the top of the light emitting element LED1) is exactly the same as the height of the protective layer PL, so that the upper electrode of the light emitting element LED1 is exposed and located at a position that is approximately flush with the upper edge of the protective layer PL (i.e., the upper electrode and the upper side of the protective layer PL are approximately located in the same plane). Therefore, in the ideal state, the metal layer ML4 formed on the protective layer PL can be easily and electrically connected with the exposed upper electrode, and the metal layer ML4 on the upper electrode area of the light emitting element LED1 can still have a uniform line width to ensure the transmission of electrical signals.

[0271] The light emitting elements LED2 and LED3 are the configuration states that can often occur in actual situations. In the configuration of the light emitting element LED2, the height of the light emitting element LED2 and the corresponding bonding portion AD is slightly less than the height of the light emitting element LED1 and its bonding portion AD, causing the height H2 of the bonding portion AD and the light emitting element LED2 as a whole to be less than the height of the protective layer PL (i.e., approximately the height H1), so that the protective layer PL will cover the upper electrode of the light emitting element LED2 when formed. In this way, because the upper electrode of the light emitting element LED2 is covered by the protective layer PL, the metal layer ML4 cannot effectively electrically connect to the upper electrode of the light emitting element LED2, so that the light emitting element LED2 cannot receive the driving signal to light up. The configuration state of the light emitting element LED2 can be considered as a configuration that is too low.

[0272] In the configuration of the light emitting element LED3, the height of the light emitting element LED3 is slightly greater than the height of the light emitting element LED1, causing the height H3 of the bonding portion AD and the light emitting element LED3 as a whole to be greater than the height of the protective layer PL (i.e., approximately the height H1), so that the upper side of the light emitting element LED3 will exceed the upper side surface of the protective layer PL, and the upper electrode of the light emitting element LED3 and the upper side surface of the protective layer PL are not in the same plane. In this way, when the metal layer ML4 is formed on the protective layer PL, because the upper electrode of the light emitting element LED is higher than the upper side surface of the protective layer PL, the metal layer ML4 needs to be bent to extend to the upper electrode of the light emitting element LED3 and be electrically connected therewith, and the line width (herein refers to the width of the metal layer ML4 in the x-z plane) at the bending portion is thin, which is easy to cause the lead to break, so that the electrical signal cannot be normally transmitted. The configuration state of the light emitting element LED3 can be considered as a configuration that is too high.

[0273] As known from the above, in the structure configuration of a general display panel, the thickness of the light emitting elements LED1-LED3 will be different in actual manufacturing, and the corresponding bonding portions AD can also form different thicknesses / heights in the manufacturing process. The differences in various manufacturing processes and materials will accumulate when the display panel 100 is packaged, resulting in different heights (such as H1-H3) of the upper electrodes of the light emitting elements LED1-LED3, and thus the above-mentioned connection failure can occur when the metal layer ML4 is formed / set.

[0274] To solve the above problems, the present application proposes various new structure designs of display panels, such as FIGS. 28A-30G as shown, wherein FIGS. 28A-29B The design of the embodiment can form independent electrodes in the display panel for touch sensing, so that the signal timing during display and during touch sensing can be independent of each other, avoiding the need to make a trade-off, thereby achieving the effects of cost saving and reducing touch signal processing complexity, FIGS. 30A-30G The design of the embodiment can be used to achieve the effect of flattening the surface of the display panel.

[0275] Please refer to FIG. 28A and FIG. 28B The display panel D400 of the embodiment includes a plurality of pixel units Pu arranged in an array, wherein each pixel unit Pu includes a display unit Du and a touch sensing unit Tc, and each display unit Du has a light emitting element (such as LED1-LED3). As seen from the cross-sectional structure of the section line II' of FIG. 28B The display panel D400 includes light emitting elements LED1-LED3, a substrate D111, a metal layer ML3, a protective layer PL, a metal layer ML4, a sealing layer SL, a wiring layer WL, a bonding portion AD, and an isolation layer CDL. The metal layer ML3 includes first electrode regions 2121, 2122, and 2123 and second electrode regions 2124 and 2125 formed on the substrate D111, wherein each first electrode region 2121-2123 is electrically connected to each other through the corresponding wiring layer WL, and the second electrode regions 2124 and 2125 are electrically independent of the first electrode regions 2121-2123. From the perspective of structure configuration, the first electrode regions 2121-2123 and the second electrode regions 2124 and 2125 are alternately arranged with intervals, that is, the second electrode regions 2124 and 2125 are arranged between every two adjacent first electrode regions 2121-2123. For example, the second electrode region 2124 is arranged between the first electrode regions 2121 and 2122, and the second electrode region 2125 is arranged between the first electrode regions 2122 and 2123.

[0276] The light emitting elements LED1-LED3 are respectively disposed on the first electrode regions 2121-2123 of the metal layer ML3, wherein each of the light emitting elements LED1-LED3 has two electrodes located on opposite sides of the light emitting element LED1-LED3. The electrode (or lower electrode or first electrode) of each of the light emitting elements LED1-LED3 close to the metal layer ML3 (or lower side) is electrically connected to the corresponding first electrode region 2121-2123.

[0277] The protection layer PL fills between the light emitting elements LED1-LED3 and covers at least part of the surface of each of the light emitting elements LED1-LED3, for avoiding unintended short circuit between the light emitting elements LED1-LED3, wherein the protection layer PL exposes the electrode (or upper electrode or second electrode) of each of the light emitting elements LED1-LED3 on the other side (i.e. the side away from the first metal layer 212, or upper side).

[0278] The metal layer ML4 includes third electrode regions 2141, 2142 and 2143 and fourth electrode regions 2144 and 2145 formed on the protection layer PL, wherein the third electrode regions 2141-2143 are respectively electrically connected to the upper electrode of the corresponding light emitting element LED1-LED3. In other words, the first electrode region 2121 and the third electrode region 2141 can serve as the upper and lower electrodes of the light emitting element LED1 to receive a driving signal, the first electrode region 2122 and the third electrode region 2142 can serve as the upper and lower electrodes of the light emitting element LED2 to receive a driving signal, and the first electrode region 2123 and the third electrode region 2143 can serve as the upper and lower electrodes of the light emitting element LED3 to receive a driving signal.

[0279] In the present embodiment, the protection layer PL forms a through hole THL on the region corresponding to the second electrode regions 2124 and 2125, so that the fourth electrode regions 2144 and 2145 of the second metal layer 214 have a second part extending through the through hole THL to be electrically connected to the second electrode regions 2124 and 2125 in addition to a first part spaced apart from the third electrode regions 2141-2143 and formed on the upper side of the protection layer 213.

[0280] Specifically, taking the corresponding configuration of the light emitting element LED1 as an example, the substrate D111 part configured by the light emitting element LED1 and the first electrode region 2121 and the third electrode region 2141 electrically connected to the light emitting element LED1 constitute a display unit Du. The second electrode region 2124 and the fourth electrode region 2144 constitute a touch sensing unit Tc adjacent to the display unit Du where the light emitting element LED1 is located on the cross line II'. The structure configuration of the corresponding display unit Du and touch sensing unit Tc will be formed in each pixel unit Pu.

[0281] On the other hand, from FIG. 28A In some embodiments, the display panel D400 is configured as shown in FIG. 12. In the top view of the display panel D400, the display panel D400 is configured as an example of 12 rows of pixel units Pu (the present application is not limited thereto). Each touch sensing unit Tc is electrically connected to the touch sensing chip via a corresponding touch scan line TX1-TXn. In some embodiments, adjacent touch scan lines TX1-TXn have different connection configurations, and each x touch scan lines TX1-TXn can have a repeated connection configuration, where x is a natural number. For example, the touch scan line TX1 is electrically connected to 8 touch sensing units Tc in the 9th to 12th rows of the right 2 columns of the display panel D400; the touch scan line TX2 is electrically connected to 12 touch sensing units Tc in the 5th to 8th rows of the right 3 columns of the display panel D400 and 4 touch sensing units Tc in the 9th to 12th rows of the right 3 columns of the display panel D400 (i.e., 16 touch sensing units Tc in the 5th to 12th rows of the right 3 columns of the display panel D400, in addition to the 8 touch sensing units Tc connected to the touch scan line TX1); and the touch scan line TX3 is electrically connected to 16 touch sensing units Tc in the 1st to 4th rows of the right 4 columns of the display panel D400 and 8 touch sensing units Tc in the 5th to 12th rows of the right 4 columns of the display panel D400 (i.e., 24 touch sensing units Tc in the 5th to 12th rows of the right 4 columns of the display panel D400, in addition to the 8 touch sensing units Tc connected to the touch scan line TX1 and the 16 touch sensing units Tc connected to the touch scan line TX2). The arrangement of other regions can be similarly derived, and is not repeated here.

[0282] More specifically, the cross-sectional structure of the display panel D400 on the cutting line II' of the present embodiment is substantially the same as that of the display panel D400 of the first embodiment. FIG. 27A and FIG. 27B The main difference between the present embodiment and the foregoing embodiments is that the present embodiment adds second electrode regions 2124 and 2125 in the first metal layer 212, which are electrically independent of the lower electrodes of the light emitting elements LED1-LED3, and that the fourth electrode regions 2144 and 2145, which are electrically independent of the upper electrodes of the light emitting elements LED1-LED3, are cut out of the metal layer ML4 of the present embodiment, compared to the metal layer ML4 of the foregoing embodiments. The second electrode region 2124 and the fourth electrode region 2144, which are electrically connected to each other, form a touch electrode in one touch sensing unit Tc, and the second electrode region 2125 and the fourth electrode region 2145, which are electrically connected to each other, form a touch electrode in another touch sensing unit Tc. In other words, the present embodiment forms touch sensing units Tc that do not affect each other by the arrangement of the second electrode regions 2124 and 2125 and the fourth electrode regions 2144 and 2145.

[0283] Therefore, under the architecture of the display panel D400 of the present embodiment, the display unit Du and the touch control sensing unit Tc can be controlled to perform display and touch control sensing respectively through the corresponding scan lines, without having to trade off the time length of display and touch control sensing in each driving cycle, so that the design difficulty of the control timing can be effectively reduced, and the sensitivity of touch control sensing can not be reduced with the picture update rate.

[0284] In some embodiments, the first electrode regions 2121~2123 may, for example, be square regions with a side length of about 10 μm, and the spacing between adjacent first electrode regions is about 25 μm, as viewed from the top structure. In other words, the side length of the second electrode regions 2124 and 2125 and the fourth electrode regions 2144 and 2145 is between 10 μm and 25 μm, but the present application is not limited thereto.

[0285] Please refer to FIG. 29A and FIG. 29B The display panel D500 of the present embodiment comprises a plurality of pixel units Pu arranged in an array, wherein each pixel unit Pu comprises a display unit Du and a touch control sensing unit Tc, and each display unit Du has light emitting elements (such as LEDs 1~3). As viewed from the cross-sectional structure of the cross-section II’ of FIG. 29B The display panel D500 comprises light emitting elements LEDs 1~3, a substrate 311, a metal layer ML3, a protective layer PL, a metal layer ML4, a sealing layer SL, a wiring layer WL, a bonding portion AD and an isolation layer CDL. The metal layer ML3 comprises first electrode regions 3121, 3122 and 3123 and second electrode regions 3124 and 3125 formed on the substrate 311, wherein each first electrode region 3121~3123 is electrically connected to each other through the corresponding wiring layer WL, and the second electrode regions 3124 and 3125 are electrically independent of the first electrode regions 3121~3123.

[0286] Specifically, the display panel D500 of the present embodiment is similar to the aforementioned FIG. 28A and FIG. 28BThe structural configuration of the display panel D400 of the embodiment is substantially the same, and the main difference is that in the metal layer ML4 of the display panel D500 of the embodiment, the metal layer adjacent to the third electrode regions 3141~3143 is removed, so that the second electrode regions 3124 and 3125 of the metal layer ML3 originally located on the lower side are not shielded by the metal layer ML4 on the upper side. Therefore, when the user's finger touches the corresponding position of the display panel D500, the finger capacitance can be directly coupled to the second electrode regions 3124 and 3125 of the metal layer ML3, and then detected. In other words, the main structural difference between the display panel D500 of the embodiment and the display panel D400 of the foregoing embodiment is that the metal layer ML4 of the embodiment does not include fourth electrode regions (such as 2144 and 2145) electrically connected to the second electrode regions 3124 and 3125, and therefore the through hole THL structure similar to FIG. 28B is not required to be formed on the protective layer PL. Other similar parts can be referred to the description of the foregoing embodiments, which will not be repeated here.

[0287] Overall, FIGS. 28A-29B The embodiments of the foregoing display panels respectively teach that by adding independent electrode regions (i.e., second electrode regions 2124 / 2125 / 3124 / 3125) on the metal layer ML3 and dividing the metal layer ML4 configuration, the independent touch electrode architecture is easily realized. In the architecture of the embodiments, the third electrode regions 2141~2143 / 3141~3143 used as the upper electrode do not shield the regions of the touch sensing unit Tc, so that the capacitance change caused by the touch panel can be coupled to the second electrode region on the lower side. In other words, in the embodiments, the orthographic projection region of the third electrode regions 2141~2143 / 3141~3143 on the substrate D111 does not completely overlap with the orthographic projection region of the second electrode regions 2124 / 2125 / 3124 / 3125 on the substrate 211 / 311 (i.e., at least partially not overlapping). In some embodiments, the orthographic projection region of the third electrode regions 2141~2143 / 3141~3143 on the substrate D111 does not completely overlap with the orthographic projection region of the second electrode regions 2124 / 2125 / 3124 / 3125 on the substrate D111.

[0288] FIGS. 30A-30GThis is a cross-sectional structural diagram of a display panel according to different embodiments of this application. In some embodiments, the protective layer of the display panel is designed to be thicker than the height of the light-emitting elements and their corresponding lower electrode wires and junctions, so that the upper surface of the protective layer is higher than the upper electrode of each light-emitting element. Then, by using a specific fabrication process (e.g., photolithography), the upper electrode covered by the protective layer can be exposed, and an opening is formed between the upper electrode of each light-emitting element and the protective layer. Thus, the upper electrode wires can be electrically connected to the upper electrode within the opening through this opening, thereby achieving a planarized display panel structure (e.g., ...). FIGS. 30A-30F (Example). In another embodiment, the light-emitting elements are subjected to a force toward the substrate during the installation process, wherein the light-emitting elements undergo different displacements due to their individual dimensions / heights, resulting in different substrate spacings, thereby keeping the upper electrodes of the light-emitting elements on the same plane. Thus, the display panel can form a flat surface to facilitate the installation of the upper electrode wires and electrical connections with each light-emitting element, thereby achieving a planarized display panel structure (e.g., FIG. 30G (Example). The following sections will discuss... FIGS. 30A-30G The structure of the embodiment will be described.

[0289] Please refer to the following first. FIG. 30A The display panel D600a of this embodiment includes a substrate D111, a metal layer ML3, a plurality of light-emitting elements LED1~LED3, a metal layer ML4, and a light-shielding portion 415. The metal layer ML3 is disposed on the substrate D111. The light-emitting elements LED1~LED3 are respectively disposed on the metal layer ML3 through corresponding bonding portions AD, so that the lower electrodes of the light-emitting elements LED1~LED3 are electrically connected to the metal layer ML3 through the bonding portions AD. A protective layer PL is formed on the substrate D111 and covers the metal layer ML3, the bonding portions AD, and the peripheral area of ​​the light-emitting elements LED1~LED3, in order to avoid unintended short circuits between adjacent light-emitting elements LED1~LED3. The protective layer PL exposes at least part or all of the upper electrodes of the light-emitting elements LED1~LED3, and the height / thickness of the protective layer PL formed on the substrate D111 is greater than or equal to the height H1~H3 corresponding to any light-emitting element LED1~LED3, so as to form an opening OP on at least one or more of the light-emitting elements LED1~LED3. The heights H1 to H3 of any light-emitting element LED1 to LED3 referred to herein can be, for example, the sum of the heights / thicknesses of any light-emitting element LED1 to LED3, its corresponding metal layer ML3, and the junction AD. The metal layer ML4 is disposed on the protective layer PL and extends toward the opening OP to be electrically connected to the upper electrode of each light-emitting element LED1 to LED3 through the opening OP.

[0290] More specifically, the metal layer ML3 includes the lower electrode wires 4121~4123, and the metal layer ML4 includes the upper electrode wires 4141~4143. The lower electrodes of the light emitting elements LED1~LED3 are electrically connected to the lower electrode wires 4121~4123 through the corresponding bonding parts AD, respectively, and the upper electrodes of the light emitting elements LED1~LED3 are electrically connected to the upper electrode wires 4141~4143 in the corresponding openings OP, respectively. Through the above configuration, the light emitting elements LED1~LED3 with different heights H1~H3 can all achieve a better electrical connection effect through the upper electrode wires 4141~4143 extending to the openings OP, and will not produce the connection failure situation as FIG. 27C described above due to the light emitting elements being in a too low configuration (such as LED2) or a too high configuration (such as LED3). In addition, since the height difference of each light emitting element LED1~LED3 can be compensated to the same height by the upper electrode wires 4141~4143 extending to the openings, the overall upper electrode wire 4141 (including the part of the line segment located on the upper surface of the protective layer PL) can have a uniform line width. In this way, the transmission of electrical signals can be ensured, and the manufacturing process risks such as disconnection and poor contact caused by bending the wire can also be avoided.

[0291] In other words, through the above FIG. 30A structural configuration, the upper surfaces of all the light emitting elements LED1~LED3 can basically be maintained at the same level, without height differences, so that the subsequent manufacturing process will not be affected by the flatness of the display panel, thereby effectively improving the manufacturing process yield and reliability.

[0292] In the present embodiment, the substrate D111 can be a flexible or rigid substrate such as a printed circuit board, a glass substrate, or a thin film substrate, and the substrate D111 can be transparent or opaque according to the selected material and the required application type, without being limited thereto.

[0293] In some embodiments, the material of the bonding part AD can be any material that can provide adhesion to stably bond the light emitting elements LED1~LED3 and the metal layer ML3, such as a tin paste, an anisotropic conductive film (ACF), or other adhesive materials. In addition, the bonding process of placing the light emitting elements LED1~LED3 on the metal layer ML3 through the bonding part AD can be implemented in a screen printing bonding, inkjet printing (IJP) bonding, or exposure development baking manner, without being limited thereto.

[0294] Please refer to FIG. 30B , the display panel D600b of the present embodiment and FIG. 30AThe embodiment is substantially the same as the above-mentioned embodiment, and includes the substrate D111, the metal layer ML3, the plurality of light emitting elements LED1-LED3, the metal layer ML4, and the light shielding portion 415. The descriptions of the related elements / configurations can refer to the above-mentioned embodiment. FIG. 30A The embodiment is substantially the same as the above-mentioned embodiment, and will not be repeated here.

[0295] The main difference between the embodiment and the above-mentioned embodiment is that the display panel D600b further includes a conductive extension 416. The conductive extension 416 is disposed in the opening OP corresponding to the light emitting element LED2, and is electrically connected to the upper electrode of the light emitting element LED2, wherein the height of the conductive extension 416 is less than or equal to the depth of the opening OP of the light emitting element LED2, and the upper electrode lead wire 4142 is electrically connected to the upper electrode of the light emitting element LED2 through the conductive extension 416. FIG. 30A Specifically, the light emitting element LED2 of the embodiment is in a configuration with a too low height (H2

[0296] It should be noted that the conductive extension 416 of the embodiment can be disposed only in the opening of the light emitting element with a too low height, and other light emitting elements that can be directly connected to the upper electrode lead wire do not need to have similar configurations.

[0297] Please refer to

[0298] The display panel D600c of the embodiment is substantially the same as the above-mentioned embodiment, and includes the substrate D111, the metal layer ML3, the plurality of light emitting elements LED1-LED3, the metal layer ML4, and the light shielding portion 415. The descriptions of the related elements / configurations can refer to the above-mentioned embodiment. FIG. 30C The main difference between the embodiment and the above-mentioned embodiment is that the display panel D600c includes a plurality of conductive extensions 4161-4163 corresponding to the light emitting elements LED1-LED3, respectively, wherein the conductive extensions 4161-4163 are disposed in the openings OP of the light emitting elements LED1-LED3, respectively, and are electrically connected to the upper electrodes of the corresponding light emitting elements LED1-LED3, respectively. FIG. 30A FIG. 30B The main difference between the embodiment and the above-mentioned embodiment is that the display panel D600c includes a plurality of conductive extensions 4161-4163 corresponding to the light emitting elements LED1-LED3, respectively, wherein the conductive extensions 4161-4163 are disposed in the openings OP of the light emitting elements LED1-LED3, respectively, and are electrically connected to the upper electrodes of the corresponding light emitting elements LED1-LED3, respectively. FIG. 30A FIG. 30B The embodiment is substantially the same as the above-mentioned embodiment, and will not be repeated here.

[0299] The main difference between the embodiment and the above-mentioned embodiment is that the display panel D600c includes a plurality of conductive extensions 4161-4163 corresponding to the light emitting elements LED1-LED3, respectively, wherein the conductive extensions 4161-4163 are disposed in the openings OP of the light emitting elements LED1-LED3, respectively, and are electrically connected to the upper electrodes of the corresponding light emitting elements LED1-LED3, respectively. FIG. 30B

[0300] ​​​In the present embodiment, each conductive extension 4161-4163 fills the corresponding opening CP, such that the upper side surface of the conductive extension 4161-4163 and the upper side surface of the protective layer are substantially in the same plane. In other words, the height H1-H3 of each light emitting element LED1-LED3 plus the height of the corresponding conductive extension 4161-4163 is equal to the height of the protective layer PL.

[0301] It is noted that the conductive extensions 4161-4163 of the present embodiment can be disposed in the opening OP of each light emitting element LED1-LED3, such that the equivalent height of each light emitting element LED1-LED3 is equal to the height of the protective layer PL. In this way, the upper electrode wires 4141-4143 formed on the protective layer PL can extend horizontally to connect to the conductive extensions 4161-4163, and electrically connect the upper electrode of the corresponding light emitting element LED1-LED3 through the conductive extensions 4161-4163. Therefore, the upper electrode wires 4141-4143 of the present embodiment can maintain a uniform line width to achieve better electrical signal transmission characteristics.

[0302] It is noted that the display panel D600d of the present embodiment is substantially the same as the display panel D600a of the above-mentioned FIG. 30D embodiment, which includes a substrate D111, a metal layer ML3, a plurality of light emitting elements LED1-LED3, a metal layer ML4, and a light shielding portion 415. The descriptions of the related elements / configurations can refer to the above-mentioned FIG. 30A embodiment, which will not be repeated here. FIG. 30A

[0303] The main difference between the present embodiment and the above-mentioned FIG. 30A embodiment is that the protective layer PL of the display panel D600d includes a spacing portion 4131 and a flat portion 4132. The spacing portion 4131 is disposed on the substrate D111 and covers the metal layer ML3, the bonding portion AD, and part of the light emitting elements LED1-LED3. The flat portion 4132 is disposed on the spacing portion and covers another part of the light emitting elements LED1-LED3 and exposes the upper electrode of the light emitting elements LED1-LED3. The sum of the heights of the spacing portion 4131 and the flat portion 4132 (i.e., the height of the protective layer PL) of the present embodiment is set to be greater than or equal to the maximum height among the light emitting elements LED1-LED3, so as to form an opening OP on at least one or part of the light emitting elements LED1-LED3. The metal layer ML4 is disposed on the flat portion 4132 and electrically connected to the light emitting elements LED1-LED3 through the opening OP.

[0304] Specifically, compared to the above-mentioned FIG. 30A ​In an embodiment, the protective layer PL of the present embodiment can be implemented using a two-layer structure, in which the lower layer structure (the spacer portion 4131) mainly provides the characteristics of insulation and support, while the upper layer structure (the planar portion 4132) mainly provides a planar upper surface, and is selected to be a material that can be removed based on a specific manufacturing process, so that the upper electrodes of the light emitting elements LED1-LED3 can be exposed after being processed by the removal manufacturing process. Therefore, by FIG. 30D the surface flatness of the display panel D600d can be further improved.

[0305] In some embodiments, the spacer portion 4131 can be implemented using a material having filling and insulating properties, such as silicon nitride (SiNx), silicon oxide (SiOx), acrylic, epoxy, or a silicon-based high-molecular organic polymer, without being limited thereto. On the other hand, the planar portion 4132 can be implemented using a material having a good surface flatness after coating, such as acrylic, epoxy, or a silicon-based high-molecular organic polymer, without being limited thereto.

[0306] Please refer to FIG. 30E , the display panel D600e of the present embodiment is substantially the same as the display panel D600a of the FIG. 30B and FIG. 30D embodiments, which includes the substrate D111, the metal layer ML3, the plurality of light emitting elements LED1-LED3, the metal layer ML4, the light shielding portion 415, and the conductive extension portion 416. The descriptions of the related elements / configurations can be referred to the descriptions of the FIG. 30B and FIG. 30D embodiments, which will not be repeated here.

[0307] The main difference between the present embodiment and the foregoing FIG. 30B embodiment is that the protective layer PL of the display panel D600e is configured using a two-layer structure as shown in FIG. 30D , which includes the spacer portion 4131 and the planar portion 4132. The descriptions of the related configurations and materials of the spacer portion 4131 and the planar portion 4132 can be referred to the descriptions of the FIG. 30D embodiment, which will not be repeated here.

[0308] Please refer to FIG. 30F , the display panel D600f of the present embodiment is substantially the same as the display panel D600b of the FIG. 30C and FIG. 30D embodiments, which includes the substrate D111, the metal layer ML3, the plurality of light emitting elements LED1-LED3, the metal layer ML4, the light shielding portion 415, and the plurality of conductive extension portions 4161-4163. The descriptions of the related elements / configurations can be referred to the descriptions of the FIG. 30C and FIG. 30D embodiments, which will not be repeated here.

[0309] This embodiment is the same as the aforementioned FIG. 30C The main difference in the embodiments is that the protective layer PL of the display panel D600f is adopted as follows: FIG. 30D The double-layer structure configuration includes a spacer portion 4131 and a leveling portion 4132. Details regarding the configuration and materials of the spacer portion 4131 and the leveling portion 4132 can be found above. FIG. 30D Examples are not repeated here.

[0310] FIG. 30G A cross-sectional structural diagram of a display panel according to an embodiment of this application. Please refer to... FIG. 30G The display panel D700 of this embodiment includes a substrate D111, a metal layer ML3, a plurality of light-emitting elements LED1~LED3, a protective layer PL, a metal layer ML4, a light-shielding portion 515, and a support portion 516. The metal layer ML3 is disposed on the substrate D111. The light-emitting elements LED1~LED3 are respectively disposed on the metal layer ML3 through corresponding bonding portions AD, so that the lower electrodes of the light-emitting elements LED1~LED3 are electrically connected to the metal layer ML3 through the bonding portions AD. The protective layer PL is formed on the substrate D111 and covers the metal layer ML3, the bonding portions AD, and the peripheral area of ​​the light-emitting elements LED1~LED3, to prevent unintended short circuits between adjacent light-emitting elements LED1~LED3. The protective layer PL exposes at least part or all of the upper electrodes of the light-emitting elements LED1~LED3, and the height / thickness of the protective layer PL formed on the substrate D111 is approximately equal to the height HL corresponding to the light-emitting elements LED1~LED3. The height HL corresponding to any light-emitting element LED1~LED3 referred to herein may, for example, be the sum of the height / thickness of any light-emitting element LED1~LED3 and its corresponding metal layer ML3 and bonding portion AD. Metal layer ML4 and light-shielding portion 515 are disposed on the protective layer PL and the upper electrode of light-emitting elements LED1~LED3, wherein metal layer ML4 is electrically connected to the upper electrode of each light-emitting element LED1~LED3. Furthermore, in the protective layer PL, a support portion 516 is disposed between adjacent light-emitting elements LED1~LED3. The support portion 516 is used to provide a supporting force to resist the applied force during the manufacturing process of applying force to light-emitting elements LED1~LED3, thereby defining the position of the upper electrode of light-emitting elements LED1~LED3, wherein the upper side of the support portion 516 and the upper electrode of light-emitting elements LED1~LED3 are approximately on the same plane. In this embodiment, the support portion 516 is, for example, columnar, and its height is less than or equal to the lowest of the light-emitting elements LED1~LED3, but this application is not limited thereto.

[0311] More specifically, metal layer ML3 includes lower electrode wires 5121-5123, and metal layer ML4 includes upper electrode wires 5141-5143. The lower electrodes of light-emitting elements LED1-LED3 are electrically connected to the lower electrode wires 5121-5123 via corresponding bonding portions AD. During the installation process, each light-emitting element LED1-LED3 is subjected to a planar force toward the substrate D111 to embed its lower electrode into the bonding portion AD. Due to differences in size / height, each light-emitting element LED1-LED3 has a different embedding depth in the bonding portion AD, resulting in corresponding differences in the distance between each light-emitting element LED1-LED3 and the substrate D111. For example, as... FIG. 30G As shown, the height H1 of light-emitting element LED1 is greater than the height H2 of light-emitting element LED2. Therefore, after a force is applied, the distance between light-emitting element LED1 and substrate D111 will be less than the distance between light-emitting element LED2 and substrate D111, so that the sum of the height H1 of light-emitting element LED1 and the corresponding distance between substrate D111 is approximately the same as the sum of the height H2 of light-emitting element LED2 and the corresponding distance between substrate D111, i.e., equal to the height HL. Similarly, the height H1 of light-emitting element LED1 is less than the height H3 of light-emitting element LED3. Therefore, after a force is applied, the distance between light-emitting element LED1 and substrate D111 will be greater than the distance between light-emitting element LED3 and substrate D111, so that the sum of the height H1 of light-emitting element LED1 and the corresponding distance between substrate D111 is approximately the same as the sum of the height H3 of light-emitting element LED3 and the corresponding distance between substrate D111.

[0312] With the above configuration, the light-emitting elements LED1 to LED3, which have different heights H1 to H3, will have different substrate spacings, so that the total height HL of each light-emitting element LED1 to LED3 is approximately the same, thereby forming a flat surface on the display panel. This prevents issues such as the light-emitting element being positioned too low (e.g., LED2) or too high (e.g., LED3) from causing problems. FIG. 27C The aforementioned connection failure situation. Furthermore, since the height differences H1~H3 of each light-emitting element LED1~LED3 have been compensated to the same height HL by the different substrate spacing, the electrode wires 5141~5143 can have a uniform linewidth overall. Therefore, the transmission of electrical signals can be guaranteed, while also avoiding manufacturing process risks such as wire breakage and poor contact caused by bending of the traces.

[0313] In other words, through the above FIG. 30GThe upper surfaces of all the light emitting elements LED1-LED3 can be substantially maintained at the same level without height difference, so that the subsequent manufacturing process is not affected by the flatness of the display panel, thereby effectively improving the manufacturing process yield and reliability.

[0314] In the embodiment, the substrate D111 can be a flexible or rigid substrate such as a printed circuit board, a glass substrate, or a thin film substrate, and can be transparent or opaque according to the selected material and the required application type, without being limited thereto.

[0315] In some embodiments, the material of the bonding portion AD can be any material capable of providing adhesion to stabilize the bonding of the light emitting elements LED1-LED3 and the metal layer ML3, such as a tin paste, an anisotropic conductive film (ACF), or the like. In addition, the bonding process of the light emitting elements LED1-LED3 to the metal layer ML3 through the bonding portion AD can be implemented by screen printing bonding, inkjet printing (IJP) bonding, or exposure development baking, without being limited thereto.

[0316] In summary, the display device and the display panel according to some embodiments of the present application can form independent electrodes in the display panel for touch sensing, so that the signal timing during display and during touch sensing can be independent of each other, avoiding the need to make a trade-off, thereby achieving the effects of cost savings and reducing the complexity of touch signal processing.

[0317] In addition, the display device and the display panel of some embodiments of the present application can be configured by setting the protective layer to be higher than or equal to the upper electrode of the light emitting element and forming an opening structure. In this configuration, the surface flatness of the display panel is determined by the protective layer, and thus is not affected by the size and process of the LED. In addition, the design of the opening structure can compensate for the height difference of the LEDs caused by the size and process, and can ensure that the upper electrode wire can be electrically connected to the upper electrode of each LED through the opening, so that the upper electrode wire formed on the protective layer has a uniform line width, and the electrical signal transmission characteristics of each LED are ensured. The display device, the display panel and the manufacturing method thereof of some other embodiments of the present application can be configured by applying a force towards the substrate to the light emitting element in the manufacturing process, so that the light emitting element has different displacements and different substrate spacings due to the individual size / height, so that the upper electrode of the light emitting element is kept in the same plane. In this configuration, the size difference of the individual LEDs is compensated by the different substrate spacings, and thus is not affected by the size and process of the LED, so that the module surface can have a flat surface. Thus, the upper electrode wire formed on the protective layer can have a uniform line width, and the electrical signal transmission characteristics of each LED are ensured. Because the upper surfaces of all the light emitting elements can be basically maintained at the same level, there is no height difference, and thus the subsequent manufacturing process is not affected by the flatness of the display panel, and the manufacturing process yield and reliability are effectively improved.

[0318] It is worth mentioning that, in some embodiments, the structure for realizing the surface flattening of the LED FIGS. 30A-30G The embodiments can also be applied to the touch display panel design of FIGS. 27A-29B to make the touch display panel have better surface flatness. In other words, although some structures in the embodiments of FIG. 29 / FIG. 30 are not shown in FIG. 30 / FIG. 29 (for example, the wiring layer WL, the isolation layer DL, etc.), those skilled in the art should understand that the scope disclosed in the present application also includes embodiments that simultaneously cover the structures of FIG. 29 and FIG. 30 after referring to the above description of the embodiments.

[0319] It should also be noted that the material layers (e.g. metal layers, insulating layers, etc.) described in the embodiments of the present application can be described using the same or different terms in different embodiments, but the terms are only used to describe the relative relationship between the elements in the current embodiment, and are not specifically limited to the relative relationship between the material layers in different embodiments. For example, "metal layer ML1" and "metal layer ML2" are used to describe two different structural and functional metal material layers in the same embodiment, that is, the metal layer ML1 (or first metal layer) in one embodiment can be the metal layer ML2 (or second metal layer) in another embodiment. In other words, unless explicitly excluded in the present application, the material layers defined by the same terms can be the same material layers or different material layers in different embodiments, which is described in advance.

[0320] Although the present application has been disclosed by the above embodiments, it is not intended to limit the present application, and any person skilled in the art can make various modifications and changes to the above embodiments without departing from the spirit and scope of the present application, which is still within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A display panel, characterized by, A display panel comprises: a substrate having a display area and a non-display area, wherein the non-display area comprises a bezel area; a pixel array disposed on the display area of the substrate and having a plurality of pixel units arranged in an array; a plurality of scan lines formed on the substrate and electrically connected to each row of pixel units of the pixel array; a plurality of data lines formed on the substrate and electrically connected to each column of pixel units of the pixel array; and an electrostatic protection structure disposed in at least part of the bezel area and comprising a first metal layer, a first insulating layer, a second metal layer, and a second insulating layer arranged in a stack, wherein at least one of the first metal layer and the second metal layer has a hole structure to form a discontinuous island structure in a cross-section of the electrostatic protection structure.

2. The display panel of claim 1, wherein, The electrostatic protection structure further comprises: a first conductive layer formed between the first insulating layer and the second insulating layer and electrically connected to one of the first metal layer and the second metal layer, wherein the first conductive layer is a light-transmitting conductive layer, the first conductive layer, the first insulating layer, and the second insulating layer are stacked to form a plurality of light-transmitting portions at the hole structure, and the plurality of light-transmitting portions are sequentially and spacedly arranged along an arrangement direction of the hole structure.

3. The display panel of claim 1, wherein, The cross-sectional width of the first metal layer is greater than the cross-sectional width of the second metal layer.

4. The display panel of claim 3, wherein, The panel electrostatic protection structure comprises an inner ring structure and an outer ring structure, wherein the inner ring structure has the first metal layer and the second metal layer, and the outer ring structure only has the first metal layer.

5. The display panel of claim 4, wherein, The electrostatic protection structure forms a metal strip pattern surrounding part of the non-display area based on the plurality of light-transmitting portions and the hole structure, and the electrostatic protection structure further comprises a bridge area disposed in another part of the non-display area, wherein the first metal layer and the second metal layer are electrically isolated from each other in the area of the metal strip pattern and are electrically connected to each other only in the bridge area.

6. The display panel of claim 1, wherein, The distance between the electrostatic protection structure and the edge of the substrate is greater than or equal to 20 mm.

7. The display panel of any one of claims 1 to 6, wherein, The display panel further comprises: a first fan-out transmission portion disposed on one side of the non-display area and having a plurality of fan-out wires, wherein the plurality of fan-out wires of the first fan-out transmission portion are respectively electrically connected to an odd number of scan lines; and a second fan-out transmission portion disposed on the other side of the non-display area opposite to the first fan-out transmission portion and having a plurality of fan-out wires, wherein the plurality of fan-out wires of the second fan-out transmission portion are respectively electrically connected to an even number of scan lines, wherein the plurality of scan lines comprise a first scan line group and a second scan line group, the plurality of fan-out wires electrically connected to the first scan line group are formed on the substrate in a first wire structure, and the plurality of fan-out wires electrically connected to the second scan line group are formed on the substrate in a second wire structure.

8. The display panel of claim 7, wherein, The first wire structure comprises a single-layer metal wire structure formed by the first metal layer, and the second wire structure comprises a double-layer metal wire structure formed by the first metal layer and the second metal layer arranged alternately.

9. The display panel of claim 8, wherein, Fan-out wirings formed by the second metal layer connect corresponding scan lines through a bridge structure, and the bridge structure includes: a first via hole formed on a portion of the second metal layer covered by the second insulating layer; a second via hole formed on a portion of the first metal layer covered by the first insulating layer and the second insulating layer; and a second conductive layer formed on the second insulating layer, connected to the second metal layer through the first via hole, and connected to the first metal layer through the second via hole, so that the first metal layer and the second metal layer are electrically connected through the second conductive layer. The non-display area further includes a data circuit fan-out area disposed adjacent to the display area, wherein a shortest distance between any scan line included in the first scan line group and the data circuit fan-out area is greater than a shortest distance between any scan line included in the second scan line group and the data circuit fan-out area.

10. The display panel of claim 7, wherein, The plurality of pixel units includes a first pixel unit, and the first pixel unit includes:

11. The display panel of any one of claims 1 to 6, wherein a thin film transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal is electrically connected to a corresponding data line, and the control terminal is electrically connected to a corresponding scan line; a third insulating layer formed on the substrate; a third metal layer formed on the third insulating layer and electrically connected to the second terminal of the thin film transistor; a fourth insulating layer covering the third metal layer; a common electrode having a grid structure and formed on the fourth insulating layer, wherein the common electrode has a first portion and a second portion, a positive projection area of the first portion of the common electrode and the third metal layer at least partially overlap, and a positive projection area of the second portion of the common electrode and the third metal layer substantially do not overlap; and an extension metal layer electrically connected to the third metal layer and covered by the fourth insulating layer, wherein at least a portion of the extension metal layer is formed in the positive projection area of the second portion of the common electrode. The first pixel unit further includes:

12. The display panel of claim 11, wherein, a counter substrate; a liquid crystal layer formed between the common electrode and the counter substrate; and a black matrix formed on a side of the counter substrate facing the substrate, wherein a positive projection area of at least a portion of the black matrix and a positive projection area of the second portion of the common electrode overlap each other, wherein the extension metal layer is located in the positive projection area of the at least a portion of the black matrix. Two adjacent pixel units of the plurality of pixel units have a spacing area, and the extension metal layer includes:

13. The display panel of claim 11, wherein, a first extension part having one end connected to the second terminal of the corresponding thin film transistor and the other end extending toward the spacing area and formed on the third insulating layer and at least partially covering the third metal layer; and a second extension part having one end connected to the other end of the first extension part and the other end extending along the positive projection area of the second portion of the common electrode and formed on the third insulating layer. Two adjacent pixel units of the plurality of pixel units have a spacing area, and the extension metal layer includes: a first extension part having one end connected to the third metal layer and the other end extending toward the spacing area and formed on the third insulating layer; and 14. The display panel of claim 11, wherein, a second extension part having one end connected to the other end of the first extension part and the other end extending along the positive projection area of the second portion of the common electrode and formed on the third insulating layer. ​ ​ A second extension part is formed on the third insulating layer, one end of which is connected to the other end of the first extension part and the other end of which extends along the projected area of the second common electrode.

15. The display panel of any one of claims 1 to 6, wherein, The plurality of pixel units comprises a first pixel unit and a second pixel unit, the first pixel unit being electrically connected to the nth scan line, and the second pixel unit being electrically connected to the (n+1)th scan line, n being a natural number, wherein the second pixel unit comprises: a thin film transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal is electrically connected to a corresponding data line, and the control terminal is electrically connected to the (n+1)th scan line; a third insulating layer formed on the substrate and covering the nth scan line; a third metal layer formed on the third insulating layer and electrically connected to the second terminal of the thin film transistor, wherein the third metal layer has a first part and a second part; a fourth insulating layer covering the third metal layer; and a common electrode having a grid structure and formed on the fourth insulating layer, and having a first part and a second part, wherein the projected area of the first part of the third metal layer and the first part of the common electrode at least partially overlaps, and wherein the projected area of the second part of the third metal layer and the second part of the common electrode and the nth scan line at least partially overlaps. The nth scan line between two adjacent rows of pixel units comprises a first line segment and a second line segment connected to each other, wherein the first line segment and the second line segment are not parallel to each other.

16. The display panel of claim 15, wherein, The overlapping area of the projected area of the second part of the third metal layer and the first line segment of the nth scan line is substantially the same as the overlapping area of the projected area of the second part of the third metal layer and the second line segment.

17. The display panel of claim 16, wherein, The overlapping area of the projected area of the second part of the third metal layer and one of the first line segment and the second line segment of the nth scan line is greater than the overlapping area of the projected area of the second part of the third metal layer and the other of the first line segment and the second line segment.

18. The display panel of claim 16, wherein, Further comprising:

19. The display panel of any one of claims 1-6, wherein, a scan driving circuit disposed on the non-display area and comprising a plurality of scan units electrically connected to the plurality of scan lines, wherein each scan unit comprises at least one holding capacitor, and the structure of the holding capacitor comprises the first metal layer, the first insulating layer, the second metal layer, the second insulating layer, a third conductive layer and a fourth conductive layer, wherein: the third conductive layer and the fourth conductive layer are light-transmitting conductive layers, the third conductive layer is disposed on the second insulating layer, and the fourth conductive layer is disposed on the first insulating layer and at least partially covered by the second insulating layer, wherein one end of the fourth conductive layer is connected to the second metal layer; wherein at least a part of the first metal layer is formed with a via hole to expose the at least part of the first metal layer from the first insulating layer and the second insulating layer, wherein the third conductive layer is connected to the at least part of the first metal layer exposed via the via hole. ​ 20. The display panel of claim 19, wherein, A portion of the second metal layer is extended to form on another partial region of the fourth conductive layer, so that the second metal layer and the fourth conductive layer at least partially overlap in the normal direction of the substrate.

21. The display panel of claim 19, wherein, The holding capacitance is the sum of a first capacitance, a second capacitance, and a third capacitance, wherein the first capacitance is based on a first overlapping region of the first metal layer and the second metal layer and the first insulating layer located in the first overlapping region, the second capacitance is based on a second overlapping region of the second metal layer and the third conductive layer and the second insulating layer located in the second overlapping region, and the third capacitance is based on a third overlapping region of the third conductive layer and the fourth conductive layer and the second insulating layer located in the third overlapping region.

22. The display panel of any one of claims 1-6, wherein: The display panel further comprises: a third metal layer formed in the display area on the substrate and comprising a plurality of first electrode regions and a plurality of second electrode regions, wherein the plurality of first electrode regions and the plurality of second electrode regions are electrically independent of each other, and the plurality of first electrode regions and the plurality of second electrode regions are alternately arranged on the substrate with intervals; a plurality of light emitting elements, wherein each of the light emitting elements comprises a first electrode and a second electrode formed on opposite sides, and the first electrode is electrically connected to a corresponding first electrode region; a protective layer filled between the plurality of light emitting elements and covering at least part of the surface of each of the light emitting elements; and a fourth metal layer formed on the protective layer and comprising a plurality of third electrode regions, wherein each of the third electrode regions is formed on a corresponding light emitting element and is electrically connected to the second electrode of the corresponding light emitting element. Each of the pixel units comprises a display unit and a touch sensing unit, the display unit comprises a corresponding light emitting element and a first electrode region and a third electrode region electrically connected to the corresponding light emitting element, and the touch sensing unit comprises a second electrode region and a fourth electrode region adjacent to the display unit. The orthographic projection region of the plurality of third electrode regions on the substrate does not completely overlap with the orthographic projection region of the plurality of second electrode regions on the substrate.

23. The display panel of claim 22, wherein, The orthographic projection region of the plurality of third electrode regions on the substrate does not completely overlap with the orthographic projection region of the plurality of second electrode regions on the substrate.

24. The display panel of claim 23, wherein, The fourth metal layer further comprises a plurality of fourth electrode regions, wherein the plurality of third electrode regions and the plurality of fourth electrode regions are electrically independent of each other, and the plurality of fourth electrode regions are respectively electrically connected to corresponding second electrode regions.

25. The display panel of claim 24, wherein, The mother substrate comprises a plurality of array blocks; and 26. An electrostatic discharge protection structure, comprising: a plurality of display panels arranged in sequence on each of the array blocks on the mother substrate, wherein each of the array blocks comprises: a first metal layer formed on each of the array blocks in a manner of surrounding at least two of the plurality of display panels to form a plurality of first electrostatic discharge lines on each of the array blocks; a first insulating layer covering the first metal layer and exposing at least a portion of the first metal layer; and a second metal layer formed on the first insulating layer and comprising a plurality of second electrode regions, wherein each of the second electrode regions is electrically connected to a corresponding second electrode region on the substrate. ​ a second metal layer formed on the first insulating layer in a manner surrounding at least two of the plurality of display panels to form a plurality of second electrostatic discharge lines corresponding to the plurality of first electrostatic discharge lines on each of the array blocks; a second insulating layer covering the second metal layer and exposing at least a portion of the second metal layer; and a first conductive layer formed in the bridge region, wherein at least a portion of the first conductive layer is connected through the portion of the first insulating layer exposed and the first metal layer, and at least another portion of the first conductive layer is connected through the portion of the second insulating layer exposed and the second metal layer, for electrically connecting the plurality of first electrostatic discharge lines and the plurality of second electrostatic discharge lines to each other in the bridge region.

27. The electrostatic discharge protection structure of claim 26, wherein, A portion of the bridge region is configured at a corner of each of the array blocks.

28. The electrostatic discharge protection structure of claim 27, wherein the first and second gate electrodes are formed of a material selected from the group consisting of polysilicon, amorphous silicon, and metal. 28 Another portion of the bridge region is configured at a position equidistant from the bridge regions of two adjacent corners.

29. The electrostatic discharge protection structure of claim 26, wherein the first and second gate electrodes are formed of a material selected from the group consisting of polysilicon, amorphous silicon, and polycide. The first insulating layer electrically isolates each of the first electrostatic discharge lines in a non-bridge region, and the second insulating layer electrically isolates each of the second electrostatic discharge lines in a non-bridge region.

30. The electrostatic discharge protection structure of claim 26, wherein the first and second gate electrodes are formed of a material selected from the group consisting of polysilicon, amorphous silicon, and metal. The pitch between two adjacent first electrostatic discharge lines or second electrostatic discharge lines is greater than 200 μm.

31. The electrostatic discharge protection structure of claim 30, wherein, The pitch between two adjacent first electrostatic discharge lines or second electrostatic discharge lines is between 200 μm and 300 μm.

32. The electrostatic discharge protection structure of claim 30, wherein the first and second gate electrodes are formed of a material selected from the group consisting of polysilicon, amorphous silicon, and polycide. The width of the plurality of first electrostatic discharge lines and the plurality of second electrostatic discharge lines is no more than 1500 μm.

33. The electrostatic discharge protection structure of any of claims 26-32, wherein the first and second gate electrodes are formed of a material selected from the group consisting of polysilicon, amorphous silicon, and metal. 33 Each of the display panels has a common electrode, and the common electrode of each of the display panels is electrically connected to the common electrode of an adjacent display panel.

34. The electrostatic discharge protection structure of claim 33, wherein the first and second gate electrodes are formed of a material selected from the group consisting of polysilicon, amorphous silicon, and metal. The plurality of display panels are arranged in the same direction.

35. The electrostatic discharge protection structure of claim 33, wherein the first and second gate electrodes are formed of a material selected from the group consisting of polysilicon, amorphous silicon, and polycide. Two rows or two columns of the plurality of display panels are arranged in opposite directions with reference to a virtual symmetry line.

36. The electrostatic discharge protection structure of any of claims 26-32, wherein the first and second gate electrodes are formed of a material selected from the group consisting of polysilicon, amorphous silicon, and metal. 37 Each of the display panels comprises: a substrate having a display region and a non-display region, wherein the non-display region comprises a bezel region; a pixel array disposed on the display region of the substrate and having a plurality of pixel units arranged in an array; a plurality of scan lines formed on the substrate and electrically connected to each row of pixel units of the pixel array; a plurality of data lines formed on the substrate and electrically connected to each column of pixel units of the pixel array; and a plurality of metal strip patterns surrounding at least a portion of the bezel region, wherein each of the metal strip patterns comprises the first metal layer, the first insulating layer, the second metal layer, and the second insulating layer stacked and arranged, wherein at least one of the first metal layer and the second metal layer has a hole structure in each of the metal strip patterns to form a discontinuous island structure in the cross section of the corresponding metal strip pattern.

37. The electrostatic discharge protection structure of claim 36, wherein the first and second gate electrodes are formed of a material selected from the group consisting of polysilicon, amorphous silicon, and polycide. Each of the metal strip patterns further comprises: a second conductive layer formed between the first insulating layer and the second insulating layer and electrically connected to one of the first metal layer and the second metal layer, The second conductive layer is a light-transmitting conductive layer, the second conductive layer, the first insulating layer and the second insulating layer are stacked at the hole structure to form a plurality of light-transmitting parts, and the plurality of light-transmitting parts are sequentially and spacedly arranged along an arrangement direction of the hole structure.

38. The electrostatic discharge protection structure of claim 36, wherein the first and second gate electrodes are formed of a material selected from the group consisting of polysilicon, amorphous silicon, and polycide. 37 Each of the metal strip patterns has an inner ring structure and an outer ring structure, the inner ring structure includes the first metal layer and the second metal layer, the outer ring structure does not include the second metal layer, and a cross-sectional width of the first metal layer is greater than a cross-sectional width of the second metal layer in each of the metal strip patterns.

39. A display device comprising: Comprise: The display panel of any one of claims 1-6, wherein each pixel unit comprises a display unit and a touch sensing unit; a display driving chip electrically connected to the display unit to control a lighting state of the display unit; and a touch sensing chip electrically connected to the touch sensing unit to drive the touch sensing unit. The display panel further comprises:

40. The display device of claim 39, wherein, a third metal layer formed in the display area on the substrate and comprising a plurality of first electrode regions and a plurality of second electrode regions, wherein the plurality of first electrode regions and the plurality of second electrode regions are electrically independent of each other, and the plurality of first electrode regions and the plurality of second electrode regions are alternately arranged on the substrate in a spaced manner; a plurality of light emitting elements, wherein each of the light emitting elements comprises a first electrode and a second electrode formed on opposite sides, and the first electrode is electrically connected to a corresponding first electrode region; a protective layer filled between the plurality of light emitting elements and covering at least part of a surface of each of the light emitting elements; and a fourth metal layer formed on the protective layer and comprising a plurality of third electrode regions, wherein each of the third electrode regions is formed on a corresponding light emitting element and is electrically connected to the second electrode of the corresponding light emitting element. Each of the pixel units comprises a display unit and a touch sensing unit, the display unit comprises a corresponding light emitting element, a first electrode region and a third electrode region electrically connected to the corresponding light emitting element, and the touch sensing unit comprises a second electrode region and a fourth electrode region adjacent to the display unit. The display panel further comprises: a first fan-out transmission part disposed on one side of the non-display area and having a plurality of fan-out wires, wherein the plurality of fan-out wires of the first fan-out transmission part are respectively electrically connected to an odd number of the scan lines; and 41. The display device of claim 40, wherein, a second fan-out transmission part disposed on the other side of the non-display area opposite to the first fan-out transmission part and having a plurality of fan-out wires, wherein the plurality of fan-out wires of the second fan-out transmission part are respectively electrically connected to an even number of the scan lines, wherein the plurality of scan lines comprise a first scan line group and a second scan line group, the plurality of fan-out wires electrically connected to the first scan line group are formed on the substrate in a first wire structure, and the plurality of fan-out wires electrically connected to the second scan line group are formed on the substrate in a second wire structure. The display driving chip comprises: ​ 42. The display device of claim 41, wherein, ​ A scan driving circuit is disposed on the non-display region and includes a plurality of scan units electrically connected to the plurality of scan lines. Each of the scan units includes at least one holding capacitor. The holding capacitor includes the first metal layer, the first insulating layer, the second metal layer, the second insulating layer, a third conductive layer, and a fourth conductive layer. The third conductive layer is disposed on the second insulating layer. The fourth conductive layer is disposed on the first insulating layer and at least partially covered by the second insulating layer. One end of the fourth conductive layer is connected to the second metal layer. The third conductive layer and the fourth conductive layer are light-transmitting conductive layers. The third conductive layer is disposed on the second insulating layer. The fourth conductive layer is disposed on the first insulating layer and at least partially covered by the second insulating layer. One end of the fourth conductive layer is connected to the second metal layer. At least a portion of the first metal layer is formed with a via hole, so that the at least a portion of the first metal layer is exposed from the first insulating layer and the second insulating layer. The third conductive layer is connected to the at least a portion of the first metal layer exposed via the via hole.

43. The display apparatus of claim 41, wherein, The plurality of pixel units includes a first pixel unit. The first pixel unit includes: a thin film transistor having a first terminal, a second terminal, and a control terminal. The first terminal is electrically connected to a corresponding data line. The control terminal is electrically connected to a corresponding scan line. a third insulating layer formed on the substrate. a third metal layer formed on the third insulating layer and electrically connected to the second terminal of the thin film transistor. a fourth insulating layer covering the third metal layer. a common electrode having a grid structure and formed on the fourth insulating layer. The common electrode has a first portion and a second portion. A projection area of the first portion of the common electrode and the third metal layer at least partially overlaps. A projection area of the second portion of the common electrode and the third metal layer substantially does not overlap. an extension metal layer electrically connected to the third metal layer and covered by the fourth insulating layer. At least a portion of the extension metal layer is formed in the projection area of the second portion of the common electrode. The plurality of pixel units includes a first pixel unit and a second pixel unit. The first pixel unit is electrically connected to an n-th scan line. The second pixel unit is electrically connected to an n+1-th scan line. n is a natural number. The second pixel unit includes:

44. The display apparatus of claim 41, wherein a thin film transistor having a first terminal, a second terminal, and a control terminal. The first terminal is electrically connected to a corresponding data line. The control terminal is electrically connected to the n+1-th scan line. a third insulating layer formed on the substrate and covering the n-th scan line. a third metal layer formed on the third insulating layer and electrically connected to the second terminal of the thin film transistor. The third metal layer has a first portion and a second portion. a fourth insulating layer covering the third metal layer. a common electrode having a grid structure and formed on the fourth insulating layer. The common electrode has a first portion and a second portion. The projection area of the first portion of the third metal layer and the first portion of the common electrode at least partially overlaps. ​ The third metal layer, the second part of the common electrode and the n-th scan line at least partially overlap in the projection region. The third metal layer, the second part of the common electrode and the n-th scan line at least partially overlap in the projection region.

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